e51aa20dd7fb04f2eb4715d50a45c88b89572bc0
[linux-3.10.git] / arch / arm / mach-tegra / board-laguna-power.c
1 /*
2  * arch/arm/mach-tegra/board-laguna-power.c
3  *
4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca954x.h>
22 #include <linux/i2c/pca953x.h>
23 #include <linux/pda_power.h>
24 #include <linux/platform_device.h>
25 #include <linux/resource.h>
26 #include <linux/io.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/driver.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/mfd/as3722-reg.h>
31 #include <linux/mfd/as3722-plat.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/userspace-consumer.h>
34
35 #include <asm/mach-types.h>
36
37 #include <mach/irqs.h>
38 #include <mach/edp.h>
39 #include <mach/gpio-tegra.h>
40
41 #include "cpu-tegra.h"
42 #include "pm.h"
43 #include "tegra-board-id.h"
44 #include "board.h"
45 #include "gpio-names.h"
46 #include "board-common.h"
47 #include "board-pmu-defines.h"
48 #include "board-ardbeg.h"
49 #include "tegra_cl_dvfs.h"
50 #include "devices.h"
51 #include "tegra11_soctherm.h"
52 #include "iomap.h"
53
54 #define PMC_CTRL                0x0
55 #define PMC_CTRL_INTR_LOW       (1 << 17)
56 #define AS3722_SUPPLY(_name) "as3722_"#_name
57
58 static struct regulator_consumer_supply as3722_ldo0_supply[] = {
59         REGULATOR_SUPPLY("avdd_pll_m", NULL),
60         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
61         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
62         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
63         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
64         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
65         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
66         REGULATOR_SUPPLY("avdd_pll_x", NULL),
67         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
68 };
69
70 static struct regulator_consumer_supply as3722_ldo1_supply[] = {
71         REGULATOR_SUPPLY("vddio_cam", "vi"),
72         REGULATOR_SUPPLY("vdd_cam_1v8_cam", NULL),
73         REGULATOR_SUPPLY("vif", "2-0010"),
74         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
75 };
76
77 static struct regulator_consumer_supply as3722_ldo2_supply[] = {
78         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
79         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
80         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
81         REGULATOR_SUPPLY("avdd_hsic_com", NULL),
82         REGULATOR_SUPPLY("avdd_hsic_mdm", NULL),
83         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
84         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
85         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
86 };
87
88 static struct regulator_consumer_supply as3722_ldo3_supply[] = {
89         REGULATOR_SUPPLY("vdd_rtc", NULL),
90 };
91
92 static struct regulator_consumer_supply as3722_ldo4_supply[] = {
93         REGULATOR_SUPPLY("vdd_2v7_hv", NULL),
94         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
95         REGULATOR_SUPPLY("vana", "2-0010"),
96 };
97
98 static struct regulator_consumer_supply as3722_ldo5_supply[] = {
99         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
100         REGULATOR_SUPPLY("vdig", "2-0010"),
101 };
102
103 static struct regulator_consumer_supply as3722_ldo6_supply[] = {
104         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
105         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
106 };
107
108 static struct regulator_consumer_supply as3722_ldo7_supply[] = {
109         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
110 };
111
112 static struct regulator_consumer_supply as3722_ldo9_supply[] = {
113         REGULATOR_SUPPLY("vdd_ts_3v0b_dis", NULL),
114 };
115
116 static struct regulator_consumer_supply as3722_ldo10_supply[] = {
117         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
118         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
119         REGULATOR_SUPPLY("imx135_reg1", NULL),
120         REGULATOR_SUPPLY("vdd", "2-000e"),
121 };
122
123 static struct regulator_consumer_supply as3722_ldo11_supply[] = {
124         REGULATOR_SUPPLY("vpp_fuse", NULL),
125 };
126
127 static struct regulator_consumer_supply as3722_sd0_supply[] = {
128         REGULATOR_SUPPLY("vdd_cpu", NULL),
129 };
130
131 static struct regulator_consumer_supply as3722_sd1_supply[] = {
132         REGULATOR_SUPPLY("vdd_core", NULL),
133 };
134
135 static struct regulator_consumer_supply as3722_sd2_supply[] = {
136         REGULATOR_SUPPLY("vddio_ddr", NULL),
137         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
138         REGULATOR_SUPPLY("vddio_ddr3", NULL),
139         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
140 };
141
142 static struct regulator_consumer_supply as3722_sd4_supply[] = {
143         REGULATOR_SUPPLY("avdd_pex_pll", NULL),
144         REGULATOR_SUPPLY("avddio_pex_pll", NULL),
145         REGULATOR_SUPPLY("dvddio_pex", NULL),
146         REGULATOR_SUPPLY("avdd_sata", NULL),
147         REGULATOR_SUPPLY("vdd_sata", NULL),
148         REGULATOR_SUPPLY("avdd_sata_pll", NULL),
149 };
150
151 static struct regulator_consumer_supply as3722_sd5_supply[] = {
152         REGULATOR_SUPPLY("vddio_sys", NULL),
153         REGULATOR_SUPPLY("vddio_sys_2", NULL),
154         REGULATOR_SUPPLY("vddio_audio", NULL),
155         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
156         REGULATOR_SUPPLY("vddio_uart", NULL),
157         REGULATOR_SUPPLY("vddio_bb", NULL),
158         REGULATOR_SUPPLY("vddio_gmi", NULL),
159         REGULATOR_SUPPLY("avdd_osc", NULL),
160 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
161         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
162         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
163         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
164         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
165         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
166 #endif
167         /* emmc 1.8v misssing
168         keyboard & touchpad 1.8v missing */
169 };
170
171 static struct regulator_consumer_supply as3722_sd6_supply[] = {
172         REGULATOR_SUPPLY("vdd_gpu", NULL),
173 };
174
175 AMS_PDATA_INIT(sd0, NULL, 700000, 1350000, 1, 1, 1, 2);
176 AMS_PDATA_INIT(sd1, NULL, 700000, 1350000, 1, 1, 1, 1);
177 AMS_PDATA_INIT(sd2, NULL, 1350000, 1350000, 1, 1, 1, 0);
178 AMS_PDATA_INIT(sd4, NULL, 1050000, 1050000, 0, 1, 1, 0);
179 AMS_PDATA_INIT(sd5, NULL, 1800000, 1800000, 1, 1, 1, 0);
180 AMS_PDATA_INIT(sd6, NULL, 900000, 1400000, 1, 1, 1, 0);
181 AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1, 1);
182 AMS_PDATA_INIT(ldo1, NULL, 1800000, 1800000, 0, 1, 1, 0);
183 AMS_PDATA_INIT(ldo2, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 1, 1, 0);
184 AMS_PDATA_INIT(ldo3, NULL, 1000000, 1000000, 1, 1, 1, 0);
185 AMS_PDATA_INIT(ldo4, NULL, 2700000, 2700000, 0, 0, 1, 0);
186 AMS_PDATA_INIT(ldo5, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
187 AMS_PDATA_INIT(ldo6, NULL, 3300000, 3300000, 0, 0, 1, 0);
188 AMS_PDATA_INIT(ldo7, AS3722_SUPPLY(sd5), 1050000, 1050000, 0, 0, 1, 0);
189 AMS_PDATA_INIT(ldo9, NULL, 3300000, 3300000, 0, 1, 1, 0);
190 AMS_PDATA_INIT(ldo10, NULL, 2700000, 2700000, 0, 0, 1, 0);
191 AMS_PDATA_INIT(ldo11, NULL, 1800000, 1800000, 0, 0, 1, 0);
192
193 /* config settings are OTP plus initial state
194  * GPIOsignal_out at 20h not configurable through OTP and is initialized to
195  * zero. To enable output, the invert bit must be turned on.
196  * GPIOxcontrol register format
197  * bit(s)  bitname
198  * ---------------------
199  *  7     gpiox_invert   invert input or output
200  * 6:3    gpiox_iosf     0: normal
201  * 2:0    gpiox_mode     0: input, 1: output push/pull, 3: ADC input (tristate)
202  *
203  * Examples:
204  * otp  meaning
205  * ------------
206  * 0x3  gpiox_invert=0(no invert), gpiox_iosf=0(normal), gpiox_mode=3(ADC input)
207  * 0x81 gpiox_invert=1(invert), gpiox_iosf=0(normal), gpiox_mode=1(output)
208  *
209  * Note: output state should be defined for gpiox_mode = output.  Do not change
210  * the state of the invert bit for critical devices such as GPIO 7 which enables
211  * SDRAM. Driver applies invert mask to output state to configure GPIOsignal_out
212  * register correctly.
213  * E.g. Invert = 1, (requested) output state = 1 => GPIOsignal_out = 0
214  */
215 static struct as3722_gpio_config as3722_gpio_cfgs[] = {
216         {
217                 /* otp = 0x3 IGPU_PRDGD*/
218                 .gpio = AS3722_GPIO0,
219                 .mode = AS3722_GPIO_MODE_OUTPUT_VDDL,
220         },
221         {
222                 /* otp = 0x1  => REGEN_3 = LP0 gate (1.8V, 5 V)*/
223                 .gpio = AS3722_GPIO1,
224                 .invert     = AS3722_GPIO_CFG_INVERT, /* don't go into LP0 */
225                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
226                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
227         },
228         {
229                 /* otp = 0x3 PMU_REGEN1*/
230                 .gpio = AS3722_GPIO2,
231                 .invert     = AS3722_GPIO_CFG_INVERT, /* don't go into LP0 */
232                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
233                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
234         },
235         {
236                 /* otp = 0x03 AP THERMISTOR */
237                 .gpio = AS3722_GPIO3,
238                 .mode = AS3722_GPIO_MODE_ADC_IN,
239         },
240         {
241                 /* otp = 0x81 => on by default
242                  * gates EN_AVDD_LCD
243                  */
244                 .gpio       = AS3722_GPIO4,
245                 .invert     = AS3722_GPIO_CFG_NO_INVERT,
246                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
247                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
248         },
249         {
250                 /* otp = 0x3  CLK 23KHZ WIFI */
251                 .gpio = AS3722_GPIO5,
252                 .mode = AS3722_GPIO_MODE_ADC_IN,
253         },
254         {
255                 /* otp = 0x3  SKIN TEMP */
256                 .gpio = AS3722_GPIO6,
257                 .mode = AS3722_GPIO_MODE_ADC_IN,
258         },
259         {
260                 /* otp = 0x81  1.6V LP0*/
261                 .gpio       = AS3722_GPIO7,
262                 .invert     = AS3722_GPIO_CFG_NO_INVERT,
263                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
264                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
265         },
266 };
267
268 static struct as3722_rtc_platform_data as3722_rtc_pdata = {
269         .enable_clk32k  = 1,
270 };
271
272 static struct as3722_platform_data as3722_pdata = {
273         .reg_pdata[AS3722_LDO0] = &as3722_ldo0_reg_pdata,
274         .reg_pdata[AS3722_LDO1] = &as3722_ldo1_reg_pdata,
275         .reg_pdata[AS3722_LDO2] = &as3722_ldo2_reg_pdata,
276         .reg_pdata[AS3722_LDO3] = &as3722_ldo3_reg_pdata,
277         .reg_pdata[AS3722_LDO4] = &as3722_ldo4_reg_pdata,
278         .reg_pdata[AS3722_LDO5] = &as3722_ldo5_reg_pdata,
279         .reg_pdata[AS3722_LDO6] = &as3722_ldo6_reg_pdata,
280         .reg_pdata[AS3722_LDO7] = &as3722_ldo7_reg_pdata,
281         .reg_pdata[AS3722_LDO9] = &as3722_ldo9_reg_pdata,
282         .reg_pdata[AS3722_LDO10] = &as3722_ldo10_reg_pdata,
283         .reg_pdata[AS3722_LDO11] = &as3722_ldo11_reg_pdata,
284
285         .reg_pdata[AS3722_SD0] = &as3722_sd0_reg_pdata,
286         .reg_pdata[AS3722_SD1] = &as3722_sd1_reg_pdata,
287         .reg_pdata[AS3722_SD2] = &as3722_sd2_reg_pdata,
288         .reg_pdata[AS3722_SD4] = &as3722_sd4_reg_pdata,
289         .reg_pdata[AS3722_SD5] = &as3722_sd5_reg_pdata,
290         .reg_pdata[AS3722_SD6] = &as3722_sd6_reg_pdata,
291
292         .core_init_data = NULL,
293         .gpio_base = AS3722_GPIO_BASE,
294         .irq_base = AS3722_IRQ_BASE,
295         .use_internal_int_pullup = 0,
296         .use_internal_i2c_pullup = 0,
297         .num_gpio_cfgs = ARRAY_SIZE(as3722_gpio_cfgs),
298         .gpio_cfgs     = as3722_gpio_cfgs,
299         .rtc_pdata      = &as3722_rtc_pdata,
300 };
301
302 static struct pca953x_platform_data tca6416_pdata = {
303         .gpio_base = PMU_TCA6416_GPIO_BASE,
304 };
305
306 static const struct i2c_board_info tca6416_expander[] = {
307         {
308                 I2C_BOARD_INFO("tca6416", 0x20),
309                 .platform_data = &tca6416_pdata,
310         },
311 };
312
313 static struct i2c_board_info __initdata as3722_regulators[] = {
314         {
315                 I2C_BOARD_INFO("as3722", 0x40),
316                 .flags = I2C_CLIENT_WAKE,
317                 .irq = INT_EXTERNAL_PMU,
318                 .platform_data = &as3722_pdata,
319         },
320 };
321
322 int __init laguna_as3722_regulator_init(void)
323 {
324         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
325         u32 pmc_ctrl;
326         struct board_info board_info;
327
328         tegra_get_board_info(&board_info);
329
330         /* AS3722: Normal state of INT request line is LOW.
331          * configure the power management controller to trigger PMU
332          * interrupts when HIGH.
333          */
334         pmc_ctrl = readl(pmc + PMC_CTRL);
335         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
336         regulator_has_full_constraints();
337         printk(KERN_INFO "%s: i2c_register_board_info\n",
338                         __func__);
339         i2c_register_board_info(4, as3722_regulators,
340                         ARRAY_SIZE(as3722_regulators));
341         if (board_info.board_id == BOARD_PM359 ||
342                         board_info.board_id == BOARD_PM358)
343                 i2c_register_board_info(0, tca6416_expander,
344                                 ARRAY_SIZE(tca6416_expander));
345         return 0;
346 }
347
348 static struct tegra_suspend_platform_data laguna_suspend_data = {
349         .cpu_timer      = 2000,
350         .cpu_off_timer  = 2000,
351         .suspend_mode   = TEGRA_SUSPEND_NONE,
352         .core_timer     = 0x7e7e,
353         .core_off_timer = 2000,
354         .corereq_high   = true,
355         .sysclkreq_high = true,
356         .cpu_lp2_min_residency = 1000,
357 };
358
359 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
360 /* board parameters for cpu dfll */
361 static struct tegra_cl_dvfs_cfg_param laguna_cl_dvfs_param = {
362         .sample_rate = 12500,
363
364         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
365         .cf = 10,
366         .ci = 0,
367         .cg = 2,
368
369         .droop_cut_value = 0xF,
370         .droop_restore_ramp = 0x0,
371         .scale_out_ramp = 0x0,
372 };
373 #endif
374
375 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
376 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
377 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
378 static inline void fill_reg_map(void)
379 {
380         int i;
381         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
382                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
383                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
384         }
385 }
386
387 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
388 static struct tegra_cl_dvfs_platform_data laguna_cl_dvfs_data = {
389         .dfll_clk_name = "dfll_cpu",
390         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
391         .u.pmu_i2c = {
392                 .fs_rate = 400000,
393                 .slave_addr = 0x86,
394                 .reg = 0x00,
395         },
396         .vdd_map = pmu_cpu_vdd_map,
397         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
398
399         .cfg_param = &laguna_cl_dvfs_param,
400 };
401
402 static int __init laguna_cl_dvfs_init(void)
403 {
404         fill_reg_map();
405         tegra_cl_dvfs_device.dev.platform_data = &laguna_cl_dvfs_data;
406         platform_device_register(&tegra_cl_dvfs_device);
407
408         return 0;
409 }
410 #endif
411
412 /* Always ON /Battery regulator */
413 static struct regulator_consumer_supply fixed_reg_battery_supply[] = {
414         REGULATOR_SUPPLY("vdd_sys_bl", NULL),
415 };
416
417 /* Always ON 1.8v */
418 static struct regulator_consumer_supply fixed_reg_aon_1v8_supply[] = {
419         REGULATOR_SUPPLY("vdd_1v8_emmc", NULL),
420         REGULATOR_SUPPLY("vdd_1v8b_com_f", NULL),
421         REGULATOR_SUPPLY("vdd_1v8b_gps_f", NULL),
422 };
423
424 /* Always ON 3.3v */
425 static struct regulator_consumer_supply fixed_reg_aon_3v3_supply[] = {
426         REGULATOR_SUPPLY("vdd_3v3_emmc", NULL),
427         REGULATOR_SUPPLY("vdd_com_3v3", NULL),
428 };
429
430 /* Always ON 1v2 */
431 static struct regulator_consumer_supply fixed_reg_aon_1v2_supply[] = {
432         REGULATOR_SUPPLY("vdd_1v2_bb_hsic", NULL),
433 };
434
435 /* EN_USB1_VBUS From TEGRA GPIO PN4 */
436 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
437         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
438         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
439         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
440
441 };
442
443 /* EN_USB2_3_VBUS From TEGRA GPIO PN5 */
444 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
445         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
446         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
447 };
448
449
450 /* Gated by GPIO_PK6  in FAB B and further*/
451 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
452         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
453 };
454
455 /* Gated by GPIO_PH7  in FAB B and further*/
456 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_supply[] = {
457         REGULATOR_SUPPLY("avdd_hdmi", "NULL"),
458         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
459 };
460 /* LCD_BL_EN GMI_AD10 */
461 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
462         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
463 };
464
465 /* AS3722 GPIO1*/
466 static struct regulator_consumer_supply fixed_reg_3v3_supply[] = {
467         REGULATOR_SUPPLY("hvdd_pex", NULL),
468         REGULATOR_SUPPLY("hvdd_pex_pll", NULL),
469         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
470         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5645"),
471         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5639"),
472         REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
473         REGULATOR_SUPPLY("vdd_nfc_3v3", NULL),
474         REGULATOR_SUPPLY("vdd_3v3_sensor", NULL),
475         REGULATOR_SUPPLY("vdd_kp_3v3", NULL),
476         REGULATOR_SUPPLY("vdd_tp_3v3", NULL),
477         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
478         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
479 };
480
481 /* AS3722 GPIO1*/
482 static struct regulator_consumer_supply fixed_reg_5v0_supply[] = {
483         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645"),
484         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639"),
485         REGULATOR_SUPPLY("vdd_5v0_sensor", NULL),
486 };
487
488 static struct regulator_consumer_supply fixed_reg_dcdc_1v8_supply[] = {
489         REGULATOR_SUPPLY("avdd_lvds0_pll", NULL),
490         REGULATOR_SUPPLY("dvdd_lcd", NULL),
491         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
492         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645"),
493         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645"),
494         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639"),
495         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639"),
496         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639"),
497         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645"),
498         REGULATOR_SUPPLY("vdd_1v8b_nfc", NULL),
499         REGULATOR_SUPPLY("vdd_1v8_sensor", NULL),
500         REGULATOR_SUPPLY("vdd_1v8_sdmmc", NULL),
501         REGULATOR_SUPPLY("vdd_kp_1v8", NULL),
502         REGULATOR_SUPPLY("vdd_tp_1v8", NULL),
503         REGULATOR_SUPPLY("vdd_modem_1v8", NULL),
504 };
505
506 /* gated by TCA6416 GPIO EXP GPIO0 */
507 static struct regulator_consumer_supply fixed_reg_dcdc_1v2_supply[] = {
508         REGULATOR_SUPPLY("vdd_1v2_en", NULL),
509 };
510
511 /* AMS GPIO2 */
512 static struct regulator_consumer_supply fixed_reg_as3722_gpio2_supply[] = {
513         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
514         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
515         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
516         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
517 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
518         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
519         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
520         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
521         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
522         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
523 #endif
524         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
525         REGULATOR_SUPPLY("vddio_hv", "NULL"),
526         REGULATOR_SUPPLY("hvdd_sata", NULL),
527 };
528
529 /* gated by AS3722 GPIO4 */
530 static struct regulator_consumer_supply fixed_reg_lcd_supply[] = {
531         REGULATOR_SUPPLY("avdd_lcd", NULL),
532 };
533
534 /* gated by GPIO_PR0 */
535 static struct regulator_consumer_supply fixed_reg_sdmmc_en_supply[] = {
536         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.1"),
537         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
538 };
539
540 /* only adding for PM358 */
541 static struct regulator_consumer_supply fixed_reg_vdd_cdc_1v2_aud_supply[] = {
542         REGULATOR_SUPPLY("ldoen", "tegra-snd-rt5639"),
543 };
544
545 static struct regulator_consumer_supply fixed_reg_vdd_amp_shut_aud_supply[] = {
546         REGULATOR_SUPPLY("epamp", "tegra-snd-rt5645"),
547 };
548 /* Macro for defining fixed regulator sub device data */
549 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
550 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,           \
551                 _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
552 static struct regulator_init_data ri_data_##_var =              \
553 {                                                               \
554         .supply_regulator = _in_supply,                         \
555         .num_consumer_supplies =                                \
556         ARRAY_SIZE(fixed_reg_##_name##_supply),                 \
557         .consumer_supplies = fixed_reg_##_name##_supply,        \
558         .constraints = {                                        \
559                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
560                                 REGULATOR_MODE_STANDBY),        \
561                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
562                                 REGULATOR_CHANGE_STATUS |       \
563                                 REGULATOR_CHANGE_VOLTAGE),      \
564                 .always_on = _always_on,                        \
565                 .boot_on = _boot_on,                            \
566         },                                                      \
567 };                                                              \
568 static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
569 {                                                               \
570         .supply_name = FIXED_SUPPLY(_name),                     \
571         .microvolts = _millivolts * 1000,                       \
572         .gpio = _gpio_nr,                                       \
573         .gpio_is_open_drain = _open_drain,                      \
574         .enable_high = _active_high,                            \
575         .enabled_at_boot = _boot_state,                         \
576         .init_data = &ri_data_##_var,                           \
577 };                                                              \
578 static struct platform_device fixed_reg_##_var##_dev = {        \
579         .name = "reg-fixed-voltage",                            \
580         .id = _id,                                              \
581         .dev = {                                                \
582                 .platform_data = &fixed_reg_##_var##_pdata,     \
583         },                                                      \
584 }
585
586 FIXED_REG(0,    battery,        battery,        NULL,   0,      0,
587                 -1,     false, true,    0,      8400);
588
589 FIXED_REG(1,    aon_1v8,        aon_1v8,        NULL,   0,      0,
590                 -1,     false, true,    0,      1800);
591
592 FIXED_REG(2,    aon_3v3,        aon_3v3,        NULL,   0,      0,
593                 -1,     false, true,    0,      3300);
594
595 FIXED_REG(3,    aon_1v2,        aon_1v2,        NULL,   0,      0,
596                 -1,     false, true,    0,      1200);
597
598 FIXED_REG(4,    vdd_hdmi_5v0,   vdd_hdmi_5v0,   NULL,   0,      0,
599                 TEGRA_GPIO_PK6, false,  true,   0,      5000);
600
601 FIXED_REG(5,    vdd_hdmi,       vdd_hdmi,       AS3722_SUPPLY(sd4),
602                 0,      0,
603                 TEGRA_GPIO_PH7, false,  true,   0,      3300);
604
605 FIXED_REG(6,    usb1_vbus,      usb1_vbus,      NULL,   0,      0,
606                 TEGRA_GPIO_PN4, true,   true,   0,      5000);
607
608 FIXED_REG(7,    usb3_vbus,      usb3_vbus,      NULL,   0,      0,
609                 TEGRA_GPIO_PN5, true,   true,   0,      5000);
610
611 FIXED_REG(8,    lcd_bl_en,      lcd_bl_en,      NULL,   0,      0,
612                 TEGRA_GPIO_PH2, false,  true,   0,      5000);
613
614 FIXED_REG(9,    3v3,            3v3,            NULL,   0,      0,
615                 -1,     false,  true,   0,      3300);
616
617 FIXED_REG(10,   5v0,            5v0,            NULL,   0,      0,
618                 -1,     false,  true,   0,      5000);
619
620 FIXED_REG(11,   dcdc_1v8,       dcdc_1v8,       NULL,   0,      0,
621                 -1,     false,  true,   0,      1800);
622
623 FIXED_REG(12,    dcdc_1v2, dcdc_1v2,    NULL,   0,      0,
624                 PMU_TCA6416_GPIO_BASE,     false,  true,   0,      1200);
625
626 FIXED_REG(13,   as3722_gpio2,   as3722_gpio2,           NULL,   0,      0,
627                 AS3722_GPIO_BASE + AS3722_GPIO2,        false,  false,  0,      3300);
628
629 FIXED_REG(14,   lcd,            lcd,            NULL,   0,      0,
630                 AS3722_GPIO_BASE + AS3722_GPIO4,        false,  true,   0,      3300);
631
632 FIXED_REG(15,   sdmmc_en,               sdmmc_en,       NULL,   0,      0,
633                 TEGRA_GPIO_PR0,         false,  true,   0,      3300);
634
635 FIXED_REG(16,   vdd_cdc_1v2_aud,        vdd_cdc_1v2_aud,        NULL,   0,      0,
636                 PMU_TCA6416_GPIO(2),    false,  true,   0,      1200);
637
638 FIXED_REG(17,   vdd_amp_shut_aud,       vdd_amp_shut_aud,       NULL,   0,      0,
639                 PMU_TCA6416_GPIO(3),    false,  true,   0,      1200);
640 /*
641  * Creating the fixed regulator device tables
642  */
643
644 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
645
646 #define LAGUNA_COMMON_FIXED_REG                 \
647         ADD_FIXED_REG(battery),                 \
648         ADD_FIXED_REG(aon_1v8),                 \
649         ADD_FIXED_REG(aon_3v3),                 \
650         ADD_FIXED_REG(aon_1v2),                 \
651         ADD_FIXED_REG(vdd_hdmi_5v0),            \
652         ADD_FIXED_REG(vdd_hdmi),                \
653         ADD_FIXED_REG(usb1_vbus),               \
654         ADD_FIXED_REG(usb3_vbus),               \
655         ADD_FIXED_REG(lcd_bl_en),               \
656         ADD_FIXED_REG(3v3),                     \
657         ADD_FIXED_REG(5v0),                     \
658         ADD_FIXED_REG(dcdc_1v8),                \
659         ADD_FIXED_REG(as3722_gpio2),            \
660         ADD_FIXED_REG(lcd),                     \
661         ADD_FIXED_REG(sdmmc_en)
662
663 #define LAGUNA_PM358_FIXED_REG          \
664         ADD_FIXED_REG(dcdc_1v2),        \
665         ADD_FIXED_REG(vdd_cdc_1v2_aud), \
666         ADD_FIXED_REG(vdd_amp_shut_aud)
667
668 #define LAGUNA_PM359_FIXED_REG          \
669         ADD_FIXED_REG(dcdc_1v2),        \
670         ADD_FIXED_REG(vdd_cdc_1v2_aud)
671
672
673 /* Gpio switch regulator platform data for laguna pm358 ERS*/
674 static struct platform_device *fixed_reg_devs_pm358[] = {
675         LAGUNA_COMMON_FIXED_REG,
676         LAGUNA_PM358_FIXED_REG
677 };
678
679 /* Gpio switch regulator platform data for laguna pm359 ERS-S*/
680 static struct platform_device *fixed_reg_devs_pm359[] = {
681         LAGUNA_COMMON_FIXED_REG,
682         LAGUNA_PM359_FIXED_REG
683 };
684
685 /* Gpio switch regulator platform data for laguna pm363 FFD*/
686 static struct platform_device *fixed_reg_devs_pm363[] = {
687         LAGUNA_COMMON_FIXED_REG
688 };
689
690 static int __init laguna_fixed_regulator_init(void)
691 {
692         struct board_info board_info;
693
694         if (!of_machine_is_compatible("nvidia,ardbeg"))
695                 return 0;
696
697         tegra_get_board_info(&board_info);
698         if (board_info.board_id == BOARD_PM358)
699                 return platform_add_devices(fixed_reg_devs_pm358,
700                                 ARRAY_SIZE(fixed_reg_devs_pm358));
701         else if (board_info.board_id == BOARD_PM359)
702                 return platform_add_devices(fixed_reg_devs_pm359,
703                                 ARRAY_SIZE(fixed_reg_devs_pm359));
704         else if (board_info.board_id == BOARD_PM363)
705                 return platform_add_devices(fixed_reg_devs_pm363,
706                                 ARRAY_SIZE(fixed_reg_devs_pm363));
707
708         return 0;
709 }
710
711 subsys_initcall_sync(laguna_fixed_regulator_init);
712
713 int __init laguna_regulator_init(void)
714 {
715
716 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
717         laguna_cl_dvfs_init();
718 #endif
719         laguna_as3722_regulator_init();
720
721         return 0;
722 }
723
724 int __init laguna_suspend_init(void)
725 {
726         tegra_init_suspend(&laguna_suspend_data);
727         return 0;
728 }
729
730 int __init laguna_edp_init(void)
731 {
732 #ifdef CONFIG_TEGRA_EDP_LIMITS
733         unsigned int regulator_mA;
734
735         regulator_mA = get_maximum_cpu_current_supported();
736         if (!regulator_mA)
737                 regulator_mA = 15000;
738
739         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
740
741         tegra_init_cpu_edp_limits(regulator_mA);
742 #endif
743         return 0;
744 }
745
746
747 static struct soctherm_platform_data laguna_soctherm_data = {
748         .therm = {
749                 [THERM_CPU] = {
750                         .zone_enable = true,
751                         .passive_delay = 1000,
752                         .hotspot_offset = 6000,
753                         .num_trips = 3,
754                         .trips = {
755                                 {
756                                         .cdev_type = "tegra-balanced",
757                                         .trip_temp = 90000,
758                                         .trip_type = THERMAL_TRIP_PASSIVE,
759                                         .upper = THERMAL_NO_LIMIT,
760                                         .lower = THERMAL_NO_LIMIT,
761                                 },
762                                 {
763                                         .cdev_type = "tegra-heavy",
764                                         .trip_temp = 100000,
765                                         .trip_type = THERMAL_TRIP_HOT,
766                                         .upper = THERMAL_NO_LIMIT,
767                                         .lower = THERMAL_NO_LIMIT,
768                                 },
769                                 {
770                                         .cdev_type = "tegra-shutdown",
771                                         .trip_temp = 102000,
772                                         .trip_type = THERMAL_TRIP_CRITICAL,
773                                         .upper = THERMAL_NO_LIMIT,
774                                         .lower = THERMAL_NO_LIMIT,
775                                 },
776                         },
777                 },
778                 [THERM_GPU] = {
779                         .zone_enable = true,
780                         .passive_delay = 1000,
781                         .hotspot_offset = 6000,
782                         .num_trips = 3,
783                         .trips = {
784                                 {
785                                         .cdev_type = "tegra-balanced",
786                                         .trip_temp = 90000,
787                                         .trip_type = THERMAL_TRIP_PASSIVE,
788                                         .upper = THERMAL_NO_LIMIT,
789                                         .lower = THERMAL_NO_LIMIT,
790                                 },
791                                 {
792                                         .cdev_type = "tegra-heavy",
793                                         .trip_temp = 100000,
794                                         .trip_type = THERMAL_TRIP_HOT,
795                                         .upper = THERMAL_NO_LIMIT,
796                                         .lower = THERMAL_NO_LIMIT,
797                                 },
798                                 {
799                                         .cdev_type = "tegra-shutdown",
800                                         .trip_temp = 102000,
801                                         .trip_type = THERMAL_TRIP_CRITICAL,
802                                         .upper = THERMAL_NO_LIMIT,
803                                         .lower = THERMAL_NO_LIMIT,
804                                 },
805                         },
806                 },
807                 [THERM_PLL] = {
808                         .zone_enable = true,
809                 },
810         },
811         .throttle = {
812                 [THROTTLE_HEAVY] = {
813                         .devs = {
814                                 [THROTTLE_DEV_CPU] = {
815                                         .enable = 1,
816                                 },
817                         },
818                 },
819         },
820 };
821
822 int __init laguna_soctherm_init(void)
823 {
824         tegra_platform_edp_init(laguna_soctherm_data.therm[THERM_CPU].trips,
825                         &laguna_soctherm_data.therm[THERM_CPU].num_trips,
826                         8000); /* edp temperature margin */
827         tegra_add_tj_trips(laguna_soctherm_data.therm[THERM_CPU].trips,
828                         &laguna_soctherm_data.therm[THERM_CPU].num_trips);
829
830         return tegra11_soctherm_init(&laguna_soctherm_data);
831 }