ARM: tegra12: dvfs: Add core rail Vmax trip-points
[linux-3.10.git] / arch / arm / mach-tegra / board-laguna-power.c
1 /*
2  * arch/arm/mach-tegra/board-laguna-power.c
3  *
4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca954x.h>
22 #include <linux/i2c/pca953x.h>
23 #include <linux/pda_power.h>
24 #include <linux/platform_device.h>
25 #include <linux/resource.h>
26 #include <linux/io.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/driver.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/mfd/as3722-plat.h>
31 #include <linux/gpio.h>
32 #include <linux/regulator/userspace-consumer.h>
33 #include <linux/pid_thermal_gov.h>
34
35 #include <asm/mach-types.h>
36
37 #include <mach/irqs.h>
38 #include <mach/edp.h>
39 #include <mach/gpio-tegra.h>
40
41 #include "cpu-tegra.h"
42 #include "pm.h"
43 #include "tegra-board-id.h"
44 #include "board.h"
45 #include "gpio-names.h"
46 #include "board-common.h"
47 #include "board-pmu-defines.h"
48 #include "board-ardbeg.h"
49 #include "tegra_cl_dvfs.h"
50 #include "devices.h"
51 #include "tegra11_soctherm.h"
52 #include "iomap.h"
53
54 #define PMC_CTRL                0x0
55 #define PMC_CTRL_INTR_LOW       (1 << 17)
56 #define AS3722_SUPPLY(_name) "as3722_"#_name
57
58 static struct regulator_consumer_supply as3722_ldo0_supply[] = {
59         REGULATOR_SUPPLY("avdd_pll_m", NULL),
60         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
61         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
62         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
63         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
64         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
65         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
66         REGULATOR_SUPPLY("avdd_pll_x", NULL),
67         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
68 };
69
70 static struct regulator_consumer_supply as3722_ldo1_supply[] = {
71         REGULATOR_SUPPLY("vddio_cam", "vi"),
72         REGULATOR_SUPPLY("pwrdet_cam", NULL),
73         REGULATOR_SUPPLY("vdd_cam_1v8_cam", NULL),
74         REGULATOR_SUPPLY("vif", "2-0010"),
75         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
76 };
77
78 static struct regulator_consumer_supply as3722_ldo2_supply[] = {
79         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
80         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
81         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.0"),
82         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.1"),
83         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
84         REGULATOR_SUPPLY("avdd_hsic_com", NULL),
85         REGULATOR_SUPPLY("avdd_hsic_mdm", NULL),
86         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
87         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
88         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
89 };
90
91 static struct regulator_consumer_supply as3722_ldo3_supply[] = {
92         REGULATOR_SUPPLY("vdd_rtc", NULL),
93 };
94
95 static struct regulator_consumer_supply as3722_ldo4_supply[] = {
96         REGULATOR_SUPPLY("vdd_2v7_hv", NULL),
97         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
98         REGULATOR_SUPPLY("vana", "2-0010"),
99 };
100
101 static struct regulator_consumer_supply as3722_ldo5_supply[] = {
102         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
103         REGULATOR_SUPPLY("vdig", "2-0010"),
104 };
105
106 static struct regulator_consumer_supply as3722_ldo6_supply[] = {
107         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
108         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
109 };
110
111 static struct regulator_consumer_supply as3722_ldo7_supply[] = {
112         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
113 };
114
115 static struct regulator_consumer_supply as3722_ldo9_supply[] = {
116         REGULATOR_SUPPLY("avdd", "spi0.0"),
117 };
118
119 static struct regulator_consumer_supply as3722_ldo10_supply[] = {
120         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
121         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
122         REGULATOR_SUPPLY("imx135_reg1", NULL),
123         REGULATOR_SUPPLY("vdd", "2-000e"),
124 };
125
126 static struct regulator_consumer_supply as3722_ldo11_supply[] = {
127         REGULATOR_SUPPLY("vpp_fuse", NULL),
128 };
129
130 static struct regulator_consumer_supply as3722_sd0_supply[] = {
131         REGULATOR_SUPPLY("vdd_cpu", NULL),
132 };
133
134 static struct regulator_consumer_supply as3722_sd1_supply[] = {
135         REGULATOR_SUPPLY("vdd_core", NULL),
136 };
137
138 static struct regulator_consumer_supply as3722_sd2_supply[] = {
139         REGULATOR_SUPPLY("vddio_ddr", NULL),
140         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
141         REGULATOR_SUPPLY("vddio_ddr3", NULL),
142         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
143 };
144
145 static struct regulator_consumer_supply as3722_sd4_supply[] = {
146         REGULATOR_SUPPLY("avdd_pex_pll", NULL),
147         REGULATOR_SUPPLY("avddio_pex_pll", NULL),
148         REGULATOR_SUPPLY("dvddio_pex", NULL),
149         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
150         REGULATOR_SUPPLY("avdd_sata", NULL),
151         REGULATOR_SUPPLY("vdd_sata", NULL),
152         REGULATOR_SUPPLY("avdd_sata_pll", NULL),
153         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
154         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
155 };
156
157 static struct regulator_consumer_supply as3722_sd5_supply[] = {
158         REGULATOR_SUPPLY("vddio_sys", NULL),
159         REGULATOR_SUPPLY("vddio_sys_2", NULL),
160         REGULATOR_SUPPLY("vddio_audio", NULL),
161         REGULATOR_SUPPLY("pwrdet_audio", NULL),
162         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
163         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
164         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
165         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
166         REGULATOR_SUPPLY("vddio_uart", NULL),
167         REGULATOR_SUPPLY("pwrdet_uart", NULL),
168         REGULATOR_SUPPLY("vddio_bb", NULL),
169         REGULATOR_SUPPLY("pwrdet_bb", NULL),
170         REGULATOR_SUPPLY("vddio_gmi", NULL),
171         REGULATOR_SUPPLY("pwrdet_nand", NULL),
172         REGULATOR_SUPPLY("avdd_osc", NULL),
173         /* emmc 1.8v misssing
174         keyboard & touchpad 1.8v missing */
175 };
176
177 static struct regulator_consumer_supply as3722_sd6_supply[] = {
178         REGULATOR_SUPPLY("vdd_gpu", NULL),
179 };
180
181 AMS_PDATA_INIT(sd0, NULL, 700000, 1400000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE2);
182 AMS_PDATA_INIT(sd1, NULL, 700000, 1350000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
183 AMS_PDATA_INIT(sd2, NULL, 1350000, 1350000, 1, 1, 1, 0);
184 AMS_PDATA_INIT(sd4, NULL, 1050000, 1050000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
185 AMS_PDATA_INIT(sd5, NULL, 1800000, 1800000, 1, 1, 1, 0);
186 AMS_PDATA_INIT(sd6, NULL, 650000, 1200000, 0, 1, 1, 0);
187 AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
188 AMS_PDATA_INIT(ldo1, NULL, 1800000, 1800000, 0, 1, 1, 0);
189 AMS_PDATA_INIT(ldo2, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 1, 1, 0);
190 AMS_PDATA_INIT(ldo3, NULL, 800000, 800000, 1, 1, 1, 0);
191 AMS_PDATA_INIT(ldo4, NULL, 2700000, 2700000, 0, 0, 1, 0);
192 AMS_PDATA_INIT(ldo5, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
193 AMS_PDATA_INIT(ldo6, NULL, 1800000, 3300000, 0, 0, 1, 0);
194 AMS_PDATA_INIT(ldo7, AS3722_SUPPLY(sd5), 1050000, 1050000, 0, 0, 1, 0);
195 AMS_PDATA_INIT(ldo9, NULL, 3300000, 3300000, 0, 1, 1, 0);
196 AMS_PDATA_INIT(ldo10, NULL, 2700000, 2700000, 0, 0, 1, 0);
197 AMS_PDATA_INIT(ldo11, NULL, 1800000, 1800000, 0, 0, 1, 0);
198
199 static struct as3722_pinctrl_platform_data as3722_pctrl_pdata[] = {
200         AS3722_PIN_CONTROL("gpio0", "gpio", NULL, NULL, NULL, "output-low"),
201         AS3722_PIN_CONTROL("gpio1", "gpio", NULL, NULL, NULL, "output-high"),
202         AS3722_PIN_CONTROL("gpio2", "gpio", NULL, NULL, NULL, "output-high"),
203         AS3722_PIN_CONTROL("gpio3", "gpio", NULL, NULL, "enabled", NULL),
204         AS3722_PIN_CONTROL("gpio4", "gpio", NULL, NULL, NULL, "output-high"),
205         AS3722_PIN_CONTROL("gpio5", "gpio", "pull-down", NULL, "enabled", NULL),
206         AS3722_PIN_CONTROL("gpio6", "gpio", NULL, NULL, "enabled", NULL),
207         AS3722_PIN_CONTROL("gpio7", "gpio", NULL, NULL, NULL, "output-high"),
208 };
209
210 static struct as3722_adc_extcon_platform_data as3722_adc_extcon_pdata = {
211         .connection_name = "as3722-extcon",
212         .enable_adc1_continuous_mode = true,
213         .enable_low_voltage_range = true,
214         .adc_channel = 12,
215         .hi_threshold =  0x100,
216         .low_threshold = 0x80,
217 };
218
219 static struct as3722_platform_data as3722_pdata = {
220         .reg_pdata[AS3722_LDO0] = &as3722_ldo0_reg_pdata,
221         .reg_pdata[AS3722_LDO1] = &as3722_ldo1_reg_pdata,
222         .reg_pdata[AS3722_LDO2] = &as3722_ldo2_reg_pdata,
223         .reg_pdata[AS3722_LDO3] = &as3722_ldo3_reg_pdata,
224         .reg_pdata[AS3722_LDO4] = &as3722_ldo4_reg_pdata,
225         .reg_pdata[AS3722_LDO5] = &as3722_ldo5_reg_pdata,
226         .reg_pdata[AS3722_LDO6] = &as3722_ldo6_reg_pdata,
227         .reg_pdata[AS3722_LDO7] = &as3722_ldo7_reg_pdata,
228         .reg_pdata[AS3722_LDO9] = &as3722_ldo9_reg_pdata,
229         .reg_pdata[AS3722_LDO10] = &as3722_ldo10_reg_pdata,
230         .reg_pdata[AS3722_LDO11] = &as3722_ldo11_reg_pdata,
231
232         .reg_pdata[AS3722_SD0] = &as3722_sd0_reg_pdata,
233         .reg_pdata[AS3722_SD1] = &as3722_sd1_reg_pdata,
234         .reg_pdata[AS3722_SD2] = &as3722_sd2_reg_pdata,
235         .reg_pdata[AS3722_SD4] = &as3722_sd4_reg_pdata,
236         .reg_pdata[AS3722_SD5] = &as3722_sd5_reg_pdata,
237         .reg_pdata[AS3722_SD6] = &as3722_sd6_reg_pdata,
238
239         .gpio_base = AS3722_GPIO_BASE,
240         .irq_base = AS3722_IRQ_BASE,
241         .use_internal_int_pullup = 0,
242         .use_internal_i2c_pullup = 0,
243         .pinctrl_pdata = as3722_pctrl_pdata,
244         .num_pinctrl = ARRAY_SIZE(as3722_pctrl_pdata),
245         .enable_clk32k_out = true,
246         .use_power_off = true,
247         .extcon_pdata = &as3722_adc_extcon_pdata,
248 };
249
250 static struct pca953x_platform_data tca6416_pdata = {
251         .gpio_base = PMU_TCA6416_GPIO_BASE,
252 };
253
254 static const struct i2c_board_info tca6416_expander[] = {
255         {
256                 I2C_BOARD_INFO("tca6416", 0x20),
257                 .platform_data = &tca6416_pdata,
258         },
259 };
260
261 static const struct i2c_board_info tca6408_expander[] = {
262         {
263                 I2C_BOARD_INFO("tca6408", 0x20),
264                 .platform_data = &tca6416_pdata,
265         },
266 };
267
268 static struct i2c_board_info __initdata as3722_regulators[] = {
269         {
270                 I2C_BOARD_INFO("as3722", 0x40),
271                 .flags = I2C_CLIENT_WAKE,
272                 .irq = INT_EXTERNAL_PMU,
273                 .platform_data = &as3722_pdata,
274         },
275 };
276
277 int __init laguna_as3722_regulator_init(void)
278 {
279         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
280         u32 pmc_ctrl;
281         struct board_info board_info;
282
283         tegra_get_board_info(&board_info);
284
285         /* AS3722: Normal state of INT request line is LOW.
286          * configure the power management controller to trigger PMU
287          * interrupts when HIGH.
288          */
289         pmc_ctrl = readl(pmc + PMC_CTRL);
290         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
291         regulator_has_full_constraints();
292         /* Set vdd_gpu init uV to 1V */
293         as3722_sd6_reg_idata.constraints.init_uV = 1000000;
294
295         /* Set overcurrent of rails. */
296         as3722_sd6_reg_idata.constraints.min_uA = 3500000;
297         as3722_sd6_reg_idata.constraints.max_uA = 3500000;
298
299         as3722_sd0_reg_idata.constraints.min_uA = 3500000;
300         as3722_sd0_reg_idata.constraints.max_uA = 3500000;
301
302         as3722_sd1_reg_idata.constraints.min_uA = 2500000;
303         as3722_sd1_reg_idata.constraints.max_uA = 2500000;
304
305         as3722_ldo3_reg_pdata.enable_tracking = true;
306         as3722_ldo3_reg_pdata.disable_tracking_suspend = true;
307
308         printk(KERN_INFO "%s: i2c_register_board_info\n",
309                         __func__);
310         if (board_info.board_id == BOARD_PM358) {
311                 switch (board_info.fab) {
312                 case BOARD_FAB_A01:
313                         as3722_pdata.reg_pdata[AS3722_LDO5] =
314                                 &as3722_ldo7_reg_pdata;
315                         as3722_pdata.reg_pdata[AS3722_LDO7] =
316                                 &as3722_ldo5_reg_pdata;
317                         as3722_pdata.reg_pdata[AS3722_LDO4] =
318                                 &as3722_ldo10_reg_pdata;
319                         as3722_pdata.reg_pdata[AS3722_LDO10] =
320                                 &as3722_ldo4_reg_pdata;
321                         break;
322                 default:
323                         break;
324                 }
325         }
326         i2c_register_board_info(4, as3722_regulators,
327                         ARRAY_SIZE(as3722_regulators));
328         if (board_info.board_id == BOARD_PM358 &&
329                         board_info.fab == BOARD_FAB_A00)
330                 i2c_register_board_info(0, tca6408_expander,
331                                 ARRAY_SIZE(tca6408_expander));
332         else if (board_info.board_id == BOARD_PM359 ||
333                         board_info.board_id == BOARD_PM358)
334                 i2c_register_board_info(0, tca6416_expander,
335                                 ARRAY_SIZE(tca6416_expander));
336         return 0;
337 }
338
339 static struct tegra_suspend_platform_data laguna_suspend_data = {
340         .cpu_timer      = 2000,
341         .cpu_off_timer  = 2000,
342         .suspend_mode   = TEGRA_SUSPEND_LP0,
343         .core_timer     = 0x7e7e,
344         .core_off_timer = 2000,
345         .corereq_high   = true,
346         .sysclkreq_high = true,
347         .cpu_lp2_min_residency = 1000,
348 };
349
350 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
351 /* board parameters for cpu dfll */
352 static struct tegra_cl_dvfs_cfg_param laguna_cl_dvfs_param = {
353         .sample_rate = 12500,
354
355         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
356         .cf = 10,
357         .ci = 0,
358         .cg = 2,
359
360         .droop_cut_value = 0xF,
361         .droop_restore_ramp = 0x0,
362         .scale_out_ramp = 0x0,
363 };
364 #endif
365
366 /* Laguna: fixed 10mV steps from 700mV to 1400mV */
367 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 700000) / 10000 + 1)
368 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
369 static inline void fill_reg_map(void)
370 {
371         int i;
372         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
373                 pmu_cpu_vdd_map[i].reg_value = i + 0xa;
374                 pmu_cpu_vdd_map[i].reg_uV = 700000 + 10000 * i;
375         }
376 }
377
378 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
379 static struct tegra_cl_dvfs_platform_data laguna_cl_dvfs_data = {
380         .dfll_clk_name = "dfll_cpu",
381         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
382         .u.pmu_i2c = {
383                 .fs_rate = 400000,
384                 .slave_addr = 0x80,
385                 .reg = 0x00,
386         },
387         .vdd_map = pmu_cpu_vdd_map,
388         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
389
390         .cfg_param = &laguna_cl_dvfs_param,
391 };
392
393 static int __init laguna_cl_dvfs_init(void)
394 {
395         fill_reg_map();
396         laguna_cl_dvfs_data.flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
397         tegra_cl_dvfs_device.dev.platform_data = &laguna_cl_dvfs_data;
398         platform_device_register(&tegra_cl_dvfs_device);
399
400         return 0;
401 }
402 #endif
403
404 /* Always ON /Battery regulator */
405 static struct regulator_consumer_supply fixed_reg_battery_supply[] = {
406         REGULATOR_SUPPLY("vdd_sys_bl", NULL),
407         REGULATOR_SUPPLY("vddio_pex_sata", "tegra-sata.0"),
408 };
409
410 /* Always ON 1.8v */
411 static struct regulator_consumer_supply fixed_reg_aon_1v8_supply[] = {
412         REGULATOR_SUPPLY("vdd_1v8_emmc", NULL),
413         REGULATOR_SUPPLY("vdd_1v8b_com_f", NULL),
414         REGULATOR_SUPPLY("vdd_1v8b_gps_f", NULL),
415 };
416
417 /* Always ON 3.3v */
418 static struct regulator_consumer_supply fixed_reg_aon_3v3_supply[] = {
419         REGULATOR_SUPPLY("vdd_3v3_emmc", NULL),
420         REGULATOR_SUPPLY("vdd_com_3v3", NULL),
421 };
422
423 /* Always ON 1v2 */
424 static struct regulator_consumer_supply fixed_reg_aon_1v2_supply[] = {
425         REGULATOR_SUPPLY("vdd_1v2_bb_hsic", NULL),
426 };
427
428 /* EN_USB0_VBUS From TEGRA GPIO PN4 */
429 static struct regulator_consumer_supply fixed_reg_usb0_vbus_pm358_supply[] = {
430         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
431         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
432         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
433 };
434
435 /* EN_USB1_USB2_VBUS From TEGRA GPIO PN5 */
436 static struct regulator_consumer_supply fixed_reg_usb1_usb2_vbus_pm358_supply[] = {
437         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
438         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
439         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
440         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
441 };
442
443 /* EN_USB0_VBUS From TEGRA GPIO PN4 */
444 static struct regulator_consumer_supply fixed_reg_usb0_usb1_vbus_pm359_supply[] = {
445         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
446         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
447         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
448         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
449         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
450 };
451
452 /* EN_USB1_USB2_VBUS From TEGRA GPIO PN5 */
453 static struct regulator_consumer_supply fixed_reg_usb2_vbus_pm359_supply[] = {
454         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
455         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
456 };
457
458 /* EN_USB0_VBUS From TEGRA GPIO PN4 */
459 static struct regulator_consumer_supply fixed_reg_usb2_vbus_pm363_supply[] = {
460         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
461         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
462 };
463
464 /* EN_USB1_USB2_VBUS From TEGRA GPIO PN5 */
465 static struct regulator_consumer_supply fixed_reg_usb0_usb1_vbus_pm363_supply[] = {
466         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
467         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
468         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
469         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
470         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
471 };
472
473 /* Gated by GPIO_PK6  in FAB B and further*/
474 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
475         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
476 };
477
478 /* Gated by GPIO_PH7  in FAB B and further*/
479 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_supply[] = {
480         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
481 };
482
483 /* VDD_LCD_BL DAP3_DOUT */
484 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_supply[] = {
485         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
486 };
487
488 /* LCD_BL_EN GMI_AD10 */
489 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
490         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
491 };
492
493 /* AS3722 GPIO1*/
494 static struct regulator_consumer_supply fixed_reg_3v3_supply[] = {
495         REGULATOR_SUPPLY("hvdd_pex", NULL),
496         REGULATOR_SUPPLY("hvdd_pex_pll", NULL),
497         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
498         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5645.0"),
499         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5639.0"),
500         REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
501         REGULATOR_SUPPLY("vdd_nfc_3v3", NULL),
502         REGULATOR_SUPPLY("vdd_3v3_sensor", NULL),
503         REGULATOR_SUPPLY("vdd_kp_3v3", NULL),
504         REGULATOR_SUPPLY("vdd_tp_3v3", NULL),
505         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
506         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
507         REGULATOR_SUPPLY("vdd", "1-004c"),
508         REGULATOR_SUPPLY("vdd", "0-0048"),
509         REGULATOR_SUPPLY("vdd", "0-0069"),
510         REGULATOR_SUPPLY("vdd", "0-000c"),
511         REGULATOR_SUPPLY("vdd", "0-0077"),
512         REGULATOR_SUPPLY("vin", "2-0030"),
513 };
514
515 /* AS3722 GPIO1*/
516 static struct regulator_consumer_supply fixed_reg_5v0_supply[] = {
517         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
518         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
519         REGULATOR_SUPPLY("vdd_5v0_sensor", NULL),
520 };
521
522 static struct regulator_consumer_supply fixed_reg_dcdc_1v8_supply[] = {
523         REGULATOR_SUPPLY("avdd_lvds0_pll", NULL),
524         REGULATOR_SUPPLY("dvdd_lcd", NULL),
525         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
526         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645.0"),
527         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645.0"),
528         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639.0"),
529         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639.0"),
530         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639.0"),
531         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645.0"),
532         REGULATOR_SUPPLY("vdd_1v8b_nfc", NULL),
533         REGULATOR_SUPPLY("vdd_1v8_sensor", NULL),
534         REGULATOR_SUPPLY("vdd_1v8_sdmmc", NULL),
535         REGULATOR_SUPPLY("vdd_kp_1v8", NULL),
536         REGULATOR_SUPPLY("vdd_tp_1v8", NULL),
537         REGULATOR_SUPPLY("vdd_modem_1v8", NULL),
538         REGULATOR_SUPPLY("vdd_1v8b", "0-0048"),
539         REGULATOR_SUPPLY("dvdd", "spi0.0"),
540         REGULATOR_SUPPLY("vlogic", "0-0069"),
541         REGULATOR_SUPPLY("vid", "0-000c"),
542         REGULATOR_SUPPLY("vddio", "0-0077"),
543         REGULATOR_SUPPLY("vi2c", "2-0030"),
544         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
545         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
546         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
547         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
548         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
549 };
550
551 /* gated by TCA6416 GPIO EXP GPIO0 */
552 static struct regulator_consumer_supply fixed_reg_dcdc_1v2_supply[] = {
553         REGULATOR_SUPPLY("vdd_1v2_en", NULL),
554 };
555
556 /* AMS GPIO2 */
557 static struct regulator_consumer_supply fixed_reg_as3722_gpio2_supply[] = {
558         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
559         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
560         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
561         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
562         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
563         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
564         REGULATOR_SUPPLY("pwrdet_hv", NULL),
565         REGULATOR_SUPPLY("hvdd_sata", NULL),
566 };
567
568 /* gated by AS3722 GPIO4 */
569 static struct regulator_consumer_supply fixed_reg_lcd_supply[] = {
570         REGULATOR_SUPPLY("avdd_lcd", NULL),
571 };
572
573 /* gated by GPIO_PR0 */
574 static struct regulator_consumer_supply fixed_reg_sdmmc_en_supply[] = {
575         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.1"),
576         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
577 };
578
579 /* only adding for PM358 */
580 static struct regulator_consumer_supply fixed_reg_vdd_cdc_1v2_aud_supply[] = {
581         REGULATOR_SUPPLY("ldoen", "tegra-snd-rt5639.0"),
582 };
583
584 static struct regulator_consumer_supply fixed_reg_vdd_amp_shut_aud_supply[] = {
585         REGULATOR_SUPPLY("epamp", "tegra-snd-rt5645.0"),
586 };
587
588 static struct regulator_consumer_supply fixed_reg_vdd_dsi_mux_supply[] = {
589         REGULATOR_SUPPLY("vdd_3v3_dsi", "NULL"),
590 };
591
592 /* Macro for defining fixed regulator sub device data */
593 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
594 #define FIXED_REG(_id, _var, _name, _in_supply,                 \
595         _always_on, _boot_on, _gpio_nr, _open_drain,            \
596         _active_high, _boot_state, _millivolts, _sdelay)        \
597 static struct regulator_init_data ri_data_##_var =              \
598 {                                                               \
599         .supply_regulator = _in_supply,                         \
600         .num_consumer_supplies =                                \
601         ARRAY_SIZE(fixed_reg_##_name##_supply),                 \
602         .consumer_supplies = fixed_reg_##_name##_supply,        \
603         .constraints = {                                        \
604                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
605                                 REGULATOR_MODE_STANDBY),        \
606                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
607                                 REGULATOR_CHANGE_STATUS |       \
608                                 REGULATOR_CHANGE_VOLTAGE),      \
609                 .always_on = _always_on,                        \
610                 .boot_on = _boot_on,                            \
611         },                                                      \
612 };                                                              \
613 static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
614 {                                                               \
615         .supply_name = FIXED_SUPPLY(_name),                     \
616         .microvolts = _millivolts * 1000,                       \
617         .gpio = _gpio_nr,                                       \
618         .gpio_is_open_drain = _open_drain,                      \
619         .enable_high = _active_high,                            \
620         .enabled_at_boot = _boot_state,                         \
621         .init_data = &ri_data_##_var,                           \
622         .startup_delay = _sdelay,                               \
623 };                                                              \
624 static struct platform_device fixed_reg_##_var##_dev = {        \
625         .name = "reg-fixed-voltage",                            \
626         .id = _id,                                              \
627         .dev = {                                                \
628                 .platform_data = &fixed_reg_##_var##_pdata,     \
629         },                                                      \
630 }
631
632 FIXED_REG(0,    battery,        battery,        NULL,   0,      0,
633                 -1,     false, true,    0,      8400,   0);
634
635 FIXED_REG(1,    aon_1v8,        aon_1v8,        NULL,   0,      0,
636                 -1,     false, true,    0,      1800,   0);
637
638 FIXED_REG(2,    aon_3v3,        aon_3v3,        NULL,   0,      0,
639                 -1,     false, true,    0,      3300,   0);
640
641 FIXED_REG(3,    aon_1v2,        aon_1v2,        NULL,   0,      0,
642                 -1,     false, true,    0,      1200,   0);
643
644 FIXED_REG(4,    vdd_hdmi_5v0,   vdd_hdmi_5v0,   NULL,   0,      0,
645                 TEGRA_GPIO_PK6, false,  true,   0,      5000,   5000);
646
647 FIXED_REG(5,    vdd_hdmi,       vdd_hdmi,       AS3722_SUPPLY(sd4),
648                 0,      0,
649                 TEGRA_GPIO_PH7, false,  false,  0,      3300,   0);
650
651 FIXED_REG(6,    usb0_vbus_pm358,        usb0_vbus_pm358,        NULL,
652                 0,      0,
653                 TEGRA_GPIO_PN4, true,   true,   0,      5000,   0);
654
655 FIXED_REG(7,    usb1_usb2_vbus_pm358,   usb1_usb2_vbus_pm358,   NULL,
656                 0,      0,
657                 TEGRA_GPIO_PN5, true,   true,   0,      5000, 0);
658
659 FIXED_REG(8,    usb0_usb1_vbus_pm359,   usb0_usb1_vbus_pm359,   NULL,
660                 0,      0,
661                 TEGRA_GPIO_PN4, true,   true,   0,      5000,   0);
662
663 FIXED_REG(9,    usb2_vbus_pm359,        usb2_vbus_pm359,        NULL,
664                 0,      0,
665                 TEGRA_GPIO_PN5, true,   true,   0,      5000, 0);
666
667 FIXED_REG(10,   usb2_vbus_pm363,        usb2_vbus_pm363,        NULL,
668                 0,      0,
669                 TEGRA_GPIO_PN4, true,   true,   0,      5000,   0);
670
671 FIXED_REG(11,   usb0_usb1_vbus_pm363,   usb0_usb1_vbus_pm363,   NULL,
672                 0,      0,
673                 TEGRA_GPIO_PN5, true,   true,   0,      5000, 0);
674
675 FIXED_REG(12,   vdd_lcd_bl,     vdd_lcd_bl,     NULL,   0,      0,
676                 TEGRA_GPIO_PP2, false,  true,   0,      3300, 0);
677
678 FIXED_REG(13,   lcd_bl_en,      lcd_bl_en,      NULL,   0,      0,
679                 TEGRA_GPIO_PH2, false,  true,   0,      5000,   0);
680
681 FIXED_REG(14,   3v3,            3v3,            NULL,   0,      0,
682                 -1,     false,  true,   0,      3300,   0);
683
684 FIXED_REG(15,   5v0,            5v0,            NULL,   0,      0,
685                 -1,     false,  true,   0,      5000,   0);
686
687 FIXED_REG(16,   dcdc_1v8,       dcdc_1v8,       NULL,   0,      0,
688                 -1,     false,  true,   0,      1800,   0);
689
690 FIXED_REG(17,    dcdc_1v2, dcdc_1v2,    NULL,   0,      0,
691                 PMU_TCA6416_GPIO_BASE,     false,  true,   0,      1200,
692                 0);
693
694 FIXED_REG(18,   as3722_gpio2,   as3722_gpio2,           NULL,   0,      true,
695                 AS3722_GPIO_BASE + AS3722_GPIO2,        false,  true,   true,
696                 3300,   0);
697
698 FIXED_REG(19,   lcd,            lcd,            NULL,   0,      0,
699                 AS3722_GPIO_BASE + AS3722_GPIO4,        false,  true,   0,
700                 3300,   0);
701
702 FIXED_REG(20,   sdmmc_en,               sdmmc_en,       NULL,   0,      0,
703                 TEGRA_GPIO_PR0,         false,  true,   0,      3300,   0);
704
705 FIXED_REG(21,   vdd_cdc_1v2_aud,        vdd_cdc_1v2_aud,        NULL,   0,
706                 0,      PMU_TCA6416_GPIO(2),    false,  true,   0,
707                 1200,   250000);
708
709 FIXED_REG(22,   vdd_amp_shut_aud,       vdd_amp_shut_aud,       NULL,   0,
710                 0,      PMU_TCA6416_GPIO(3),    false,  true,   0,
711                 1200,   0);
712
713 FIXED_REG(23,   vdd_dsi_mux,            vdd_dsi_mux,    NULL,   0,      0,
714                 PMU_TCA6416_GPIO(13),   false,  true,   0,      3300,   0);
715 /*
716  * Creating the fixed regulator device tables
717  */
718
719 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
720
721 #define LAGUNA_COMMON_FIXED_REG                 \
722         ADD_FIXED_REG(battery),                 \
723         ADD_FIXED_REG(aon_1v8),                 \
724         ADD_FIXED_REG(aon_3v3),                 \
725         ADD_FIXED_REG(aon_1v2),                 \
726         ADD_FIXED_REG(vdd_hdmi_5v0),            \
727         ADD_FIXED_REG(vdd_hdmi),                \
728         ADD_FIXED_REG(vdd_lcd_bl),              \
729         ADD_FIXED_REG(lcd_bl_en),               \
730         ADD_FIXED_REG(3v3),                     \
731         ADD_FIXED_REG(5v0),                     \
732         ADD_FIXED_REG(dcdc_1v8),                \
733         ADD_FIXED_REG(as3722_gpio2),            \
734         ADD_FIXED_REG(lcd),                     \
735         ADD_FIXED_REG(sdmmc_en)
736
737 #define LAGUNA_PM358_FIXED_REG                  \
738         ADD_FIXED_REG(usb0_vbus_pm358),         \
739         ADD_FIXED_REG(usb1_usb2_vbus_pm358),    \
740         ADD_FIXED_REG(dcdc_1v2),                \
741         ADD_FIXED_REG(vdd_cdc_1v2_aud),         \
742         ADD_FIXED_REG(vdd_amp_shut_aud),         \
743         ADD_FIXED_REG(vdd_dsi_mux)
744
745 #define LAGUNA_PM359_FIXED_REG                  \
746         ADD_FIXED_REG(usb0_usb1_vbus_pm359),    \
747         ADD_FIXED_REG(usb2_vbus_pm359),         \
748         ADD_FIXED_REG(dcdc_1v2),                \
749         ADD_FIXED_REG(vdd_cdc_1v2_aud)
750
751 #define LAGUNA_PM363_FIXED_REG                  \
752         ADD_FIXED_REG(usb2_vbus_pm363),         \
753         ADD_FIXED_REG(usb0_usb1_vbus_pm363),
754
755 /* Gpio switch regulator platform data for laguna pm358 ERS*/
756 static struct platform_device *fixed_reg_devs_pm358[] = {
757         LAGUNA_COMMON_FIXED_REG,
758         LAGUNA_PM358_FIXED_REG
759 };
760
761 /* Gpio switch regulator platform data for laguna pm359 ERS-S*/
762 static struct platform_device *fixed_reg_devs_pm359[] = {
763         LAGUNA_COMMON_FIXED_REG,
764         LAGUNA_PM359_FIXED_REG
765 };
766
767 /* Gpio switch regulator platform data for laguna pm363 FFD*/
768 static struct platform_device *fixed_reg_devs_pm363[] = {
769         LAGUNA_COMMON_FIXED_REG,
770         LAGUNA_PM363_FIXED_REG
771 };
772
773 static int __init laguna_fixed_regulator_init(void)
774 {
775         struct board_info board_info;
776
777         if (!of_machine_is_compatible("nvidia,laguna"))
778                 return 0;
779
780         tegra_get_board_info(&board_info);
781         if (board_info.board_id == BOARD_PM358)
782                 return platform_add_devices(fixed_reg_devs_pm358,
783                                 ARRAY_SIZE(fixed_reg_devs_pm358));
784         else if (board_info.board_id == BOARD_PM359)
785                 return platform_add_devices(fixed_reg_devs_pm359,
786                                 ARRAY_SIZE(fixed_reg_devs_pm359));
787         else if (board_info.board_id == BOARD_PM363)
788                 return platform_add_devices(fixed_reg_devs_pm363,
789                                 ARRAY_SIZE(fixed_reg_devs_pm363));
790
791         return 0;
792 }
793
794 subsys_initcall_sync(laguna_fixed_regulator_init);
795
796 int __init laguna_regulator_init(void)
797 {
798
799 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
800         laguna_cl_dvfs_init();
801 #endif
802         laguna_as3722_regulator_init();
803
804         return 0;
805 }
806
807 int __init laguna_suspend_init(void)
808 {
809         tegra_init_suspend(&laguna_suspend_data);
810         return 0;
811 }
812
813 int __init laguna_edp_init(void)
814 {
815         unsigned int regulator_mA;
816
817         regulator_mA = get_maximum_cpu_current_supported();
818         if (!regulator_mA)
819                 regulator_mA = 15000;
820
821         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
822
823         tegra_init_cpu_edp_limits(regulator_mA);
824
825         /* gpu maximum current */
826         regulator_mA = 8000;
827         pr_info("%s: GPU regulator %d mA\n", __func__, regulator_mA);
828
829         tegra_init_gpu_edp_limits(regulator_mA);
830         return 0;
831 }
832
833 static struct pid_thermal_gov_params soctherm_pid_params = {
834         .max_err_temp = 9000,
835         .max_err_gain = 1000,
836
837         .gain_p = 1000,
838         .gain_d = 0,
839
840         .up_compensation = 20,
841         .down_compensation = 20,
842 };
843
844 static struct thermal_zone_params soctherm_tzp = {
845         .governor_name = "pid_thermal_gov",
846         .governor_params = &soctherm_pid_params,
847 };
848
849 static struct soctherm_platform_data laguna_soctherm_data = {
850         .therm = {
851                 [THERM_CPU] = {
852                         .zone_enable = true,
853                         .passive_delay = 1000,
854                         .hotspot_offset = 6000,
855                         .num_trips = 3,
856                         .trips = {
857                                 {
858                                         .cdev_type = "tegra-shutdown",
859                                         .trip_temp = 103000,
860                                         .trip_type = THERMAL_TRIP_CRITICAL,
861                                         .upper = THERMAL_NO_LIMIT,
862                                         .lower = THERMAL_NO_LIMIT,
863                                 },
864                                 {
865                                         .cdev_type = "tegra-heavy",
866                                         .trip_temp = 101000,
867                                         .trip_type = THERMAL_TRIP_HOT,
868                                         .upper = THERMAL_NO_LIMIT,
869                                         .lower = THERMAL_NO_LIMIT,
870                                 },
871                                 {
872                                         .cdev_type = "tegra-balanced",
873                                         .trip_temp = 91000,
874                                         .trip_type = THERMAL_TRIP_PASSIVE,
875                                         .upper = THERMAL_NO_LIMIT,
876                                         .lower = THERMAL_NO_LIMIT,
877                                 },
878                         },
879                         .tzp = &soctherm_tzp,
880                 },
881                 [THERM_GPU] = {
882                         .zone_enable = true,
883                         .passive_delay = 1000,
884                         .hotspot_offset = 6000,
885                         .num_trips = 3,
886                         .trips = {
887                                 {
888                                         .cdev_type = "tegra-shutdown",
889                                         .trip_temp = 104000,
890                                         .trip_type = THERMAL_TRIP_CRITICAL,
891                                         .upper = THERMAL_NO_LIMIT,
892                                         .lower = THERMAL_NO_LIMIT,
893                                 },
894                                 {
895                                         .cdev_type = "tegra-balanced",
896                                         .trip_temp = 92000,
897                                         .trip_type = THERMAL_TRIP_PASSIVE,
898                                         .upper = THERMAL_NO_LIMIT,
899                                         .lower = THERMAL_NO_LIMIT,
900                                 },
901 /*
902                                 {
903                                         .cdev_type = "gk20a_cdev",
904                                         .trip_temp = 102000,
905                                         .trip_type = THERMAL_TRIP_PASSIVE,
906                                         .upper = THERMAL_NO_LIMIT,
907                                         .lower = THERMAL_NO_LIMIT,
908                                 },
909                                 {
910                                         .cdev_type = "tegra-heavy",
911                                         .trip_temp = 102000,
912                                         .trip_type = THERMAL_TRIP_HOT,
913                                         .upper = THERMAL_NO_LIMIT,
914                                         .lower = THERMAL_NO_LIMIT,
915                                 },
916 */
917                         },
918                         .tzp = &soctherm_tzp,
919                 },
920                 [THERM_MEM] = {
921                         .zone_enable = true,
922                         .num_trips = 1,
923                         .trips = {
924                                 {
925                                         .cdev_type = "tegra-shutdown",
926                                         .trip_temp = 104000, /* = GPU shut */
927                                         .trip_type = THERMAL_TRIP_CRITICAL,
928                                         .upper = THERMAL_NO_LIMIT,
929                                         .lower = THERMAL_NO_LIMIT,
930                                 },
931                         },
932                 },
933                 [THERM_PLL] = {
934                         .zone_enable = true,
935                         .tzp = &soctherm_tzp,
936                 },
937         },
938         .throttle = {
939                 [THROTTLE_HEAVY] = {
940                         .priority = 100,
941                         .devs = {
942                                 [THROTTLE_DEV_CPU] = {
943                                         .enable = true,
944                                         .depth = 80,
945                                 },
946                                 [THROTTLE_DEV_GPU] = {
947                                         .enable = false,
948                                         .throttling_depth = "heavy_throttling",
949                                 },
950                         },
951                 },
952         },
953 };
954
955 int __init laguna_soctherm_init(void)
956 {
957         tegra_platform_edp_init(laguna_soctherm_data.therm[THERM_CPU].trips,
958                         &laguna_soctherm_data.therm[THERM_CPU].num_trips,
959                         7000); /* edp temperature margin */
960         tegra_platform_gpu_edp_init(
961                         laguna_soctherm_data.therm[THERM_GPU].trips,
962                         &laguna_soctherm_data.therm[THERM_GPU].num_trips,
963                         7000);
964         tegra_add_tj_trips(laguna_soctherm_data.therm[THERM_CPU].trips,
965                         &laguna_soctherm_data.therm[THERM_CPU].num_trips);
966         tegra_add_tgpu_trips(laguna_soctherm_data.therm[THERM_GPU].trips,
967                         &laguna_soctherm_data.therm[THERM_GPU].num_trips);
968         tegra_add_vc_trips(laguna_soctherm_data.therm[THERM_CPU].trips,
969                         &laguna_soctherm_data.therm[THERM_CPU].num_trips);
970         tegra_add_tpll_trips(laguna_soctherm_data.therm[THERM_PLL].trips,
971                         &laguna_soctherm_data.therm[THERM_PLL].num_trips);
972
973         return tegra11_soctherm_init(&laguna_soctherm_data);
974 }