ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-laguna-power.c
1 /*
2  * arch/arm/mach-tegra/board-laguna-power.c
3  *
4  * Copyright (c) 2013-2014 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca954x.h>
22 #include <linux/i2c/pca953x.h>
23 #include <linux/pda_power.h>
24 #include <linux/platform_device.h>
25 #include <linux/resource.h>
26 #include <linux/io.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/driver.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/mfd/as3722-plat.h>
31 #include <linux/gpio.h>
32 #include <linux/regulator/userspace-consumer.h>
33 #include <linux/pid_thermal_gov.h>
34 #include <linux/power/bq2471x-charger.h>
35
36 #include <asm/mach-types.h>
37
38 #include <mach/irqs.h>
39 #include <mach/edp.h>
40 #include <mach/gpio-tegra.h>
41
42 #include "cpu-tegra.h"
43 #include "pm.h"
44 #include "tegra-board-id.h"
45 #include "board.h"
46 #include "gpio-names.h"
47 #include "board-common.h"
48 #include "board-pmu-defines.h"
49 #include "board-ardbeg.h"
50 #include "tegra_cl_dvfs.h"
51 #include "devices.h"
52 #include "tegra11_soctherm.h"
53 #include "iomap.h"
54
55 #define PMC_CTRL                0x0
56 #define PMC_CTRL_INTR_LOW       (1 << 17)
57 #define AS3722_SUPPLY(_name) "as3722_"#_name
58
59 static struct regulator_consumer_supply as3722_ldo0_supply[] = {
60         REGULATOR_SUPPLY("avdd_pll_m", NULL),
61         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
62         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
63         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
64         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
65         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
66         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
67         REGULATOR_SUPPLY("avdd_pll_x", NULL),
68         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
69 };
70
71 static struct regulator_consumer_supply as3722_ldo1_supply[] = {
72         REGULATOR_SUPPLY("vddio_cam", "vi"),
73         REGULATOR_SUPPLY("pwrdet_cam", NULL),
74         REGULATOR_SUPPLY("vdd_cam_1v8_cam", NULL),
75         REGULATOR_SUPPLY("vif", "2-0010"),
76         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
77         REGULATOR_SUPPLY("vcc-pullup", "0-0070"),
78 };
79
80 static struct regulator_consumer_supply as3722_ldo2_supply[] = {
81         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
82         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
83         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.0"),
84         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.1"),
85         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
86         REGULATOR_SUPPLY("avdd_hsic_com", NULL),
87         REGULATOR_SUPPLY("avdd_hsic_mdm", NULL),
88         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
89         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
90         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
91 };
92
93 static struct regulator_consumer_supply as3722_ldo3_supply[] = {
94         REGULATOR_SUPPLY("vdd_rtc", NULL),
95 };
96
97 static struct regulator_consumer_supply as3722_ldo4_supply[] = {
98         REGULATOR_SUPPLY("vdd_2v7_hv", NULL),
99         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
100         REGULATOR_SUPPLY("vana", "2-0010"),
101 };
102
103 static struct regulator_consumer_supply as3722_ldo5_supply[] = {
104         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
105         REGULATOR_SUPPLY("vdig", "2-0010"),
106 };
107
108 static struct regulator_consumer_supply as3722_ldo6_supply[] = {
109         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
110         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
111         REGULATOR_SUPPLY("vcc", "0-0070"),
112 };
113
114 static struct regulator_consumer_supply as3722_ldo7_supply[] = {
115         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
116 };
117
118 static struct regulator_consumer_supply as3722_ldo9_supply[] = {
119         REGULATOR_SUPPLY("avdd", "spi0.0"),
120 };
121
122 static struct regulator_consumer_supply as3722_ldo10_supply[] = {
123         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
124         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
125         REGULATOR_SUPPLY("imx135_reg1", NULL),
126         REGULATOR_SUPPLY("vdd", "2-000e"),
127 };
128
129 static struct regulator_consumer_supply as3722_ldo11_supply[] = {
130         REGULATOR_SUPPLY("vpp_fuse", NULL),
131 };
132
133 static struct regulator_consumer_supply as3722_sd0_supply[] = {
134         REGULATOR_SUPPLY("vdd_cpu", NULL),
135 };
136
137 static struct regulator_consumer_supply as3722_sd1_supply[] = {
138         REGULATOR_SUPPLY("vdd_core", NULL),
139 };
140
141 static struct regulator_consumer_supply as3722_sd2_supply[] = {
142         REGULATOR_SUPPLY("vddio_ddr", NULL),
143         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
144         REGULATOR_SUPPLY("vddio_ddr3", NULL),
145         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
146 };
147
148 static struct regulator_consumer_supply as3722_sd4_supply[] = {
149         REGULATOR_SUPPLY("avdd_pex_pll", NULL),
150         REGULATOR_SUPPLY("avddio_pex_pll", NULL),
151         REGULATOR_SUPPLY("dvddio_pex", NULL),
152         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
153         REGULATOR_SUPPLY("avdd_sata", NULL),
154         REGULATOR_SUPPLY("vdd_sata", NULL),
155         REGULATOR_SUPPLY("avdd_sata_pll", NULL),
156         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
157         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
158 #ifdef CONFIG_TEGRA_HDMI_PRIMARY
159         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.0"),
160 #endif
161 };
162
163 static struct regulator_consumer_supply as3722_sd5_supply[] = {
164         REGULATOR_SUPPLY("vddio_sys", NULL),
165         REGULATOR_SUPPLY("vddio_sys_2", NULL),
166         REGULATOR_SUPPLY("vddio_audio", NULL),
167         REGULATOR_SUPPLY("pwrdet_audio", NULL),
168         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
169         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
170         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
171         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
172         REGULATOR_SUPPLY("vddio_uart", NULL),
173         REGULATOR_SUPPLY("pwrdet_uart", NULL),
174         REGULATOR_SUPPLY("vddio_bb", NULL),
175         REGULATOR_SUPPLY("pwrdet_bb", NULL),
176         REGULATOR_SUPPLY("vddio_gmi", NULL),
177         REGULATOR_SUPPLY("pwrdet_nand", NULL),
178         REGULATOR_SUPPLY("avdd_osc", NULL),
179         /* emmc 1.8v misssing
180         keyboard & touchpad 1.8v missing */
181 };
182
183 static struct regulator_consumer_supply as3722_sd6_supply[] = {
184         REGULATOR_SUPPLY("vdd_gpu", NULL),
185         REGULATOR_SUPPLY("vdd_gpu_simon", NULL),
186 };
187
188 AMS_PDATA_INIT(sd0, NULL, 700000, 1400000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE2);
189 AMS_PDATA_INIT(sd1, NULL, 700000, 1350000, 1, 1, 1, 0);
190 AMS_PDATA_INIT(sd2, NULL, 1350000, 1350000, 1, 1, 1, 0);
191 AMS_PDATA_INIT(sd4, NULL, 1050000, 1050000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
192 AMS_PDATA_INIT(sd5, NULL, 1800000, 1800000, 1, 1, 1, 0);
193 AMS_PDATA_INIT(sd6, NULL, 650000, 1200000, 0, 1, 1, 0);
194 AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
195 AMS_PDATA_INIT(ldo1, NULL, 1800000, 1800000, 0, 1, 1, 0);
196 AMS_PDATA_INIT(ldo2, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 1, 1, 0);
197 AMS_PDATA_INIT(ldo3, NULL, 800000, 800000, 1, 1, 1, 0);
198 AMS_PDATA_INIT(ldo4, NULL, 2700000, 2700000, 0, 0, 1, 0);
199 AMS_PDATA_INIT(ldo5, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
200 AMS_PDATA_INIT(ldo6, NULL, 1800000, 3300000, 0, 0, 1, 0);
201 AMS_PDATA_INIT(ldo7, AS3722_SUPPLY(sd5), 1050000, 1050000, 0, 0, 1, 0);
202 AMS_PDATA_INIT(ldo9, NULL, 3300000, 3300000, 0, 1, 1, 0);
203 AMS_PDATA_INIT(ldo10, NULL, 2700000, 2700000, 0, 0, 1, 0);
204 AMS_PDATA_INIT(ldo11, NULL, 1800000, 1800000, 0, 0, 1, 0);
205
206 static struct as3722_pinctrl_platform_data as3722_pctrl_pdata[] = {
207         AS3722_PIN_CONTROL("gpio0", "gpio", NULL, NULL, NULL, "output-low"),
208         AS3722_PIN_CONTROL("gpio1", "gpio", "pull-down", NULL, NULL, "output-high"),
209         AS3722_PIN_CONTROL("gpio2", "gpio", "pull-down", NULL, NULL, "output-high"),
210         AS3722_PIN_CONTROL("gpio3", "gpio", NULL, NULL, "enabled", NULL),
211         AS3722_PIN_CONTROL("gpio4", "gpio", NULL, NULL, NULL, "output-high"),
212         AS3722_PIN_CONTROL("gpio5", "gpio", "pull-down", NULL, "enabled", NULL),
213         AS3722_PIN_CONTROL("gpio6", "gpio", NULL, NULL, "enabled", NULL),
214         AS3722_PIN_CONTROL("gpio7", "gpio", NULL, NULL, NULL, "output-high"),
215 };
216
217 static struct as3722_adc_extcon_platform_data as3722_adc_extcon_pdata = {
218         .connection_name = "as3722-extcon",
219         .enable_adc1_continuous_mode = true,
220         .enable_low_voltage_range = true,
221         .adc_channel = 12,
222         .hi_threshold =  0x100,
223         .low_threshold = 0x80,
224 };
225
226 static struct as3722_platform_data as3722_pdata = {
227         .reg_pdata[AS3722_LDO0] = &as3722_ldo0_reg_pdata,
228         .reg_pdata[AS3722_LDO1] = &as3722_ldo1_reg_pdata,
229         .reg_pdata[AS3722_LDO2] = &as3722_ldo2_reg_pdata,
230         .reg_pdata[AS3722_LDO3] = &as3722_ldo3_reg_pdata,
231         .reg_pdata[AS3722_LDO4] = &as3722_ldo4_reg_pdata,
232         .reg_pdata[AS3722_LDO5] = &as3722_ldo5_reg_pdata,
233         .reg_pdata[AS3722_LDO6] = &as3722_ldo6_reg_pdata,
234         .reg_pdata[AS3722_LDO7] = &as3722_ldo7_reg_pdata,
235         .reg_pdata[AS3722_LDO9] = &as3722_ldo9_reg_pdata,
236         .reg_pdata[AS3722_LDO10] = &as3722_ldo10_reg_pdata,
237         .reg_pdata[AS3722_LDO11] = &as3722_ldo11_reg_pdata,
238
239         .reg_pdata[AS3722_SD0] = &as3722_sd0_reg_pdata,
240         .reg_pdata[AS3722_SD1] = &as3722_sd1_reg_pdata,
241         .reg_pdata[AS3722_SD2] = &as3722_sd2_reg_pdata,
242         .reg_pdata[AS3722_SD4] = &as3722_sd4_reg_pdata,
243         .reg_pdata[AS3722_SD5] = &as3722_sd5_reg_pdata,
244         .reg_pdata[AS3722_SD6] = &as3722_sd6_reg_pdata,
245
246         .gpio_base = AS3722_GPIO_BASE,
247         .irq_base = AS3722_IRQ_BASE,
248         .use_internal_int_pullup = 0,
249         .use_internal_i2c_pullup = 0,
250         .pinctrl_pdata = as3722_pctrl_pdata,
251         .num_pinctrl = ARRAY_SIZE(as3722_pctrl_pdata),
252         .enable_clk32k_out = true,
253         .use_power_off = true,
254         .extcon_pdata = &as3722_adc_extcon_pdata,
255         .major_rev = 1,
256         .minor_rev = 1,
257 };
258
259 static struct pca953x_platform_data tca6416_pdata = {
260         .gpio_base = PMU_TCA6416_GPIO_BASE,
261 };
262
263 static const struct i2c_board_info tca6416_expander[] = {
264         {
265                 I2C_BOARD_INFO("tca6416", 0x20),
266                 .platform_data = &tca6416_pdata,
267         },
268 };
269
270 static const struct i2c_board_info tca6408_expander[] = {
271         {
272                 I2C_BOARD_INFO("tca6408", 0x20),
273                 .platform_data = &tca6416_pdata,
274         },
275 };
276
277 struct bq2471x_platform_data laguna_bq2471x_pdata = {
278         .charge_broadcast_mode = 1,
279         .gpio_active_low = 1,
280         .gpio = TEGRA_GPIO_PK3,
281 };
282
283 static struct i2c_board_info __initdata bq2471x_boardinfo[] = {
284         {
285                 I2C_BOARD_INFO("bq2471x", 0x09),
286                 .platform_data  = &laguna_bq2471x_pdata,
287         },
288 };
289
290 static struct i2c_board_info __initdata as3722_regulators[] = {
291         {
292                 I2C_BOARD_INFO("as3722", 0x40),
293                 .flags = I2C_CLIENT_WAKE,
294                 .irq = INT_EXTERNAL_PMU,
295                 .platform_data = &as3722_pdata,
296         },
297 };
298
299 int __init laguna_as3722_regulator_init(void)
300 {
301         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
302         u32 pmc_ctrl;
303         struct board_info board_info;
304
305         tegra_get_board_info(&board_info);
306
307         /* AS3722: Normal state of INT request line is LOW.
308          * configure the power management controller to trigger PMU
309          * interrupts when HIGH.
310          */
311         pmc_ctrl = readl(pmc + PMC_CTRL);
312         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
313         regulator_has_full_constraints();
314         /* Set vdd_gpu init uV to 1V */
315         as3722_sd6_reg_idata.constraints.init_uV = 1000000;
316
317         /* Set overcurrent of rails. */
318         as3722_sd6_reg_idata.constraints.min_uA = 3500000;
319         as3722_sd6_reg_idata.constraints.max_uA = 3500000;
320
321         as3722_sd0_reg_idata.constraints.min_uA = 3500000;
322         as3722_sd0_reg_idata.constraints.max_uA = 3500000;
323
324         as3722_sd1_reg_idata.constraints.min_uA = 2500000;
325         as3722_sd1_reg_idata.constraints.max_uA = 2500000;
326
327         as3722_ldo3_reg_pdata.enable_tracking = true;
328         as3722_ldo3_reg_pdata.disable_tracking_suspend = true;
329
330         if (board_info.board_id == BOARD_PM375 ||
331             board_info.board_id == BOARD_PM377 ||
332             ((board_info.board_id == BOARD_PM359) &&
333              (board_info.major_revision == 'C')))
334                 as3722_pdata.minor_rev = 2;
335
336         printk(KERN_INFO "%s: i2c_register_board_info\n",
337                         __func__);
338         if (board_info.board_id == BOARD_PM358) {
339                 switch (board_info.fab) {
340                 case BOARD_FAB_A01:
341                         as3722_pdata.reg_pdata[AS3722_LDO5] =
342                                 &as3722_ldo7_reg_pdata;
343                         as3722_pdata.reg_pdata[AS3722_LDO7] =
344                                 &as3722_ldo5_reg_pdata;
345                         as3722_pdata.reg_pdata[AS3722_LDO4] =
346                                 &as3722_ldo10_reg_pdata;
347                         as3722_pdata.reg_pdata[AS3722_LDO10] =
348                                 &as3722_ldo4_reg_pdata;
349                         break;
350                 default:
351                         break;
352                 }
353         }
354         i2c_register_board_info(4, as3722_regulators,
355                         ARRAY_SIZE(as3722_regulators));
356         if (board_info.board_id == BOARD_PM358 &&
357                         board_info.fab == BOARD_FAB_A00)
358                 i2c_register_board_info(0, tca6408_expander,
359                                 ARRAY_SIZE(tca6408_expander));
360         else if (board_info.board_id == BOARD_PM359 ||
361                         board_info.board_id == BOARD_PM370 ||
362                         board_info.board_id == BOARD_PM374 ||
363                         board_info.board_id == BOARD_PM358)
364                 i2c_register_board_info(0, tca6416_expander,
365                                 ARRAY_SIZE(tca6416_expander));
366         return 0;
367 }
368
369 static struct tegra_suspend_platform_data laguna_suspend_data = {
370         .cpu_timer      = 2000,
371         .cpu_off_timer  = 2000,
372         .suspend_mode   = TEGRA_SUSPEND_LP0,
373         .core_timer     = 0x7e7e,
374         .core_off_timer = 2000,
375         .corereq_high   = true,
376         .sysclkreq_high = true,
377         .cpu_lp2_min_residency = 1000,
378 };
379
380 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
381 /* board parameters for cpu dfll */
382 static struct tegra_cl_dvfs_cfg_param laguna_cl_dvfs_param = {
383         .sample_rate = 12500,
384
385         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
386         .cf = 10,
387         .ci = 0,
388         .cg = 2,
389
390         .droop_cut_value = 0xF,
391         .droop_restore_ramp = 0x0,
392         .scale_out_ramp = 0x0,
393 };
394 #endif
395
396 /* Laguna: fixed 10mV steps from 700mV to 1400mV */
397 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 700000) / 10000 + 1)
398 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
399 static inline void fill_reg_map(void)
400 {
401         int i;
402         u32 reg_init_value = 0x0a;
403         struct board_info board_info;
404
405         tegra_get_board_info(&board_info);
406         if ((board_info.board_id == BOARD_PM375) ||
407                 (board_info.board_id == BOARD_PM377) ||
408                 ((board_info.board_id == BOARD_PM359) &&
409                                 (board_info.major_revision == 'C')))
410                 reg_init_value = 0x1e;
411
412         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
413                 pmu_cpu_vdd_map[i].reg_value = i + reg_init_value;
414                 pmu_cpu_vdd_map[i].reg_uV = 700000 + 10000 * i;
415         }
416 }
417
418 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
419 static struct tegra_cl_dvfs_platform_data laguna_cl_dvfs_data = {
420         .dfll_clk_name = "dfll_cpu",
421         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
422         .u.pmu_i2c = {
423                 .fs_rate = 400000,
424                 .slave_addr = 0x80,
425                 .reg = 0x00,
426         },
427         .vdd_map = pmu_cpu_vdd_map,
428         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
429
430         .cfg_param = &laguna_cl_dvfs_param,
431 };
432
433 static int __init laguna_cl_dvfs_init(void)
434 {
435         fill_reg_map();
436         laguna_cl_dvfs_data.flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
437         tegra_cl_dvfs_device.dev.platform_data = &laguna_cl_dvfs_data;
438         platform_device_register(&tegra_cl_dvfs_device);
439
440         return 0;
441 }
442 #endif
443
444 /* Always ON /Battery regulator */
445 static struct regulator_consumer_supply fixed_reg_battery_supply[] = {
446         REGULATOR_SUPPLY("vdd_sys_bl", NULL),
447         REGULATOR_SUPPLY("vddio_pex_sata", "tegra-sata.0"),
448 };
449
450 /* Always ON 1.8v */
451 static struct regulator_consumer_supply fixed_reg_aon_1v8_supply[] = {
452         REGULATOR_SUPPLY("vdd_1v8_emmc", NULL),
453         REGULATOR_SUPPLY("vdd_1v8b_com_f", NULL),
454         REGULATOR_SUPPLY("vdd_1v8b_gps_f", NULL),
455 };
456
457 /* Always ON 3.3v */
458 static struct regulator_consumer_supply fixed_reg_aon_3v3_supply[] = {
459         REGULATOR_SUPPLY("vdd_3v3_emmc", NULL),
460         REGULATOR_SUPPLY("vdd_com_3v3", NULL),
461 };
462
463 /* Always ON 1v2 */
464 static struct regulator_consumer_supply fixed_reg_aon_1v2_supply[] = {
465         REGULATOR_SUPPLY("vdd_1v2_bb_hsic", NULL),
466 };
467
468 /* EN_USB0_VBUS From TEGRA GPIO PN4 */
469 static struct regulator_consumer_supply fixed_reg_usb0_vbus_pm358_supply[] = {
470         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
471         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
472         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
473 };
474
475 /* EN_USB1_USB2_VBUS From TEGRA GPIO PN5 */
476 static struct regulator_consumer_supply fixed_reg_usb1_usb2_vbus_pm358_supply[] = {
477         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
478         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
479         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
480         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
481 };
482
483 /* EN_USB0_VBUS From TEGRA GPIO PN4 */
484 static struct regulator_consumer_supply fixed_reg_usb0_usb1_vbus_pm359_supply[] = {
485         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
486         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
487         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
488 };
489
490 /* EN_USB1_USB2_VBUS From TEGRA GPIO PN5 */
491 static struct regulator_consumer_supply fixed_reg_usb2_vbus_pm359_supply[] = {
492         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
493         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
494         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
495         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
496 };
497
498 /* EN_USB0_VBUS From TEGRA GPIO PN4 */
499 static struct regulator_consumer_supply fixed_reg_usb2_vbus_pm363_supply[] = {
500         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
501         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
502 };
503
504 /* EN_USB1_USB2_VBUS From TEGRA GPIO PN5 */
505 static struct regulator_consumer_supply fixed_reg_usb0_usb1_vbus_pm363_supply[] = {
506         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
507         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
508         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
509         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
510         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
511 };
512
513 /* Gated by GPIO_PK6  in FAB B and further*/
514 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
515         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.0"),
516         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
517 };
518
519 /* Gated by GPIO_PH7  in FAB B and further*/
520 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_supply[] = {
521         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.0"),
522         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
523 };
524
525 /* VDD_LCD_BL DAP3_DOUT */
526 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_supply[] = {
527         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
528 };
529
530 /* LCD_BL_EN GMI_AD10 */
531 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
532         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
533 };
534
535 /* AS3722 GPIO1*/
536 static struct regulator_consumer_supply fixed_reg_3v3_supply[] = {
537         REGULATOR_SUPPLY("hvdd_pex", NULL),
538         REGULATOR_SUPPLY("hvdd_pex_pll", NULL),
539         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
540         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5645.0"),
541         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5639.0"),
542         REGULATOR_SUPPLY("spkvdd", "tegra-snd-max98090.0"),
543         REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
544         REGULATOR_SUPPLY("vdd_nfc_3v3", NULL),
545         REGULATOR_SUPPLY("vdd_3v3_sensor", NULL),
546         REGULATOR_SUPPLY("vdd_kp_3v3", NULL),
547         REGULATOR_SUPPLY("vdd_tp_3v3", NULL),
548         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
549         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
550         REGULATOR_SUPPLY("vdd", "1-004c"),
551         REGULATOR_SUPPLY("vdd", "0-004c"),
552         REGULATOR_SUPPLY("vdd", "0-0048"),
553         REGULATOR_SUPPLY("vdd", "0-0069"),
554         REGULATOR_SUPPLY("vdd", "0-000c"),
555         REGULATOR_SUPPLY("vdd", "0-0077"),
556         REGULATOR_SUPPLY("vin", "2-0030"),
557         REGULATOR_SUPPLY("pcie_usb_vbus", "tegra-xhci"),
558 };
559
560 /* AS3722 GPIO1*/
561 static struct regulator_consumer_supply fixed_reg_5v0_supply[] = {
562         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
563         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
564         REGULATOR_SUPPLY("vdd_5v0_sensor", NULL),
565 };
566
567 static struct regulator_consumer_supply fixed_reg_dcdc_1v8_supply[] = {
568         REGULATOR_SUPPLY("avdd_lvds0_pll", NULL),
569         REGULATOR_SUPPLY("dvdd_lcd", NULL),
570         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
571         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645.0"),
572         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645.0"),
573         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639.0"),
574         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639.0"),
575         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639.0"),
576         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645.0"),
577         REGULATOR_SUPPLY("vdd_aud_dgtl", "tegra-snd-max98090.0"),
578         REGULATOR_SUPPLY("vdd_1v8b_nfc", NULL),
579         REGULATOR_SUPPLY("vdd_1v8_sensor", NULL),
580         REGULATOR_SUPPLY("vdd_1v8_sdmmc", NULL),
581         REGULATOR_SUPPLY("vdd_kp_1v8", NULL),
582         REGULATOR_SUPPLY("vdd_tp_1v8", NULL),
583         REGULATOR_SUPPLY("vdd_modem_1v8", NULL),
584         REGULATOR_SUPPLY("vdd_1v8b", "0-0048"),
585         REGULATOR_SUPPLY("dvdd", "spi0.0"),
586         REGULATOR_SUPPLY("vlogic", "0-0069"),
587         REGULATOR_SUPPLY("vid", "0-000c"),
588         REGULATOR_SUPPLY("vddio", "0-0077"),
589         REGULATOR_SUPPLY("vi2c", "2-0030"),
590         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
591         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
592         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
593         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
594         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
595 };
596
597 /* gated by TCA6416 GPIO EXP GPIO0 */
598 static struct regulator_consumer_supply fixed_reg_dcdc_1v2_supply[] = {
599         REGULATOR_SUPPLY("vdd_1v2_en", NULL),
600         REGULATOR_SUPPLY("avdd_aud", "tegra-snd-max98090.0"),
601 };
602
603 /* AMS GPIO2 */
604 static struct regulator_consumer_supply fixed_reg_as3722_gpio2_supply[] = {
605         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
606         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
607         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
608         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
609         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
610         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
611         REGULATOR_SUPPLY("pwrdet_hv", NULL),
612         REGULATOR_SUPPLY("hvdd_sata", NULL),
613 };
614
615 /* gated by AS3722 GPIO4 */
616 static struct regulator_consumer_supply fixed_reg_lcd_supply[] = {
617         REGULATOR_SUPPLY("avdd_lcd", NULL),
618 };
619
620 /* gated by GPIO_PR0 */
621 static struct regulator_consumer_supply fixed_reg_sdmmc_en_supply[] = {
622         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.1"),
623         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
624 };
625
626 /* only adding for PM358 */
627 static struct regulator_consumer_supply fixed_reg_vdd_cdc_1v2_aud_supply[] = {
628         REGULATOR_SUPPLY("ldoen", "tegra-snd-rt5639.0"),
629 };
630
631 static struct regulator_consumer_supply
632 fixed_reg_vdd_cdc_1v2_aud_pm375_supply[] = {
633         REGULATOR_SUPPLY("ldoen", "tegra-snd-rt5639.0"),
634 };
635 static struct regulator_consumer_supply fixed_reg_vdd_amp_shut_aud_supply[] = {
636         REGULATOR_SUPPLY("epamp", "tegra-snd-rt5645.0"),
637 };
638
639 static struct regulator_consumer_supply fixed_reg_vdd_dsi_mux_supply[] = {
640         REGULATOR_SUPPLY("vdd_3v3_dsi", "NULL"),
641 };
642
643 /* Macro for defining fixed regulator sub device data */
644 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
645 #define FIXED_REG(_id, _var, _name, _in_supply,                 \
646         _always_on, _boot_on, _gpio_nr, _open_drain,            \
647         _active_high, _boot_state, _millivolts, _sdelay)        \
648 static struct regulator_init_data ri_data_##_var =              \
649 {                                                               \
650         .supply_regulator = _in_supply,                         \
651         .num_consumer_supplies =                                \
652         ARRAY_SIZE(fixed_reg_##_name##_supply),                 \
653         .consumer_supplies = fixed_reg_##_name##_supply,        \
654         .constraints = {                                        \
655                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
656                                 REGULATOR_MODE_STANDBY),        \
657                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
658                                 REGULATOR_CHANGE_STATUS |       \
659                                 REGULATOR_CHANGE_VOLTAGE),      \
660                 .always_on = _always_on,                        \
661                 .boot_on = _boot_on,                            \
662         },                                                      \
663 };                                                              \
664 static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
665 {                                                               \
666         .supply_name = FIXED_SUPPLY(_name),                     \
667         .microvolts = _millivolts * 1000,                       \
668         .gpio = _gpio_nr,                                       \
669         .gpio_is_open_drain = _open_drain,                      \
670         .enable_high = _active_high,                            \
671         .enabled_at_boot = _boot_state,                         \
672         .init_data = &ri_data_##_var,                           \
673         .startup_delay = _sdelay,                               \
674 };                                                              \
675 static struct platform_device fixed_reg_##_var##_dev = {        \
676         .name = "reg-fixed-voltage",                            \
677         .id = _id,                                              \
678         .dev = {                                                \
679                 .platform_data = &fixed_reg_##_var##_pdata,     \
680         },                                                      \
681 }
682
683 FIXED_REG(0,    battery,        battery,        NULL,   0,      0,
684                 -1,     false, true,    0,      8400,   0);
685
686 FIXED_REG(1,    aon_1v8,        aon_1v8,        NULL,   0,      0,
687                 -1,     false, true,    0,      1800,   0);
688
689 FIXED_REG(2,    aon_3v3,        aon_3v3,        NULL,   0,      0,
690                 -1,     false, true,    0,      3300,   0);
691
692 FIXED_REG(3,    aon_1v2,        aon_1v2,        NULL,   0,      0,
693                 -1,     false, true,    0,      1200,   0);
694
695 FIXED_REG(4,    vdd_hdmi_5v0,   vdd_hdmi_5v0,   NULL,   0,      0,
696                 TEGRA_GPIO_PK6, false,  true,   0,      5000,   5000);
697
698 FIXED_REG(5,    vdd_hdmi,       vdd_hdmi,       AS3722_SUPPLY(sd4),
699                 0,      0,
700                 TEGRA_GPIO_PH7, false,  false,  0,      3300,   0);
701
702 FIXED_REG(6,    usb0_vbus_pm358,        usb0_vbus_pm358,        NULL,
703                 0,      0,
704                 TEGRA_GPIO_PN4, true,   true,   0,      5000,   0);
705
706 FIXED_REG(7,    usb1_usb2_vbus_pm358,   usb1_usb2_vbus_pm358,   NULL,
707                 0,      0,
708                 TEGRA_GPIO_PN5, true,   true,   0,      5000, 0);
709
710 FIXED_REG(8,    usb0_usb1_vbus_pm359,   usb0_usb1_vbus_pm359,   NULL,
711                 0,      0,
712                 TEGRA_GPIO_PN4, true,   true,   0,      5000,   0);
713
714 FIXED_REG(9,    usb2_vbus_pm359,        usb2_vbus_pm359,        NULL,
715                 0,      0,
716                 TEGRA_GPIO_PN5, true,   true,   0,      5000, 0);
717
718 FIXED_REG(10,   usb2_vbus_pm363,        usb2_vbus_pm363,        NULL,
719                 0,      0,
720                 TEGRA_GPIO_PN4, true,   true,   0,      5000,   0);
721
722 FIXED_REG(11,   usb0_usb1_vbus_pm363,   usb0_usb1_vbus_pm363,   NULL,
723                 0,      0,
724                 TEGRA_GPIO_PN5, true,   true,   0,      5000, 0);
725
726 FIXED_REG(12,   vdd_lcd_bl,     vdd_lcd_bl,     NULL,   0,      0,
727                 TEGRA_GPIO_PP2, false,  true,   0,      3300, 0);
728
729 FIXED_REG(13,   lcd_bl_en,      lcd_bl_en,      NULL,   0,      0,
730                 TEGRA_GPIO_PH2, false,  true,   0,      5000,   0);
731
732 FIXED_REG(14,   3v3,            3v3,            NULL,   0,      0,
733                 -1,     false,  true,   0,      3300,   0);
734
735 FIXED_REG(15,   5v0,            5v0,            NULL,   0,      0,
736                 -1,     false,  true,   0,      5000,   0);
737
738 FIXED_REG(16,   dcdc_1v8,       dcdc_1v8,       NULL,   0,      0,
739                 -1,     false,  true,   0,      1800,   0);
740
741 FIXED_REG(17,    dcdc_1v2, dcdc_1v2,    NULL,   0,      0,
742                 PMU_TCA6416_GPIO_BASE,     false,  true,   0,      1200,
743                 0);
744
745 FIXED_REG(18,   as3722_gpio2,   as3722_gpio2,           NULL,   0,      true,
746                 AS3722_GPIO_BASE + AS3722_GPIO2,        false,  true,   true,
747                 3300,   0);
748
749 FIXED_REG(19,   lcd,            lcd,            NULL,   0,      0,
750                 AS3722_GPIO_BASE + AS3722_GPIO4,        false,  true,   0,
751                 3300,   0);
752
753 FIXED_REG(20,   sdmmc_en,               sdmmc_en,       NULL,   0,      0,
754                 TEGRA_GPIO_PR0,         false,  true,   0,      3300,   0);
755
756 FIXED_REG(21,   vdd_cdc_1v2_aud,        vdd_cdc_1v2_aud,        NULL,   0,
757                 0,      PMU_TCA6416_GPIO(2),    false,  true,   0,
758                 1200,   250000);
759
760 FIXED_REG(21,   vdd_cdc_1v2_aud_pm375,  vdd_cdc_1v2_aud_pm375,  NULL,   0,
761                 0,      TEGRA_GPIO_PR2, false,  true,   0,
762                 1200,   250000);
763
764 FIXED_REG(22,   vdd_amp_shut_aud,       vdd_amp_shut_aud,       NULL,   0,
765                 0,      PMU_TCA6416_GPIO(3),    false,  true,   0,
766                 1200,   0);
767
768 FIXED_REG(23,   vdd_dsi_mux,            vdd_dsi_mux,    NULL,   0,      0,
769                 PMU_TCA6416_GPIO(13),   false,  true,   0,      3300,   0);
770 /*
771  * Creating the fixed regulator device tables
772  */
773
774 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
775
776 #define LAGUNA_COMMON_FIXED_REG                 \
777         ADD_FIXED_REG(battery),                 \
778         ADD_FIXED_REG(aon_1v8),                 \
779         ADD_FIXED_REG(aon_3v3),                 \
780         ADD_FIXED_REG(aon_1v2),                 \
781         ADD_FIXED_REG(vdd_hdmi_5v0),            \
782         ADD_FIXED_REG(vdd_hdmi),                \
783         ADD_FIXED_REG(vdd_lcd_bl),              \
784         ADD_FIXED_REG(lcd_bl_en),               \
785         ADD_FIXED_REG(3v3),                     \
786         ADD_FIXED_REG(5v0),                     \
787         ADD_FIXED_REG(dcdc_1v8),                \
788         ADD_FIXED_REG(as3722_gpio2),            \
789         ADD_FIXED_REG(lcd),                     \
790         ADD_FIXED_REG(sdmmc_en)
791
792 #define LAGUNA_PM358_FIXED_REG                  \
793         ADD_FIXED_REG(usb0_vbus_pm358),         \
794         ADD_FIXED_REG(usb1_usb2_vbus_pm358),    \
795         ADD_FIXED_REG(dcdc_1v2),                \
796         ADD_FIXED_REG(vdd_cdc_1v2_aud),         \
797         ADD_FIXED_REG(vdd_amp_shut_aud),         \
798         ADD_FIXED_REG(vdd_dsi_mux)
799
800 #define LAGUNA_PM359_FIXED_REG                  \
801         ADD_FIXED_REG(usb0_usb1_vbus_pm359),    \
802         ADD_FIXED_REG(usb2_vbus_pm359),         \
803         ADD_FIXED_REG(dcdc_1v2),                \
804         ADD_FIXED_REG(vdd_cdc_1v2_aud)
805
806 #define LAGUNA_PM363_FIXED_REG                  \
807         ADD_FIXED_REG(usb2_vbus_pm363),         \
808         ADD_FIXED_REG(usb0_usb1_vbus_pm363),
809
810 #define BEAVER_PM375_FIXED_REG                  \
811         ADD_FIXED_REG(vdd_cdc_1v2_aud_pm375),   \
812         ADD_FIXED_REG(usb2_vbus_pm359),         \
813         ADD_FIXED_REG(usb0_usb1_vbus_pm359),
814
815
816 /* Gpio switch regulator platform data for laguna pm358 ERS*/
817 static struct platform_device *fixed_reg_devs_pm358[] = {
818         LAGUNA_COMMON_FIXED_REG,
819         LAGUNA_PM358_FIXED_REG
820 };
821
822 /* Gpio switch regulator platform data for laguna pm359 ERS-S*/
823 static struct platform_device *fixed_reg_devs_pm359[] = {
824         LAGUNA_COMMON_FIXED_REG,
825         LAGUNA_PM359_FIXED_REG
826 };
827
828 /* Gpio switch regulator platform data for laguna pm363 FFD*/
829 static struct platform_device *fixed_reg_devs_pm363[] = {
830         LAGUNA_COMMON_FIXED_REG,
831         LAGUNA_PM363_FIXED_REG
832 };
833 /* Gpio switch regulator platform data for laguna pm370 FFD*/
834 static struct platform_device *fixed_reg_devs_pm370[] = {
835         LAGUNA_COMMON_FIXED_REG,
836         LAGUNA_PM358_FIXED_REG
837 };
838
839 /* Gpio switch regulator platform data for laguna pm374 FFD*/
840 static struct platform_device *fixed_reg_devs_pm374[] = {
841         LAGUNA_COMMON_FIXED_REG,
842         LAGUNA_PM358_FIXED_REG
843 };
844
845 /* Gpio switch regulator platform data for BEAVER PM375 && PM377*/
846 static struct platform_device *fixed_reg_devs_pm375[] = {
847         LAGUNA_COMMON_FIXED_REG,
848         BEAVER_PM375_FIXED_REG
849 };
850
851 static int __init laguna_fixed_regulator_init(void)
852 {
853         struct board_info board_info;
854
855         if (!of_machine_is_compatible("nvidia,laguna") &&
856             !of_machine_is_compatible("nvidia,jetson-tk1"))
857                 return 0;
858
859         tegra_get_board_info(&board_info);
860         if (board_info.board_id == BOARD_PM374)
861                 return platform_add_devices(fixed_reg_devs_pm374,
862                                 ARRAY_SIZE(fixed_reg_devs_pm374));
863         else if ((board_info.board_id == BOARD_PM375) ||
864                 (board_info.board_id == BOARD_PM377))
865                 return platform_add_devices(fixed_reg_devs_pm375,
866                                 ARRAY_SIZE(fixed_reg_devs_pm375));
867         else if (board_info.board_id == BOARD_PM359)
868                 return platform_add_devices(fixed_reg_devs_pm359,
869                                 ARRAY_SIZE(fixed_reg_devs_pm359));
870         else if (board_info.board_id == BOARD_PM358)
871                 return platform_add_devices(fixed_reg_devs_pm358,
872                                 ARRAY_SIZE(fixed_reg_devs_pm358));
873         else if (board_info.board_id == BOARD_PM370)
874                 return platform_add_devices(fixed_reg_devs_pm370,
875                                 ARRAY_SIZE(fixed_reg_devs_pm370));
876         else if (board_info.board_id == BOARD_PM363)
877                 return platform_add_devices(fixed_reg_devs_pm363,
878                                 ARRAY_SIZE(fixed_reg_devs_pm363));
879
880         return 0;
881 }
882
883 subsys_initcall_sync(laguna_fixed_regulator_init);
884
885 int __init laguna_regulator_init(void)
886 {
887
888 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
889         laguna_cl_dvfs_init();
890 #endif
891         laguna_as3722_regulator_init();
892
893         if (get_power_supply_type() == POWER_SUPPLY_TYPE_BATTERY)
894                 i2c_register_board_info(1, bq2471x_boardinfo,
895                         ARRAY_SIZE(bq2471x_boardinfo));
896
897         return 0;
898 }
899
900 int __init laguna_suspend_init(void)
901 {
902         tegra_init_suspend(&laguna_suspend_data);
903         return 0;
904 }
905
906 int __init laguna_edp_init(void)
907 {
908         unsigned int regulator_mA;
909
910         regulator_mA = get_maximum_cpu_current_supported();
911         if (!regulator_mA)
912                 regulator_mA = 15000;
913
914         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
915
916         tegra_init_cpu_edp_limits(regulator_mA);
917
918         /* gpu maximum current */
919         regulator_mA = 8000;
920         pr_info("%s: GPU regulator %d mA\n", __func__, regulator_mA);
921
922         tegra_init_gpu_edp_limits(regulator_mA);
923         return 0;
924 }
925
926 static struct pid_thermal_gov_params soctherm_pid_params = {
927         .max_err_temp = 9000,
928         .max_err_gain = 1000,
929
930         .gain_p = 1000,
931         .gain_d = 0,
932
933         .up_compensation = 20,
934         .down_compensation = 20,
935 };
936
937 static struct thermal_zone_params soctherm_tzp = {
938         .governor_name = "pid_thermal_gov",
939         .governor_params = &soctherm_pid_params,
940 };
941
942 static struct soctherm_platform_data laguna_soctherm_data = {
943         .therm = {
944                 [THERM_CPU] = {
945                         .zone_enable = true,
946                         .passive_delay = 1000,
947                         .hotspot_offset = 6000,
948                         .num_trips = 3,
949                         .trips = {
950                                 {
951                                         .cdev_type = "tegra-shutdown",
952                                         .trip_temp = 103000,
953                                         .trip_type = THERMAL_TRIP_CRITICAL,
954                                         .upper = THERMAL_NO_LIMIT,
955                                         .lower = THERMAL_NO_LIMIT,
956                                 },
957                                 {
958                                         .cdev_type = "tegra-heavy",
959                                         .trip_temp = 101000,
960                                         .trip_type = THERMAL_TRIP_HOT,
961                                         .upper = THERMAL_NO_LIMIT,
962                                         .lower = THERMAL_NO_LIMIT,
963                                 },
964                                 {
965                                         .cdev_type = "tegra-balanced",
966                                         .trip_temp = 91000,
967                                         .trip_type = THERMAL_TRIP_PASSIVE,
968                                         .upper = THERMAL_NO_LIMIT,
969                                         .lower = THERMAL_NO_LIMIT,
970                                 },
971                         },
972                         .tzp = &soctherm_tzp,
973                 },
974                 [THERM_GPU] = {
975                         .zone_enable = true,
976                         .passive_delay = 1000,
977                         .hotspot_offset = 6000,
978                         .num_trips = 3,
979                         .trips = {
980                                 {
981                                         .cdev_type = "tegra-shutdown",
982                                         .trip_temp = 104000,
983                                         .trip_type = THERMAL_TRIP_CRITICAL,
984                                         .upper = THERMAL_NO_LIMIT,
985                                         .lower = THERMAL_NO_LIMIT,
986                                 },
987                                 {
988                                         .cdev_type = "tegra-balanced",
989                                         .trip_temp = 92000,
990                                         .trip_type = THERMAL_TRIP_PASSIVE,
991                                         .upper = THERMAL_NO_LIMIT,
992                                         .lower = THERMAL_NO_LIMIT,
993                                 },
994 /*
995                                 {
996                                         .cdev_type = "gk20a_cdev",
997                                         .trip_temp = 102000,
998                                         .trip_type = THERMAL_TRIP_PASSIVE,
999                                         .upper = THERMAL_NO_LIMIT,
1000                                         .lower = THERMAL_NO_LIMIT,
1001                                 },
1002                                 {
1003                                         .cdev_type = "tegra-heavy",
1004                                         .trip_temp = 102000,
1005                                         .trip_type = THERMAL_TRIP_HOT,
1006                                         .upper = THERMAL_NO_LIMIT,
1007                                         .lower = THERMAL_NO_LIMIT,
1008                                 },
1009 */
1010                         },
1011                         .tzp = &soctherm_tzp,
1012                 },
1013                 [THERM_MEM] = {
1014                         .zone_enable = true,
1015                         .num_trips = 1,
1016                         .trips = {
1017                                 {
1018                                         .cdev_type = "tegra-shutdown",
1019                                         .trip_temp = 104000, /* = GPU shut */
1020                                         .trip_type = THERMAL_TRIP_CRITICAL,
1021                                         .upper = THERMAL_NO_LIMIT,
1022                                         .lower = THERMAL_NO_LIMIT,
1023                                 },
1024                         },
1025                 },
1026                 [THERM_PLL] = {
1027                         .zone_enable = true,
1028                         .tzp = &soctherm_tzp,
1029                 },
1030         },
1031         .throttle = {
1032                 [THROTTLE_HEAVY] = {
1033                         .priority = 100,
1034                         .devs = {
1035                                 [THROTTLE_DEV_CPU] = {
1036                                         .enable = true,
1037                                         .depth = 80,
1038                                 },
1039                                 [THROTTLE_DEV_GPU] = {
1040                                         .enable = false,
1041                                         .throttling_depth = "heavy_throttling",
1042                                 },
1043                         },
1044                 },
1045         },
1046 };
1047
1048 int __init laguna_soctherm_init(void)
1049 {
1050         tegra_platform_edp_init(laguna_soctherm_data.therm[THERM_CPU].trips,
1051                         &laguna_soctherm_data.therm[THERM_CPU].num_trips,
1052                         7000); /* edp temperature margin */
1053         tegra_platform_gpu_edp_init(
1054                         laguna_soctherm_data.therm[THERM_GPU].trips,
1055                         &laguna_soctherm_data.therm[THERM_GPU].num_trips,
1056                         7000);
1057         tegra_add_cpu_vmax_trips(laguna_soctherm_data.therm[THERM_CPU].trips,
1058                         &laguna_soctherm_data.therm[THERM_CPU].num_trips);
1059         tegra_add_tgpu_trips(laguna_soctherm_data.therm[THERM_GPU].trips,
1060                         &laguna_soctherm_data.therm[THERM_GPU].num_trips);
1061         tegra_add_vc_trips(laguna_soctherm_data.therm[THERM_CPU].trips,
1062                         &laguna_soctherm_data.therm[THERM_CPU].num_trips);
1063         tegra_add_core_vmax_trips(laguna_soctherm_data.therm[THERM_PLL].trips,
1064                         &laguna_soctherm_data.therm[THERM_PLL].num_trips);
1065
1066         return tegra11_soctherm_init(&laguna_soctherm_data);
1067 }