be958f3ebda0a29c943014f95bf76277c1576736
[linux-3.10.git] / arch / arm / mach-tegra / board-laguna-power.c
1 /*
2  * arch/arm/mach-tegra/board-laguna-power.c
3  *
4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca954x.h>
22 #include <linux/i2c/pca953x.h>
23 #include <linux/pda_power.h>
24 #include <linux/platform_device.h>
25 #include <linux/resource.h>
26 #include <linux/io.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/driver.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/mfd/as3722-reg.h>
31 #include <linux/mfd/as3722-plat.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/userspace-consumer.h>
34
35 #include <asm/mach-types.h>
36
37 #include <mach/irqs.h>
38 #include <mach/edp.h>
39 #include <mach/gpio-tegra.h>
40
41 #include "cpu-tegra.h"
42 #include "pm.h"
43 #include "tegra-board-id.h"
44 #include "board.h"
45 #include "gpio-names.h"
46 #include "board-common.h"
47 #include "board-pmu-defines.h"
48 #include "board-ardbeg.h"
49 #include "tegra_cl_dvfs.h"
50 #include "devices.h"
51 #include "tegra11_soctherm.h"
52 #include "iomap.h"
53
54 #define PMC_CTRL                0x0
55 #define PMC_CTRL_INTR_LOW       (1 << 17)
56 #define AS3722_SUPPLY(_name) "as3722_"#_name
57
58 static struct regulator_consumer_supply as3722_ldo0_supply[] = {
59         REGULATOR_SUPPLY("avdd_pll_m", NULL),
60         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
61         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
62         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
63         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
64         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
65         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
66         REGULATOR_SUPPLY("avdd_pll_x", NULL),
67         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
68 };
69
70 static struct regulator_consumer_supply as3722_ldo1_supply[] = {
71         REGULATOR_SUPPLY("vddio_cam", "vi"),
72         REGULATOR_SUPPLY("pwrdet_cam", NULL),
73         REGULATOR_SUPPLY("vdd_cam_1v8_cam", NULL),
74         REGULATOR_SUPPLY("vif", "2-0010"),
75         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
76 };
77
78 static struct regulator_consumer_supply as3722_ldo2_supply[] = {
79         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
80         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
81         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
82         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
83         REGULATOR_SUPPLY("avdd_hsic_com", NULL),
84         REGULATOR_SUPPLY("avdd_hsic_mdm", NULL),
85         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
86         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
87         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
88 };
89
90 static struct regulator_consumer_supply as3722_ldo3_supply[] = {
91         REGULATOR_SUPPLY("vdd_rtc", NULL),
92 };
93
94 static struct regulator_consumer_supply as3722_ldo4_supply[] = {
95         REGULATOR_SUPPLY("vdd_2v7_hv", NULL),
96         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
97         REGULATOR_SUPPLY("vana", "2-0010"),
98 };
99
100 static struct regulator_consumer_supply as3722_ldo5_supply[] = {
101         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
102         REGULATOR_SUPPLY("vdig", "2-0010"),
103 };
104
105 static struct regulator_consumer_supply as3722_ldo6_supply[] = {
106         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
107         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
108 };
109
110 static struct regulator_consumer_supply as3722_ldo7_supply[] = {
111         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
112 };
113
114 static struct regulator_consumer_supply as3722_ldo9_supply[] = {
115         REGULATOR_SUPPLY("vdd_ts_3v0b_dis", NULL),
116 };
117
118 static struct regulator_consumer_supply as3722_ldo10_supply[] = {
119         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
120         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
121         REGULATOR_SUPPLY("imx135_reg1", NULL),
122         REGULATOR_SUPPLY("vdd", "2-000e"),
123 };
124
125 static struct regulator_consumer_supply as3722_ldo11_supply[] = {
126         REGULATOR_SUPPLY("vpp_fuse", NULL),
127 };
128
129 static struct regulator_consumer_supply as3722_sd0_supply[] = {
130         REGULATOR_SUPPLY("vdd_cpu", NULL),
131 };
132
133 static struct regulator_consumer_supply as3722_sd1_supply[] = {
134         REGULATOR_SUPPLY("vdd_core", NULL),
135 };
136
137 static struct regulator_consumer_supply as3722_sd2_supply[] = {
138         REGULATOR_SUPPLY("vddio_ddr", NULL),
139         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
140         REGULATOR_SUPPLY("vddio_ddr3", NULL),
141         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
142 };
143
144 static struct regulator_consumer_supply as3722_sd4_supply[] = {
145         REGULATOR_SUPPLY("avdd_pex_pll", NULL),
146         REGULATOR_SUPPLY("avddio_pex_pll", NULL),
147         REGULATOR_SUPPLY("dvddio_pex", NULL),
148         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
149         REGULATOR_SUPPLY("avdd_sata", NULL),
150         REGULATOR_SUPPLY("vdd_sata", NULL),
151         REGULATOR_SUPPLY("avdd_sata_pll", NULL),
152         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
153         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
154 };
155
156 static struct regulator_consumer_supply as3722_sd5_supply[] = {
157         REGULATOR_SUPPLY("vddio_sys", NULL),
158         REGULATOR_SUPPLY("vddio_sys_2", NULL),
159         REGULATOR_SUPPLY("vddio_audio", NULL),
160         REGULATOR_SUPPLY("pwrdet_audio", NULL),
161         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
162         REGULATOR_SUPPLY("pwrdet_sdmmc4", "sdhci-tegra.3"),
163         REGULATOR_SUPPLY("vddio_uart", NULL),
164         REGULATOR_SUPPLY("pwrdet_uart", NULL),
165         REGULATOR_SUPPLY("vddio_bb", NULL),
166         REGULATOR_SUPPLY("pwrdet_bb", NULL),
167         REGULATOR_SUPPLY("vddio_gmi", NULL),
168         REGULATOR_SUPPLY("pwrdet_nand", NULL),
169         REGULATOR_SUPPLY("avdd_osc", NULL),
170         /* emmc 1.8v misssing
171         keyboard & touchpad 1.8v missing */
172 };
173
174 static struct regulator_consumer_supply as3722_sd6_supply[] = {
175         REGULATOR_SUPPLY("vdd_gpu", NULL),
176 };
177
178 AMS_PDATA_INIT(sd0, NULL, 700000, 1350000, 1, 1, 1, 2);
179 AMS_PDATA_INIT(sd1, NULL, 700000, 1350000, 1, 1, 1, 1);
180 AMS_PDATA_INIT(sd2, NULL, 1350000, 1350000, 1, 1, 1, 0);
181 AMS_PDATA_INIT(sd4, NULL, 1050000, 1050000, 0, 1, 1, 0);
182 AMS_PDATA_INIT(sd5, NULL, 1800000, 1800000, 1, 1, 1, 0);
183 AMS_PDATA_INIT(sd6, NULL, 800000, 1200000, 1, 1, 1, 0);
184 AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1, 1);
185 AMS_PDATA_INIT(ldo1, NULL, 1800000, 1800000, 0, 1, 1, 0);
186 AMS_PDATA_INIT(ldo2, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 1, 1, 0);
187 AMS_PDATA_INIT(ldo3, NULL, 1000000, 1000000, 1, 1, 1, 0);
188 AMS_PDATA_INIT(ldo4, NULL, 2700000, 2700000, 0, 0, 1, 0);
189 AMS_PDATA_INIT(ldo5, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
190 AMS_PDATA_INIT(ldo6, NULL, 3300000, 3300000, 0, 0, 1, 0);
191 AMS_PDATA_INIT(ldo7, AS3722_SUPPLY(sd5), 1050000, 1050000, 0, 0, 1, 0);
192 AMS_PDATA_INIT(ldo9, NULL, 3300000, 3300000, 0, 1, 1, 0);
193 AMS_PDATA_INIT(ldo10, NULL, 2700000, 2700000, 0, 0, 1, 0);
194 AMS_PDATA_INIT(ldo11, NULL, 1800000, 1800000, 0, 0, 1, 0);
195
196 /* config settings are OTP plus initial state
197  * GPIOsignal_out at 20h not configurable through OTP and is initialized to
198  * zero. To enable output, the invert bit must be turned on.
199  * GPIOxcontrol register format
200  * bit(s)  bitname
201  * ---------------------
202  *  7     gpiox_invert   invert input or output
203  * 6:3    gpiox_iosf     0: normal
204  * 2:0    gpiox_mode     0: input, 1: output push/pull, 3: ADC input (tristate)
205  *
206  * Examples:
207  * otp  meaning
208  * ------------
209  * 0x3  gpiox_invert=0(no invert), gpiox_iosf=0(normal), gpiox_mode=3(ADC input)
210  * 0x81 gpiox_invert=1(invert), gpiox_iosf=0(normal), gpiox_mode=1(output)
211  *
212  * Note: output state should be defined for gpiox_mode = output.  Do not change
213  * the state of the invert bit for critical devices such as GPIO 7 which enables
214  * SDRAM. Driver applies invert mask to output state to configure GPIOsignal_out
215  * register correctly.
216  * E.g. Invert = 1, (requested) output state = 1 => GPIOsignal_out = 0
217  */
218 static struct as3722_gpio_config as3722_gpio_cfgs[] = {
219         {
220                 /* otp = 0x3 IGPU_PRDGD*/
221                 .gpio = AS3722_GPIO0,
222                 .mode = AS3722_GPIO_MODE_OUTPUT_VDDL,
223         },
224         {
225                 /* otp = 0x1  => REGEN_3 = LP0 gate (1.8V, 5 V)*/
226                 .gpio = AS3722_GPIO1,
227                 .invert     = AS3722_GPIO_CFG_INVERT, /* don't go into LP0 */
228                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
229                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
230         },
231         {
232                 /* otp = 0x3 PMU_REGEN1*/
233                 .gpio = AS3722_GPIO2,
234                 .invert     = AS3722_GPIO_CFG_INVERT, /* don't go into LP0 */
235                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
236                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
237         },
238         {
239                 /* otp = 0x03 AP THERMISTOR */
240                 .gpio = AS3722_GPIO3,
241                 .mode = AS3722_GPIO_MODE_ADC_IN,
242         },
243         {
244                 /* otp = 0x81 => on by default
245                  * gates EN_AVDD_LCD
246                  */
247                 .gpio       = AS3722_GPIO4,
248                 .invert     = AS3722_GPIO_CFG_NO_INVERT,
249                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
250                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
251         },
252         {
253                 /* otp = 0x3  CLK 23KHZ WIFI */
254                 .gpio = AS3722_GPIO5,
255                 .mode = AS3722_GPIO_MODE_ADC_IN,
256         },
257         {
258                 /* otp = 0x3  SKIN TEMP */
259                 .gpio = AS3722_GPIO6,
260                 .mode = AS3722_GPIO_MODE_ADC_IN,
261         },
262         {
263                 /* otp = 0x81  1.6V LP0*/
264                 .gpio       = AS3722_GPIO7,
265                 .invert     = AS3722_GPIO_CFG_NO_INVERT,
266                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
267                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
268         },
269 };
270
271 static struct as3722_rtc_platform_data as3722_rtc_pdata = {
272         .enable_clk32k  = 1,
273 };
274
275 static struct as3722_platform_data as3722_pdata = {
276         .reg_pdata[AS3722_LDO0] = &as3722_ldo0_reg_pdata,
277         .reg_pdata[AS3722_LDO1] = &as3722_ldo1_reg_pdata,
278         .reg_pdata[AS3722_LDO2] = &as3722_ldo2_reg_pdata,
279         .reg_pdata[AS3722_LDO3] = &as3722_ldo3_reg_pdata,
280         .reg_pdata[AS3722_LDO4] = &as3722_ldo4_reg_pdata,
281         .reg_pdata[AS3722_LDO5] = &as3722_ldo5_reg_pdata,
282         .reg_pdata[AS3722_LDO6] = &as3722_ldo6_reg_pdata,
283         .reg_pdata[AS3722_LDO7] = &as3722_ldo7_reg_pdata,
284         .reg_pdata[AS3722_LDO9] = &as3722_ldo9_reg_pdata,
285         .reg_pdata[AS3722_LDO10] = &as3722_ldo10_reg_pdata,
286         .reg_pdata[AS3722_LDO11] = &as3722_ldo11_reg_pdata,
287
288         .reg_pdata[AS3722_SD0] = &as3722_sd0_reg_pdata,
289         .reg_pdata[AS3722_SD1] = &as3722_sd1_reg_pdata,
290         .reg_pdata[AS3722_SD2] = &as3722_sd2_reg_pdata,
291         .reg_pdata[AS3722_SD4] = &as3722_sd4_reg_pdata,
292         .reg_pdata[AS3722_SD5] = &as3722_sd5_reg_pdata,
293         .reg_pdata[AS3722_SD6] = &as3722_sd6_reg_pdata,
294
295         .core_init_data = NULL,
296         .gpio_base = AS3722_GPIO_BASE,
297         .irq_base = AS3722_IRQ_BASE,
298         .use_internal_int_pullup = 0,
299         .use_internal_i2c_pullup = 0,
300         .num_gpio_cfgs = ARRAY_SIZE(as3722_gpio_cfgs),
301         .gpio_cfgs     = as3722_gpio_cfgs,
302         .rtc_pdata      = &as3722_rtc_pdata,
303         .use_power_off = true,
304         .enable_ldo3_tracking = true,
305         .disabe_ldo3_tracking_suspend = true,
306 };
307
308 static struct pca953x_platform_data tca6416_pdata = {
309         .gpio_base = PMU_TCA6416_GPIO_BASE,
310 };
311
312 static const struct i2c_board_info tca6416_expander[] = {
313         {
314                 I2C_BOARD_INFO("tca6416", 0x20),
315                 .platform_data = &tca6416_pdata,
316         },
317 };
318
319 static const struct i2c_board_info tca6408_expander[] = {
320         {
321                 I2C_BOARD_INFO("tca6408", 0x20),
322                 .platform_data = &tca6416_pdata,
323         },
324 };
325
326 static struct i2c_board_info __initdata as3722_regulators[] = {
327         {
328                 I2C_BOARD_INFO("as3722", 0x40),
329                 .flags = I2C_CLIENT_WAKE,
330                 .irq = INT_EXTERNAL_PMU,
331                 .platform_data = &as3722_pdata,
332         },
333 };
334
335 int __init laguna_as3722_regulator_init(void)
336 {
337         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
338         u32 pmc_ctrl;
339         struct board_info board_info;
340
341         tegra_get_board_info(&board_info);
342
343         /* AS3722: Normal state of INT request line is LOW.
344          * configure the power management controller to trigger PMU
345          * interrupts when HIGH.
346          */
347         pmc_ctrl = readl(pmc + PMC_CTRL);
348         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
349         regulator_has_full_constraints();
350         /* Set vdd_gpu init uV to 1V */
351         as3722_sd6_reg_idata.constraints.init_uV = 1000000;
352         printk(KERN_INFO "%s: i2c_register_board_info\n",
353                         __func__);
354         if (board_info.board_id == BOARD_PM358) {
355                 switch (board_info.fab) {
356                 case BOARD_FAB_A01:
357                         as3722_pdata.reg_pdata[AS3722_LDO5] =
358                                 &as3722_ldo7_reg_pdata;
359                         as3722_pdata.reg_pdata[AS3722_LDO7] =
360                                 &as3722_ldo5_reg_pdata;
361                         as3722_pdata.reg_pdata[AS3722_LDO4] =
362                                 &as3722_ldo10_reg_pdata;
363                         as3722_pdata.reg_pdata[AS3722_LDO10] =
364                                 &as3722_ldo4_reg_pdata;
365                         break;
366                 default:
367                         break;
368                 }
369         }
370         i2c_register_board_info(4, as3722_regulators,
371                         ARRAY_SIZE(as3722_regulators));
372         if (board_info.board_id == BOARD_PM358 &&
373                         board_info.fab == BOARD_FAB_A00)
374                 i2c_register_board_info(0, tca6408_expander,
375                                 ARRAY_SIZE(tca6408_expander));
376         else if (board_info.board_id == BOARD_PM359 ||
377                         board_info.board_id == BOARD_PM358)
378                 i2c_register_board_info(0, tca6416_expander,
379                                 ARRAY_SIZE(tca6416_expander));
380         return 0;
381 }
382
383 static struct tegra_suspend_platform_data laguna_suspend_data = {
384         .cpu_timer      = 2000,
385         .cpu_off_timer  = 2000,
386         .suspend_mode   = TEGRA_SUSPEND_NONE,
387         .core_timer     = 0x7e7e,
388         .core_off_timer = 2000,
389         .corereq_high   = true,
390         .sysclkreq_high = true,
391         .cpu_lp2_min_residency = 1000,
392 };
393
394 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
395 /* board parameters for cpu dfll */
396 static struct tegra_cl_dvfs_cfg_param laguna_cl_dvfs_param = {
397         .sample_rate = 12500,
398
399         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
400         .cf = 10,
401         .ci = 0,
402         .cg = 2,
403
404         .droop_cut_value = 0xF,
405         .droop_restore_ramp = 0x0,
406         .scale_out_ramp = 0x0,
407 };
408 #endif
409
410 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
411 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
412 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
413 static inline void fill_reg_map(void)
414 {
415         int i;
416         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
417                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
418                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
419         }
420 }
421
422 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
423 static struct tegra_cl_dvfs_platform_data laguna_cl_dvfs_data = {
424         .dfll_clk_name = "dfll_cpu",
425         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
426         .u.pmu_i2c = {
427                 .fs_rate = 400000,
428                 .slave_addr = 0x86,
429                 .reg = 0x00,
430         },
431         .vdd_map = pmu_cpu_vdd_map,
432         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
433
434         .cfg_param = &laguna_cl_dvfs_param,
435 };
436
437 static int __init laguna_cl_dvfs_init(void)
438 {
439         fill_reg_map();
440         tegra_cl_dvfs_device.dev.platform_data = &laguna_cl_dvfs_data;
441         platform_device_register(&tegra_cl_dvfs_device);
442
443         return 0;
444 }
445 #endif
446
447 /* Always ON /Battery regulator */
448 static struct regulator_consumer_supply fixed_reg_battery_supply[] = {
449         REGULATOR_SUPPLY("vdd_sys_bl", NULL),
450 };
451
452 /* Always ON 1.8v */
453 static struct regulator_consumer_supply fixed_reg_aon_1v8_supply[] = {
454         REGULATOR_SUPPLY("vdd_1v8_emmc", NULL),
455         REGULATOR_SUPPLY("vdd_1v8b_com_f", NULL),
456         REGULATOR_SUPPLY("vdd_1v8b_gps_f", NULL),
457 };
458
459 /* Always ON 3.3v */
460 static struct regulator_consumer_supply fixed_reg_aon_3v3_supply[] = {
461         REGULATOR_SUPPLY("vdd_3v3_emmc", NULL),
462         REGULATOR_SUPPLY("vdd_com_3v3", NULL),
463 };
464
465 /* Always ON 1v2 */
466 static struct regulator_consumer_supply fixed_reg_aon_1v2_supply[] = {
467         REGULATOR_SUPPLY("vdd_1v2_bb_hsic", NULL),
468 };
469
470 /* EN_USB0_VBUS From TEGRA GPIO PN4 */
471 static struct regulator_consumer_supply fixed_reg_usb0_vbus_supply[] = {
472         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
473         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
474         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
475 };
476
477 /* EN_USB1_VBUS From TEGRA GPIO PN5 */
478 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
479         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
480         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
481 };
482
483 /* EN_USB2_VBUS From TEGRA GPIO PPF1 */
484 static struct regulator_consumer_supply fixed_reg_usb2_vbus_supply[] = {
485         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
486         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
487 };
488
489
490 /* Gated by GPIO_PK6  in FAB B and further*/
491 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
492         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
493 };
494
495 /* Gated by GPIO_PH7  in FAB B and further*/
496 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_supply[] = {
497         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
498 };
499
500 /* VDD_LCD_BL DAP3_DOUT */
501 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_supply[] = {
502         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
503 };
504
505 /* LCD_BL_EN GMI_AD10 */
506 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
507         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
508 };
509
510 /* AS3722 GPIO1*/
511 static struct regulator_consumer_supply fixed_reg_3v3_supply[] = {
512         REGULATOR_SUPPLY("hvdd_pex", NULL),
513         REGULATOR_SUPPLY("hvdd_pex_pll", NULL),
514         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
515         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5645.0"),
516         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5639.0"),
517         REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
518         REGULATOR_SUPPLY("vdd_nfc_3v3", NULL),
519         REGULATOR_SUPPLY("vdd_3v3_sensor", NULL),
520         REGULATOR_SUPPLY("vdd_kp_3v3", NULL),
521         REGULATOR_SUPPLY("vdd_tp_3v3", NULL),
522         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
523         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
524         REGULATOR_SUPPLY("vdd", "1-004c"),
525         REGULATOR_SUPPLY("vdd", "0-0048"),
526         REGULATOR_SUPPLY("vdd", "0-0069"),
527         REGULATOR_SUPPLY("vdd", "0-000c"),
528         REGULATOR_SUPPLY("vdd", "0-0077"),
529         REGULATOR_SUPPLY("vin", "2-0030"),
530 };
531
532 /* AS3722 GPIO1*/
533 static struct regulator_consumer_supply fixed_reg_5v0_supply[] = {
534         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
535         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
536         REGULATOR_SUPPLY("vdd_5v0_sensor", NULL),
537 };
538
539 static struct regulator_consumer_supply fixed_reg_dcdc_1v8_supply[] = {
540         REGULATOR_SUPPLY("avdd_lvds0_pll", NULL),
541         REGULATOR_SUPPLY("dvdd_lcd", NULL),
542         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
543         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645.0"),
544         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645.0"),
545         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639.0"),
546         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639.0"),
547         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639.0"),
548         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645.0"),
549         REGULATOR_SUPPLY("vdd_1v8b_nfc", NULL),
550         REGULATOR_SUPPLY("vdd_1v8_sensor", NULL),
551         REGULATOR_SUPPLY("vdd_1v8_sdmmc", NULL),
552         REGULATOR_SUPPLY("vdd_kp_1v8", NULL),
553         REGULATOR_SUPPLY("vdd_tp_1v8", NULL),
554         REGULATOR_SUPPLY("vdd_modem_1v8", NULL),
555         REGULATOR_SUPPLY("vdd_1v8b", "0-0048"),
556         REGULATOR_SUPPLY("vlogic", "0-0069"),
557         REGULATOR_SUPPLY("vid", "0-000c"),
558         REGULATOR_SUPPLY("vddio", "0-0077"),
559         REGULATOR_SUPPLY("vi2c", "2-0030"),
560 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
561         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
562         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
563         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
564         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
565         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
566 #endif
567 };
568
569 /* gated by TCA6416 GPIO EXP GPIO0 */
570 static struct regulator_consumer_supply fixed_reg_dcdc_1v2_supply[] = {
571         REGULATOR_SUPPLY("vdd_1v2_en", NULL),
572 };
573
574 /* AMS GPIO2 */
575 static struct regulator_consumer_supply fixed_reg_as3722_gpio2_supply[] = {
576         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
577         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
578         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
579         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
580         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
581 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
582         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
583         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
584         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
585         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
586         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
587 #endif
588         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
589         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
590         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
591         REGULATOR_SUPPLY("pwrdet_hv", NULL),
592         REGULATOR_SUPPLY("hvdd_sata", NULL),
593 };
594
595 /* gated by AS3722 GPIO4 */
596 static struct regulator_consumer_supply fixed_reg_lcd_supply[] = {
597         REGULATOR_SUPPLY("avdd_lcd", NULL),
598 };
599
600 /* gated by GPIO_PR0 */
601 static struct regulator_consumer_supply fixed_reg_sdmmc_en_supply[] = {
602         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.1"),
603         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
604 };
605
606 /* only adding for PM358 */
607 static struct regulator_consumer_supply fixed_reg_vdd_cdc_1v2_aud_supply[] = {
608         REGULATOR_SUPPLY("ldoen", "tegra-snd-rt5639.0"),
609 };
610
611 static struct regulator_consumer_supply fixed_reg_vdd_amp_shut_aud_supply[] = {
612         REGULATOR_SUPPLY("epamp", "tegra-snd-rt5645.0"),
613 };
614
615 static struct regulator_consumer_supply fixed_reg_vdd_dsi_mux_supply[] = {
616         REGULATOR_SUPPLY("vdd_3v3_dsi", "NULL"),
617 };
618
619 /* Macro for defining fixed regulator sub device data */
620 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
621 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,           \
622                 _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
623 static struct regulator_init_data ri_data_##_var =              \
624 {                                                               \
625         .supply_regulator = _in_supply,                         \
626         .num_consumer_supplies =                                \
627         ARRAY_SIZE(fixed_reg_##_name##_supply),                 \
628         .consumer_supplies = fixed_reg_##_name##_supply,        \
629         .constraints = {                                        \
630                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
631                                 REGULATOR_MODE_STANDBY),        \
632                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
633                                 REGULATOR_CHANGE_STATUS |       \
634                                 REGULATOR_CHANGE_VOLTAGE),      \
635                 .always_on = _always_on,                        \
636                 .boot_on = _boot_on,                            \
637         },                                                      \
638 };                                                              \
639 static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
640 {                                                               \
641         .supply_name = FIXED_SUPPLY(_name),                     \
642         .microvolts = _millivolts * 1000,                       \
643         .gpio = _gpio_nr,                                       \
644         .gpio_is_open_drain = _open_drain,                      \
645         .enable_high = _active_high,                            \
646         .enabled_at_boot = _boot_state,                         \
647         .init_data = &ri_data_##_var,                           \
648 };                                                              \
649 static struct platform_device fixed_reg_##_var##_dev = {        \
650         .name = "reg-fixed-voltage",                            \
651         .id = _id,                                              \
652         .dev = {                                                \
653                 .platform_data = &fixed_reg_##_var##_pdata,     \
654         },                                                      \
655 }
656
657 FIXED_REG(0,    battery,        battery,        NULL,   0,      0,
658                 -1,     false, true,    0,      8400);
659
660 FIXED_REG(1,    aon_1v8,        aon_1v8,        NULL,   0,      0,
661                 -1,     false, true,    0,      1800);
662
663 FIXED_REG(2,    aon_3v3,        aon_3v3,        NULL,   0,      0,
664                 -1,     false, true,    0,      3300);
665
666 FIXED_REG(3,    aon_1v2,        aon_1v2,        NULL,   0,      0,
667                 -1,     false, true,    0,      1200);
668
669 FIXED_REG(4,    vdd_hdmi_5v0,   vdd_hdmi_5v0,   NULL,   0,      0,
670                 TEGRA_GPIO_PK6, false,  true,   0,      5000);
671
672 FIXED_REG(5,    vdd_hdmi,       vdd_hdmi,       AS3722_SUPPLY(sd4),
673                 0,      0,
674                 TEGRA_GPIO_PH7, false,  false,  0,      3300);
675
676 FIXED_REG(6,    usb0_vbus,      usb0_vbus,      NULL,   0,      0,
677                 TEGRA_GPIO_PN4, true,   true,   0,      5000);
678
679 FIXED_REG(7,    usb1_vbus,      usb1_vbus,      NULL,   0,      0,
680                 TEGRA_GPIO_PN5, true,   true,   0,      5000);
681
682 FIXED_REG(8,    usb2_vbus,      usb2_vbus,      NULL,   0,      0,
683                 TEGRA_GPIO_PFF1,        false,  true,   0,      5000);
684
685 FIXED_REG(9,    vdd_lcd_bl,     vdd_lcd_bl,     NULL,   0,      0,
686                 TEGRA_GPIO_PP2, false,  true,   0,      3300);
687
688 FIXED_REG(10,   lcd_bl_en,      lcd_bl_en,      NULL,   0,      0,
689                 TEGRA_GPIO_PH2, false,  true,   0,      5000);
690
691 FIXED_REG(11,   3v3,            3v3,            NULL,   0,      0,
692                 -1,     false,  true,   0,      3300);
693
694 FIXED_REG(12,   5v0,            5v0,            NULL,   0,      0,
695                 -1,     false,  true,   0,      5000);
696
697 FIXED_REG(13,   dcdc_1v8,       dcdc_1v8,       NULL,   0,      0,
698                 -1,     false,  true,   0,      1800);
699
700 FIXED_REG(14,    dcdc_1v2, dcdc_1v2,    NULL,   0,      0,
701                 PMU_TCA6416_GPIO_BASE,     false,  true,   0,      1200);
702
703 FIXED_REG(15,   as3722_gpio2,   as3722_gpio2,           NULL,   0,      0,
704                 AS3722_GPIO_BASE + AS3722_GPIO2,        false,  false,  0,      3300);
705
706 FIXED_REG(16,   lcd,            lcd,            NULL,   0,      0,
707                 AS3722_GPIO_BASE + AS3722_GPIO4,        false,  true,   0,      3300);
708
709 FIXED_REG(17,   sdmmc_en,               sdmmc_en,       NULL,   0,      0,
710                 TEGRA_GPIO_PR0,         false,  true,   0,      3300);
711
712 FIXED_REG(18,   vdd_cdc_1v2_aud,        vdd_cdc_1v2_aud,        NULL,   0,      0,
713                 PMU_TCA6416_GPIO(2),    false,  true,   0,      1200);
714
715 FIXED_REG(19,   vdd_amp_shut_aud,       vdd_amp_shut_aud,       NULL,   0,      0,
716                 PMU_TCA6416_GPIO(3),    false,  true,   0,      1200);
717
718 FIXED_REG(20,   vdd_dsi_mux,            vdd_dsi_mux,    NULL,   0,      0,
719                 PMU_TCA6416_GPIO(13),   false,  true,   0,      3300);
720 /*
721  * Creating the fixed regulator device tables
722  */
723
724 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
725
726 #define LAGUNA_COMMON_FIXED_REG                 \
727         ADD_FIXED_REG(battery),                 \
728         ADD_FIXED_REG(aon_1v8),                 \
729         ADD_FIXED_REG(aon_3v3),                 \
730         ADD_FIXED_REG(aon_1v2),                 \
731         ADD_FIXED_REG(vdd_hdmi_5v0),            \
732         ADD_FIXED_REG(vdd_hdmi),                \
733         ADD_FIXED_REG(usb0_vbus),               \
734         ADD_FIXED_REG(usb1_vbus),               \
735         ADD_FIXED_REG(usb2_vbus),               \
736         ADD_FIXED_REG(vdd_lcd_bl),              \
737         ADD_FIXED_REG(lcd_bl_en),               \
738         ADD_FIXED_REG(3v3),                     \
739         ADD_FIXED_REG(5v0),                     \
740         ADD_FIXED_REG(dcdc_1v8),                \
741         ADD_FIXED_REG(as3722_gpio2),            \
742         ADD_FIXED_REG(lcd),                     \
743         ADD_FIXED_REG(sdmmc_en)
744
745 #define LAGUNA_PM358_FIXED_REG          \
746         ADD_FIXED_REG(dcdc_1v2),        \
747         ADD_FIXED_REG(vdd_cdc_1v2_aud), \
748         ADD_FIXED_REG(vdd_amp_shut_aud), \
749         ADD_FIXED_REG(vdd_dsi_mux)
750
751 #define LAGUNA_PM359_FIXED_REG          \
752         ADD_FIXED_REG(dcdc_1v2),        \
753         ADD_FIXED_REG(vdd_cdc_1v2_aud)
754
755
756 /* Gpio switch regulator platform data for laguna pm358 ERS*/
757 static struct platform_device *fixed_reg_devs_pm358[] = {
758         LAGUNA_COMMON_FIXED_REG,
759         LAGUNA_PM358_FIXED_REG
760 };
761
762 /* Gpio switch regulator platform data for laguna pm359 ERS-S*/
763 static struct platform_device *fixed_reg_devs_pm359[] = {
764         LAGUNA_COMMON_FIXED_REG,
765         LAGUNA_PM359_FIXED_REG
766 };
767
768 /* Gpio switch regulator platform data for laguna pm363 FFD*/
769 static struct platform_device *fixed_reg_devs_pm363[] = {
770         LAGUNA_COMMON_FIXED_REG
771 };
772
773 static int __init laguna_fixed_regulator_init(void)
774 {
775         struct board_info board_info;
776
777         if (!of_machine_is_compatible("nvidia,ardbeg"))
778                 return 0;
779
780         tegra_get_board_info(&board_info);
781         if (board_info.board_id == BOARD_PM358)
782                 return platform_add_devices(fixed_reg_devs_pm358,
783                                 ARRAY_SIZE(fixed_reg_devs_pm358));
784         else if (board_info.board_id == BOARD_PM359)
785                 return platform_add_devices(fixed_reg_devs_pm359,
786                                 ARRAY_SIZE(fixed_reg_devs_pm359));
787         else if (board_info.board_id == BOARD_PM363)
788                 return platform_add_devices(fixed_reg_devs_pm363,
789                                 ARRAY_SIZE(fixed_reg_devs_pm363));
790
791         return 0;
792 }
793
794 subsys_initcall_sync(laguna_fixed_regulator_init);
795
796 int __init laguna_regulator_init(void)
797 {
798
799 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
800         laguna_cl_dvfs_init();
801 #endif
802         laguna_as3722_regulator_init();
803
804         return 0;
805 }
806
807 int __init laguna_suspend_init(void)
808 {
809         tegra_init_suspend(&laguna_suspend_data);
810         return 0;
811 }
812
813 int __init laguna_edp_init(void)
814 {
815 #ifdef CONFIG_TEGRA_EDP_LIMITS
816         unsigned int regulator_mA;
817
818         regulator_mA = get_maximum_cpu_current_supported();
819         if (!regulator_mA)
820                 regulator_mA = 15000;
821
822         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
823
824         tegra_init_cpu_edp_limits(regulator_mA);
825 #endif
826         return 0;
827 }
828
829
830 static struct soctherm_platform_data laguna_soctherm_data = {
831         .therm = {
832                 [THERM_CPU] = {
833                         .zone_enable = true,
834                         .passive_delay = 1000,
835                         .hotspot_offset = 6000,
836                         .num_trips = 3,
837                         .trips = {
838                                 {
839                                         .cdev_type = "tegra-balanced",
840                                         .trip_temp = 90000,
841                                         .trip_type = THERMAL_TRIP_PASSIVE,
842                                         .upper = THERMAL_NO_LIMIT,
843                                         .lower = THERMAL_NO_LIMIT,
844                                 },
845                                 {
846                                         .cdev_type = "tegra-heavy",
847                                         .trip_temp = 100000,
848                                         .trip_type = THERMAL_TRIP_HOT,
849                                         .upper = THERMAL_NO_LIMIT,
850                                         .lower = THERMAL_NO_LIMIT,
851                                 },
852                                 {
853                                         .cdev_type = "tegra-shutdown",
854                                         .trip_temp = 102000,
855                                         .trip_type = THERMAL_TRIP_CRITICAL,
856                                         .upper = THERMAL_NO_LIMIT,
857                                         .lower = THERMAL_NO_LIMIT,
858                                 },
859                         },
860                 },
861                 [THERM_GPU] = {
862                         .zone_enable = true,
863                         .passive_delay = 1000,
864                         .hotspot_offset = 6000,
865                         .num_trips = 3,
866                         .trips = {
867                                 {
868                                         .cdev_type = "tegra-balanced",
869                                         .trip_temp = 90000,
870                                         .trip_type = THERMAL_TRIP_PASSIVE,
871                                         .upper = THERMAL_NO_LIMIT,
872                                         .lower = THERMAL_NO_LIMIT,
873                                 },
874                                 {
875                                         .cdev_type = "tegra-heavy",
876                                         .trip_temp = 100000,
877                                         .trip_type = THERMAL_TRIP_HOT,
878                                         .upper = THERMAL_NO_LIMIT,
879                                         .lower = THERMAL_NO_LIMIT,
880                                 },
881                                 {
882                                         .cdev_type = "tegra-shutdown",
883                                         .trip_temp = 102000,
884                                         .trip_type = THERMAL_TRIP_CRITICAL,
885                                         .upper = THERMAL_NO_LIMIT,
886                                         .lower = THERMAL_NO_LIMIT,
887                                 },
888                         },
889                 },
890                 [THERM_PLL] = {
891                         .zone_enable = true,
892                 },
893         },
894         .throttle = {
895                 [THROTTLE_HEAVY] = {
896                         .devs = {
897                                 [THROTTLE_DEV_CPU] = {
898                                         .enable = 1,
899                                 },
900                         },
901                 },
902         },
903 };
904
905 int __init laguna_soctherm_init(void)
906 {
907         tegra_platform_edp_init(laguna_soctherm_data.therm[THERM_CPU].trips,
908                         &laguna_soctherm_data.therm[THERM_CPU].num_trips,
909                         8000); /* edp temperature margin */
910         tegra_add_tj_trips(laguna_soctherm_data.therm[THERM_CPU].trips,
911                         &laguna_soctherm_data.therm[THERM_CPU].num_trips);
912
913         return tegra11_soctherm_init(&laguna_soctherm_data);
914 }