ARM: tegra: pcie: Remove dock detect variable
[linux-3.10.git] / arch / arm / mach-tegra / board-laguna-power.c
1 /*
2  * arch/arm/mach-tegra/board-laguna-power.c
3  *
4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca954x.h>
22 #include <linux/i2c/pca953x.h>
23 #include <linux/pda_power.h>
24 #include <linux/platform_device.h>
25 #include <linux/resource.h>
26 #include <linux/io.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/driver.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/mfd/as3722-plat.h>
31 #include <linux/gpio.h>
32 #include <linux/regulator/userspace-consumer.h>
33 #include <linux/pid_thermal_gov.h>
34 #include <linux/power/bq2471x-charger.h>
35
36 #include <asm/mach-types.h>
37
38 #include <mach/irqs.h>
39 #include <mach/edp.h>
40 #include <mach/gpio-tegra.h>
41
42 #include "cpu-tegra.h"
43 #include "pm.h"
44 #include "tegra-board-id.h"
45 #include "board.h"
46 #include "gpio-names.h"
47 #include "board-common.h"
48 #include "board-pmu-defines.h"
49 #include "board-ardbeg.h"
50 #include "tegra_cl_dvfs.h"
51 #include "devices.h"
52 #include "tegra11_soctherm.h"
53 #include "iomap.h"
54
55 #define PMC_CTRL                0x0
56 #define PMC_CTRL_INTR_LOW       (1 << 17)
57 #define AS3722_SUPPLY(_name) "as3722_"#_name
58
59 static struct regulator_consumer_supply as3722_ldo0_supply[] = {
60         REGULATOR_SUPPLY("avdd_pll_m", NULL),
61         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
62         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
63         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
64         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
65         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
66         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
67         REGULATOR_SUPPLY("avdd_pll_x", NULL),
68         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
69 };
70
71 static struct regulator_consumer_supply as3722_ldo1_supply[] = {
72         REGULATOR_SUPPLY("vddio_cam", "vi"),
73         REGULATOR_SUPPLY("pwrdet_cam", NULL),
74         REGULATOR_SUPPLY("vdd_cam_1v8_cam", NULL),
75         REGULATOR_SUPPLY("vif", "2-0010"),
76         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
77 };
78
79 static struct regulator_consumer_supply as3722_ldo2_supply[] = {
80         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
81         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
82         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.0"),
83         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.1"),
84         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
85         REGULATOR_SUPPLY("avdd_hsic_com", NULL),
86         REGULATOR_SUPPLY("avdd_hsic_mdm", NULL),
87         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
88         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
89         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
90 };
91
92 static struct regulator_consumer_supply as3722_ldo3_supply[] = {
93         REGULATOR_SUPPLY("vdd_rtc", NULL),
94 };
95
96 static struct regulator_consumer_supply as3722_ldo4_supply[] = {
97         REGULATOR_SUPPLY("vdd_2v7_hv", NULL),
98         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
99         REGULATOR_SUPPLY("vana", "2-0010"),
100 };
101
102 static struct regulator_consumer_supply as3722_ldo5_supply[] = {
103         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
104         REGULATOR_SUPPLY("vdig", "2-0010"),
105 };
106
107 static struct regulator_consumer_supply as3722_ldo6_supply[] = {
108         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
109         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
110 };
111
112 static struct regulator_consumer_supply as3722_ldo7_supply[] = {
113         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
114 };
115
116 static struct regulator_consumer_supply as3722_ldo9_supply[] = {
117         REGULATOR_SUPPLY("avdd", "spi0.0"),
118 };
119
120 static struct regulator_consumer_supply as3722_ldo10_supply[] = {
121         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
122         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
123         REGULATOR_SUPPLY("imx135_reg1", NULL),
124         REGULATOR_SUPPLY("vdd", "2-000e"),
125 };
126
127 static struct regulator_consumer_supply as3722_ldo11_supply[] = {
128         REGULATOR_SUPPLY("vpp_fuse", NULL),
129 };
130
131 static struct regulator_consumer_supply as3722_sd0_supply[] = {
132         REGULATOR_SUPPLY("vdd_cpu", NULL),
133 };
134
135 static struct regulator_consumer_supply as3722_sd1_supply[] = {
136         REGULATOR_SUPPLY("vdd_core", NULL),
137 };
138
139 static struct regulator_consumer_supply as3722_sd2_supply[] = {
140         REGULATOR_SUPPLY("vddio_ddr", NULL),
141         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
142         REGULATOR_SUPPLY("vddio_ddr3", NULL),
143         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
144 };
145
146 static struct regulator_consumer_supply as3722_sd4_supply[] = {
147         REGULATOR_SUPPLY("avdd_pex_pll", NULL),
148         REGULATOR_SUPPLY("avddio_pex_pll", NULL),
149         REGULATOR_SUPPLY("dvddio_pex", NULL),
150         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
151         REGULATOR_SUPPLY("avdd_sata", NULL),
152         REGULATOR_SUPPLY("vdd_sata", NULL),
153         REGULATOR_SUPPLY("avdd_sata_pll", NULL),
154         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
155         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
156 };
157
158 static struct regulator_consumer_supply as3722_sd5_supply[] = {
159         REGULATOR_SUPPLY("vddio_sys", NULL),
160         REGULATOR_SUPPLY("vddio_sys_2", NULL),
161         REGULATOR_SUPPLY("vddio_audio", NULL),
162         REGULATOR_SUPPLY("pwrdet_audio", NULL),
163         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
164         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
165         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
166         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
167         REGULATOR_SUPPLY("vddio_uart", NULL),
168         REGULATOR_SUPPLY("pwrdet_uart", NULL),
169         REGULATOR_SUPPLY("vddio_bb", NULL),
170         REGULATOR_SUPPLY("pwrdet_bb", NULL),
171         REGULATOR_SUPPLY("vddio_gmi", NULL),
172         REGULATOR_SUPPLY("pwrdet_nand", NULL),
173         REGULATOR_SUPPLY("avdd_osc", NULL),
174         /* emmc 1.8v misssing
175         keyboard & touchpad 1.8v missing */
176 };
177
178 static struct regulator_consumer_supply as3722_sd6_supply[] = {
179         REGULATOR_SUPPLY("vdd_gpu", NULL),
180 };
181
182 AMS_PDATA_INIT(sd0, NULL, 700000, 1400000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE2);
183 AMS_PDATA_INIT(sd1, NULL, 700000, 1350000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
184 AMS_PDATA_INIT(sd2, NULL, 1350000, 1350000, 1, 1, 1, 0);
185 AMS_PDATA_INIT(sd4, NULL, 1050000, 1050000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
186 AMS_PDATA_INIT(sd5, NULL, 1800000, 1800000, 1, 1, 1, 0);
187 AMS_PDATA_INIT(sd6, NULL, 650000, 1200000, 0, 1, 1, 0);
188 AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
189 AMS_PDATA_INIT(ldo1, NULL, 1800000, 1800000, 0, 1, 1, 0);
190 AMS_PDATA_INIT(ldo2, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 1, 1, 0);
191 AMS_PDATA_INIT(ldo3, NULL, 800000, 800000, 1, 1, 1, 0);
192 AMS_PDATA_INIT(ldo4, NULL, 2700000, 2700000, 0, 0, 1, 0);
193 AMS_PDATA_INIT(ldo5, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
194 AMS_PDATA_INIT(ldo6, NULL, 1800000, 3300000, 0, 0, 1, 0);
195 AMS_PDATA_INIT(ldo7, AS3722_SUPPLY(sd5), 1050000, 1050000, 0, 0, 1, 0);
196 AMS_PDATA_INIT(ldo9, NULL, 3300000, 3300000, 0, 1, 1, 0);
197 AMS_PDATA_INIT(ldo10, NULL, 2700000, 2700000, 0, 0, 1, 0);
198 AMS_PDATA_INIT(ldo11, NULL, 1800000, 1800000, 0, 0, 1, 0);
199
200 static struct as3722_pinctrl_platform_data as3722_pctrl_pdata[] = {
201         AS3722_PIN_CONTROL("gpio0", "gpio", NULL, NULL, NULL, "output-low"),
202         AS3722_PIN_CONTROL("gpio1", "gpio", NULL, NULL, NULL, "output-high"),
203         AS3722_PIN_CONTROL("gpio2", "gpio", NULL, NULL, NULL, "output-high"),
204         AS3722_PIN_CONTROL("gpio3", "gpio", NULL, NULL, "enabled", NULL),
205         AS3722_PIN_CONTROL("gpio4", "gpio", NULL, NULL, NULL, "output-high"),
206         AS3722_PIN_CONTROL("gpio5", "gpio", "pull-down", NULL, "enabled", NULL),
207         AS3722_PIN_CONTROL("gpio6", "gpio", NULL, NULL, "enabled", NULL),
208         AS3722_PIN_CONTROL("gpio7", "gpio", NULL, NULL, NULL, "output-high"),
209 };
210
211 static struct as3722_adc_extcon_platform_data as3722_adc_extcon_pdata = {
212         .connection_name = "as3722-extcon",
213         .enable_adc1_continuous_mode = true,
214         .enable_low_voltage_range = true,
215         .adc_channel = 12,
216         .hi_threshold =  0x100,
217         .low_threshold = 0x80,
218 };
219
220 static struct as3722_platform_data as3722_pdata = {
221         .reg_pdata[AS3722_LDO0] = &as3722_ldo0_reg_pdata,
222         .reg_pdata[AS3722_LDO1] = &as3722_ldo1_reg_pdata,
223         .reg_pdata[AS3722_LDO2] = &as3722_ldo2_reg_pdata,
224         .reg_pdata[AS3722_LDO3] = &as3722_ldo3_reg_pdata,
225         .reg_pdata[AS3722_LDO4] = &as3722_ldo4_reg_pdata,
226         .reg_pdata[AS3722_LDO5] = &as3722_ldo5_reg_pdata,
227         .reg_pdata[AS3722_LDO6] = &as3722_ldo6_reg_pdata,
228         .reg_pdata[AS3722_LDO7] = &as3722_ldo7_reg_pdata,
229         .reg_pdata[AS3722_LDO9] = &as3722_ldo9_reg_pdata,
230         .reg_pdata[AS3722_LDO10] = &as3722_ldo10_reg_pdata,
231         .reg_pdata[AS3722_LDO11] = &as3722_ldo11_reg_pdata,
232
233         .reg_pdata[AS3722_SD0] = &as3722_sd0_reg_pdata,
234         .reg_pdata[AS3722_SD1] = &as3722_sd1_reg_pdata,
235         .reg_pdata[AS3722_SD2] = &as3722_sd2_reg_pdata,
236         .reg_pdata[AS3722_SD4] = &as3722_sd4_reg_pdata,
237         .reg_pdata[AS3722_SD5] = &as3722_sd5_reg_pdata,
238         .reg_pdata[AS3722_SD6] = &as3722_sd6_reg_pdata,
239
240         .gpio_base = AS3722_GPIO_BASE,
241         .irq_base = AS3722_IRQ_BASE,
242         .use_internal_int_pullup = 0,
243         .use_internal_i2c_pullup = 0,
244         .pinctrl_pdata = as3722_pctrl_pdata,
245         .num_pinctrl = ARRAY_SIZE(as3722_pctrl_pdata),
246         .enable_clk32k_out = true,
247         .use_power_off = true,
248         .extcon_pdata = &as3722_adc_extcon_pdata,
249         .major_rev = 1,
250         .minor_rev = 1,
251 };
252
253 static struct pca953x_platform_data tca6416_pdata = {
254         .gpio_base = PMU_TCA6416_GPIO_BASE,
255 };
256
257 static const struct i2c_board_info tca6416_expander[] = {
258         {
259                 I2C_BOARD_INFO("tca6416", 0x20),
260                 .platform_data = &tca6416_pdata,
261         },
262 };
263
264 static const struct i2c_board_info tca6408_expander[] = {
265         {
266                 I2C_BOARD_INFO("tca6408", 0x20),
267                 .platform_data = &tca6416_pdata,
268         },
269 };
270
271 struct bq2471x_platform_data laguna_bq2471x_pdata = {
272         .charge_broadcast_mode = 1,
273         .gpio_active_low = 1,
274         .gpio = TEGRA_GPIO_PK3,
275 };
276
277 static struct i2c_board_info __initdata bq2471x_boardinfo[] = {
278         {
279                 I2C_BOARD_INFO("bq2471x", 0x09),
280                 .platform_data  = &laguna_bq2471x_pdata,
281         },
282 };
283
284 static struct i2c_board_info __initdata as3722_regulators[] = {
285         {
286                 I2C_BOARD_INFO("as3722", 0x40),
287                 .flags = I2C_CLIENT_WAKE,
288                 .irq = INT_EXTERNAL_PMU,
289                 .platform_data = &as3722_pdata,
290         },
291 };
292
293 int __init laguna_as3722_regulator_init(void)
294 {
295         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
296         u32 pmc_ctrl;
297         struct board_info board_info;
298
299         tegra_get_board_info(&board_info);
300
301         /* AS3722: Normal state of INT request line is LOW.
302          * configure the power management controller to trigger PMU
303          * interrupts when HIGH.
304          */
305         pmc_ctrl = readl(pmc + PMC_CTRL);
306         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
307         regulator_has_full_constraints();
308         /* Set vdd_gpu init uV to 1V */
309         as3722_sd6_reg_idata.constraints.init_uV = 1000000;
310
311         /* Set overcurrent of rails. */
312         as3722_sd6_reg_idata.constraints.min_uA = 3500000;
313         as3722_sd6_reg_idata.constraints.max_uA = 3500000;
314
315         as3722_sd0_reg_idata.constraints.min_uA = 3500000;
316         as3722_sd0_reg_idata.constraints.max_uA = 3500000;
317
318         as3722_sd1_reg_idata.constraints.min_uA = 2500000;
319         as3722_sd1_reg_idata.constraints.max_uA = 2500000;
320
321         as3722_ldo3_reg_pdata.enable_tracking = true;
322         as3722_ldo3_reg_pdata.disable_tracking_suspend = true;
323
324         if ((board_info.board_id == BOARD_PM359) &&
325                                 (board_info.major_revision == 'C'))
326                 as3722_pdata.minor_rev = 2;
327
328         printk(KERN_INFO "%s: i2c_register_board_info\n",
329                         __func__);
330         if (board_info.board_id == BOARD_PM358) {
331                 switch (board_info.fab) {
332                 case BOARD_FAB_A01:
333                         as3722_pdata.reg_pdata[AS3722_LDO5] =
334                                 &as3722_ldo7_reg_pdata;
335                         as3722_pdata.reg_pdata[AS3722_LDO7] =
336                                 &as3722_ldo5_reg_pdata;
337                         as3722_pdata.reg_pdata[AS3722_LDO4] =
338                                 &as3722_ldo10_reg_pdata;
339                         as3722_pdata.reg_pdata[AS3722_LDO10] =
340                                 &as3722_ldo4_reg_pdata;
341                         break;
342                 default:
343                         break;
344                 }
345         }
346         i2c_register_board_info(4, as3722_regulators,
347                         ARRAY_SIZE(as3722_regulators));
348         if (board_info.board_id == BOARD_PM358 &&
349                         board_info.fab == BOARD_FAB_A00)
350                 i2c_register_board_info(0, tca6408_expander,
351                                 ARRAY_SIZE(tca6408_expander));
352         else if (board_info.board_id == BOARD_PM359 ||
353                         board_info.board_id == BOARD_PM370 ||
354                         board_info.board_id == BOARD_PM374 ||
355                         board_info.board_id == BOARD_PM358)
356                 i2c_register_board_info(0, tca6416_expander,
357                                 ARRAY_SIZE(tca6416_expander));
358         return 0;
359 }
360
361 static struct tegra_suspend_platform_data laguna_suspend_data = {
362         .cpu_timer      = 2000,
363         .cpu_off_timer  = 2000,
364         .suspend_mode   = TEGRA_SUSPEND_LP0,
365         .core_timer     = 0x7e7e,
366         .core_off_timer = 2000,
367         .corereq_high   = true,
368         .sysclkreq_high = true,
369         .cpu_lp2_min_residency = 1000,
370 };
371
372 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
373 /* board parameters for cpu dfll */
374 static struct tegra_cl_dvfs_cfg_param laguna_cl_dvfs_param = {
375         .sample_rate = 12500,
376
377         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
378         .cf = 10,
379         .ci = 0,
380         .cg = 2,
381
382         .droop_cut_value = 0xF,
383         .droop_restore_ramp = 0x0,
384         .scale_out_ramp = 0x0,
385 };
386 #endif
387
388 /* Laguna: fixed 10mV steps from 700mV to 1400mV */
389 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 700000) / 10000 + 1)
390 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
391 static inline void fill_reg_map(void)
392 {
393         int i;
394         u32 reg_init_value = 0x0a;
395         struct board_info board_info;
396
397         tegra_get_board_info(&board_info);
398         if ((board_info.board_id == BOARD_PM359) &&
399                                 (board_info.major_revision == 'C'))
400                 reg_init_value = 0x1e;
401
402         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
403                 pmu_cpu_vdd_map[i].reg_value = i + reg_init_value;
404                 pmu_cpu_vdd_map[i].reg_uV = 700000 + 10000 * i;
405         }
406 }
407
408 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
409 static struct tegra_cl_dvfs_platform_data laguna_cl_dvfs_data = {
410         .dfll_clk_name = "dfll_cpu",
411         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
412         .u.pmu_i2c = {
413                 .fs_rate = 400000,
414                 .slave_addr = 0x80,
415                 .reg = 0x00,
416         },
417         .vdd_map = pmu_cpu_vdd_map,
418         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
419
420         .cfg_param = &laguna_cl_dvfs_param,
421 };
422
423 static int __init laguna_cl_dvfs_init(void)
424 {
425         fill_reg_map();
426         laguna_cl_dvfs_data.flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
427         tegra_cl_dvfs_device.dev.platform_data = &laguna_cl_dvfs_data;
428         platform_device_register(&tegra_cl_dvfs_device);
429
430         return 0;
431 }
432 #endif
433
434 /* Always ON /Battery regulator */
435 static struct regulator_consumer_supply fixed_reg_battery_supply[] = {
436         REGULATOR_SUPPLY("vdd_sys_bl", NULL),
437         REGULATOR_SUPPLY("vddio_pex_sata", "tegra-sata.0"),
438 };
439
440 /* Always ON 1.8v */
441 static struct regulator_consumer_supply fixed_reg_aon_1v8_supply[] = {
442         REGULATOR_SUPPLY("vdd_1v8_emmc", NULL),
443         REGULATOR_SUPPLY("vdd_1v8b_com_f", NULL),
444         REGULATOR_SUPPLY("vdd_1v8b_gps_f", NULL),
445 };
446
447 /* Always ON 3.3v */
448 static struct regulator_consumer_supply fixed_reg_aon_3v3_supply[] = {
449         REGULATOR_SUPPLY("vdd_3v3_emmc", NULL),
450         REGULATOR_SUPPLY("vdd_com_3v3", NULL),
451 };
452
453 /* Always ON 1v2 */
454 static struct regulator_consumer_supply fixed_reg_aon_1v2_supply[] = {
455         REGULATOR_SUPPLY("vdd_1v2_bb_hsic", NULL),
456 };
457
458 /* EN_USB0_VBUS From TEGRA GPIO PN4 */
459 static struct regulator_consumer_supply fixed_reg_usb0_vbus_pm358_supply[] = {
460         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
461         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
462         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
463 };
464
465 /* EN_USB1_USB2_VBUS From TEGRA GPIO PN5 */
466 static struct regulator_consumer_supply fixed_reg_usb1_usb2_vbus_pm358_supply[] = {
467         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
468         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
469         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
470         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
471 };
472
473 /* EN_USB0_VBUS From TEGRA GPIO PN4 */
474 static struct regulator_consumer_supply fixed_reg_usb0_usb1_vbus_pm359_supply[] = {
475         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
476         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
477         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
478         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
479         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
480 };
481
482 /* EN_USB1_USB2_VBUS From TEGRA GPIO PN5 */
483 static struct regulator_consumer_supply fixed_reg_usb2_vbus_pm359_supply[] = {
484         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
485         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
486 };
487
488 /* EN_USB0_VBUS From TEGRA GPIO PN4 */
489 static struct regulator_consumer_supply fixed_reg_usb2_vbus_pm363_supply[] = {
490         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
491         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
492 };
493
494 /* EN_USB1_USB2_VBUS From TEGRA GPIO PN5 */
495 static struct regulator_consumer_supply fixed_reg_usb0_usb1_vbus_pm363_supply[] = {
496         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
497         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
498         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
499         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
500         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
501 };
502
503 /* Gated by GPIO_PK6  in FAB B and further*/
504 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
505         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
506 };
507
508 /* Gated by GPIO_PH7  in FAB B and further*/
509 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_supply[] = {
510         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
511 };
512
513 /* VDD_LCD_BL DAP3_DOUT */
514 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_supply[] = {
515         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
516 };
517
518 /* LCD_BL_EN GMI_AD10 */
519 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
520         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
521 };
522
523 /* AS3722 GPIO1*/
524 static struct regulator_consumer_supply fixed_reg_3v3_supply[] = {
525         REGULATOR_SUPPLY("hvdd_pex", NULL),
526         REGULATOR_SUPPLY("hvdd_pex_pll", NULL),
527         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
528         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5645.0"),
529         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5639.0"),
530         REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
531         REGULATOR_SUPPLY("vdd_nfc_3v3", NULL),
532         REGULATOR_SUPPLY("vdd_3v3_sensor", NULL),
533         REGULATOR_SUPPLY("vdd_kp_3v3", NULL),
534         REGULATOR_SUPPLY("vdd_tp_3v3", NULL),
535         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
536         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
537         REGULATOR_SUPPLY("vdd", "1-004c"),
538         REGULATOR_SUPPLY("vdd", "0-0048"),
539         REGULATOR_SUPPLY("vdd", "0-0069"),
540         REGULATOR_SUPPLY("vdd", "0-000c"),
541         REGULATOR_SUPPLY("vdd", "0-0077"),
542         REGULATOR_SUPPLY("vin", "2-0030"),
543 };
544
545 /* AS3722 GPIO1*/
546 static struct regulator_consumer_supply fixed_reg_5v0_supply[] = {
547         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
548         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
549         REGULATOR_SUPPLY("vdd_5v0_sensor", NULL),
550 };
551
552 static struct regulator_consumer_supply fixed_reg_dcdc_1v8_supply[] = {
553         REGULATOR_SUPPLY("avdd_lvds0_pll", NULL),
554         REGULATOR_SUPPLY("dvdd_lcd", NULL),
555         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
556         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645.0"),
557         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645.0"),
558         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639.0"),
559         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639.0"),
560         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639.0"),
561         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645.0"),
562         REGULATOR_SUPPLY("vdd_1v8b_nfc", NULL),
563         REGULATOR_SUPPLY("vdd_1v8_sensor", NULL),
564         REGULATOR_SUPPLY("vdd_1v8_sdmmc", NULL),
565         REGULATOR_SUPPLY("vdd_kp_1v8", NULL),
566         REGULATOR_SUPPLY("vdd_tp_1v8", NULL),
567         REGULATOR_SUPPLY("vdd_modem_1v8", NULL),
568         REGULATOR_SUPPLY("vdd_1v8b", "0-0048"),
569         REGULATOR_SUPPLY("dvdd", "spi0.0"),
570         REGULATOR_SUPPLY("vlogic", "0-0069"),
571         REGULATOR_SUPPLY("vid", "0-000c"),
572         REGULATOR_SUPPLY("vddio", "0-0077"),
573         REGULATOR_SUPPLY("vi2c", "2-0030"),
574         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
575         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
576         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
577         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
578         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
579 };
580
581 /* gated by TCA6416 GPIO EXP GPIO0 */
582 static struct regulator_consumer_supply fixed_reg_dcdc_1v2_supply[] = {
583         REGULATOR_SUPPLY("vdd_1v2_en", NULL),
584 };
585
586 /* AMS GPIO2 */
587 static struct regulator_consumer_supply fixed_reg_as3722_gpio2_supply[] = {
588         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
589         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
590         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
591         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
592         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
593         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
594         REGULATOR_SUPPLY("pwrdet_hv", NULL),
595         REGULATOR_SUPPLY("hvdd_sata", NULL),
596 };
597
598 /* gated by AS3722 GPIO4 */
599 static struct regulator_consumer_supply fixed_reg_lcd_supply[] = {
600         REGULATOR_SUPPLY("avdd_lcd", NULL),
601 };
602
603 /* gated by GPIO_PR0 */
604 static struct regulator_consumer_supply fixed_reg_sdmmc_en_supply[] = {
605         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.1"),
606         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
607 };
608
609 /* only adding for PM358 */
610 static struct regulator_consumer_supply fixed_reg_vdd_cdc_1v2_aud_supply[] = {
611         REGULATOR_SUPPLY("ldoen", "tegra-snd-rt5639.0"),
612 };
613
614 static struct regulator_consumer_supply fixed_reg_vdd_amp_shut_aud_supply[] = {
615         REGULATOR_SUPPLY("epamp", "tegra-snd-rt5645.0"),
616 };
617
618 static struct regulator_consumer_supply fixed_reg_vdd_dsi_mux_supply[] = {
619         REGULATOR_SUPPLY("vdd_3v3_dsi", "NULL"),
620 };
621
622 /* Macro for defining fixed regulator sub device data */
623 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
624 #define FIXED_REG(_id, _var, _name, _in_supply,                 \
625         _always_on, _boot_on, _gpio_nr, _open_drain,            \
626         _active_high, _boot_state, _millivolts, _sdelay)        \
627 static struct regulator_init_data ri_data_##_var =              \
628 {                                                               \
629         .supply_regulator = _in_supply,                         \
630         .num_consumer_supplies =                                \
631         ARRAY_SIZE(fixed_reg_##_name##_supply),                 \
632         .consumer_supplies = fixed_reg_##_name##_supply,        \
633         .constraints = {                                        \
634                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
635                                 REGULATOR_MODE_STANDBY),        \
636                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
637                                 REGULATOR_CHANGE_STATUS |       \
638                                 REGULATOR_CHANGE_VOLTAGE),      \
639                 .always_on = _always_on,                        \
640                 .boot_on = _boot_on,                            \
641         },                                                      \
642 };                                                              \
643 static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
644 {                                                               \
645         .supply_name = FIXED_SUPPLY(_name),                     \
646         .microvolts = _millivolts * 1000,                       \
647         .gpio = _gpio_nr,                                       \
648         .gpio_is_open_drain = _open_drain,                      \
649         .enable_high = _active_high,                            \
650         .enabled_at_boot = _boot_state,                         \
651         .init_data = &ri_data_##_var,                           \
652         .startup_delay = _sdelay,                               \
653 };                                                              \
654 static struct platform_device fixed_reg_##_var##_dev = {        \
655         .name = "reg-fixed-voltage",                            \
656         .id = _id,                                              \
657         .dev = {                                                \
658                 .platform_data = &fixed_reg_##_var##_pdata,     \
659         },                                                      \
660 }
661
662 FIXED_REG(0,    battery,        battery,        NULL,   0,      0,
663                 -1,     false, true,    0,      8400,   0);
664
665 FIXED_REG(1,    aon_1v8,        aon_1v8,        NULL,   0,      0,
666                 -1,     false, true,    0,      1800,   0);
667
668 FIXED_REG(2,    aon_3v3,        aon_3v3,        NULL,   0,      0,
669                 -1,     false, true,    0,      3300,   0);
670
671 FIXED_REG(3,    aon_1v2,        aon_1v2,        NULL,   0,      0,
672                 -1,     false, true,    0,      1200,   0);
673
674 FIXED_REG(4,    vdd_hdmi_5v0,   vdd_hdmi_5v0,   NULL,   0,      0,
675                 TEGRA_GPIO_PK6, false,  true,   0,      5000,   5000);
676
677 FIXED_REG(5,    vdd_hdmi,       vdd_hdmi,       AS3722_SUPPLY(sd4),
678                 0,      0,
679                 TEGRA_GPIO_PH7, false,  false,  0,      3300,   0);
680
681 FIXED_REG(6,    usb0_vbus_pm358,        usb0_vbus_pm358,        NULL,
682                 0,      0,
683                 TEGRA_GPIO_PN4, true,   true,   0,      5000,   0);
684
685 FIXED_REG(7,    usb1_usb2_vbus_pm358,   usb1_usb2_vbus_pm358,   NULL,
686                 0,      0,
687                 TEGRA_GPIO_PN5, true,   true,   0,      5000, 0);
688
689 FIXED_REG(8,    usb0_usb1_vbus_pm359,   usb0_usb1_vbus_pm359,   NULL,
690                 0,      0,
691                 TEGRA_GPIO_PN4, true,   true,   0,      5000,   0);
692
693 FIXED_REG(9,    usb2_vbus_pm359,        usb2_vbus_pm359,        NULL,
694                 0,      0,
695                 TEGRA_GPIO_PN5, true,   true,   0,      5000, 0);
696
697 FIXED_REG(10,   usb2_vbus_pm363,        usb2_vbus_pm363,        NULL,
698                 0,      0,
699                 TEGRA_GPIO_PN4, true,   true,   0,      5000,   0);
700
701 FIXED_REG(11,   usb0_usb1_vbus_pm363,   usb0_usb1_vbus_pm363,   NULL,
702                 0,      0,
703                 TEGRA_GPIO_PN5, true,   true,   0,      5000, 0);
704
705 FIXED_REG(12,   vdd_lcd_bl,     vdd_lcd_bl,     NULL,   0,      0,
706                 TEGRA_GPIO_PP2, false,  true,   0,      3300, 0);
707
708 FIXED_REG(13,   lcd_bl_en,      lcd_bl_en,      NULL,   0,      0,
709                 TEGRA_GPIO_PH2, false,  true,   0,      5000,   0);
710
711 FIXED_REG(14,   3v3,            3v3,            NULL,   0,      0,
712                 -1,     false,  true,   0,      3300,   0);
713
714 FIXED_REG(15,   5v0,            5v0,            NULL,   0,      0,
715                 -1,     false,  true,   0,      5000,   0);
716
717 FIXED_REG(16,   dcdc_1v8,       dcdc_1v8,       NULL,   0,      0,
718                 -1,     false,  true,   0,      1800,   0);
719
720 FIXED_REG(17,    dcdc_1v2, dcdc_1v2,    NULL,   0,      0,
721                 PMU_TCA6416_GPIO_BASE,     false,  true,   0,      1200,
722                 0);
723
724 FIXED_REG(18,   as3722_gpio2,   as3722_gpio2,           NULL,   0,      true,
725                 AS3722_GPIO_BASE + AS3722_GPIO2,        false,  true,   true,
726                 3300,   0);
727
728 FIXED_REG(19,   lcd,            lcd,            NULL,   0,      0,
729                 AS3722_GPIO_BASE + AS3722_GPIO4,        false,  true,   0,
730                 3300,   0);
731
732 FIXED_REG(20,   sdmmc_en,               sdmmc_en,       NULL,   0,      0,
733                 TEGRA_GPIO_PR0,         false,  true,   0,      3300,   0);
734
735 FIXED_REG(21,   vdd_cdc_1v2_aud,        vdd_cdc_1v2_aud,        NULL,   0,
736                 0,      PMU_TCA6416_GPIO(2),    false,  true,   0,
737                 1200,   250000);
738
739 FIXED_REG(22,   vdd_amp_shut_aud,       vdd_amp_shut_aud,       NULL,   0,
740                 0,      PMU_TCA6416_GPIO(3),    false,  true,   0,
741                 1200,   0);
742
743 FIXED_REG(23,   vdd_dsi_mux,            vdd_dsi_mux,    NULL,   0,      0,
744                 PMU_TCA6416_GPIO(13),   false,  true,   0,      3300,   0);
745 /*
746  * Creating the fixed regulator device tables
747  */
748
749 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
750
751 #define LAGUNA_COMMON_FIXED_REG                 \
752         ADD_FIXED_REG(battery),                 \
753         ADD_FIXED_REG(aon_1v8),                 \
754         ADD_FIXED_REG(aon_3v3),                 \
755         ADD_FIXED_REG(aon_1v2),                 \
756         ADD_FIXED_REG(vdd_hdmi_5v0),            \
757         ADD_FIXED_REG(vdd_hdmi),                \
758         ADD_FIXED_REG(vdd_lcd_bl),              \
759         ADD_FIXED_REG(lcd_bl_en),               \
760         ADD_FIXED_REG(3v3),                     \
761         ADD_FIXED_REG(5v0),                     \
762         ADD_FIXED_REG(dcdc_1v8),                \
763         ADD_FIXED_REG(as3722_gpio2),            \
764         ADD_FIXED_REG(lcd),                     \
765         ADD_FIXED_REG(sdmmc_en)
766
767 #define LAGUNA_PM358_FIXED_REG                  \
768         ADD_FIXED_REG(usb0_vbus_pm358),         \
769         ADD_FIXED_REG(usb1_usb2_vbus_pm358),    \
770         ADD_FIXED_REG(dcdc_1v2),                \
771         ADD_FIXED_REG(vdd_cdc_1v2_aud),         \
772         ADD_FIXED_REG(vdd_amp_shut_aud),         \
773         ADD_FIXED_REG(vdd_dsi_mux)
774
775 #define LAGUNA_PM359_FIXED_REG                  \
776         ADD_FIXED_REG(usb0_usb1_vbus_pm359),    \
777         ADD_FIXED_REG(usb2_vbus_pm359),         \
778         ADD_FIXED_REG(dcdc_1v2),                \
779         ADD_FIXED_REG(vdd_cdc_1v2_aud)
780
781 #define LAGUNA_PM363_FIXED_REG                  \
782         ADD_FIXED_REG(usb2_vbus_pm363),         \
783         ADD_FIXED_REG(usb0_usb1_vbus_pm363),
784
785 /* Gpio switch regulator platform data for laguna pm358 ERS*/
786 static struct platform_device *fixed_reg_devs_pm358[] = {
787         LAGUNA_COMMON_FIXED_REG,
788         LAGUNA_PM358_FIXED_REG
789 };
790
791 /* Gpio switch regulator platform data for laguna pm359 ERS-S*/
792 static struct platform_device *fixed_reg_devs_pm359[] = {
793         LAGUNA_COMMON_FIXED_REG,
794         LAGUNA_PM359_FIXED_REG
795 };
796
797 /* Gpio switch regulator platform data for laguna pm363 FFD*/
798 static struct platform_device *fixed_reg_devs_pm363[] = {
799         LAGUNA_COMMON_FIXED_REG,
800         LAGUNA_PM363_FIXED_REG
801 };
802 /* Gpio switch regulator platform data for laguna pm370 FFD*/
803 static struct platform_device *fixed_reg_devs_pm370[] = {
804         LAGUNA_COMMON_FIXED_REG,
805         LAGUNA_PM358_FIXED_REG
806 };
807
808 /* Gpio switch regulator platform data for laguna pm374 FFD*/
809 static struct platform_device *fixed_reg_devs_pm374[] = {
810         LAGUNA_COMMON_FIXED_REG,
811         LAGUNA_PM358_FIXED_REG
812 };
813
814 static int __init laguna_fixed_regulator_init(void)
815 {
816         struct board_info board_info;
817
818         if (!of_machine_is_compatible("nvidia,laguna"))
819                 return 0;
820
821         tegra_get_board_info(&board_info);
822         if (board_info.board_id == BOARD_PM374)
823                 return platform_add_devices(fixed_reg_devs_pm374,
824                                 ARRAY_SIZE(fixed_reg_devs_pm374));
825         else if (board_info.board_id == BOARD_PM359)
826                 return platform_add_devices(fixed_reg_devs_pm359,
827                                 ARRAY_SIZE(fixed_reg_devs_pm359));
828         else if (board_info.board_id == BOARD_PM358)
829                 return platform_add_devices(fixed_reg_devs_pm358,
830                                 ARRAY_SIZE(fixed_reg_devs_pm358));
831         else if (board_info.board_id == BOARD_PM370)
832                 return platform_add_devices(fixed_reg_devs_pm370,
833                                 ARRAY_SIZE(fixed_reg_devs_pm370));
834         else if (board_info.board_id == BOARD_PM363)
835                 return platform_add_devices(fixed_reg_devs_pm363,
836                                 ARRAY_SIZE(fixed_reg_devs_pm363));
837
838         return 0;
839 }
840
841 subsys_initcall_sync(laguna_fixed_regulator_init);
842
843 int __init laguna_regulator_init(void)
844 {
845
846 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
847         laguna_cl_dvfs_init();
848 #endif
849         laguna_as3722_regulator_init();
850
851         if (get_power_supply_type() == POWER_SUPPLY_TYPE_BATTERY)
852                 i2c_register_board_info(1, bq2471x_boardinfo,
853                         ARRAY_SIZE(bq2471x_boardinfo));
854
855         return 0;
856 }
857
858 int __init laguna_suspend_init(void)
859 {
860         tegra_init_suspend(&laguna_suspend_data);
861         return 0;
862 }
863
864 int __init laguna_edp_init(void)
865 {
866         unsigned int regulator_mA;
867
868         regulator_mA = get_maximum_cpu_current_supported();
869         if (!regulator_mA)
870                 regulator_mA = 15000;
871
872         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
873
874         tegra_init_cpu_edp_limits(regulator_mA);
875
876         /* gpu maximum current */
877         regulator_mA = 8000;
878         pr_info("%s: GPU regulator %d mA\n", __func__, regulator_mA);
879
880         tegra_init_gpu_edp_limits(regulator_mA);
881         return 0;
882 }
883
884 static struct pid_thermal_gov_params soctherm_pid_params = {
885         .max_err_temp = 9000,
886         .max_err_gain = 1000,
887
888         .gain_p = 1000,
889         .gain_d = 0,
890
891         .up_compensation = 20,
892         .down_compensation = 20,
893 };
894
895 static struct thermal_zone_params soctherm_tzp = {
896         .governor_name = "pid_thermal_gov",
897         .governor_params = &soctherm_pid_params,
898 };
899
900 static struct soctherm_platform_data laguna_soctherm_data = {
901         .therm = {
902                 [THERM_CPU] = {
903                         .zone_enable = true,
904                         .passive_delay = 1000,
905                         .hotspot_offset = 6000,
906                         .num_trips = 3,
907                         .trips = {
908                                 {
909                                         .cdev_type = "tegra-shutdown",
910                                         .trip_temp = 103000,
911                                         .trip_type = THERMAL_TRIP_CRITICAL,
912                                         .upper = THERMAL_NO_LIMIT,
913                                         .lower = THERMAL_NO_LIMIT,
914                                 },
915                                 {
916                                         .cdev_type = "tegra-heavy",
917                                         .trip_temp = 101000,
918                                         .trip_type = THERMAL_TRIP_HOT,
919                                         .upper = THERMAL_NO_LIMIT,
920                                         .lower = THERMAL_NO_LIMIT,
921                                 },
922                                 {
923                                         .cdev_type = "tegra-balanced",
924                                         .trip_temp = 91000,
925                                         .trip_type = THERMAL_TRIP_PASSIVE,
926                                         .upper = THERMAL_NO_LIMIT,
927                                         .lower = THERMAL_NO_LIMIT,
928                                 },
929                         },
930                         .tzp = &soctherm_tzp,
931                 },
932                 [THERM_GPU] = {
933                         .zone_enable = true,
934                         .passive_delay = 1000,
935                         .hotspot_offset = 6000,
936                         .num_trips = 3,
937                         .trips = {
938                                 {
939                                         .cdev_type = "tegra-shutdown",
940                                         .trip_temp = 104000,
941                                         .trip_type = THERMAL_TRIP_CRITICAL,
942                                         .upper = THERMAL_NO_LIMIT,
943                                         .lower = THERMAL_NO_LIMIT,
944                                 },
945                                 {
946                                         .cdev_type = "tegra-balanced",
947                                         .trip_temp = 92000,
948                                         .trip_type = THERMAL_TRIP_PASSIVE,
949                                         .upper = THERMAL_NO_LIMIT,
950                                         .lower = THERMAL_NO_LIMIT,
951                                 },
952 /*
953                                 {
954                                         .cdev_type = "gk20a_cdev",
955                                         .trip_temp = 102000,
956                                         .trip_type = THERMAL_TRIP_PASSIVE,
957                                         .upper = THERMAL_NO_LIMIT,
958                                         .lower = THERMAL_NO_LIMIT,
959                                 },
960                                 {
961                                         .cdev_type = "tegra-heavy",
962                                         .trip_temp = 102000,
963                                         .trip_type = THERMAL_TRIP_HOT,
964                                         .upper = THERMAL_NO_LIMIT,
965                                         .lower = THERMAL_NO_LIMIT,
966                                 },
967 */
968                         },
969                         .tzp = &soctherm_tzp,
970                 },
971                 [THERM_MEM] = {
972                         .zone_enable = true,
973                         .num_trips = 1,
974                         .trips = {
975                                 {
976                                         .cdev_type = "tegra-shutdown",
977                                         .trip_temp = 104000, /* = GPU shut */
978                                         .trip_type = THERMAL_TRIP_CRITICAL,
979                                         .upper = THERMAL_NO_LIMIT,
980                                         .lower = THERMAL_NO_LIMIT,
981                                 },
982                         },
983                 },
984                 [THERM_PLL] = {
985                         .zone_enable = true,
986                         .tzp = &soctherm_tzp,
987                 },
988         },
989         .throttle = {
990                 [THROTTLE_HEAVY] = {
991                         .priority = 100,
992                         .devs = {
993                                 [THROTTLE_DEV_CPU] = {
994                                         .enable = true,
995                                         .depth = 80,
996                                 },
997                                 [THROTTLE_DEV_GPU] = {
998                                         .enable = false,
999                                         .throttling_depth = "heavy_throttling",
1000                                 },
1001                         },
1002                 },
1003         },
1004 };
1005
1006 int __init laguna_soctherm_init(void)
1007 {
1008         tegra_platform_edp_init(laguna_soctherm_data.therm[THERM_CPU].trips,
1009                         &laguna_soctherm_data.therm[THERM_CPU].num_trips,
1010                         7000); /* edp temperature margin */
1011         tegra_platform_gpu_edp_init(
1012                         laguna_soctherm_data.therm[THERM_GPU].trips,
1013                         &laguna_soctherm_data.therm[THERM_GPU].num_trips,
1014                         7000);
1015         tegra_add_cpu_vmax_trips(laguna_soctherm_data.therm[THERM_CPU].trips,
1016                         &laguna_soctherm_data.therm[THERM_CPU].num_trips);
1017         tegra_add_tgpu_trips(laguna_soctherm_data.therm[THERM_GPU].trips,
1018                         &laguna_soctherm_data.therm[THERM_GPU].num_trips);
1019         tegra_add_vc_trips(laguna_soctherm_data.therm[THERM_CPU].trips,
1020                         &laguna_soctherm_data.therm[THERM_CPU].num_trips);
1021         tegra_add_core_vmax_trips(laguna_soctherm_data.therm[THERM_PLL].trips,
1022                         &laguna_soctherm_data.therm[THERM_PLL].num_trips);
1023
1024         return tegra11_soctherm_init(&laguna_soctherm_data);
1025 }