ARM: tegra: unified board file
[linux-3.10.git] / arch / arm / mach-tegra / board-laguna-power.c
1 /*
2  * arch/arm/mach-tegra/board-laguna-power.c
3  *
4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca954x.h>
22 #include <linux/i2c/pca953x.h>
23 #include <linux/pda_power.h>
24 #include <linux/platform_device.h>
25 #include <linux/resource.h>
26 #include <linux/io.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/driver.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/mfd/as3722-reg.h>
31 #include <linux/mfd/as3722-plat.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/userspace-consumer.h>
34
35 #include <asm/mach-types.h>
36
37 #include <mach/irqs.h>
38 #include <mach/edp.h>
39 #include <mach/gpio-tegra.h>
40
41 #include "cpu-tegra.h"
42 #include "pm.h"
43 #include "tegra-board-id.h"
44 #include "board.h"
45 #include "gpio-names.h"
46 #include "board-common.h"
47 #include "board-ardbeg.h"
48 #include "tegra_cl_dvfs.h"
49 #include "devices.h"
50 #include "tegra11_soctherm.h"
51 #include "iomap.h"
52
53 #define PMC_CTRL                0x0
54 #define PMC_CTRL_INTR_LOW       (1 << 17)
55
56 static struct regulator_consumer_supply as3722_ldo0_supply[] = {
57         REGULATOR_SUPPLY("avdd_pll_m", NULL),
58         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
59         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
60         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
61         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
62         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
63         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
64         REGULATOR_SUPPLY("avdd_pll_x", NULL),
65         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
66 };
67
68 static struct regulator_consumer_supply as3722_ldo1_supply[] = {
69         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
70         REGULATOR_SUPPLY("vdd_cam1_1v8_cam", NULL),
71         REGULATOR_SUPPLY("vdd_cam2_1v8_cam", NULL),
72 };
73
74 static struct regulator_consumer_supply as3722_ldo2_supply[] = {
75         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
76         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
77         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
78 };
79
80 static struct regulator_consumer_supply as3722_ldo3_supply[] = {
81         REGULATOR_SUPPLY("vdd_rtc", NULL),
82 };
83
84 static struct regulator_consumer_supply as3722_ldo4_supply[] = {
85         REGULATOR_SUPPLY("vdd_2v7_hv", NULL),
86         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
87         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
88         REGULATOR_SUPPLY("avdd_cam3_cam", NULL),
89 };
90
91 static struct regulator_consumer_supply as3722_ldo5_supply[] = {
92         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
93 };
94
95 static struct regulator_consumer_supply as3722_ldo6_supply[] = {
96         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
97         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
98 };
99
100 static struct regulator_consumer_supply as3722_ldo7_supply[] = {
101         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
102 };
103
104 static struct regulator_consumer_supply as3722_ldo9_supply[] = {
105         REGULATOR_SUPPLY("vdd_ts_3v0b_dis", NULL),
106 };
107
108 static struct regulator_consumer_supply as3722_ldo10_supply[] = {
109         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
110 };
111
112 static struct regulator_consumer_supply as3722_ldo11_supply[] = {
113         REGULATOR_SUPPLY("vpp_fuse", NULL),
114 };
115
116 static struct regulator_consumer_supply as3722_sd0_supply[] = {
117         REGULATOR_SUPPLY("vdd_cpu", NULL),
118 };
119
120 static struct regulator_consumer_supply as3722_sd1_supply[] = {
121         REGULATOR_SUPPLY("vdd_core", NULL),
122 };
123
124 static struct regulator_consumer_supply as3722_sd2_supply[] = {
125         REGULATOR_SUPPLY("vddio_ddr", NULL),
126         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
127         REGULATOR_SUPPLY("vddio_ddr3", NULL),
128         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
129 };
130
131 static struct regulator_consumer_supply as3722_sd4_supply[] = {
132         REGULATOR_SUPPLY("avdd_pex_pll", NULL),
133         REGULATOR_SUPPLY("avddio_pex_pll", NULL),
134         REGULATOR_SUPPLY("dvddio_pex", NULL),
135         REGULATOR_SUPPLY("avdd_sata", NULL),
136         REGULATOR_SUPPLY("vdd_sata", NULL),
137         REGULATOR_SUPPLY("avdd_sata_pll", NULL),
138         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
139         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
140         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
141         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
142 };
143
144 static struct regulator_consumer_supply as3722_sd5_supply[] = {
145         REGULATOR_SUPPLY("vddio_sys", NULL),
146         REGULATOR_SUPPLY("vddio_sys_2", NULL),
147         REGULATOR_SUPPLY("vddio_audio", NULL),
148         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
149         REGULATOR_SUPPLY("vddio_uart", NULL),
150         REGULATOR_SUPPLY("vddio_bb", NULL),
151         REGULATOR_SUPPLY("vddio_gmi", NULL),
152         REGULATOR_SUPPLY("avdd_osc", NULL),
153         /* emmc 1.8v misssing
154         keyboard & touchpad 1.8v missing */
155 };
156
157 static struct regulator_consumer_supply as3722_sd6_supply[] = {
158         REGULATOR_SUPPLY("vdd_gpu", NULL),
159 };
160
161 static struct regulator_init_data as3722_ldo0 = {
162         .constraints = {
163                 .min_uV = 1050000,
164                 .max_uV = 1250000,
165                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
166                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
167                         | REGULATOR_CHANGE_VOLTAGE
168                         | REGULATOR_CHANGE_CURRENT,
169                 .always_on = false,
170                 .boot_on = 1,
171                 .apply_uV = 1,
172         },
173         .consumer_supplies = as3722_ldo0_supply,
174         .num_consumer_supplies = ARRAY_SIZE(as3722_ldo0_supply),
175 };
176
177 static struct regulator_init_data as3722_ldo1 = {
178         .constraints = {
179                 .min_uV = 1800000,
180                 .max_uV = 1800000,
181                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
182                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
183                         | REGULATOR_CHANGE_VOLTAGE
184                         | REGULATOR_CHANGE_CURRENT,
185                 .always_on = true,
186                 .boot_on = 1,
187                 .apply_uV = 1,
188         },
189         .consumer_supplies = as3722_ldo1_supply,
190         .num_consumer_supplies = ARRAY_SIZE(as3722_ldo1_supply),
191 };
192
193 static struct regulator_init_data as3722_ldo2 = {
194         .constraints = {
195                 .min_uV = 1200000,
196                 .max_uV = 1200000,
197                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
198                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
199                         | REGULATOR_CHANGE_VOLTAGE
200                         | REGULATOR_CHANGE_CURRENT,
201                 .always_on = false,
202                 .boot_on = 1,
203                 .apply_uV = 1,
204         },
205         .consumer_supplies = as3722_ldo2_supply,
206         .num_consumer_supplies = ARRAY_SIZE(as3722_ldo2_supply),
207 };
208
209 static struct regulator_init_data as3722_ldo3 = {
210         .constraints = {
211                 .min_uV = 1000000,
212                 .max_uV = 1000000,
213                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
214                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
215                         | REGULATOR_CHANGE_VOLTAGE,
216                 .always_on = true,
217                 .boot_on = 1,
218                 .apply_uV = 1,
219         },
220         .consumer_supplies = as3722_ldo3_supply,
221         .num_consumer_supplies = ARRAY_SIZE(as3722_ldo3_supply),
222 };
223
224 static struct regulator_init_data as3722_ldo4 = {
225         .constraints = {
226                 .min_uV = 2700000,
227                 .max_uV = 2700000,
228                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
229                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
230                         | REGULATOR_CHANGE_VOLTAGE
231                         | REGULATOR_CHANGE_CURRENT,
232                 .always_on = false,
233                 .boot_on = 0,
234                 .apply_uV = 1,
235         },
236         .consumer_supplies = as3722_ldo4_supply,
237         .num_consumer_supplies = ARRAY_SIZE(as3722_ldo4_supply),
238 };
239
240 static struct regulator_init_data as3722_ldo5 = {
241         .constraints = {
242                 .min_uV = 1200000,
243                 .max_uV = 1200000,
244                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
245                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
246                         | REGULATOR_CHANGE_VOLTAGE
247                         | REGULATOR_CHANGE_CURRENT,
248                 .always_on = false,
249                 .boot_on = 0,
250                 .apply_uV = 1,
251         },
252         .consumer_supplies = as3722_ldo5_supply,
253         .num_consumer_supplies = ARRAY_SIZE(as3722_ldo5_supply),
254 };
255
256 static struct regulator_init_data as3722_ldo6 = {
257         .constraints = {
258                 .min_uV = 3300000,
259                 .max_uV = 3300000,
260                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
261                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
262                         | REGULATOR_CHANGE_VOLTAGE
263                         | REGULATOR_CHANGE_CURRENT,
264                 .always_on = false,
265                 .boot_on = 0,
266                 .apply_uV = 1,
267         },
268         .consumer_supplies = as3722_ldo6_supply,
269         .num_consumer_supplies = ARRAY_SIZE(as3722_ldo6_supply),
270 };
271
272 static struct regulator_init_data as3722_ldo7 = {
273         .constraints = {
274                 .min_uV = 1050000,
275                 .max_uV = 1050000,
276                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
277                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
278                         | REGULATOR_CHANGE_VOLTAGE
279                         | REGULATOR_CHANGE_CURRENT,
280                 .always_on = false,
281                 .boot_on = 0,
282                 .apply_uV = 1,
283         },
284         .consumer_supplies = as3722_ldo7_supply,
285         .num_consumer_supplies = ARRAY_SIZE(as3722_ldo7_supply),
286 };
287
288 static struct regulator_init_data as3722_ldo9 = {
289         .constraints = {
290                 .min_uV = 3300000,
291                 .max_uV = 3300000,
292                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
293                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
294                         | REGULATOR_CHANGE_VOLTAGE
295                         | REGULATOR_CHANGE_CURRENT,
296                 .always_on = false,
297                 .boot_on = 1,
298                 .apply_uV = 1,
299         },
300         .consumer_supplies = as3722_ldo9_supply,
301         .num_consumer_supplies = ARRAY_SIZE(as3722_ldo9_supply),
302 };
303
304 static struct regulator_init_data as3722_ldo10 = {
305         .constraints = {
306                 .min_uV = 2700000,
307                 .max_uV = 2700000,
308                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
309                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
310                         | REGULATOR_CHANGE_VOLTAGE
311                         | REGULATOR_CHANGE_CURRENT,
312                 .always_on = false,
313                 .boot_on = 0,
314                 .apply_uV = 1,
315         },
316         .consumer_supplies = as3722_ldo10_supply,
317         .num_consumer_supplies = ARRAY_SIZE(as3722_ldo10_supply),
318 };
319
320 static struct regulator_init_data as3722_ldo11 = {
321         .constraints = {
322                 .min_uV = 1800000,
323                 .max_uV = 1800000,
324                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
325                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
326                         | REGULATOR_CHANGE_VOLTAGE
327                         | REGULATOR_CHANGE_CURRENT,
328                 .always_on = false,
329                 .boot_on = 0,
330                 .apply_uV = 1,
331         },
332         .consumer_supplies = as3722_ldo11_supply,
333         .num_consumer_supplies = ARRAY_SIZE(as3722_ldo11_supply),
334 };
335
336
337 static struct regulator_init_data as3722_sd0 = {
338         .constraints = {
339                 .min_uV = 1000000,
340                 .max_uV = 1000000,
341                 .valid_modes_mask = REGULATOR_MODE_NORMAL
342                         | REGULATOR_MODE_FAST,
343                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
344                         | REGULATOR_CHANGE_VOLTAGE
345                         | REGULATOR_CHANGE_MODE,
346                 .always_on = true,
347                 .boot_on = 1,
348                 .apply_uV = 1,
349         },
350         .consumer_supplies = as3722_sd0_supply,
351         .num_consumer_supplies = ARRAY_SIZE(as3722_sd0_supply),
352 };
353
354 static struct regulator_init_data as3722_sd1 = {
355         .constraints = {
356                 .min_uV = 1000000,
357                 .max_uV = 1000000,
358                 .valid_modes_mask = REGULATOR_MODE_NORMAL
359                         | REGULATOR_MODE_FAST,
360                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
361                         | REGULATOR_CHANGE_VOLTAGE
362                         | REGULATOR_CHANGE_MODE,
363                 .always_on = true,
364                 .boot_on = 1,
365                 .apply_uV = 0,
366         },
367         .consumer_supplies = as3722_sd1_supply,
368         .num_consumer_supplies = ARRAY_SIZE(as3722_sd1_supply),
369 };
370
371 static struct regulator_init_data as3722_sd2 = {
372         .constraints = {
373                 .min_uV = 1350000,
374                 .max_uV = 1350000,
375                 .valid_modes_mask = REGULATOR_MODE_NORMAL
376                         | REGULATOR_MODE_FAST,
377                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
378                         | REGULATOR_CHANGE_VOLTAGE
379                         | REGULATOR_CHANGE_MODE,
380                 .always_on = true,
381                 .boot_on = 1,
382                 .apply_uV = 1,
383         },
384         .consumer_supplies = as3722_sd2_supply,
385         .num_consumer_supplies = ARRAY_SIZE(as3722_sd2_supply),
386 };
387
388 static struct regulator_init_data as3722_sd4 = {
389         .constraints = {
390                 .min_uV = 1050000,
391                 .max_uV = 1050000,
392                 .valid_modes_mask = REGULATOR_MODE_NORMAL
393                         | REGULATOR_MODE_FAST,
394                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
395                         | REGULATOR_CHANGE_VOLTAGE
396                         | REGULATOR_CHANGE_MODE,
397                 .always_on = false,
398                 .boot_on = 1,
399                 .apply_uV = 1,
400         },
401         .consumer_supplies = as3722_sd4_supply,
402         .num_consumer_supplies = ARRAY_SIZE(as3722_sd4_supply),
403 };
404
405 static struct regulator_init_data as3722_sd5 = {
406         .constraints = {
407                 .min_uV = 1800000,
408                 .max_uV = 1800000,
409                 .valid_modes_mask = REGULATOR_MODE_NORMAL
410                         | REGULATOR_MODE_FAST,
411                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
412                         | REGULATOR_CHANGE_VOLTAGE
413                         | REGULATOR_CHANGE_MODE,
414                 .always_on = true,
415                 .boot_on = 1,
416                 .apply_uV = 1,
417         },
418         .consumer_supplies = as3722_sd5_supply,
419         .num_consumer_supplies = ARRAY_SIZE(as3722_sd5_supply),
420 };
421
422 static struct regulator_init_data as3722_sd6 = {
423         .constraints = {
424                 .min_uV = 1000000,
425                 .max_uV = 1000000,
426                 .valid_modes_mask = REGULATOR_MODE_NORMAL
427                         | REGULATOR_MODE_FAST,
428                 .valid_ops_mask = REGULATOR_CHANGE_STATUS
429                         | REGULATOR_CHANGE_VOLTAGE
430                         | REGULATOR_CHANGE_MODE,
431                 .always_on = true,
432                 .boot_on = 1,
433                 .apply_uV = 1,
434         },
435         .consumer_supplies = as3722_sd6_supply,
436         .num_consumer_supplies = ARRAY_SIZE(as3722_sd6_supply),
437 };
438
439 static struct as3722_reg_init as3722_core_init_data[] = {
440         /* disable all regulators */
441 #if 0
442         AS3722_REG_INIT(AS3722_SD_CONTROL_REG, 0x00),
443         AS3722_REG_INIT(AS3722_LDOCONTROL0_REG, 0x00),
444         AS3722_REG_INIT(AS3722_LDOCONTROL1_REG, 0x00),
445         /* set to lowest voltage output */
446         AS3722_REG_INIT(AS3722_SD0_VOLTAGE_REG, 0x01),
447         AS3722_REG_INIT(AS3722_SD1_VOLTAGE_REG, 0x01),
448         AS3722_REG_INIT(AS3722_SD2_VOLTAGE_REG, 0x01),
449         AS3722_REG_INIT(AS3722_SD3_VOLTAGE_REG, 0x01),
450         AS3722_REG_INIT(AS3722_SD4_VOLTAGE_REG, 0x01),
451         AS3722_REG_INIT(AS3722_SD5_VOLTAGE_REG, 0x01),
452         AS3722_REG_INIT(AS3722_SD6_VOLTAGE_REG, 0x01),
453         AS3722_REG_INIT(AS3722_LDO0_VOLTAGE_REG, 0x01),
454         AS3722_REG_INIT(AS3722_LDO1_VOLTAGE_REG, 0x01),
455         AS3722_REG_INIT(AS3722_LDO2_VOLTAGE_REG, 0x01),
456         AS3722_REG_INIT(AS3722_LDO3_VOLTAGE_REG, 0x01),
457         AS3722_REG_INIT(AS3722_LDO4_VOLTAGE_REG, 0x01),
458         AS3722_REG_INIT(AS3722_LDO5_VOLTAGE_REG, 0x01),
459         AS3722_REG_INIT(AS3722_LDO6_VOLTAGE_REG, 0x01),
460         AS3722_REG_INIT(AS3722_LDO7_VOLTAGE_REG, 0x01),
461         AS3722_REG_INIT(AS3722_LDO9_VOLTAGE_REG, 0x01),
462         AS3722_REG_INIT(AS3722_LDO10_VOLTAGE_REG, 0x01),
463         AS3722_REG_INIT(AS3722_LDO11_VOLTAGE_REG, 0x01),
464 #endif
465         {.reg = AS3722_REG_INIT_TERMINATE},
466 };
467
468 /* config settings are OTP plus initial state
469  * GPIOsignal_out at 20h not configurable through OTP and is initialized to
470  * zero. To enable output, the invert bit must be turned on.
471  * GPIOxcontrol register format
472  * bit(s)  bitname
473  * ---------------------
474  *  7     gpiox_invert   invert input or output
475  * 6:3    gpiox_iosf     0: normal
476  * 2:0    gpiox_mode     0: input, 1: output push/pull, 3: ADC input (tristate)
477  *
478  * Examples:
479  * otp  meaning
480  * ------------
481  * 0x3  gpiox_invert=0(no invert), gpiox_iosf=0(normal), gpiox_mode=3(ADC input)
482  * 0x81 gpiox_invert=1(invert), gpiox_iosf=0(normal), gpiox_mode=1(output)
483  *
484  * Note: output state should be defined for gpiox_mode = output.  Do not change
485  * the state of the invert bit for critical devices such as GPIO 7 which enables
486  * SDRAM. Driver applies invert mask to output state to configure GPIOsignal_out
487  * register correctly.
488  * E.g. Invert = 1, (requested) output state = 1 => GPIOsignal_out = 0
489  */
490 static struct as3722_gpio_config as3722_gpio_cfgs[] = {
491         {
492                 /* otp = 0x3 IGPU_PRDGD*/
493                 .gpio = AS3722_GPIO0,
494                 .mode = AS3722_GPIO_MODE_OUTPUT_VDDL,
495         },
496         {
497                 /* otp = 0x1  => REGEN_3 = LP0 gate (1.8V, 5 V)*/
498                 .gpio = AS3722_GPIO1,
499                 .invert     = AS3722_GPIO_CFG_INVERT, /* don't go into LP0 */
500                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
501                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
502         },
503         {
504                 /* otp = 0x3 PMU_REGEN1*/
505                 .gpio = AS3722_GPIO2,
506                 .invert     = AS3722_GPIO_CFG_INVERT, /* don't go into LP0 */
507                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
508                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
509         },
510         {
511                 /* otp = 0x03 AP THERMISTOR */
512                 .gpio = AS3722_GPIO3,
513                 .mode = AS3722_GPIO_MODE_ADC_IN,
514         },
515         {
516                 /* otp = 0x81 => on by default
517                  * gates EN_AVDD_LCD
518                  */
519                 .gpio       = AS3722_GPIO4,
520                 .invert     = AS3722_GPIO_CFG_NO_INVERT,
521                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
522                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
523         },
524         {
525                 /* otp = 0x3  CLK 23KHZ WIFI */
526                 .gpio = AS3722_GPIO5,
527                 .mode = AS3722_GPIO_MODE_ADC_IN,
528         },
529         {
530                 /* otp = 0x3  SKIN TEMP */
531                 .gpio = AS3722_GPIO6,
532                 .mode = AS3722_GPIO_MODE_ADC_IN,
533         },
534         {
535                 /* otp = 0x81  1.6V LP0*/
536                 .gpio       = AS3722_GPIO7,
537                 .invert     = AS3722_GPIO_CFG_INVERT,
538                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
539                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
540         },
541 };
542
543 static struct as3722_platform_data as3722_pdata = {
544         .reg_init[AS3722_LDO0] = &as3722_ldo0,
545         .reg_init[AS3722_LDO1] = &as3722_ldo1,
546         .reg_init[AS3722_LDO2] = &as3722_ldo2,
547         .reg_init[AS3722_LDO3] = &as3722_ldo3,
548         .reg_init[AS3722_LDO4] = &as3722_ldo4,
549         .reg_init[AS3722_LDO5] = &as3722_ldo5,
550         .reg_init[AS3722_LDO6] = &as3722_ldo6,
551         .reg_init[AS3722_LDO7] = &as3722_ldo7,
552         .reg_init[AS3722_LDO9] = &as3722_ldo9,
553         .reg_init[AS3722_LDO10] = &as3722_ldo10,
554         .reg_init[AS3722_LDO11] = &as3722_ldo11,
555
556         .reg_init[AS3722_SD0] = &as3722_sd0,
557         .reg_init[AS3722_SD1] = &as3722_sd1,
558         .reg_init[AS3722_SD2] = &as3722_sd2,
559         .reg_init[AS3722_SD4] = &as3722_sd4,
560         .reg_init[AS3722_SD5] = &as3722_sd5,
561         .reg_init[AS3722_SD6] = &as3722_sd6,
562
563         .core_init_data = &as3722_core_init_data[0],
564         .gpio_base = AS3722_GPIO_BASE,
565         .irq_base = AS3722_IRQ_BASE,
566         /* .irq_type = IRQF_TRIGGER_FALLING, */
567         .use_internal_int_pullup = 0,
568         .use_internal_i2c_pullup = 0,
569         .num_gpio_cfgs = ARRAY_SIZE(as3722_gpio_cfgs),
570         .gpio_cfgs     = as3722_gpio_cfgs,
571 };
572
573 static struct pca953x_platform_data tca6416_pdata = {
574         .gpio_base = PMU_TCA6416_GPIO_BASE,
575 };
576
577 static const struct i2c_board_info tca6416_expander[] = {
578         {
579                 I2C_BOARD_INFO("tca6416", 0x20),
580                 .platform_data = &tca6416_pdata,
581         },
582 };
583
584
585 static struct i2c_board_info __initdata as3722_regulators[] = {
586         {
587                 I2C_BOARD_INFO("as3722", 0x40),
588                 .flags = I2C_CLIENT_WAKE,
589                 .irq = INT_EXTERNAL_PMU,
590                 .platform_data = &as3722_pdata,
591         },
592 };
593
594 int __init laguna_as3722_regulator_init(void)
595 {
596         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
597         u32 pmc_ctrl;
598
599
600         /* AS3722: Normal state of INT request line is LOW.
601          * configure the power management controller to trigger PMU
602          * interrupts when HIGH.
603          */
604         pmc_ctrl = readl(pmc + PMC_CTRL);
605         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
606
607         printk(KERN_INFO "%s: i2c_register_board_info\n",
608                         __func__);
609         i2c_register_board_info(4, as3722_regulators,
610                         ARRAY_SIZE(as3722_regulators));
611         i2c_register_board_info(0, tca6416_expander,
612                         ARRAY_SIZE(tca6416_expander));
613         return 0;
614 }
615
616 static struct tegra_suspend_platform_data laguna_suspend_data = {
617         .cpu_timer      = 2000,
618         .cpu_off_timer  = 2000,
619         .suspend_mode   = TEGRA_SUSPEND_NONE,
620         .core_timer     = 0x7e7e,
621         .core_off_timer = 2000,
622         .corereq_high   = true,
623         .sysclkreq_high = true,
624         .cpu_lp2_min_residency = 1000,
625 };
626
627 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
628 /* board parameters for cpu dfll */
629 static struct tegra_cl_dvfs_cfg_param laguna_cl_dvfs_param = {
630         .sample_rate = 12500,
631
632         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
633         .cf = 10,
634         .ci = 0,
635         .cg = 2,
636
637         .droop_cut_value = 0xF,
638         .droop_restore_ramp = 0x0,
639         .scale_out_ramp = 0x0,
640 };
641 #endif
642
643 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
644 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
645 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
646 static inline void fill_reg_map(void)
647 {
648         int i;
649         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
650                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
651                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
652         }
653 }
654
655 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
656 static struct tegra_cl_dvfs_platform_data laguna_cl_dvfs_data = {
657         .dfll_clk_name = "dfll_cpu",
658         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
659         .u.pmu_i2c = {
660                 .fs_rate = 400000,
661                 .slave_addr = 0x86,
662                 .reg = 0x00,
663         },
664         .vdd_map = pmu_cpu_vdd_map,
665         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
666
667         .cfg_param = &laguna_cl_dvfs_param,
668 };
669
670 static int __init laguna_cl_dvfs_init(void)
671 {
672         fill_reg_map();
673         tegra_cl_dvfs_device.dev.platform_data = &laguna_cl_dvfs_data;
674         platform_device_register(&tegra_cl_dvfs_device);
675
676         return 0;
677 }
678 #endif
679
680 /* Always ON /Battery regulator */
681 static struct regulator_consumer_supply fixed_reg_battery_supply[] = {
682         REGULATOR_SUPPLY("vdd_sys_bl", NULL),
683 };
684
685 /* EN_USB1_VBUS From TEGRA GPIO PN4 */
686 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
687         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
688 };
689
690 /* EN_USB3_VBUS From TEGRA GPIO PK6 */
691 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
692         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
693         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci"),
694 };
695
696
697 /* Gated by PMU_REGEN3 From AMS7230 GPIO3*/
698 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
699         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
700 };
701
702 /* LCD_BL_EN GMI_AD10 */
703 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
704         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
705 };
706
707 /* GPIO ?*/
708 static struct regulator_consumer_supply fixed_reg_3v3_supply[] = {
709         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
710         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
711         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
712         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
713         REGULATOR_SUPPLY("avdd_hdmi", "NULL"),
714         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
715         REGULATOR_SUPPLY("avdd_3v3_pex", NULL),
716         REGULATOR_SUPPLY("avdd_3v3_pex_pll", NULL),
717         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
718         REGULATOR_SUPPLY("vddio_hv", "NULL"),
719         REGULATOR_SUPPLY("hvdd_sata", NULL),
720         REGULATOR_SUPPLY("avdd_lcd", NULL),
721 };
722
723 static struct regulator_consumer_supply fixed_reg_dcdc_1v8_supply[] = {
724         REGULATOR_SUPPLY("avdd_lvds0_pll", NULL),
725         REGULATOR_SUPPLY("vdd_utmip_pll", NULL),
726         REGULATOR_SUPPLY("dvdd_lcd", NULL),
727         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
728 };
729
730 /* gated by GPIO EXP GPIO0 */
731 static struct regulator_consumer_supply fixed_reg_dcdc_1v2_supply[] = {
732         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
733 };
734
735
736 /* Macro for defining fixed regulator sub device data */
737 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
738 #define FIXED_REG(_id, _var, _name, _always_on, _boot_on,       \
739                 _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
740 static struct regulator_init_data ri_data_##_var =              \
741 {                                                               \
742         .num_consumer_supplies =                                \
743         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
744         .consumer_supplies = fixed_reg_##_name##_supply,        \
745         .constraints = {                                        \
746                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
747                                 REGULATOR_MODE_STANDBY),        \
748                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
749                                 REGULATOR_CHANGE_STATUS |       \
750                                 REGULATOR_CHANGE_VOLTAGE),      \
751                 .always_on = _always_on,                        \
752                 .boot_on = _boot_on,                            \
753         },                                                      \
754 };                                                              \
755 static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
756 {                                                               \
757         .supply_name = FIXED_SUPPLY(_name),                     \
758         .microvolts = _millivolts * 1000,                       \
759         .gpio = _gpio_nr,                                       \
760         .gpio_is_open_drain = _open_drain,                      \
761         .enable_high = _active_high,                            \
762         .enabled_at_boot = _boot_state,                         \
763         .init_data = &ri_data_##_var,                           \
764 };                                                              \
765 static struct platform_device fixed_reg_##_var##_dev = {        \
766         .name = "reg-fixed-voltage",                            \
767         .id = _id,                                              \
768         .dev = {                                                \
769                 .platform_data = &fixed_reg_##_var##_pdata,     \
770         },                                                      \
771 }
772
773 FIXED_REG(0,    battery,        battery,        0,      0,
774                 -1,     false, true,    0,      8400);
775
776 FIXED_REG(1,    vdd_hdmi_5v0,   vdd_hdmi_5v0,   0,      0,
777                 TEGRA_GPIO_PK1, false,  true,   0,      5000);
778
779 FIXED_REG(2,    usb1_vbus,      usb1_vbus,      0,      0,
780                 TEGRA_GPIO_PN4, true,   true,   0,      5000);
781
782 FIXED_REG(3,    usb3_vbus,      usb3_vbus,      0,      0,
783                 TEGRA_GPIO_PK6, true,   true,   0,      5000);
784
785 FIXED_REG(4,    lcd_bl_en,      lcd_bl_en,      0,      0,
786                 TEGRA_GPIO_PH2, false,  true,   0,      5000);
787
788 FIXED_REG(5,    3v3,            3v3,            0,      0,
789                 -1,     false,  true,   0,      3300);
790
791 FIXED_REG(6,    dcdc_1v8,       dcdc_1v8,       0,      0,
792                 -1,     false,  true,   0,      1800);
793
794 FIXED_REG(7,    dcdc_1v2,       dcdc_1v2,       0,      0,
795                 PMU_TCA6416_GPIO_BASE,     false,  true,   0,      1200);
796 /*
797  * Creating the fixed regulator device tables
798  */
799
800 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
801
802 #define LAGUNA_COMMON_FIXED_REG                 \
803         ADD_FIXED_REG(battery),                 \
804         ADD_FIXED_REG(vdd_hdmi_5v0),            \
805         ADD_FIXED_REG(usb1_vbus),               \
806         ADD_FIXED_REG(usb3_vbus),               \
807         ADD_FIXED_REG(lcd_bl_en),               \
808         ADD_FIXED_REG(3v3),                     \
809         ADD_FIXED_REG(dcdc_1v8),                \
810         ADD_FIXED_REG(dcdc_1v2),
811
812 /* Gpio switch regulator platform data for laguna */
813 static struct platform_device *fixed_reg_devs_pm360[] = {
814         LAGUNA_COMMON_FIXED_REG
815 };
816
817
818 static int __init laguna_fixed_regulator_init(void)
819 {
820
821         if (!of_machine_is_compatible("nvidia,ardbeg"))
822                 return 0;
823
824         return platform_add_devices(fixed_reg_devs_pm360,
825                         ARRAY_SIZE(fixed_reg_devs_pm360));
826 }
827
828 subsys_initcall_sync(laguna_fixed_regulator_init);
829
830 int __init laguna_regulator_init(void)
831 {
832
833 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
834         laguna_cl_dvfs_init();
835 #endif
836         laguna_as3722_regulator_init();
837
838         return 0;
839 }
840
841 int __init laguna_suspend_init(void)
842 {
843         tegra_init_suspend(&laguna_suspend_data);
844         return 0;
845 }
846
847 int __init laguna_edp_init(void)
848 {
849 #ifdef CONFIG_TEGRA_EDP_LIMITS
850         unsigned int regulator_mA;
851
852         regulator_mA = get_maximum_cpu_current_supported();
853         if (!regulator_mA)
854                 regulator_mA = 15000;
855
856         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
857
858         tegra_init_cpu_edp_limits(regulator_mA);
859 #endif
860         return 0;
861 }
862
863
864 static struct soctherm_platform_data laguna_soctherm_data = {
865         .therm = {
866                 [THERM_CPU] = {
867                         .zone_enable = true,
868                         .passive_delay = 1000,
869                         .hotspot_offset = 6000,
870                         .num_trips = 3,
871                         .trips = {
872                                 {
873                                         .cdev_type = "tegra-balanced",
874                                         .trip_temp = 90000,
875                                         .trip_type = THERMAL_TRIP_PASSIVE,
876                                         .upper = THERMAL_NO_LIMIT,
877                                         .lower = THERMAL_NO_LIMIT,
878                                 },
879                                 {
880                                         .cdev_type = "tegra-heavy",
881                                         .trip_temp = 100000,
882                                         .trip_type = THERMAL_TRIP_HOT,
883                                         .upper = THERMAL_NO_LIMIT,
884                                         .lower = THERMAL_NO_LIMIT,
885                                 },
886                                 {
887                                         .cdev_type = "tegra-shutdown",
888                                         .trip_temp = 102000,
889                                         .trip_type = THERMAL_TRIP_CRITICAL,
890                                         .upper = THERMAL_NO_LIMIT,
891                                         .lower = THERMAL_NO_LIMIT,
892                                 },
893                         },
894                 },
895                 [THERM_GPU] = {
896                         .zone_enable = true,
897                         .passive_delay = 1000,
898                         .hotspot_offset = 6000,
899                         .num_trips = 3,
900                         .trips = {
901                                 {
902                                         .cdev_type = "tegra-balanced",
903                                         .trip_temp = 90000,
904                                         .trip_type = THERMAL_TRIP_PASSIVE,
905                                         .upper = THERMAL_NO_LIMIT,
906                                         .lower = THERMAL_NO_LIMIT,
907                                 },
908                                 {
909                                         .cdev_type = "tegra-heavy",
910                                         .trip_temp = 100000,
911                                         .trip_type = THERMAL_TRIP_HOT,
912                                         .upper = THERMAL_NO_LIMIT,
913                                         .lower = THERMAL_NO_LIMIT,
914                                 },
915                                 {
916                                         .cdev_type = "tegra-shutdown",
917                                         .trip_temp = 102000,
918                                         .trip_type = THERMAL_TRIP_CRITICAL,
919                                         .upper = THERMAL_NO_LIMIT,
920                                         .lower = THERMAL_NO_LIMIT,
921                                 },
922                         },
923                 },
924                 [THERM_PLL] = {
925                         .zone_enable = true,
926                 },
927         },
928         .throttle = {
929                 [THROTTLE_HEAVY] = {
930                         .devs = {
931                                 [THROTTLE_DEV_CPU] = {
932                                         .enable = 1,
933                                 },
934                         },
935                 },
936         },
937 };
938
939 int __init laguna_soctherm_init(void)
940 {
941         tegra_platform_edp_init(laguna_soctherm_data.therm[THERM_CPU].trips,
942                         &laguna_soctherm_data.therm[THERM_CPU].num_trips,
943                         8000); /* edp temperature margin */
944         tegra_add_tj_trips(laguna_soctherm_data.therm[THERM_CPU].trips,
945                         &laguna_soctherm_data.therm[THERM_CPU].num_trips);
946
947         return tegra11_soctherm_init(&laguna_soctherm_data);
948 }