arch/arm/mach-tegra/board-laguna-power.c

   1 /*
   2  * arch/arm/mach-tegra/board-laguna-power.c
   3  *
   4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  18  */
  19
  20 #include <linux/i2c.h>
  21 #include <linux/i2c/pca954x.h>
  22 #include <linux/i2c/pca953x.h>
  23 #include <linux/pda_power.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/resource.h>
  26 #include <linux/io.h>
  27 #include <linux/regulator/machine.h>
  28 #include <linux/regulator/driver.h>
  29 #include <linux/regulator/fixed.h>
  30 #include <linux/mfd/as3722-reg.h>
  31 #include <linux/mfd/as3722-plat.h>
  32 #include <linux/gpio.h>
  33 #include <linux/regulator/userspace-consumer.h>
  34
  35 #include <asm/mach-types.h>
  36
  37 #include <mach/irqs.h>
  38 #include <mach/edp.h>
  39 #include <mach/gpio-tegra.h>
  40
  41 #include "cpu-tegra.h"
  42 #include "pm.h"
  43 #include "tegra-board-id.h"
  44 #include "board.h"
  45 #include "gpio-names.h"
  46 #include "board-common.h"
  47 #include "board-pmu-defines.h"
  48 #include "board-ardbeg.h"
  49 #include "tegra_cl_dvfs.h"
  50 #include "devices.h"
  51 #include "tegra11_soctherm.h"
  52 #include "iomap.h"
  53
  54 #define PMC_CTRL                0x0
  55 #define PMC_CTRL_INTR_LOW       (1 << 17)
  56 #define AS3722_SUPPLY(_name) "as3722_"#_name
  57
  58 static struct regulator_consumer_supply as3722_ldo0_supply[] = {
  59         REGULATOR_SUPPLY("avdd_pll_m", NULL),
  60         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
  61         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
  62         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
  63         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
  64         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
  65         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
  66         REGULATOR_SUPPLY("avdd_pll_x", NULL),
  67         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
  68 };
  69
  70 static struct regulator_consumer_supply as3722_ldo1_supply[] = {
  71         REGULATOR_SUPPLY("vddio_cam", "vi"),
  72         REGULATOR_SUPPLY("pwrdet_cam", NULL),
  73         REGULATOR_SUPPLY("vdd_cam_1v8_cam", NULL),
  74         REGULATOR_SUPPLY("vif", "2-0010"),
  75         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
  76 };
  77
  78 static struct regulator_consumer_supply as3722_ldo2_supply[] = {
  79         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
  80         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
  81         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
  82         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
  83         REGULATOR_SUPPLY("avdd_hsic_com", NULL),
  84         REGULATOR_SUPPLY("avdd_hsic_mdm", NULL),
  85         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
  86         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
  87         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
  88 };
  89
  90 static struct regulator_consumer_supply as3722_ldo3_supply[] = {
  91         REGULATOR_SUPPLY("vdd_rtc", NULL),
  92 };
  93
  94 static struct regulator_consumer_supply as3722_ldo4_supply[] = {
  95         REGULATOR_SUPPLY("vdd_2v7_hv", NULL),
  96         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
  97         REGULATOR_SUPPLY("vana", "2-0010"),
  98 };
  99
 100 static struct regulator_consumer_supply as3722_ldo5_supply[] = {
 101         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
 102         REGULATOR_SUPPLY("vdig", "2-0010"),
 103 };
 104
 105 static struct regulator_consumer_supply as3722_ldo6_supply[] = {
 106         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
 107         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
 108 };
 109
 110 static struct regulator_consumer_supply as3722_ldo7_supply[] = {
 111         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
 112 };
 113
 114 static struct regulator_consumer_supply as3722_ldo9_supply[] = {
 115         REGULATOR_SUPPLY("vdd_ts_3v0b_dis", NULL),
 116 };
 117
 118 static struct regulator_consumer_supply as3722_ldo10_supply[] = {
 119         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
 120         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
 121         REGULATOR_SUPPLY("imx135_reg1", NULL),
 122         REGULATOR_SUPPLY("vdd", "2-000e"),
 123 };
 124
 125 static struct regulator_consumer_supply as3722_ldo11_supply[] = {
 126         REGULATOR_SUPPLY("vpp_fuse", NULL),
 127 };
 128
 129 static struct regulator_consumer_supply as3722_sd0_supply[] = {
 130         REGULATOR_SUPPLY("vdd_cpu", NULL),
 131 };
 132
 133 static struct regulator_consumer_supply as3722_sd1_supply[] = {
 134         REGULATOR_SUPPLY("vdd_core", NULL),
 135 };
 136
 137 static struct regulator_consumer_supply as3722_sd2_supply[] = {
 138         REGULATOR_SUPPLY("vddio_ddr", NULL),
 139         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
 140         REGULATOR_SUPPLY("vddio_ddr3", NULL),
 141         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
 142 };
 143
 144 static struct regulator_consumer_supply as3722_sd4_supply[] = {
 145         REGULATOR_SUPPLY("avdd_pex_pll", NULL),
 146         REGULATOR_SUPPLY("avddio_pex_pll", NULL),
 147         REGULATOR_SUPPLY("dvddio_pex", NULL),
 148         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
 149         REGULATOR_SUPPLY("avdd_sata", NULL),
 150         REGULATOR_SUPPLY("vdd_sata", NULL),
 151         REGULATOR_SUPPLY("avdd_sata_pll", NULL),
 152         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
 153         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
 154 };
 155
 156 static struct regulator_consumer_supply as3722_sd5_supply[] = {
 157         REGULATOR_SUPPLY("vddio_sys", NULL),
 158         REGULATOR_SUPPLY("vddio_sys_2", NULL),
 159         REGULATOR_SUPPLY("vddio_audio", NULL),
 160         REGULATOR_SUPPLY("pwrdet_audio", NULL),
 161         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
 162         REGULATOR_SUPPLY("pwrdet_sdmmc4", "sdhci-tegra.3"),
 163         REGULATOR_SUPPLY("vddio_uart", NULL),
 164         REGULATOR_SUPPLY("pwrdet_uart", NULL),
 165         REGULATOR_SUPPLY("vddio_bb", NULL),
 166         REGULATOR_SUPPLY("pwrdet_bb", NULL),
 167         REGULATOR_SUPPLY("vddio_gmi", NULL),
 168         REGULATOR_SUPPLY("pwrdet_nand", NULL),
 169         REGULATOR_SUPPLY("avdd_osc", NULL),
 170         /* emmc 1.8v misssing
 171         keyboard & touchpad 1.8v missing */
 172 };
 173
 174 static struct regulator_consumer_supply as3722_sd6_supply[] = {
 175         REGULATOR_SUPPLY("vdd_gpu", NULL),
 176 };
 177
 178 AMS_PDATA_INIT(sd0, NULL, 700000, 1400000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE2);
 179 AMS_PDATA_INIT(sd1, NULL, 700000, 1350000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
 180 AMS_PDATA_INIT(sd2, NULL, 1350000, 1350000, 1, 1, 1, 0);
 181 AMS_PDATA_INIT(sd4, NULL, 1050000, 1050000, 0, 1, 1, 0);
 182 AMS_PDATA_INIT(sd5, NULL, 1800000, 1800000, 1, 1, 1, 0);
 183 AMS_PDATA_INIT(sd6, NULL, 800000, 1200000, 1, 1, 1, 0);
 184 AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
 185 AMS_PDATA_INIT(ldo1, NULL, 1800000, 1800000, 0, 1, 1, 0);
 186 AMS_PDATA_INIT(ldo2, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 1, 1, 0);
 187 AMS_PDATA_INIT(ldo3, NULL, 800000, 800000, 1, 1, 1, 0);
 188 AMS_PDATA_INIT(ldo4, NULL, 2700000, 2700000, 0, 0, 1, 0);
 189 AMS_PDATA_INIT(ldo5, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
 190 AMS_PDATA_INIT(ldo6, NULL, 1800000, 3300000, 0, 0, 1, 0);
 191 AMS_PDATA_INIT(ldo7, AS3722_SUPPLY(sd5), 1050000, 1050000, 0, 0, 1, 0);
 192 AMS_PDATA_INIT(ldo9, NULL, 3300000, 3300000, 0, 1, 1, 0);
 193 AMS_PDATA_INIT(ldo10, NULL, 2700000, 2700000, 0, 0, 1, 0);
 194 AMS_PDATA_INIT(ldo11, NULL, 1800000, 1800000, 0, 0, 1, 0);
 195
 196 /* config settings are OTP plus initial state
 197  * GPIOsignal_out at 20h not configurable through OTP and is initialized to
 198  * zero. To enable output, the invert bit must be turned on.
 199  * GPIOxcontrol register format
 200  * bit(s)  bitname
 201  * ---------------------
 202  *  7     gpiox_invert   invert input or output
 203  * 6:3    gpiox_iosf     0: normal
 204  * 2:0    gpiox_mode     0: input, 1: output push/pull, 3: ADC input (tristate)
 205  *
 206  * Examples:
 207  * otp  meaning
 208  * ------------
 209  * 0x3  gpiox_invert=0(no invert), gpiox_iosf=0(normal), gpiox_mode=3(ADC input)
 210  * 0x81 gpiox_invert=1(invert), gpiox_iosf=0(normal), gpiox_mode=1(output)
 211  *
 212  * Note: output state should be defined for gpiox_mode = output.  Do not change
 213  * the state of the invert bit for critical devices such as GPIO 7 which enables
 214  * SDRAM. Driver applies invert mask to output state to configure GPIOsignal_out
 215  * register correctly.
 216  * E.g. Invert = 1, (requested) output state = 1 => GPIOsignal_out = 0
 217  */
 218 static struct as3722_gpio_config as3722_gpio_cfgs[] = {
 219         {
 220                 /* otp = 0x3 IGPU_PRDGD*/
 221                 .gpio = AS3722_GPIO0,
 222                 .mode = AS3722_GPIO_MODE_OUTPUT_VDDL,
 223         },
 224         {
 225                 /* otp = 0x1  => REGEN_3 = LP0 gate (1.8V, 5 V)*/
 226                 .gpio = AS3722_GPIO1,
 227                 .invert     = AS3722_GPIO_CFG_INVERT, /* don't go into LP0 */
 228                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
 229                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
 230         },
 231         {
 232                 /* otp = 0x3 PMU_REGEN1*/
 233                 .gpio = AS3722_GPIO2,
 234                 .invert     = AS3722_GPIO_CFG_INVERT, /* don't go into LP0 */
 235                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
 236                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
 237         },
 238         {
 239                 /* otp = 0x03 AP THERMISTOR */
 240                 .gpio = AS3722_GPIO3,
 241                 .mode = AS3722_GPIO_MODE_ADC_IN,
 242         },
 243         {
 244                 /* otp = 0x81 => on by default
 245                  * gates EN_AVDD_LCD
 246                  */
 247                 .gpio       = AS3722_GPIO4,
 248                 .invert     = AS3722_GPIO_CFG_NO_INVERT,
 249                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
 250                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
 251         },
 252         {
 253                 /* otp = 0x3  CLK 23KHZ WIFI */
 254                 .gpio = AS3722_GPIO5,
 255                 .mode = AS3722_GPIO_MODE_ADC_IN,
 256         },
 257         {
 258                 /* otp = 0x3  SKIN TEMP */
 259                 .gpio = AS3722_GPIO6,
 260                 .mode = AS3722_GPIO_MODE_ADC_IN,
 261         },
 262         {
 263                 /* otp = 0x81  1.6V LP0*/
 264                 .gpio       = AS3722_GPIO7,
 265                 .invert     = AS3722_GPIO_CFG_NO_INVERT,
 266                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
 267                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
 268         },
 269 };
 270
 271 static struct as3722_rtc_platform_data as3722_rtc_pdata = {
 272         .enable_clk32k  = 1,
 273 };
 274
 275 static struct as3722_adc_extcon_platform_data as3722_adc_extcon_pdata = {
 276         .connection_name = "as3722-extcon",
 277         .enable_adc1_continuous_mode = true,
 278         .enable_low_voltage_range = true,
 279         .adc_channel = 12,
 280         .hi_threshold =  0x100,
 281         .low_threshold = 0x80,
 282 };
 283
 284 static struct as3722_platform_data as3722_pdata = {
 285         .reg_pdata[AS3722_LDO0] = &as3722_ldo0_reg_pdata,
 286         .reg_pdata[AS3722_LDO1] = &as3722_ldo1_reg_pdata,
 287         .reg_pdata[AS3722_LDO2] = &as3722_ldo2_reg_pdata,
 288         .reg_pdata[AS3722_LDO3] = &as3722_ldo3_reg_pdata,
 289         .reg_pdata[AS3722_LDO4] = &as3722_ldo4_reg_pdata,
 290         .reg_pdata[AS3722_LDO5] = &as3722_ldo5_reg_pdata,
 291         .reg_pdata[AS3722_LDO6] = &as3722_ldo6_reg_pdata,
 292         .reg_pdata[AS3722_LDO7] = &as3722_ldo7_reg_pdata,
 293         .reg_pdata[AS3722_LDO9] = &as3722_ldo9_reg_pdata,
 294         .reg_pdata[AS3722_LDO10] = &as3722_ldo10_reg_pdata,
 295         .reg_pdata[AS3722_LDO11] = &as3722_ldo11_reg_pdata,
 296
 297         .reg_pdata[AS3722_SD0] = &as3722_sd0_reg_pdata,
 298         .reg_pdata[AS3722_SD1] = &as3722_sd1_reg_pdata,
 299         .reg_pdata[AS3722_SD2] = &as3722_sd2_reg_pdata,
 300         .reg_pdata[AS3722_SD4] = &as3722_sd4_reg_pdata,
 301         .reg_pdata[AS3722_SD5] = &as3722_sd5_reg_pdata,
 302         .reg_pdata[AS3722_SD6] = &as3722_sd6_reg_pdata,
 303
 304         .core_init_data = NULL,
 305         .gpio_base = AS3722_GPIO_BASE,
 306         .irq_base = AS3722_IRQ_BASE,
 307         .use_internal_int_pullup = 0,
 308         .use_internal_i2c_pullup = 0,
 309         .num_gpio_cfgs = ARRAY_SIZE(as3722_gpio_cfgs),
 310         .gpio_cfgs     = as3722_gpio_cfgs,
 311         .rtc_pdata      = &as3722_rtc_pdata,
 312         .use_power_off = true,
 313         .enable_ldo3_tracking = true,
 314         .disabe_ldo3_tracking_suspend = true,
 315         .extcon_pdata = &as3722_adc_extcon_pdata,
 316 };
 317
 318 static struct pca953x_platform_data tca6416_pdata = {
 319         .gpio_base = PMU_TCA6416_GPIO_BASE,
 320 };
 321
 322 static const struct i2c_board_info tca6416_expander[] = {
 323         {
 324                 I2C_BOARD_INFO("tca6416", 0x20),
 325                 .platform_data = &tca6416_pdata,
 326         },
 327 };
 328
 329 static const struct i2c_board_info tca6408_expander[] = {
 330         {
 331                 I2C_BOARD_INFO("tca6408", 0x20),
 332                 .platform_data = &tca6416_pdata,
 333         },
 334 };
 335
 336 static struct i2c_board_info __initdata as3722_regulators[] = {
 337         {
 338                 I2C_BOARD_INFO("as3722", 0x40),
 339                 .flags = I2C_CLIENT_WAKE,
 340                 .irq = INT_EXTERNAL_PMU,
 341                 .platform_data = &as3722_pdata,
 342         },
 343 };
 344
 345 int __init laguna_as3722_regulator_init(void)
 346 {
 347         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
 348         u32 pmc_ctrl;
 349         struct board_info board_info;
 350
 351         tegra_get_board_info(&board_info);
 352
 353         /* AS3722: Normal state of INT request line is LOW.
 354          * configure the power management controller to trigger PMU
 355          * interrupts when HIGH.
 356          */
 357         pmc_ctrl = readl(pmc + PMC_CTRL);
 358         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
 359         regulator_has_full_constraints();
 360         /* Set vdd_gpu init uV to 1V */
 361         as3722_sd6_reg_idata.constraints.init_uV = 1000000;
 362
 363         /* Set overcurrent of rails. */
 364         as3722_sd6_reg_pdata.oc_configure_enable = true;
 365         as3722_sd6_reg_pdata.oc_trip_thres_perphase = 3500;
 366         as3722_sd6_reg_pdata.oc_alarm_thres_perphase = 0;
 367
 368         as3722_sd0_reg_pdata.oc_configure_enable = true;
 369         as3722_sd0_reg_pdata.oc_trip_thres_perphase = 3500;
 370         as3722_sd0_reg_pdata.oc_alarm_thres_perphase = 0;
 371
 372         as3722_sd1_reg_pdata.oc_configure_enable = true;
 373         as3722_sd1_reg_pdata.oc_trip_thres_perphase = 2500;
 374         as3722_sd1_reg_pdata.oc_alarm_thres_perphase = 0;
 375
 376         printk(KERN_INFO "%s: i2c_register_board_info\n",
 377                         __func__);
 378         if (board_info.board_id == BOARD_PM358) {
 379                 switch (board_info.fab) {
 380                 case BOARD_FAB_A01:
 381                         as3722_pdata.reg_pdata[AS3722_LDO5] =
 382                                 &as3722_ldo7_reg_pdata;
 383                         as3722_pdata.reg_pdata[AS3722_LDO7] =
 384                                 &as3722_ldo5_reg_pdata;
 385                         as3722_pdata.reg_pdata[AS3722_LDO4] =
 386                                 &as3722_ldo10_reg_pdata;
 387                         as3722_pdata.reg_pdata[AS3722_LDO10] =
 388                                 &as3722_ldo4_reg_pdata;
 389                         break;
 390                 default:
 391                         break;
 392                 }
 393         }
 394         i2c_register_board_info(4, as3722_regulators,
 395                         ARRAY_SIZE(as3722_regulators));
 396         if (board_info.board_id == BOARD_PM358 &&
 397                         board_info.fab == BOARD_FAB_A00)
 398                 i2c_register_board_info(0, tca6408_expander,
 399                                 ARRAY_SIZE(tca6408_expander));
 400         else if (board_info.board_id == BOARD_PM359 ||
 401                         board_info.board_id == BOARD_PM358)
 402                 i2c_register_board_info(0, tca6416_expander,
 403                                 ARRAY_SIZE(tca6416_expander));
 404         return 0;
 405 }
 406
 407 static struct tegra_suspend_platform_data laguna_suspend_data = {
 408         .cpu_timer      = 2000,
 409         .cpu_off_timer  = 2000,
 410         .suspend_mode   = TEGRA_SUSPEND_LP0,
 411         .core_timer     = 0x7e7e,
 412         .core_off_timer = 2000,
 413         .corereq_high   = true,
 414         .sysclkreq_high = true,
 415         .cpu_lp2_min_residency = 1000,
 416 };
 417
 418 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
 419 /* board parameters for cpu dfll */
 420 static struct tegra_cl_dvfs_cfg_param laguna_cl_dvfs_param = {
 421         .sample_rate = 12500,
 422
 423         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
 424         .cf = 10,
 425         .ci = 0,
 426         .cg = 2,
 427
 428         .droop_cut_value = 0xF,
 429         .droop_restore_ramp = 0x0,
 430         .scale_out_ramp = 0x0,
 431 };
 432 #endif
 433
 434 /* Laguna: fixed 10mV steps from 700mV to 1400mV */
 435 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 700000) / 10000 + 1)
 436 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
 437 static inline void fill_reg_map(void)
 438 {
 439         int i;
 440         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
 441                 pmu_cpu_vdd_map[i].reg_value = i + 0xa;
 442                 pmu_cpu_vdd_map[i].reg_uV = 700000 + 10000 * i;
 443         }
 444 }
 445
 446 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
 447 static struct tegra_cl_dvfs_platform_data laguna_cl_dvfs_data = {
 448         .dfll_clk_name = "dfll_cpu",
 449         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
 450         .u.pmu_i2c = {
 451                 .fs_rate = 400000,
 452                 .slave_addr = 0x80,
 453                 .reg = 0x00,
 454         },
 455         .vdd_map = pmu_cpu_vdd_map,
 456         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
 457
 458         .cfg_param = &laguna_cl_dvfs_param,
 459 };
 460
 461 static int __init laguna_cl_dvfs_init(void)
 462 {
 463         fill_reg_map();
 464         laguna_cl_dvfs_data.flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
 465         tegra_cl_dvfs_device.dev.platform_data = &laguna_cl_dvfs_data;
 466         platform_device_register(&tegra_cl_dvfs_device);
 467
 468         return 0;
 469 }
 470 #endif
 471
 472 /* Always ON /Battery regulator */
 473 static struct regulator_consumer_supply fixed_reg_battery_supply[] = {
 474         REGULATOR_SUPPLY("vdd_sys_bl", NULL),
 475 };
 476
 477 /* Always ON 1.8v */
 478 static struct regulator_consumer_supply fixed_reg_aon_1v8_supply[] = {
 479         REGULATOR_SUPPLY("vdd_1v8_emmc", NULL),
 480         REGULATOR_SUPPLY("vdd_1v8b_com_f", NULL),
 481         REGULATOR_SUPPLY("vdd_1v8b_gps_f", NULL),
 482 };
 483
 484 /* Always ON 3.3v */
 485 static struct regulator_consumer_supply fixed_reg_aon_3v3_supply[] = {
 486         REGULATOR_SUPPLY("vdd_3v3_emmc", NULL),
 487         REGULATOR_SUPPLY("vdd_com_3v3", NULL),
 488 };
 489
 490 /* Always ON 1v2 */
 491 static struct regulator_consumer_supply fixed_reg_aon_1v2_supply[] = {
 492         REGULATOR_SUPPLY("vdd_1v2_bb_hsic", NULL),
 493 };
 494
 495 /* EN_USB0_VBUS From TEGRA GPIO PN4 */
 496 static struct regulator_consumer_supply fixed_reg_usb0_vbus_supply[] = {
 497         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
 498         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
 499         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
 500 };
 501
 502 /* EN_USB1_USB2_VBUS From TEGRA GPIO PN5 */
 503 static struct regulator_consumer_supply fixed_reg_usb1_usb2_vbus_supply[] = {
 504         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
 505         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
 506         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
 507         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
 508 };
 509
 510
 511 /* Gated by GPIO_PK6  in FAB B and further*/
 512 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
 513         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
 514 };
 515
 516 /* Gated by GPIO_PH7  in FAB B and further*/
 517 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_supply[] = {
 518         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
 519 };
 520
 521 /* VDD_LCD_BL DAP3_DOUT */
 522 static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_supply[] = {
 523         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
 524 };
 525
 526 /* LCD_BL_EN GMI_AD10 */
 527 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
 528         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
 529 };
 530
 531 /* AS3722 GPIO1*/
 532 static struct regulator_consumer_supply fixed_reg_3v3_supply[] = {
 533         REGULATOR_SUPPLY("hvdd_pex", NULL),
 534         REGULATOR_SUPPLY("hvdd_pex_pll", NULL),
 535         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
 536         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5645.0"),
 537         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5639.0"),
 538         REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
 539         REGULATOR_SUPPLY("vdd_nfc_3v3", NULL),
 540         REGULATOR_SUPPLY("vdd_3v3_sensor", NULL),
 541         REGULATOR_SUPPLY("vdd_kp_3v3", NULL),
 542         REGULATOR_SUPPLY("vdd_tp_3v3", NULL),
 543         REGULATOR_SUPPLY("vdd_dtv_3v3", NULL),
 544         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
 545         REGULATOR_SUPPLY("vdd", "1-004c"),
 546         REGULATOR_SUPPLY("vdd", "0-0048"),
 547         REGULATOR_SUPPLY("vdd", "0-0069"),
 548         REGULATOR_SUPPLY("vdd", "0-000c"),
 549         REGULATOR_SUPPLY("vdd", "0-0077"),
 550         REGULATOR_SUPPLY("vin", "2-0030"),
 551 };
 552
 553 /* AS3722 GPIO1*/
 554 static struct regulator_consumer_supply fixed_reg_5v0_supply[] = {
 555         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
 556         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
 557         REGULATOR_SUPPLY("vdd_5v0_sensor", NULL),
 558 };
 559
 560 static struct regulator_consumer_supply fixed_reg_dcdc_1v8_supply[] = {
 561         REGULATOR_SUPPLY("avdd_lvds0_pll", NULL),
 562         REGULATOR_SUPPLY("dvdd_lcd", NULL),
 563         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
 564         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645.0"),
 565         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645.0"),
 566         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639.0"),
 567         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639.0"),
 568         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639.0"),
 569         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645.0"),
 570         REGULATOR_SUPPLY("vdd_1v8b_nfc", NULL),
 571         REGULATOR_SUPPLY("vdd_1v8_sensor", NULL),
 572         REGULATOR_SUPPLY("vdd_1v8_sdmmc", NULL),
 573         REGULATOR_SUPPLY("vdd_kp_1v8", NULL),
 574         REGULATOR_SUPPLY("vdd_tp_1v8", NULL),
 575         REGULATOR_SUPPLY("vdd_modem_1v8", NULL),
 576         REGULATOR_SUPPLY("vdd_1v8b", "0-0048"),
 577         REGULATOR_SUPPLY("vlogic", "0-0069"),
 578         REGULATOR_SUPPLY("vid", "0-000c"),
 579         REGULATOR_SUPPLY("vddio", "0-0077"),
 580         REGULATOR_SUPPLY("vi2c", "2-0030"),
 581         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
 582         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
 583         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
 584         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
 585         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
 586 };
 587
 588 /* gated by TCA6416 GPIO EXP GPIO0 */
 589 static struct regulator_consumer_supply fixed_reg_dcdc_1v2_supply[] = {
 590         REGULATOR_SUPPLY("vdd_1v2_en", NULL),
 591 };
 592
 593 /* AMS GPIO2 */
 594 static struct regulator_consumer_supply fixed_reg_as3722_gpio2_supply[] = {
 595         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
 596         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
 597         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
 598         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
 599         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
 600         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
 601         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
 602         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
 603         REGULATOR_SUPPLY("pwrdet_hv", NULL),
 604         REGULATOR_SUPPLY("hvdd_sata", NULL),
 605 };
 606
 607 /* gated by AS3722 GPIO4 */
 608 static struct regulator_consumer_supply fixed_reg_lcd_supply[] = {
 609         REGULATOR_SUPPLY("avdd_lcd", NULL),
 610 };
 611
 612 /* gated by GPIO_PR0 */
 613 static struct regulator_consumer_supply fixed_reg_sdmmc_en_supply[] = {
 614         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.1"),
 615         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
 616 };
 617
 618 /* only adding for PM358 */
 619 static struct regulator_consumer_supply fixed_reg_vdd_cdc_1v2_aud_supply[] = {
 620         REGULATOR_SUPPLY("ldoen", "tegra-snd-rt5639.0"),
 621 };
 622
 623 static struct regulator_consumer_supply fixed_reg_vdd_amp_shut_aud_supply[] = {
 624         REGULATOR_SUPPLY("epamp", "tegra-snd-rt5645.0"),
 625 };
 626
 627 static struct regulator_consumer_supply fixed_reg_vdd_dsi_mux_supply[] = {
 628         REGULATOR_SUPPLY("vdd_3v3_dsi", "NULL"),
 629 };
 630
 631 /* Macro for defining fixed regulator sub device data */
 632 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
 633 #define FIXED_REG(_id, _var, _name, _in_supply,                 \
 634         _always_on, _boot_on, _gpio_nr, _open_drain,            \
 635         _active_high, _boot_state, _millivolts, _sdelay)        \
 636 static struct regulator_init_data ri_data_##_var =              \
 637 {                                                               \
 638         .supply_regulator = _in_supply,                         \
 639         .num_consumer_supplies =                                \
 640         ARRAY_SIZE(fixed_reg_##_name##_supply),                 \
 641         .consumer_supplies = fixed_reg_##_name##_supply,        \
 642         .constraints = {                                        \
 643                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
 644                                 REGULATOR_MODE_STANDBY),        \
 645                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
 646                                 REGULATOR_CHANGE_STATUS |       \
 647                                 REGULATOR_CHANGE_VOLTAGE),      \
 648                 .always_on = _always_on,                        \
 649                 .boot_on = _boot_on,                            \
 650         },                                                      \
 651 };                                                              \
 652 static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
 653 {                                                               \
 654         .supply_name = FIXED_SUPPLY(_name),                     \
 655         .microvolts = _millivolts * 1000,                       \
 656         .gpio = _gpio_nr,                                       \
 657         .gpio_is_open_drain = _open_drain,                      \
 658         .enable_high = _active_high,                            \
 659         .enabled_at_boot = _boot_state,                         \
 660         .init_data = &ri_data_##_var,                           \
 661         .startup_delay = _sdelay,                               \
 662 };                                                              \
 663 static struct platform_device fixed_reg_##_var##_dev = {        \
 664         .name = "reg-fixed-voltage",                            \
 665         .id = _id,                                              \
 666         .dev = {                                                \
 667                 .platform_data = &fixed_reg_##_var##_pdata,     \
 668         },                                                      \
 669 }
 670
 671 FIXED_REG(0,    battery,        battery,        NULL,   0,      0,
 672                 -1,     false, true,    0,      8400,   0);
 673
 674 FIXED_REG(1,    aon_1v8,        aon_1v8,        NULL,   0,      0,
 675                 -1,     false, true,    0,      1800,   0);
 676
 677 FIXED_REG(2,    aon_3v3,        aon_3v3,        NULL,   0,      0,
 678                 -1,     false, true,    0,      3300,   0);
 679
 680 FIXED_REG(3,    aon_1v2,        aon_1v2,        NULL,   0,      0,
 681                 -1,     false, true,    0,      1200,   0);
 682
 683 FIXED_REG(4,    vdd_hdmi_5v0,   vdd_hdmi_5v0,   NULL,   0,      0,
 684                 TEGRA_GPIO_PK6, false,  true,   0,      5000,   5000);
 685
 686 FIXED_REG(5,    vdd_hdmi,       vdd_hdmi,       AS3722_SUPPLY(sd4),
 687                 0,      0,
 688                 TEGRA_GPIO_PH7, false,  false,  0,      3300,   0);
 689
 690 FIXED_REG(6,    usb0_vbus,      usb0_vbus,      NULL,   0,      0,
 691                 TEGRA_GPIO_PN4, true,   true,   0,      5000,   0);
 692
 693 FIXED_REG(7,    usb1_usb2_vbus, usb1_usb2_vbus, NULL,   0,      0,
 694                 TEGRA_GPIO_PN5, true,   true,   0,      5000, 0);
 695
 696 FIXED_REG(8,    vdd_lcd_bl,     vdd_lcd_bl,     NULL,   0,      0,
 697                 TEGRA_GPIO_PP2, false,  true,   0,      3300, 0);
 698
 699 FIXED_REG(9,    lcd_bl_en,      lcd_bl_en,      NULL,   0,      0,
 700                 TEGRA_GPIO_PH2, false,  true,   0,      5000,   0);
 701
 702 FIXED_REG(10,   3v3,            3v3,            NULL,   0,      0,
 703                 -1,     false,  true,   0,      3300,   0);
 704
 705 FIXED_REG(11,   5v0,            5v0,            NULL,   0,      0,
 706                 -1,     false,  true,   0,      5000,   0);
 707
 708 FIXED_REG(12,   dcdc_1v8,       dcdc_1v8,       NULL,   0,      0,
 709                 -1,     false,  true,   0,      1800,   0);
 710
 711 FIXED_REG(13,    dcdc_1v2, dcdc_1v2,    NULL,   0,      0,
 712                 PMU_TCA6416_GPIO_BASE,     false,  true,   0,      1200,
 713                 0);
 714
 715 FIXED_REG(14,   as3722_gpio2,   as3722_gpio2,           NULL,   0,      0,
 716                 AS3722_GPIO_BASE + AS3722_GPIO2,        false,  false,  0,
 717                 3300,   0);
 718
 719 FIXED_REG(15,   lcd,            lcd,            NULL,   0,      0,
 720                 AS3722_GPIO_BASE + AS3722_GPIO4,        false,  true,   0,
 721                 3300,   0);
 722
 723 FIXED_REG(16,   sdmmc_en,               sdmmc_en,       NULL,   0,      0,
 724                 TEGRA_GPIO_PR0,         false,  true,   0,      3300,   0);
 725
 726 FIXED_REG(17,   vdd_cdc_1v2_aud,        vdd_cdc_1v2_aud,        NULL,   0,
 727                 0,      PMU_TCA6416_GPIO(2),    false,  true,   0,
 728                 1200,   250000);
 729
 730 FIXED_REG(18,   vdd_amp_shut_aud,       vdd_amp_shut_aud,       NULL,   0,
 731                 0,      PMU_TCA6416_GPIO(3),    false,  true,   0,
 732                 1200,   0);
 733
 734 FIXED_REG(19,   vdd_dsi_mux,            vdd_dsi_mux,    NULL,   0,      0,
 735                 PMU_TCA6416_GPIO(13),   false,  true,   0,      3300,   0);
 736 /*
 737  * Creating the fixed regulator device tables
 738  */
 739
 740 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
 741
 742 #define LAGUNA_COMMON_FIXED_REG                 \
 743         ADD_FIXED_REG(battery),                 \
 744         ADD_FIXED_REG(aon_1v8),                 \
 745         ADD_FIXED_REG(aon_3v3),                 \
 746         ADD_FIXED_REG(aon_1v2),                 \
 747         ADD_FIXED_REG(vdd_hdmi_5v0),            \
 748         ADD_FIXED_REG(vdd_hdmi),                \
 749         ADD_FIXED_REG(usb0_vbus),               \
 750         ADD_FIXED_REG(usb1_usb2_vbus),          \
 751         ADD_FIXED_REG(vdd_lcd_bl),              \
 752         ADD_FIXED_REG(lcd_bl_en),               \
 753         ADD_FIXED_REG(3v3),                     \
 754         ADD_FIXED_REG(5v0),                     \
 755         ADD_FIXED_REG(dcdc_1v8),                \
 756         ADD_FIXED_REG(as3722_gpio2),            \
 757         ADD_FIXED_REG(lcd),                     \
 758         ADD_FIXED_REG(sdmmc_en)
 759
 760 #define LAGUNA_PM358_FIXED_REG          \
 761         ADD_FIXED_REG(dcdc_1v2),        \
 762         ADD_FIXED_REG(vdd_cdc_1v2_aud), \
 763         ADD_FIXED_REG(vdd_amp_shut_aud), \
 764         ADD_FIXED_REG(vdd_dsi_mux)
 765
 766 #define LAGUNA_PM359_FIXED_REG          \
 767         ADD_FIXED_REG(dcdc_1v2),        \
 768         ADD_FIXED_REG(vdd_cdc_1v2_aud)
 769
 770
 771 /* Gpio switch regulator platform data for laguna pm358 ERS*/
 772 static struct platform_device *fixed_reg_devs_pm358[] = {
 773         LAGUNA_COMMON_FIXED_REG,
 774         LAGUNA_PM358_FIXED_REG
 775 };
 776
 777 /* Gpio switch regulator platform data for laguna pm359 ERS-S*/
 778 static struct platform_device *fixed_reg_devs_pm359[] = {
 779         LAGUNA_COMMON_FIXED_REG,
 780         LAGUNA_PM359_FIXED_REG
 781 };
 782
 783 /* Gpio switch regulator platform data for laguna pm363 FFD*/
 784 static struct platform_device *fixed_reg_devs_pm363[] = {
 785         LAGUNA_COMMON_FIXED_REG
 786 };
 787
 788 static int __init laguna_fixed_regulator_init(void)
 789 {
 790         struct board_info board_info;
 791
 792         if (!of_machine_is_compatible("nvidia,laguna"))
 793                 return 0;
 794
 795         tegra_get_board_info(&board_info);
 796         if (board_info.board_id == BOARD_PM358)
 797                 return platform_add_devices(fixed_reg_devs_pm358,
 798                                 ARRAY_SIZE(fixed_reg_devs_pm358));
 799         else if (board_info.board_id == BOARD_PM359)
 800                 return platform_add_devices(fixed_reg_devs_pm359,
 801                                 ARRAY_SIZE(fixed_reg_devs_pm359));
 802         else if (board_info.board_id == BOARD_PM363)
 803                 return platform_add_devices(fixed_reg_devs_pm363,
 804                                 ARRAY_SIZE(fixed_reg_devs_pm363));
 805
 806         return 0;
 807 }
 808
 809 subsys_initcall_sync(laguna_fixed_regulator_init);
 810
 811 int __init laguna_regulator_init(void)
 812 {
 813
 814 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
 815         laguna_cl_dvfs_init();
 816 #endif
 817         laguna_as3722_regulator_init();
 818
 819         return 0;
 820 }
 821
 822 int __init laguna_suspend_init(void)
 823 {
 824         tegra_init_suspend(&laguna_suspend_data);
 825         return 0;
 826 }
 827
 828 int __init laguna_edp_init(void)
 829 {
 830 #ifdef CONFIG_TEGRA_EDP_LIMITS
 831         unsigned int regulator_mA;
 832
 833         regulator_mA = get_maximum_cpu_current_supported();
 834         if (!regulator_mA)
 835                 regulator_mA = 15000;
 836
 837         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
 838
 839         tegra_init_cpu_edp_limits(regulator_mA);
 840 #endif
 841         return 0;
 842 }
 843
 844
 845 static struct soctherm_platform_data laguna_soctherm_data = {
 846         .therm = {
 847                 [THERM_CPU] = {
 848                         .zone_enable = true,
 849                         .passive_delay = 1000,
 850                         .hotspot_offset = 6000,
 851                         .num_trips = 3,
 852                         .trips = {
 853                                 {
 854                                         .cdev_type = "tegra-balanced",
 855                                         .trip_temp = 90000,
 856                                         .trip_type = THERMAL_TRIP_PASSIVE,
 857                                         .upper = THERMAL_NO_LIMIT,
 858                                         .lower = THERMAL_NO_LIMIT,
 859                                 },
 860                                 {
 861                                         .cdev_type = "tegra-heavy",
 862                                         .trip_temp = 100000,
 863                                         .trip_type = THERMAL_TRIP_HOT,
 864                                         .upper = THERMAL_NO_LIMIT,
 865                                         .lower = THERMAL_NO_LIMIT,
 866                                 },
 867                                 {
 868                                         .cdev_type = "tegra-shutdown",
 869                                         .trip_temp = 102000,
 870                                         .trip_type = THERMAL_TRIP_CRITICAL,
 871                                         .upper = THERMAL_NO_LIMIT,
 872                                         .lower = THERMAL_NO_LIMIT,
 873                                 },
 874                         },
 875                 },
 876                 [THERM_GPU] = {
 877                         .zone_enable = true,
 878                         .passive_delay = 1000,
 879                         .hotspot_offset = 6000,
 880                         .num_trips = 3,
 881                         .trips = {
 882                                 {
 883                                         .cdev_type = "tegra-balanced",
 884                                         .trip_temp = 90000,
 885                                         .trip_type = THERMAL_TRIP_PASSIVE,
 886                                         .upper = THERMAL_NO_LIMIT,
 887                                         .lower = THERMAL_NO_LIMIT,
 888                                 },
 889                                 {
 890                                         .cdev_type = "tegra-heavy",
 891                                         .trip_temp = 100000,
 892                                         .trip_type = THERMAL_TRIP_HOT,
 893                                         .upper = THERMAL_NO_LIMIT,
 894                                         .lower = THERMAL_NO_LIMIT,
 895                                 },
 896                                 {
 897                                         .cdev_type = "tegra-shutdown",
 898                                         .trip_temp = 102000,
 899                                         .trip_type = THERMAL_TRIP_CRITICAL,
 900                                         .upper = THERMAL_NO_LIMIT,
 901                                         .lower = THERMAL_NO_LIMIT,
 902                                 },
 903                         },
 904                 },
 905                 [THERM_PLL] = {
 906                         .zone_enable = true,
 907                 },
 908         },
 909         .throttle = {
 910                 [THROTTLE_HEAVY] = {
 911                         .devs = {
 912                                 [THROTTLE_DEV_CPU] = {
 913                                         .enable = 1,
 914                                 },
 915                         },
 916                 },
 917         },
 918 };
 919
 920 int __init laguna_soctherm_init(void)
 921 {
 922         tegra_platform_edp_init(laguna_soctherm_data.therm[THERM_CPU].trips,
 923                         &laguna_soctherm_data.therm[THERM_CPU].num_trips,
 924                         8000); /* edp temperature margin */
 925         tegra_add_tj_trips(laguna_soctherm_data.therm[THERM_CPU].trips,
 926                         &laguna_soctherm_data.therm[THERM_CPU].num_trips);
 927
 928         return tegra11_soctherm_init(&laguna_soctherm_data);
 929 }