ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-dt-tegra30.c
1 /*
2  * arch/arm/mach-tegra/board-dt-tegra30.c
3  *
4  * NVIDIA Tegra30 device tree board support
5  *
6  * Copyright (C) 2011-2013 NVIDIA Corporation
7  *
8  * Derived from:
9  *
10  * arch/arm/mach-tegra/board-dt-tegra20.c
11  *
12  * Copyright (C) 2010 Secret Lab Technologies, Ltd.
13  * Copyright (C) 2010 Google, Inc.
14  *
15  * This software is licensed under the terms of the GNU General Public
16  * License version 2, as published by the Free Software Foundation, and
17  * may be copied, distributed, and modified under those terms.
18  *
19  * This program is distributed in the hope that it will be useful,
20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22  * GNU General Public License for more details.
23  *
24  */
25
26 #include <linux/kernel.h>
27 #include <linux/of.h>
28 #include <linux/of_address.h>
29 #include <linux/of_fdt.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/irqchip.h>
33
34 #include <asm/mach/arch.h>
35
36 #include "board.h"
37 #include "common.h"
38 #include "iomap.h"
39
40 #ifdef CONFIG_USE_OF
41
42 struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
43         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
44         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),
45         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL),
46         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", NULL),
47         OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL),
48         OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL),
49         OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
50         OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
51         OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
52         OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
53         OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
54         OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
55         OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL),
56         OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL),
57         OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL),
58         OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
59         OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
60         OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
61         OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL),
62         OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL),
63         OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL),
64         OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL),
65         OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL),
66         OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL),
67         {}
68 };
69
70 static void __init tegra30_dt_init(void)
71 {
72         of_platform_populate(NULL, of_default_bus_match_table,
73                                 tegra30_auxdata_lookup, NULL);
74 }
75
76 static const char *tegra30_dt_board_compat[] = {
77         "nvidia,tegra30",
78         NULL
79 };
80
81 DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
82         .smp            = smp_ops(tegra_smp_ops),
83         .map_io         = tegra_map_common_io,
84         .init_early     = tegra30_init_early,
85         .init_irq       = irqchip_init,
86         .init_time      = tegra_init_timer,
87         .init_machine   = tegra30_dt_init,
88         .init_late      = tegra_init_late,
89         .restart        = tegra_assert_system_reset,
90         .dt_compat      = tegra30_dt_board_compat,
91 MACHINE_END
92
93 #endif