ARM: tegra: soctherm: set initial soctherm values
[linux-3.10.git] / arch / arm / mach-tegra / board-dalmore-power.c
1 /*
2  * arch/arm/mach-tegra/board-dalmore-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/max77663-core.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/mfd/tps65090.h>
31 #include <linux/regulator/max77663-regulator.h>
32 #include <linux/regulator/tps65090-regulator.h>
33 #include <linux/regulator/tps51632-regulator.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/userspace-consumer.h>
36
37 #include <asm/mach-types.h>
38
39 #include <mach/iomap.h>
40 #include <mach/irqs.h>
41 #include <mach/edp.h>
42 #include <mach/gpio-tegra.h>
43
44 #include "cpu-tegra.h"
45 #include "pm.h"
46 #include "tegra-board-id.h"
47 #include "board.h"
48 #include "gpio-names.h"
49 #include "board-dalmore.h"
50 #include "tegra_cl_dvfs.h"
51 #include "devices.h"
52 #include "tegra11_soctherm.h"
53
54 #define PMC_CTRL                0x0
55 #define PMC_CTRL_INTR_LOW       (1 << 17)
56
57 /*TPS65090 consumer rails */
58 static struct regulator_consumer_supply tps65090_dcdc1_supply[] = {
59         REGULATOR_SUPPLY("vdd_sys_5v0", NULL),
60         REGULATOR_SUPPLY("vdd_spk", NULL),
61         REGULATOR_SUPPLY("vdd_sys_modem_5v0", NULL),
62         REGULATOR_SUPPLY("vdd_sys_cam_5v0", NULL),
63 };
64
65 static struct regulator_consumer_supply tps65090_dcdc2_supply[] = {
66         REGULATOR_SUPPLY("vdd_sys_3v3", NULL),
67         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
68         REGULATOR_SUPPLY("pwrdet_hv", NULL),
69         REGULATOR_SUPPLY("vdd_sys_ds_3v3", NULL),
70         REGULATOR_SUPPLY("vdd_sys_nfc_3v3", NULL),
71         REGULATOR_SUPPLY("vdd_hv_nfc_3v3", NULL),
72         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
73         REGULATOR_SUPPLY("vdd_sys_sensor_3v3", NULL),
74         REGULATOR_SUPPLY("vdd_sys_audio_3v3", NULL),
75         REGULATOR_SUPPLY("vdd_sys_dtv_3v3", NULL),
76         REGULATOR_SUPPLY("vcc", "0-007c"),
77         REGULATOR_SUPPLY("vcc", "0-0030"),
78         REGULATOR_SUPPLY("vin", "2-0030"),
79 };
80
81 static struct regulator_consumer_supply tps65090_dcdc3_supply[] = {
82         REGULATOR_SUPPLY("vdd_ao", NULL),
83 };
84
85 static struct regulator_consumer_supply tps65090_ldo1_supply[] = {
86         REGULATOR_SUPPLY("vdd_sby_5v0", NULL),
87 };
88
89 static struct regulator_consumer_supply tps65090_ldo2_supply[] = {
90         REGULATOR_SUPPLY("vdd_sby_3v3", NULL),
91 };
92
93 static struct regulator_consumer_supply tps65090_fet1_supply[] = {
94         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
95 };
96
97 static struct regulator_consumer_supply tps65090_fet3_supply[] = {
98         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
99 };
100
101 static struct regulator_consumer_supply tps65090_fet4_supply[] = {
102         REGULATOR_SUPPLY("avdd_lcd", NULL),
103         REGULATOR_SUPPLY("vdd_ts_3v3", NULL),
104 };
105
106 static struct regulator_consumer_supply tps65090_fet5_supply[] = {
107         REGULATOR_SUPPLY("vdd_lvds", NULL),
108 };
109
110 static struct regulator_consumer_supply tps65090_fet6_supply[] = {
111         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
112 };
113
114 static struct regulator_consumer_supply tps65090_fet7_supply[] = {
115         REGULATOR_SUPPLY("vdd_wifi_3v3", NULL),
116         REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
117         REGULATOR_SUPPLY("vdd_bt_3v3", NULL),
118 };
119
120 #define TPS65090_PDATA_INIT(_id, _name, _supply_reg,                    \
121                 _always_on, _boot_on, _apply_uV, _en_ext_ctrl, _gpio)   \
122 static struct regulator_init_data ri_data_##_name =                     \
123 {                                                                       \
124         .supply_regulator = _supply_reg,                                \
125         .constraints = {                                                \
126                 .name = tps65090_rails(_id),                            \
127                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
128                                      REGULATOR_MODE_STANDBY),           \
129                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
130                                    REGULATOR_CHANGE_STATUS |            \
131                                    REGULATOR_CHANGE_VOLTAGE),           \
132                 .always_on = _always_on,                                \
133                 .boot_on = _boot_on,                                    \
134                 .apply_uV = _apply_uV,                                  \
135         },                                                              \
136         .num_consumer_supplies =                                        \
137                 ARRAY_SIZE(tps65090_##_name##_supply),                  \
138         .consumer_supplies = tps65090_##_name##_supply,                 \
139 };                                                                      \
140 static struct tps65090_regulator_platform_data                          \
141                         tps65090_regulator_pdata_##_name =              \
142 {                                                                       \
143         .id = TPS65090_REGULATOR_##_id,                                 \
144         .enable_ext_control = _en_ext_ctrl,                             \
145         .gpio = _gpio,                                                  \
146         .reg_init_data = &ri_data_##_name ,                             \
147 }
148
149 TPS65090_PDATA_INIT(DCDC1, dcdc1, NULL, 1, 1, 0, false, -1);
150 TPS65090_PDATA_INIT(DCDC2, dcdc2, NULL, 1, 1, 0, false, -1);
151 TPS65090_PDATA_INIT(DCDC3, dcdc3, NULL, 1, 1, 0, false, -1);
152 TPS65090_PDATA_INIT(LDO1, ldo1, NULL, 1, 1, 0, false, -1);
153 TPS65090_PDATA_INIT(LDO2, ldo2, NULL, 1, 1, 0, false, -1);
154 TPS65090_PDATA_INIT(FET1, fet1, NULL, 0, 0, 0, false, -1);
155 TPS65090_PDATA_INIT(FET3, fet3, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
156 TPS65090_PDATA_INIT(FET4, fet4, tps65090_rails(DCDC2), 1, 1, 0, false, -1); /* always_on and boot_on */
157 TPS65090_PDATA_INIT(FET5, fet5, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
158 TPS65090_PDATA_INIT(FET6, fet6, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
159 TPS65090_PDATA_INIT(FET7, fet7, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
160
161 #define ADD_TPS65090_REG(_name) (&tps65090_regulator_pdata_##_name)
162 static struct tps65090_regulator_platform_data *tps65090_reg_pdata[] = {
163         ADD_TPS65090_REG(dcdc1),
164         ADD_TPS65090_REG(dcdc2),
165         ADD_TPS65090_REG(dcdc3),
166         ADD_TPS65090_REG(ldo1),
167         ADD_TPS65090_REG(ldo2),
168         ADD_TPS65090_REG(fet1),
169         ADD_TPS65090_REG(fet3),
170         ADD_TPS65090_REG(fet4),
171         ADD_TPS65090_REG(fet5),
172         ADD_TPS65090_REG(fet6),
173         ADD_TPS65090_REG(fet7),
174 };
175
176 static struct tps65090_platform_data tps65090_pdata = {
177         .irq_base = -1,
178         .num_reg_pdata =  ARRAY_SIZE(tps65090_reg_pdata),
179         .reg_pdata = tps65090_reg_pdata
180 };
181
182 /* MAX77663 consumer rails */
183 static struct regulator_consumer_supply max77663_sd0_supply[] = {
184         REGULATOR_SUPPLY("vdd_core", NULL),
185 };
186
187 static struct regulator_consumer_supply max77663_sd1_supply[] = {
188         REGULATOR_SUPPLY("vddio_ddr", NULL),
189         REGULATOR_SUPPLY("vddio_ddr0", NULL),
190         REGULATOR_SUPPLY("vddio_ddr1", NULL),
191 };
192
193 static struct regulator_consumer_supply max77663_sd2_supply[] = {
194         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
195         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
196         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
197         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
198         REGULATOR_SUPPLY("pwrdet_cam", NULL),
199         REGULATOR_SUPPLY("avdd_osc", NULL),
200         REGULATOR_SUPPLY("vddio_sys", NULL),
201         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
202         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
203         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
204         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
205         REGULATOR_SUPPLY("vdd_emmc", NULL),
206         REGULATOR_SUPPLY("vddio_audio", NULL),
207         REGULATOR_SUPPLY("pwrdet_audio", NULL),
208         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
209         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
210         REGULATOR_SUPPLY("vddio_modem", NULL),
211         REGULATOR_SUPPLY("vddio_modem_1v8", NULL),
212         REGULATOR_SUPPLY("vddio_bb", NULL),
213         REGULATOR_SUPPLY("pwrdet_bb", NULL),
214         REGULATOR_SUPPLY("vddio_bb_1v8", NULL),
215         REGULATOR_SUPPLY("vddio_uart", NULL),
216         REGULATOR_SUPPLY("pwrdet_uart", NULL),
217         REGULATOR_SUPPLY("vddio_gmi", NULL),
218         REGULATOR_SUPPLY("pwrdet_nand", NULL),
219         REGULATOR_SUPPLY("vdd_sensor_1v8", NULL),
220         REGULATOR_SUPPLY("vdd_mic_1v8", NULL),
221         REGULATOR_SUPPLY("vdd_nfc_1v8", NULL),
222         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
223         REGULATOR_SUPPLY("vdd_ts_1v8", NULL),
224         REGULATOR_SUPPLY("vdd_spi_1v8", NULL),
225         REGULATOR_SUPPLY("dvdd_lcd", NULL),
226         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
227         REGULATOR_SUPPLY("vddio_wifi_1v8", NULL),
228         REGULATOR_SUPPLY("vdd_gps_1v8", NULL),
229         REGULATOR_SUPPLY("vddio_bt_1v8", NULL),
230         REGULATOR_SUPPLY("vdd_dtv_1v8", NULL),
231 };
232
233 static struct regulator_consumer_supply max77663_sd3_supply[] = {
234         REGULATOR_SUPPLY("vcore_emmc", NULL),
235 };
236
237 static struct regulator_consumer_supply max77663_ldo0_supply[] = {
238         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
239         REGULATOR_SUPPLY("avdd_pllx", NULL),
240         REGULATOR_SUPPLY("avdd_plle", NULL),
241         REGULATOR_SUPPLY("avdd_pllm", NULL),
242         REGULATOR_SUPPLY("avdd_pllu", NULL),
243         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
244         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
245         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
246 };
247
248 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
249         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
250 };
251
252 static struct regulator_consumer_supply max77663_ldo2_supply[] = {
253         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
254         REGULATOR_SUPPLY("vdd_als", NULL),
255         REGULATOR_SUPPLY("vdd", "0-004c"),
256 };
257
258 static struct regulator_consumer_supply max77663_ldo3_supply[] = {
259         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
260         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
261         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
262 };
263
264 static struct regulator_consumer_supply max77663_ldo4_supply[] = {
265         REGULATOR_SUPPLY("vdd_rtc", NULL),
266 };
267
268 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
269         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
270         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
271         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
272         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
273         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
274         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
275         REGULATOR_SUPPLY("vddio_bb_hsic", NULL),
276 };
277
278 static struct regulator_consumer_supply max77663_ldo6_supply[] = {
279         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
280         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
281 };
282
283 /* FIXME!! Put the device address of camera */
284 static struct regulator_consumer_supply max77663_ldo7_supply[] = {
285         REGULATOR_SUPPLY("avdd_cam1", NULL),
286         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
287         REGULATOR_SUPPLY("vana", "2-0036"),
288 };
289
290 /* FIXME!! Put the device address of camera */
291 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
292         REGULATOR_SUPPLY("avdd_cam2", NULL),
293         REGULATOR_SUPPLY("avdd", "2-0010"),
294 };
295
296 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
297         {
298                 .src = FPS_SRC_0,
299                 .en_src = FPS_EN_SRC_EN0,
300                 .time_period = FPS_TIME_PERIOD_DEF,
301         },
302         {
303                 .src = FPS_SRC_1,
304                 .en_src = FPS_EN_SRC_EN1,
305                 .time_period = FPS_TIME_PERIOD_DEF,
306         },
307         {
308                 .src = FPS_SRC_2,
309                 .en_src = FPS_EN_SRC_EN0,
310                 .time_period = FPS_TIME_PERIOD_DEF,
311         },
312 };
313
314 #define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg,   \
315                 _always_on, _boot_on, _apply_uV,                        \
316                 _fps_src, _fps_pu_period, _fps_pd_period, _flags)       \
317         static struct regulator_init_data max77663_regulator_idata_##_id = {   \
318                 .supply_regulator = _supply_reg,                        \
319                 .constraints = {                                        \
320                         .name = max77663_rails(_id),                    \
321                         .min_uV = _min_uV,                              \
322                         .max_uV = _max_uV,                              \
323                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
324                                              REGULATOR_MODE_STANDBY),   \
325                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
326                                            REGULATOR_CHANGE_STATUS |    \
327                                            REGULATOR_CHANGE_VOLTAGE),   \
328                         .always_on = _always_on,                        \
329                         .boot_on = _boot_on,                            \
330                         .apply_uV = _apply_uV,                          \
331                 },                                                      \
332                 .num_consumer_supplies =                                \
333                         ARRAY_SIZE(max77663_##_id##_supply),            \
334                 .consumer_supplies = max77663_##_id##_supply,           \
335         };                                                              \
336 static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id =\
337 {                                                                       \
338                 .reg_init_data = &max77663_regulator_idata_##_id,       \
339                 .id = MAX77663_REGULATOR_ID_##_rid,                     \
340                 .fps_src = _fps_src,                                    \
341                 .fps_pu_period = _fps_pu_period,                        \
342                 .fps_pd_period = _fps_pd_period,                        \
343                 .fps_cfgs = max77663_fps_cfgs,                          \
344                 .flags = _flags,                                        \
345         }
346
347 MAX77663_PDATA_INIT(SD0, sd0,  900000, 1400000, tps65090_rails(DCDC3), 1, 1, 0,
348                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
349
350 MAX77663_PDATA_INIT(SD1, sd1,  1200000, 1200000, tps65090_rails(DCDC3), 1, 1, 1,
351                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
352
353 MAX77663_PDATA_INIT(SD2, sd2,  1800000, 1800000, tps65090_rails(DCDC3), 1, 1, 1,
354                     FPS_SRC_0, -1, -1, 0);
355
356 MAX77663_PDATA_INIT(SD3, sd3,  2850000, 2850000, tps65090_rails(DCDC3), 1, 1, 1,
357                     FPS_SRC_NONE, -1, -1, 0);
358
359 MAX77663_PDATA_INIT(LDO0, ldo0, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
360                     FPS_SRC_1, -1, -1, 0);
361
362 MAX77663_PDATA_INIT(LDO1, ldo1, 1050000, 1050000, max77663_rails(sd2), 0, 0, 1,
363                     FPS_SRC_NONE, -1, -1, 0);
364
365 MAX77663_PDATA_INIT(LDO2, ldo2, 2850000, 2850000, tps65090_rails(DCDC2), 1, 1,
366                     1, FPS_SRC_1, -1, -1, 0);
367
368 MAX77663_PDATA_INIT(LDO3, ldo3, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
369                     FPS_SRC_NONE, -1, -1, 0);
370
371 MAX77663_PDATA_INIT(LDO4, ldo4, 1100000, 1100000, tps65090_rails(DCDC2), 1, 1,
372                     1, FPS_SRC_NONE, -1, -1, 0);
373
374 MAX77663_PDATA_INIT(LDO5, ldo5, 1200000, 1200000, max77663_rails(sd2), 0, 1, 1,
375                     FPS_SRC_NONE, -1, -1, 0);
376
377 MAX77663_PDATA_INIT(LDO6, ldo6, 1800000, 3300000, tps65090_rails(DCDC2), 0, 0, 0,
378                     FPS_SRC_NONE, -1, -1, 0);
379
380 MAX77663_PDATA_INIT(LDO7, ldo7, 2800000, 2800000, tps65090_rails(DCDC2), 0, 0, 1,
381                     FPS_SRC_NONE, -1, -1, 0);
382
383 MAX77663_PDATA_INIT(LDO8, ldo8, 2800000, 2800000, tps65090_rails(DCDC2), 0, 1, 1,
384                     FPS_SRC_1, -1, -1, 0);
385
386 #define MAX77663_REG(_id, _data) (&max77663_regulator_pdata_##_data)
387
388 static struct max77663_regulator_platform_data *max77663_reg_pdata[] = {
389         MAX77663_REG(SD0, sd0),
390         MAX77663_REG(SD1, sd1),
391         MAX77663_REG(SD2, sd2),
392         MAX77663_REG(SD3, sd3),
393         MAX77663_REG(LDO0, ldo0),
394         MAX77663_REG(LDO1, ldo1),
395         MAX77663_REG(LDO2, ldo2),
396         MAX77663_REG(LDO3, ldo3),
397         MAX77663_REG(LDO4, ldo4),
398         MAX77663_REG(LDO5, ldo5),
399         MAX77663_REG(LDO6, ldo6),
400         MAX77663_REG(LDO7, ldo7),
401         MAX77663_REG(LDO8, ldo8),
402 };
403
404 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
405         {
406                 .gpio = MAX77663_GPIO0,
407                 .dir = GPIO_DIR_OUT,
408                 .dout = GPIO_DOUT_LOW,
409                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
410                 .alternate = GPIO_ALT_DISABLE,
411         },
412         {
413                 .gpio = MAX77663_GPIO1,
414                 .dir = GPIO_DIR_IN,
415                 .dout = GPIO_DOUT_HIGH,
416                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
417                 .pull_up = GPIO_PU_ENABLE,
418                 .alternate = GPIO_ALT_DISABLE,
419         },
420         {
421                 .gpio = MAX77663_GPIO2,
422                 .dir = GPIO_DIR_OUT,
423                 .dout = GPIO_DOUT_HIGH,
424                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
425                 .pull_up = GPIO_PU_ENABLE,
426                 .alternate = GPIO_ALT_DISABLE,
427         },
428         {
429                 .gpio = MAX77663_GPIO3,
430                 .dir = GPIO_DIR_OUT,
431                 .dout = GPIO_DOUT_HIGH,
432                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
433                 .pull_up = GPIO_PU_ENABLE,
434                 .alternate = GPIO_ALT_DISABLE,
435         },
436         {
437                 .gpio = MAX77663_GPIO4,
438                 .dir = GPIO_DIR_OUT,
439                 .dout = GPIO_DOUT_HIGH,
440                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
441                 .alternate = GPIO_ALT_ENABLE,
442         },
443         {
444                 .gpio = MAX77663_GPIO5,
445                 .dir = GPIO_DIR_OUT,
446                 .dout = GPIO_DOUT_LOW,
447                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
448                 .alternate = GPIO_ALT_DISABLE,
449         },
450         {
451                 .gpio = MAX77663_GPIO6,
452                 .dir = GPIO_DIR_OUT,
453                 .dout = GPIO_DOUT_LOW,
454                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
455                 .alternate = GPIO_ALT_DISABLE,
456         },
457         {
458                 .gpio = MAX77663_GPIO7,
459                 .dir = GPIO_DIR_OUT,
460                 .dout = GPIO_DOUT_LOW,
461                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
462                 .alternate = GPIO_ALT_DISABLE,
463         },
464 };
465
466 static struct max77663_platform_data max77663_pdata = {
467         .irq_base       = MAX77663_IRQ_BASE,
468         .gpio_base      = MAX77663_GPIO_BASE,
469
470         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
471         .gpio_cfgs      = max77663_gpio_cfgs,
472
473         .regulator_pdata = max77663_reg_pdata,
474         .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata),
475
476         .rtc_i2c_addr   = 0x68,
477
478         .use_power_off  = false,
479 };
480
481 static struct i2c_board_info __initdata max77663_regulators[] = {
482         {
483                 /* The I2C address was determined by OTP factory setting */
484                 I2C_BOARD_INFO("max77663", 0x3c),
485                 .irq            = INT_EXTERNAL_PMU,
486                 .platform_data  = &max77663_pdata,
487         },
488 };
489
490 static struct i2c_board_info __initdata tps65090_regulators[] = {
491         {
492                 I2C_BOARD_INFO("tps65090", 0x48),
493                 .platform_data  = &tps65090_pdata,
494         },
495 };
496
497 /* TPS51632 DC-DC converter */
498 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
499         REGULATOR_SUPPLY("vdd_cpu", NULL),
500 };
501
502 static struct regulator_init_data tps51632_init_data = {
503         .constraints = {                                                \
504                 .min_uV = 500000,                                       \
505                 .max_uV = 1520000,                                      \
506                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
507                                         REGULATOR_MODE_STANDBY),        \
508                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
509                                         REGULATOR_CHANGE_STATUS |       \
510                                         REGULATOR_CHANGE_VOLTAGE),      \
511                 .always_on = 1,                                         \
512                 .boot_on =  1,                                          \
513                 .apply_uV = 0,                                          \
514         },                                                              \
515         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
516                 .consumer_supplies = tps51632_dcdc_supply,              \
517 };
518
519 static struct tps51632_regulator_platform_data tps51632_pdata = {
520         .reg_init_data = &tps51632_init_data,           \
521         .enable_pwm = false,                            \
522         .max_voltage_uV = 1520000,                      \
523         .base_voltage_uV = 500000,                      \
524         .slew_rate_uv_per_us = 6000,                    \
525 };
526
527 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
528         {
529                 I2C_BOARD_INFO("tps51632", 0x43),
530                 .platform_data  = &tps51632_pdata,
531         },
532 };
533
534 /************************ Palmas based regulator ****************/
535 static struct regulator_consumer_supply palmas_smps12_supply[] = {
536         REGULATOR_SUPPLY("vddio_ddr3l", NULL),
537         REGULATOR_SUPPLY("vcore_ddr3l", NULL),
538         REGULATOR_SUPPLY("vref2_ddr3l", NULL),
539 };
540
541 #define palmas_smps3_supply max77663_sd2_supply
542 #define palmas_smps45_supply max77663_sd0_supply
543
544 static struct regulator_consumer_supply palmas_smps8_supply[] = {
545         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
546         REGULATOR_SUPPLY("avdd_pllm", NULL),
547         REGULATOR_SUPPLY("avdd_pllu", NULL),
548         REGULATOR_SUPPLY("avdd_pllx", NULL),
549         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
550         REGULATOR_SUPPLY("avdd_plle", NULL),
551         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
552         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
553         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
554         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
555         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
556         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
557
558 };
559
560 static struct regulator_consumer_supply palmas_smps9_supply[] = {
561         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
562 };
563
564 #define palmas_ldo1_supply max77663_ldo7_supply
565 #define palmas_ldo2_supply max77663_ldo8_supply
566 #define palmas_ldo3_supply max77663_ldo5_supply
567
568 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
569         REGULATOR_SUPPLY("vpp_fuse", NULL),
570 };
571
572 #define palmas_ldo6_supply max77663_ldo2_supply
573
574 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
575         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
576         REGULATOR_SUPPLY("vdd", "2-000e"),
577 };
578
579 #define palmas_ldo8_supply max77663_ldo4_supply
580 #define palmas_ldo9_supply max77663_ldo6_supply
581
582 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
583         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
584 };
585
586 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
587         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
588         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
589         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
590         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
591         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
592 };
593
594 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
595         _boot_on, _apply_uv)                                            \
596         static struct regulator_init_data reg_idata_##_name = {         \
597                 .constraints = {                                        \
598                         .name = palmas_rails(_name),                    \
599                         .min_uV = (_minmv)*1000,                        \
600                         .max_uV = (_maxmv)*1000,                        \
601                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
602                                         REGULATOR_MODE_STANDBY),        \
603                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
604                                         REGULATOR_CHANGE_STATUS |       \
605                                         REGULATOR_CHANGE_VOLTAGE),      \
606                         .always_on = _always_on,                        \
607                         .boot_on = _boot_on,                            \
608                         .apply_uV = _apply_uv,                          \
609                 },                                                      \
610                 .num_consumer_supplies =                                \
611                         ARRAY_SIZE(palmas_##_name##_supply),            \
612                 .consumer_supplies = palmas_##_name##_supply,           \
613                 .supply_regulator = _supply_reg,                        \
614         }
615
616 PALMAS_PDATA_INIT(smps12, 1350,  1350, tps65090_rails(DCDC3), 0, 0, 0);
617 PALMAS_PDATA_INIT(smps3, 1800,  1800, tps65090_rails(DCDC3), 0, 0, 0);
618 PALMAS_PDATA_INIT(smps45, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0);
619 PALMAS_PDATA_INIT(smps8, 1050,  1050, tps65090_rails(DCDC2), 0, 1, 1);
620 PALMAS_PDATA_INIT(smps9, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 0);
621 PALMAS_PDATA_INIT(ldo1, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
622 PALMAS_PDATA_INIT(ldo2, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
623 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps3), 0, 0, 1);
624 PALMAS_PDATA_INIT(ldo4, 1800,  1800, tps65090_rails(DCDC2), 0, 0, 0);
625 PALMAS_PDATA_INIT(ldo6, 2850,  2850, tps65090_rails(DCDC2), 0, 0, 1);
626 PALMAS_PDATA_INIT(ldo7, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
627 PALMAS_PDATA_INIT(ldo8, 900,  900, tps65090_rails(DCDC3), 1, 1, 1);
628 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
629 PALMAS_PDATA_INIT(ldoln, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1);
630 PALMAS_PDATA_INIT(ldousb, 3300,  3300, tps65090_rails(DCDC1), 0, 0, 1);
631
632 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
633
634 static struct regulator_init_data *dalmore_e1611_reg_data[PALMAS_NUM_REGS] = {
635         PALMAS_REG_PDATA(smps12),
636         NULL,
637         PALMAS_REG_PDATA(smps3),
638         PALMAS_REG_PDATA(smps45),
639         NULL,
640         NULL,
641         NULL,
642         PALMAS_REG_PDATA(smps8),
643         PALMAS_REG_PDATA(smps9),
644         NULL,
645         PALMAS_REG_PDATA(ldo1),
646         PALMAS_REG_PDATA(ldo2),
647         PALMAS_REG_PDATA(ldo3),
648         PALMAS_REG_PDATA(ldo4),
649         NULL,
650         PALMAS_REG_PDATA(ldo6),
651         PALMAS_REG_PDATA(ldo7),
652         PALMAS_REG_PDATA(ldo8),
653         PALMAS_REG_PDATA(ldo9),
654         PALMAS_REG_PDATA(ldoln),
655         PALMAS_REG_PDATA(ldousb),
656         NULL,
657         NULL,
658         NULL,
659         NULL,
660         NULL,
661 };
662
663 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
664                 _tstep, _vsel)                                          \
665         static struct palmas_reg_init reg_init_data_##_name = {         \
666                 .warm_reset = _warm_reset,                              \
667                 .roof_floor =   _roof_floor,                            \
668                 .mode_sleep = _mode_sleep,                              \
669                 .tstep = _tstep,                                        \
670                 .vsel = _vsel,                                          \
671         }
672
673 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
674 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
675 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
676 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
677 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
678 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
679 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
680 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
681 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
682 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
683 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
684 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
685 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
686 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
687 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
688 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
689 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
690 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
691 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
692 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
693 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
694 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
695 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
696 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
697 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
698 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
699
700 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
701 static struct palmas_reg_init *dalmore_e1611_reg_init[PALMAS_NUM_REGS] = {
702         PALMAS_REG_INIT_DATA(smps12),
703         PALMAS_REG_INIT_DATA(smps123),
704         PALMAS_REG_INIT_DATA(smps3),
705         PALMAS_REG_INIT_DATA(smps45),
706         PALMAS_REG_INIT_DATA(smps457),
707         PALMAS_REG_INIT_DATA(smps6),
708         PALMAS_REG_INIT_DATA(smps7),
709         PALMAS_REG_INIT_DATA(smps8),
710         PALMAS_REG_INIT_DATA(smps9),
711         PALMAS_REG_INIT_DATA(smps10),
712         PALMAS_REG_INIT_DATA(ldo1),
713         PALMAS_REG_INIT_DATA(ldo2),
714         PALMAS_REG_INIT_DATA(ldo3),
715         PALMAS_REG_INIT_DATA(ldo4),
716         PALMAS_REG_INIT_DATA(ldo5),
717         PALMAS_REG_INIT_DATA(ldo6),
718         PALMAS_REG_INIT_DATA(ldo7),
719         PALMAS_REG_INIT_DATA(ldo8),
720         PALMAS_REG_INIT_DATA(ldo9),
721         PALMAS_REG_INIT_DATA(ldoln),
722         PALMAS_REG_INIT_DATA(ldousb),
723         PALMAS_REG_INIT_DATA(regen1),
724         PALMAS_REG_INIT_DATA(regen2),
725         PALMAS_REG_INIT_DATA(regen3),
726         PALMAS_REG_INIT_DATA(sysen1),
727         PALMAS_REG_INIT_DATA(sysen2),
728 };
729
730 static struct palmas_pmic_platform_data pmic_platform = {
731         .enable_ldo8_tracking = true,
732         .disabe_ldo8_tracking_suspend = true,
733 };
734
735 static struct palmas_platform_data palmas_pdata = {
736         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
737         .irq_base = PALMAS_TEGRA_IRQ_BASE,
738         .pmic_pdata = &pmic_platform,
739         .mux_from_pdata = true,
740         .pad1 = 0,
741         .pad2 = 0,
742         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
743 };
744
745 static struct i2c_board_info palma_device[] = {
746         {
747                 I2C_BOARD_INFO("tps65913", 0x58),
748                 .irq            = INT_EXTERNAL_PMU,
749                 .platform_data  = &palmas_pdata,
750         },
751 };
752
753 /* EN_AVDD_USB_HDMI From PMU GP1 */
754 static struct regulator_consumer_supply fixed_reg_avdd_usb_hdmi_supply[] = {
755         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
756         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
757         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
758         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
759         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
760         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
761 };
762
763 /* EN_CAM_1v8 From PMU GP5 */
764 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
765         REGULATOR_SUPPLY("dvdd_cam", NULL),
766         REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
767         REGULATOR_SUPPLY("vi2c", "2-0030"),
768         REGULATOR_SUPPLY("vif", "2-0036"),
769         REGULATOR_SUPPLY("dovdd", "2-0010"),
770         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
771 };
772
773 /* EN_CAM_1v8 on e1611 From PMU GP6 */
774 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_e1611_supply[] = {
775         REGULATOR_SUPPLY("dvdd_cam", NULL),
776         REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
777         REGULATOR_SUPPLY("vi2c", "2-0030"),
778         REGULATOR_SUPPLY("vif", "2-0036"),
779         REGULATOR_SUPPLY("dovdd", "2-0010"),
780         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
781 };
782
783 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
784         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
785 };
786
787 /* EN_USB1_VBUS From TEGRA GPIO PN4 PR3(T30) */
788 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
789         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
790 };
791
792 /* EN_3V3_FUSE From TEGRA GPIO PX4 */
793 static struct regulator_consumer_supply fixed_reg_vpp_fuse_supply[] = {
794         REGULATOR_SUPPLY("vpp_fuse", NULL),
795 };
796
797 /* EN_USB3_VBUS From TEGRA GPIO PM5 */
798 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
799         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
800 };
801
802 /* Macro for defining fixed regulator sub device data */
803 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
804 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
805         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
806         static struct regulator_init_data ri_data_##_var =              \
807         {                                                               \
808                 .supply_regulator = _in_supply,                         \
809                 .num_consumer_supplies =                                \
810                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
811                 .consumer_supplies = fixed_reg_##_name##_supply,        \
812                 .constraints = {                                        \
813                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
814                                         REGULATOR_MODE_STANDBY),        \
815                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
816                                         REGULATOR_CHANGE_STATUS |       \
817                                         REGULATOR_CHANGE_VOLTAGE),      \
818                         .always_on = _always_on,                        \
819                         .boot_on = _boot_on,                            \
820                 },                                                      \
821         };                                                              \
822         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
823         {                                                               \
824                 .supply_name = FIXED_SUPPLY(_name),                     \
825                 .microvolts = _millivolts * 1000,                       \
826                 .gpio = _gpio_nr,                                       \
827                 .gpio_is_open_drain = _open_drain,                      \
828                 .enable_high = _active_high,                            \
829                 .enabled_at_boot = _boot_state,                         \
830                 .init_data = &ri_data_##_var,                           \
831         };                                                              \
832         static struct platform_device fixed_reg_##_var##_dev = {        \
833                 .name = "reg-fixed-voltage",                            \
834                 .id = _id,                                              \
835                 .dev = {                                                \
836                         .platform_data = &fixed_reg_##_var##_pdata,     \
837                 },                                                      \
838         }
839
840 FIXED_REG(1,    avdd_usb_hdmi,  avdd_usb_hdmi,
841         tps65090_rails(DCDC2),  0,      0,
842         MAX77663_GPIO_BASE + MAX77663_GPIO1,    true,   true,   1,      3300);
843
844 FIXED_REG(2,    en_1v8_cam,     en_1v8_cam,
845         max77663_rails(sd2),    0,      0,
846         MAX77663_GPIO_BASE + MAX77663_GPIO5,    false,  true,   0,      1800);
847
848 FIXED_REG(3,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
849         tps65090_rails(DCDC1),  0,      0,
850         TEGRA_GPIO_PK1, false,  true,   0,      5000);
851
852 FIXED_REG(4,    vpp_fuse,       vpp_fuse,
853         max77663_rails(sd2),    0,      0,
854         TEGRA_GPIO_PX4, false,  true,   0,      3300);
855
856 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
857 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
858         tps65090_rails(DCDC1),  0,      0,
859         TEGRA_GPIO_PN4, true,   true,   0,      5000);
860 #else
861 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
862         tps65090_rails(DCDC1),  0,      0,
863         TEGRA_GPIO_PR3, true,   true,   0,      5000);
864 #endif
865
866 FIXED_REG(6,    usb3_vbus,      usb3_vbus,
867         tps65090_rails(DCDC1),  0,      0,
868         TEGRA_GPIO_PK6, true,   true,   0,      5000);
869
870 FIXED_REG(7,    en_1v8_cam_e1611,       en_1v8_cam_e1611,
871         palmas_rails(smps3),    0,      0,
872         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
873
874 /*
875  * Creating the fixed regulator device tables
876  */
877
878 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
879
880 #define DALMORE_COMMON_FIXED_REG                \
881         ADD_FIXED_REG(usb1_vbus),               \
882         ADD_FIXED_REG(usb3_vbus),               \
883         ADD_FIXED_REG(vdd_hdmi_5v0),
884
885 #define E1612_FIXED_REG                         \
886         ADD_FIXED_REG(avdd_usb_hdmi),           \
887         ADD_FIXED_REG(en_1v8_cam),              \
888         ADD_FIXED_REG(vpp_fuse),                \
889
890 #define E1611_FIXED_REG                         \
891         ADD_FIXED_REG(en_1v8_cam_e1611),
892
893 /* Gpio switch regulator platform data for Dalmore E1611 */
894 static struct platform_device *fixed_reg_devs_e1611_a00[] = {
895         DALMORE_COMMON_FIXED_REG
896         E1611_FIXED_REG
897 };
898
899 /* Gpio switch regulator platform data for Dalmore E1612 */
900 static struct platform_device *fixed_reg_devs_e1612_a00[] = {
901         DALMORE_COMMON_FIXED_REG
902         E1612_FIXED_REG
903 };
904
905 int __init dalmore_palmas_regulator_init(void)
906 {
907         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
908         u32 pmc_ctrl;
909         int i;
910 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
911         int ret;
912
913         ret = gpio_request(TEGRA_GPIO_PCC3, "pmic_nreswarm");
914         if (ret < 0)
915                 pr_err("%s: gpio_request failed for gpio %d\n",
916                                 __func__, TEGRA_GPIO_PCC3);
917         else
918                 gpio_direction_output(TEGRA_GPIO_PCC3, 1);
919 #endif
920         /* TPS65913: Normal state of INT request line is LOW.
921          * configure the power management controller to trigger PMU
922          * interrupts when HIGH.
923          */
924         pmc_ctrl = readl(pmc + PMC_CTRL);
925         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
926         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
927                 pmic_platform.reg_data[i] = dalmore_e1611_reg_data[i];
928                 pmic_platform.reg_init[i] = dalmore_e1611_reg_init[i];
929         }
930
931         i2c_register_board_info(4, palma_device,
932                         ARRAY_SIZE(palma_device));
933         return 0;
934 }
935
936 static int ac_online(void)
937 {
938         return 1;
939 }
940
941 static struct resource dalmore_pda_resources[] = {
942         [0] = {
943                 .name   = "ac",
944         },
945 };
946
947 static struct pda_power_pdata dalmore_pda_data = {
948         .is_ac_online   = ac_online,
949 };
950
951 static struct platform_device dalmore_pda_power_device = {
952         .name           = "pda-power",
953         .id             = -1,
954         .resource       = dalmore_pda_resources,
955         .num_resources  = ARRAY_SIZE(dalmore_pda_resources),
956         .dev    = {
957                 .platform_data  = &dalmore_pda_data,
958         },
959 };
960
961 static struct tegra_suspend_platform_data dalmore_suspend_data = {
962         .cpu_timer      = 300,
963         .cpu_off_timer  = 300,
964         .suspend_mode   = TEGRA_SUSPEND_LP0,
965         .core_timer     = 0x157e,
966         .core_off_timer = 2000,
967         .corereq_high   = true,
968         .sysclkreq_high = true,
969         .min_residency_noncpu = 600,
970         .min_residency_crail = 1000,
971 };
972 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
973 /* board parameters for cpu dfll */
974 static struct tegra_cl_dvfs_cfg_param dalmore_cl_dvfs_param = {
975         .sample_rate = 12500,
976
977         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
978         .cf = 10,
979         .ci = 0,
980         .cg = 2,
981
982         .droop_cut_value = 0xF,
983         .droop_restore_ramp = 0x0,
984         .scale_out_ramp = 0x0,
985 };
986 #endif
987
988 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
989 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
990 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
991 static inline void fill_reg_map(void)
992 {
993         int i;
994         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
995                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
996                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
997         }
998 }
999
1000 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1001 static struct tegra_cl_dvfs_platform_data dalmore_cl_dvfs_data = {
1002         .dfll_clk_name = "dfll_cpu",
1003         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
1004         .u.pmu_i2c = {
1005                 .fs_rate = 400000,
1006                 .slave_addr = 0x86,
1007                 .reg = 0x00,
1008         },
1009         .vdd_map = pmu_cpu_vdd_map,
1010         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
1011
1012         .cfg_param = &dalmore_cl_dvfs_param,
1013 };
1014
1015 static int __init dalmore_cl_dvfs_init(void)
1016 {
1017         fill_reg_map();
1018         tegra_cl_dvfs_device.dev.platform_data = &dalmore_cl_dvfs_data;
1019         platform_device_register(&tegra_cl_dvfs_device);
1020
1021         return 0;
1022 }
1023 #endif
1024
1025 static int __init dalmore_max77663_regulator_init(void)
1026 {
1027         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
1028         u32 pmc_ctrl;
1029
1030         /* configure the power management controller to trigger PMU
1031          * interrupts when low */
1032         pmc_ctrl = readl(pmc + PMC_CTRL);
1033         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
1034
1035         i2c_register_board_info(4, max77663_regulators,
1036                                 ARRAY_SIZE(max77663_regulators));
1037
1038         return 0;
1039 }
1040
1041 static struct regulator_bulk_data dalmore_gps_regulator_supply[] = {
1042         [0] = {
1043                 .supply = "vdd_gps_3v3",
1044         },
1045         [1] = {
1046                 .supply = "vdd_gps_1v8",
1047         },
1048 };
1049
1050 static struct regulator_userspace_consumer_data dalmore_gps_regulator_pdata = {
1051         .num_supplies   = ARRAY_SIZE(dalmore_gps_regulator_supply),
1052         .supplies       = dalmore_gps_regulator_supply,
1053 };
1054
1055 static struct platform_device dalmore_gps_regulator_device = {
1056         .name   = "reg-userspace-consumer",
1057         .id     = 2,
1058         .dev    = {
1059                         .platform_data = &dalmore_gps_regulator_pdata,
1060         },
1061 };
1062
1063 static struct regulator_bulk_data dalmore_bt_regulator_supply[] = {
1064         [0] = {
1065                 .supply = "vdd_bt_3v3",
1066         },
1067         [1] = {
1068                 .supply = "vddio_bt_1v8",
1069         },
1070 };
1071
1072 static struct regulator_userspace_consumer_data dalmore_bt_regulator_pdata = {
1073         .num_supplies   = ARRAY_SIZE(dalmore_bt_regulator_supply),
1074         .supplies       = dalmore_bt_regulator_supply,
1075 };
1076
1077 static struct platform_device dalmore_bt_regulator_device = {
1078         .name   = "reg-userspace-consumer",
1079         .id     = 1,
1080         .dev    = {
1081                         .platform_data = &dalmore_bt_regulator_pdata,
1082         },
1083 };
1084
1085 static int __init dalmore_fixed_regulator_init(void)
1086 {
1087         struct board_info board_info;
1088
1089         if (!machine_is_dalmore())
1090                 return 0;
1091
1092         tegra_get_board_info(&board_info);
1093
1094         if (board_info.board_id == BOARD_E1611 ||
1095                 board_info.board_id == BOARD_P2454)
1096                 return platform_add_devices(fixed_reg_devs_e1611_a00,
1097                                 ARRAY_SIZE(fixed_reg_devs_e1611_a00));
1098         else
1099                 return platform_add_devices(fixed_reg_devs_e1612_a00,
1100                                 ARRAY_SIZE(fixed_reg_devs_e1612_a00));
1101 }
1102 subsys_initcall_sync(dalmore_fixed_regulator_init);
1103
1104 int __init dalmore_regulator_init(void)
1105 {
1106         struct board_info board_info;
1107         i2c_register_board_info(4, tps65090_regulators,
1108                         ARRAY_SIZE(tps65090_regulators));
1109 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1110         dalmore_cl_dvfs_init();
1111 #endif
1112         tegra_get_board_info(&board_info);
1113         if (board_info.board_id == BOARD_E1611 ||
1114                 board_info.board_id == BOARD_P2454)
1115                 dalmore_palmas_regulator_init();
1116         else
1117                 dalmore_max77663_regulator_init();
1118
1119         i2c_register_board_info(4, tps51632_boardinfo, 1);
1120         platform_device_register(&dalmore_pda_power_device);
1121         platform_device_register(&dalmore_bt_regulator_device);
1122         platform_device_register(&dalmore_gps_regulator_device);
1123         return 0;
1124 }
1125
1126 int __init dalmore_suspend_init(void)
1127 {
1128         tegra_init_suspend(&dalmore_suspend_data);
1129         return 0;
1130 }
1131
1132 int __init dalmore_edp_init(void)
1133 {
1134 #ifdef CONFIG_TEGRA_EDP_LIMITS
1135         unsigned int regulator_mA;
1136
1137         regulator_mA = get_maximum_cpu_current_supported();
1138         if (!regulator_mA)
1139                 regulator_mA = 15000;
1140
1141         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1142
1143         tegra_init_cpu_edp_limits(regulator_mA);
1144 #endif
1145         return 0;
1146 }
1147
1148 static struct soctherm_platform_data dalmore_soctherm_data = {
1149         .soctherm_clk_rate = 136000000,
1150         .tsensor_clk_rate = 500000,
1151         .sensor_data = {
1152                 [TSENSE_CPU0] = {
1153                         .enable = true,
1154                         .therm_a = 570,
1155                         .therm_b = -744,
1156                         .tall = 16300,
1157                         .tiddq = 1,
1158                         .ten_count = 1,
1159                         .tsample = 163,
1160                         .pdiv = 10,
1161                 },
1162                 [TSENSE_CPU1] = {
1163                         .enable = true,
1164                         .therm_a = 570,
1165                         .therm_b = -744,
1166                         .tall = 16300,
1167                         .tiddq = 1,
1168                         .ten_count = 1,
1169                         .tsample = 163,
1170                         .pdiv = 10,
1171                 },
1172                 [TSENSE_CPU2] = {
1173                         .enable = true,
1174                         .therm_a = 570,
1175                         .therm_b = -744,
1176                         .tall = 16300,
1177                         .tiddq = 1,
1178                         .ten_count = 1,
1179                         .tsample = 163,
1180                         .pdiv = 10,
1181                 },
1182                 [TSENSE_CPU3] = {
1183                         .enable = true,
1184                         .therm_a = 570,
1185                         .therm_b = -744,
1186                         .tall = 16300,
1187                         .tiddq = 1,
1188                         .ten_count = 1,
1189                         .tsample = 163,
1190                         .pdiv = 10,
1191                 },
1192                 [TSENSE_MEM0] = {
1193                         .enable = true,
1194                         .therm_a = 570,
1195                         .therm_b = -744,
1196                         .tall = 16300,
1197                         .tiddq = 1,
1198                         .ten_count = 1,
1199                         .tsample = 163,
1200                         .pdiv = 10,
1201                 },
1202                 [TSENSE_MEM1] = {
1203                         .enable = true,
1204                         .therm_a = 570,
1205                         .therm_b = -744,
1206                         .tall = 16300,
1207                         .tiddq = 1,
1208                         .ten_count = 1,
1209                         .tsample = 163,
1210                         .pdiv = 10,
1211                 },
1212                 [TSENSE_GPU] = {
1213                         .enable = true,
1214                         .therm_a = 570,
1215                         .therm_b = -744,
1216                         .tall = 16300,
1217                         .tiddq = 1,
1218                         .ten_count = 1,
1219                         .tsample = 163,
1220                         .pdiv = 10,
1221                 },
1222                 [TSENSE_PLLX] = {
1223                         .enable = true,
1224                         .therm_a = 570,
1225                         .therm_b = -744,
1226                         .tall = 16300,
1227                         .tiddq = 1,
1228                         .ten_count = 1,
1229                         .tsample = 163,
1230                         .pdiv = 10,
1231                 },
1232         },
1233 };
1234
1235 static struct balanced_throttle tj_throttle = {
1236         .throt_tab_size = 10,
1237         .throt_tab = {
1238                 {      0, 1000 },
1239                 { 640000, 1000 },
1240                 { 640000, 1000 },
1241                 { 640000, 1000 },
1242                 { 640000, 1000 },
1243                 { 640000, 1000 },
1244                 { 760000, 1000 },
1245                 { 760000, 1050 },
1246                 {1000000, 1050 },
1247                 {1000000, 1100 },
1248         },
1249 };
1250
1251 static int __init dalmore_soctherm_init(void)
1252 {
1253         dalmore_soctherm_data.therm[THERM_CPU].cdev =
1254                         balanced_throttle_register(&tj_throttle);
1255
1256         return tegra11_soctherm_init(&dalmore_soctherm_data);
1257 }
1258 module_init(dalmore_soctherm_init);