ARM: tegra: Dalmore: define 1v8 touch regulator
[linux-3.10.git] / arch / arm / mach-tegra / board-dalmore-power.c
1 /*
2  * arch/arm/mach-tegra/board-dalmore-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/max77663-core.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/mfd/tps65090.h>
31 #include <linux/regulator/max77663-regulator.h>
32 #include <linux/regulator/tps65090-regulator.h>
33 #include <linux/regulator/tps51632-regulator.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/userspace-consumer.h>
36
37 #include <asm/mach-types.h>
38
39 #include <mach/iomap.h>
40 #include <mach/irqs.h>
41 #include <mach/edp.h>
42 #include <mach/gpio-tegra.h>
43
44 #include "cpu-tegra.h"
45 #include "pm.h"
46 #include "tegra-board-id.h"
47 #include "board.h"
48 #include "gpio-names.h"
49 #include "board-dalmore.h"
50 #include "tegra_cl_dvfs.h"
51 #include "devices.h"
52 #include "tegra11_soctherm.h"
53
54 #define PMC_CTRL                0x0
55 #define PMC_CTRL_INTR_LOW       (1 << 17)
56
57 /*TPS65090 consumer rails */
58 static struct regulator_consumer_supply tps65090_dcdc1_supply[] = {
59         REGULATOR_SUPPLY("vdd_sys_5v0", NULL),
60         REGULATOR_SUPPLY("vdd_spk", NULL),
61         REGULATOR_SUPPLY("vdd_sys_modem_5v0", NULL),
62         REGULATOR_SUPPLY("vdd_sys_cam_5v0", NULL),
63 };
64
65 static struct regulator_consumer_supply tps65090_dcdc2_supply[] = {
66         REGULATOR_SUPPLY("vdd_sys_3v3", NULL),
67         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
68         REGULATOR_SUPPLY("pwrdet_hv", NULL),
69         REGULATOR_SUPPLY("vdd_sys_ds_3v3", NULL),
70         REGULATOR_SUPPLY("vdd_sys_nfc_3v3", NULL),
71         REGULATOR_SUPPLY("vdd_hv_nfc_3v3", NULL),
72         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
73         REGULATOR_SUPPLY("vdd_sys_sensor_3v3", NULL),
74         REGULATOR_SUPPLY("vdd_sys_audio_3v3", NULL),
75         REGULATOR_SUPPLY("vdd_sys_dtv_3v3", NULL),
76         REGULATOR_SUPPLY("vcc", "0-007c"),
77         REGULATOR_SUPPLY("vcc", "0-0030"),
78         REGULATOR_SUPPLY("vin", "2-0030"),
79 };
80
81 static struct regulator_consumer_supply tps65090_dcdc3_supply[] = {
82         REGULATOR_SUPPLY("vdd_ao", NULL),
83 };
84
85 static struct regulator_consumer_supply tps65090_ldo1_supply[] = {
86         REGULATOR_SUPPLY("vdd_sby_5v0", NULL),
87 };
88
89 static struct regulator_consumer_supply tps65090_ldo2_supply[] = {
90         REGULATOR_SUPPLY("vdd_sby_3v3", NULL),
91 };
92
93 static struct regulator_consumer_supply tps65090_fet1_supply[] = {
94         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
95 };
96
97 static struct regulator_consumer_supply tps65090_fet3_supply[] = {
98         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
99 };
100
101 static struct regulator_consumer_supply tps65090_fet4_supply[] = {
102         REGULATOR_SUPPLY("avdd_lcd", NULL),
103         REGULATOR_SUPPLY("avdd", "spi3.2"),
104 };
105
106 static struct regulator_consumer_supply tps65090_fet5_supply[] = {
107         REGULATOR_SUPPLY("vdd_lvds", NULL),
108 };
109
110 static struct regulator_consumer_supply tps65090_fet6_supply[] = {
111         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
112 };
113
114 static struct regulator_consumer_supply tps65090_fet7_supply[] = {
115         REGULATOR_SUPPLY("vdd_wifi_3v3", "bcm4329_wlan.1"),
116         REGULATOR_SUPPLY("vdd_gps_3v3", "reg-userspace-consumer.2"),
117         REGULATOR_SUPPLY("vdd_bt_3v3", "reg-userspace-consumer.1"),
118 };
119
120 #define TPS65090_PDATA_INIT(_id, _name, _supply_reg,                    \
121                 _always_on, _boot_on, _apply_uV, _en_ext_ctrl, _gpio)   \
122 static struct regulator_init_data ri_data_##_name =                     \
123 {                                                                       \
124         .supply_regulator = _supply_reg,                                \
125         .constraints = {                                                \
126                 .name = tps65090_rails(_id),                            \
127                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
128                                      REGULATOR_MODE_STANDBY),           \
129                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
130                                    REGULATOR_CHANGE_STATUS |            \
131                                    REGULATOR_CHANGE_VOLTAGE),           \
132                 .always_on = _always_on,                                \
133                 .boot_on = _boot_on,                                    \
134                 .apply_uV = _apply_uV,                                  \
135         },                                                              \
136         .num_consumer_supplies =                                        \
137                 ARRAY_SIZE(tps65090_##_name##_supply),                  \
138         .consumer_supplies = tps65090_##_name##_supply,                 \
139 };                                                                      \
140 static struct tps65090_regulator_platform_data                          \
141                         tps65090_regulator_pdata_##_name =              \
142 {                                                                       \
143         .id = TPS65090_REGULATOR_##_id,                                 \
144         .enable_ext_control = _en_ext_ctrl,                             \
145         .gpio = _gpio,                                                  \
146         .reg_init_data = &ri_data_##_name ,                             \
147 }
148
149 TPS65090_PDATA_INIT(DCDC1, dcdc1, NULL, 1, 1, 0, false, -1);
150 TPS65090_PDATA_INIT(DCDC2, dcdc2, NULL, 1, 1, 0, false, -1);
151 TPS65090_PDATA_INIT(DCDC3, dcdc3, NULL, 1, 1, 0, false, -1);
152 TPS65090_PDATA_INIT(LDO1, ldo1, NULL, 1, 1, 0, false, -1);
153 TPS65090_PDATA_INIT(LDO2, ldo2, NULL, 1, 1, 0, false, -1);
154 TPS65090_PDATA_INIT(FET1, fet1, NULL, 0, 0, 0, false, -1);
155 TPS65090_PDATA_INIT(FET3, fet3, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
156 TPS65090_PDATA_INIT(FET4, fet4, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
157 TPS65090_PDATA_INIT(FET5, fet5, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
158 TPS65090_PDATA_INIT(FET6, fet6, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
159 TPS65090_PDATA_INIT(FET7, fet7, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
160
161 #define ADD_TPS65090_REG(_name) (&tps65090_regulator_pdata_##_name)
162 static struct tps65090_regulator_platform_data *tps65090_reg_pdata[] = {
163         ADD_TPS65090_REG(dcdc1),
164         ADD_TPS65090_REG(dcdc2),
165         ADD_TPS65090_REG(dcdc3),
166         ADD_TPS65090_REG(ldo1),
167         ADD_TPS65090_REG(ldo2),
168         ADD_TPS65090_REG(fet1),
169         ADD_TPS65090_REG(fet3),
170         ADD_TPS65090_REG(fet4),
171         ADD_TPS65090_REG(fet5),
172         ADD_TPS65090_REG(fet6),
173         ADD_TPS65090_REG(fet7),
174 };
175
176 static struct tps65090_platform_data tps65090_pdata = {
177         .irq_base = -1,
178         .num_reg_pdata =  ARRAY_SIZE(tps65090_reg_pdata),
179         .reg_pdata = tps65090_reg_pdata
180 };
181
182 /* MAX77663 consumer rails */
183 static struct regulator_consumer_supply max77663_sd0_supply[] = {
184         REGULATOR_SUPPLY("vdd_core", NULL),
185 };
186
187 static struct regulator_consumer_supply max77663_sd1_supply[] = {
188         REGULATOR_SUPPLY("vddio_ddr", NULL),
189         REGULATOR_SUPPLY("vddio_ddr0", NULL),
190         REGULATOR_SUPPLY("vddio_ddr1", NULL),
191 };
192
193 static struct regulator_consumer_supply max77663_sd2_supply[] = {
194         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
195         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
196         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
197         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
198         REGULATOR_SUPPLY("pwrdet_cam", NULL),
199         REGULATOR_SUPPLY("avdd_osc", NULL),
200         REGULATOR_SUPPLY("vddio_sys", NULL),
201         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
202         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
203         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
204         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
205         REGULATOR_SUPPLY("vdd_emmc", NULL),
206         REGULATOR_SUPPLY("vddio_audio", NULL),
207         REGULATOR_SUPPLY("pwrdet_audio", NULL),
208         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
209         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
210         REGULATOR_SUPPLY("vddio_modem", NULL),
211         REGULATOR_SUPPLY("vddio_modem_1v8", NULL),
212         REGULATOR_SUPPLY("vddio_bb", NULL),
213         REGULATOR_SUPPLY("pwrdet_bb", NULL),
214         REGULATOR_SUPPLY("vddio_bb_1v8", NULL),
215         REGULATOR_SUPPLY("vddio_uart", NULL),
216         REGULATOR_SUPPLY("pwrdet_uart", NULL),
217         REGULATOR_SUPPLY("vddio_gmi", NULL),
218         REGULATOR_SUPPLY("pwrdet_nand", NULL),
219         REGULATOR_SUPPLY("vdd_sensor_1v8", NULL),
220         REGULATOR_SUPPLY("vdd_mic_1v8", NULL),
221         REGULATOR_SUPPLY("vdd_nfc_1v8", NULL),
222         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
223         REGULATOR_SUPPLY("vdd_spi_1v8", NULL),
224         REGULATOR_SUPPLY("dvdd_lcd", NULL),
225         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
226         REGULATOR_SUPPLY("vddio_wifi_1v8", "bcm4329_wlan.1"),
227         REGULATOR_SUPPLY("vdd_gps_1v8", "reg-userspace-consumer.2"),
228         REGULATOR_SUPPLY("vddio_bt_1v8", "reg-userspace-consumer.1"),
229         REGULATOR_SUPPLY("vdd_dtv_1v8", NULL),
230 };
231
232 static struct regulator_consumer_supply max77663_sd3_supply[] = {
233         REGULATOR_SUPPLY("vcore_emmc", NULL),
234 };
235
236 static struct regulator_consumer_supply max77663_ldo0_supply[] = {
237         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
238         REGULATOR_SUPPLY("avdd_pllx", NULL),
239         REGULATOR_SUPPLY("avdd_plle", NULL),
240         REGULATOR_SUPPLY("avdd_pllm", NULL),
241         REGULATOR_SUPPLY("avdd_pllu", NULL),
242         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
243         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
244         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
245 };
246
247 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
248         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
249 };
250
251 static struct regulator_consumer_supply max77663_ldo2_supply[] = {
252         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
253         REGULATOR_SUPPLY("vdd_als", NULL),
254         REGULATOR_SUPPLY("vdd", "0-004c"),
255 };
256
257 static struct regulator_consumer_supply max77663_ldo3_supply[] = {
258         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
259         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
260         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
261 };
262
263 static struct regulator_consumer_supply max77663_ldo4_supply[] = {
264         REGULATOR_SUPPLY("vdd_rtc", NULL),
265 };
266
267 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
268         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
269         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
270         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
271         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
272         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
273         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
274         REGULATOR_SUPPLY("vddio_bb_hsic", NULL),
275 };
276
277 static struct regulator_consumer_supply max77663_ldo6_supply[] = {
278         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
279         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
280 };
281
282 /* FIXME!! Put the device address of camera */
283 static struct regulator_consumer_supply max77663_ldo7_supply[] = {
284         REGULATOR_SUPPLY("avdd_cam1", NULL),
285         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
286         REGULATOR_SUPPLY("vana", "2-0036"),
287 };
288
289 /* FIXME!! Put the device address of camera */
290 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
291         REGULATOR_SUPPLY("avdd_cam2", NULL),
292         REGULATOR_SUPPLY("avdd", "2-0010"),
293 };
294
295 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
296         {
297                 .src = FPS_SRC_0,
298                 .en_src = FPS_EN_SRC_EN0,
299                 .time_period = FPS_TIME_PERIOD_DEF,
300         },
301         {
302                 .src = FPS_SRC_1,
303                 .en_src = FPS_EN_SRC_EN1,
304                 .time_period = FPS_TIME_PERIOD_DEF,
305         },
306         {
307                 .src = FPS_SRC_2,
308                 .en_src = FPS_EN_SRC_EN0,
309                 .time_period = FPS_TIME_PERIOD_DEF,
310         },
311 };
312
313 #define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg,   \
314                 _always_on, _boot_on, _apply_uV,                        \
315                 _fps_src, _fps_pu_period, _fps_pd_period, _flags)       \
316         static struct regulator_init_data max77663_regulator_idata_##_id = {   \
317                 .supply_regulator = _supply_reg,                        \
318                 .constraints = {                                        \
319                         .name = max77663_rails(_id),                    \
320                         .min_uV = _min_uV,                              \
321                         .max_uV = _max_uV,                              \
322                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
323                                              REGULATOR_MODE_STANDBY),   \
324                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
325                                            REGULATOR_CHANGE_STATUS |    \
326                                            REGULATOR_CHANGE_VOLTAGE),   \
327                         .always_on = _always_on,                        \
328                         .boot_on = _boot_on,                            \
329                         .apply_uV = _apply_uV,                          \
330                 },                                                      \
331                 .num_consumer_supplies =                                \
332                         ARRAY_SIZE(max77663_##_id##_supply),            \
333                 .consumer_supplies = max77663_##_id##_supply,           \
334         };                                                              \
335 static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id =\
336 {                                                                       \
337                 .reg_init_data = &max77663_regulator_idata_##_id,       \
338                 .id = MAX77663_REGULATOR_ID_##_rid,                     \
339                 .fps_src = _fps_src,                                    \
340                 .fps_pu_period = _fps_pu_period,                        \
341                 .fps_pd_period = _fps_pd_period,                        \
342                 .fps_cfgs = max77663_fps_cfgs,                          \
343                 .flags = _flags,                                        \
344         }
345
346 MAX77663_PDATA_INIT(SD0, sd0,  900000, 1400000, tps65090_rails(DCDC3), 1, 1, 0,
347                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
348
349 MAX77663_PDATA_INIT(SD1, sd1,  1200000, 1200000, tps65090_rails(DCDC3), 1, 1, 1,
350                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
351
352 MAX77663_PDATA_INIT(SD2, sd2,  1800000, 1800000, tps65090_rails(DCDC3), 1, 1, 1,
353                     FPS_SRC_0, -1, -1, 0);
354
355 MAX77663_PDATA_INIT(SD3, sd3,  2850000, 2850000, tps65090_rails(DCDC3), 1, 1, 1,
356                     FPS_SRC_NONE, -1, -1, 0);
357
358 MAX77663_PDATA_INIT(LDO0, ldo0, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
359                     FPS_SRC_1, -1, -1, 0);
360
361 MAX77663_PDATA_INIT(LDO1, ldo1, 1050000, 1050000, max77663_rails(sd2), 0, 0, 1,
362                     FPS_SRC_NONE, -1, -1, 0);
363
364 MAX77663_PDATA_INIT(LDO2, ldo2, 2850000, 2850000, tps65090_rails(DCDC2), 1, 1,
365                     1, FPS_SRC_1, -1, -1, 0);
366
367 MAX77663_PDATA_INIT(LDO3, ldo3, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
368                     FPS_SRC_NONE, -1, -1, 0);
369
370 MAX77663_PDATA_INIT(LDO4, ldo4, 1100000, 1100000, tps65090_rails(DCDC2), 1, 1,
371                     1, FPS_SRC_NONE, -1, -1, 0);
372
373 MAX77663_PDATA_INIT(LDO5, ldo5, 1200000, 1200000, max77663_rails(sd2), 0, 1, 1,
374                     FPS_SRC_NONE, -1, -1, 0);
375
376 MAX77663_PDATA_INIT(LDO6, ldo6, 1800000, 3300000, tps65090_rails(DCDC2), 0, 0, 0,
377                     FPS_SRC_NONE, -1, -1, 0);
378
379 MAX77663_PDATA_INIT(LDO7, ldo7, 2800000, 2800000, tps65090_rails(DCDC2), 0, 0, 1,
380                     FPS_SRC_NONE, -1, -1, 0);
381
382 MAX77663_PDATA_INIT(LDO8, ldo8, 2800000, 2800000, tps65090_rails(DCDC2), 0, 1, 1,
383                     FPS_SRC_1, -1, -1, 0);
384
385 #define MAX77663_REG(_id, _data) (&max77663_regulator_pdata_##_data)
386
387 static struct max77663_regulator_platform_data *max77663_reg_pdata[] = {
388         MAX77663_REG(SD0, sd0),
389         MAX77663_REG(SD1, sd1),
390         MAX77663_REG(SD2, sd2),
391         MAX77663_REG(SD3, sd3),
392         MAX77663_REG(LDO0, ldo0),
393         MAX77663_REG(LDO1, ldo1),
394         MAX77663_REG(LDO2, ldo2),
395         MAX77663_REG(LDO3, ldo3),
396         MAX77663_REG(LDO4, ldo4),
397         MAX77663_REG(LDO5, ldo5),
398         MAX77663_REG(LDO6, ldo6),
399         MAX77663_REG(LDO7, ldo7),
400         MAX77663_REG(LDO8, ldo8),
401 };
402
403 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
404         {
405                 .gpio = MAX77663_GPIO0,
406                 .dir = GPIO_DIR_OUT,
407                 .dout = GPIO_DOUT_LOW,
408                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
409                 .alternate = GPIO_ALT_DISABLE,
410         },
411         {
412                 .gpio = MAX77663_GPIO1,
413                 .dir = GPIO_DIR_IN,
414                 .dout = GPIO_DOUT_HIGH,
415                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
416                 .pull_up = GPIO_PU_ENABLE,
417                 .alternate = GPIO_ALT_DISABLE,
418         },
419         {
420                 .gpio = MAX77663_GPIO2,
421                 .dir = GPIO_DIR_OUT,
422                 .dout = GPIO_DOUT_HIGH,
423                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
424                 .pull_up = GPIO_PU_ENABLE,
425                 .alternate = GPIO_ALT_DISABLE,
426         },
427         {
428                 .gpio = MAX77663_GPIO3,
429                 .dir = GPIO_DIR_OUT,
430                 .dout = GPIO_DOUT_HIGH,
431                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
432                 .pull_up = GPIO_PU_ENABLE,
433                 .alternate = GPIO_ALT_DISABLE,
434         },
435         {
436                 .gpio = MAX77663_GPIO4,
437                 .dir = GPIO_DIR_OUT,
438                 .dout = GPIO_DOUT_HIGH,
439                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
440                 .alternate = GPIO_ALT_ENABLE,
441         },
442         {
443                 .gpio = MAX77663_GPIO5,
444                 .dir = GPIO_DIR_OUT,
445                 .dout = GPIO_DOUT_LOW,
446                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
447                 .alternate = GPIO_ALT_DISABLE,
448         },
449         {
450                 .gpio = MAX77663_GPIO6,
451                 .dir = GPIO_DIR_OUT,
452                 .dout = GPIO_DOUT_LOW,
453                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
454                 .alternate = GPIO_ALT_DISABLE,
455         },
456         {
457                 .gpio = MAX77663_GPIO7,
458                 .dir = GPIO_DIR_OUT,
459                 .dout = GPIO_DOUT_LOW,
460                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
461                 .alternate = GPIO_ALT_DISABLE,
462         },
463 };
464
465 static struct max77663_platform_data max77663_pdata = {
466         .irq_base       = MAX77663_IRQ_BASE,
467         .gpio_base      = MAX77663_GPIO_BASE,
468
469         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
470         .gpio_cfgs      = max77663_gpio_cfgs,
471
472         .regulator_pdata = max77663_reg_pdata,
473         .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata),
474
475         .rtc_i2c_addr   = 0x68,
476
477         .use_power_off  = false,
478 };
479
480 static struct i2c_board_info __initdata max77663_regulators[] = {
481         {
482                 /* The I2C address was determined by OTP factory setting */
483                 I2C_BOARD_INFO("max77663", 0x3c),
484                 .irq            = INT_EXTERNAL_PMU,
485                 .platform_data  = &max77663_pdata,
486         },
487 };
488
489 static struct i2c_board_info __initdata tps65090_regulators[] = {
490         {
491                 I2C_BOARD_INFO("tps65090", 0x48),
492                 .platform_data  = &tps65090_pdata,
493         },
494 };
495
496 /* TPS51632 DC-DC converter */
497 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
498         REGULATOR_SUPPLY("vdd_cpu", NULL),
499 };
500
501 static struct regulator_init_data tps51632_init_data = {
502         .constraints = {                                                \
503                 .min_uV = 500000,                                       \
504                 .max_uV = 1520000,                                      \
505                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
506                                         REGULATOR_MODE_STANDBY),        \
507                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
508                                         REGULATOR_CHANGE_STATUS |       \
509                                         REGULATOR_CHANGE_VOLTAGE),      \
510                 .always_on = 1,                                         \
511                 .boot_on =  1,                                          \
512                 .apply_uV = 0,                                          \
513         },                                                              \
514         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
515                 .consumer_supplies = tps51632_dcdc_supply,              \
516 };
517
518 static struct tps51632_regulator_platform_data tps51632_pdata = {
519         .reg_init_data = &tps51632_init_data,           \
520         .enable_pwm = false,                            \
521         .max_voltage_uV = 1520000,                      \
522         .base_voltage_uV = 500000,                      \
523         .slew_rate_uv_per_us = 6000,                    \
524 };
525
526 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
527         {
528                 I2C_BOARD_INFO("tps51632", 0x43),
529                 .platform_data  = &tps51632_pdata,
530         },
531 };
532
533 /************************ Palmas based regulator ****************/
534 static struct regulator_consumer_supply palmas_smps12_supply[] = {
535         REGULATOR_SUPPLY("vddio_ddr3l", NULL),
536         REGULATOR_SUPPLY("vcore_ddr3l", NULL),
537         REGULATOR_SUPPLY("vref2_ddr3l", NULL),
538 };
539
540 #define palmas_smps3_supply max77663_sd2_supply
541 #define palmas_smps45_supply max77663_sd0_supply
542
543 static struct regulator_consumer_supply palmas_smps8_supply[] = {
544         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
545         REGULATOR_SUPPLY("avdd_pllm", NULL),
546         REGULATOR_SUPPLY("avdd_pllu", NULL),
547         REGULATOR_SUPPLY("avdd_pllx", NULL),
548         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
549         REGULATOR_SUPPLY("avdd_plle", NULL),
550         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
551         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
552         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
553         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
554         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
555         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
556
557 };
558
559 static struct regulator_consumer_supply palmas_smps9_supply[] = {
560         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
561 };
562
563 #define palmas_ldo1_supply max77663_ldo7_supply
564 #define palmas_ldo2_supply max77663_ldo8_supply
565 #define palmas_ldo3_supply max77663_ldo5_supply
566
567 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
568         REGULATOR_SUPPLY("vpp_fuse", NULL),
569 };
570
571 #define palmas_ldo6_supply max77663_ldo2_supply
572
573 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
574         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
575         REGULATOR_SUPPLY("vdd", "2-000e"),
576 };
577
578 #define palmas_ldo8_supply max77663_ldo4_supply
579 #define palmas_ldo9_supply max77663_ldo6_supply
580
581 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
582         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
583 };
584
585 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
586         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
587         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
588         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
589         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
590         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
591 };
592
593 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
594         _boot_on, _apply_uv)                                            \
595         static struct regulator_init_data reg_idata_##_name = {         \
596                 .constraints = {                                        \
597                         .name = palmas_rails(_name),                    \
598                         .min_uV = (_minmv)*1000,                        \
599                         .max_uV = (_maxmv)*1000,                        \
600                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
601                                         REGULATOR_MODE_STANDBY),        \
602                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
603                                         REGULATOR_CHANGE_STATUS |       \
604                                         REGULATOR_CHANGE_VOLTAGE),      \
605                         .always_on = _always_on,                        \
606                         .boot_on = _boot_on,                            \
607                         .apply_uV = _apply_uv,                          \
608                 },                                                      \
609                 .num_consumer_supplies =                                \
610                         ARRAY_SIZE(palmas_##_name##_supply),            \
611                 .consumer_supplies = palmas_##_name##_supply,           \
612                 .supply_regulator = _supply_reg,                        \
613         }
614
615 PALMAS_PDATA_INIT(smps12, 1350,  1350, tps65090_rails(DCDC3), 0, 0, 0);
616 PALMAS_PDATA_INIT(smps3, 1800,  1800, tps65090_rails(DCDC3), 0, 0, 0);
617 PALMAS_PDATA_INIT(smps45, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0);
618 PALMAS_PDATA_INIT(smps8, 1050,  1050, tps65090_rails(DCDC2), 0, 1, 1);
619 PALMAS_PDATA_INIT(smps9, 2800,  2800, tps65090_rails(DCDC2), 1, 0, 0);
620 PALMAS_PDATA_INIT(ldo1, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
621 PALMAS_PDATA_INIT(ldo2, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
622 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps3), 0, 0, 1);
623 PALMAS_PDATA_INIT(ldo4, 1800,  1800, tps65090_rails(DCDC2), 0, 0, 0);
624 PALMAS_PDATA_INIT(ldo6, 2850,  2850, tps65090_rails(DCDC2), 0, 0, 1);
625 PALMAS_PDATA_INIT(ldo7, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
626 PALMAS_PDATA_INIT(ldo8, 900,  900, tps65090_rails(DCDC3), 1, 1, 1);
627 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
628 PALMAS_PDATA_INIT(ldoln, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1);
629 PALMAS_PDATA_INIT(ldousb, 3300,  3300, tps65090_rails(DCDC1), 0, 0, 1);
630
631 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
632
633 static struct regulator_init_data *dalmore_e1611_reg_data[PALMAS_NUM_REGS] = {
634         PALMAS_REG_PDATA(smps12),
635         NULL,
636         PALMAS_REG_PDATA(smps3),
637         PALMAS_REG_PDATA(smps45),
638         NULL,
639         NULL,
640         NULL,
641         PALMAS_REG_PDATA(smps8),
642         PALMAS_REG_PDATA(smps9),
643         NULL,
644         PALMAS_REG_PDATA(ldo1),
645         PALMAS_REG_PDATA(ldo2),
646         PALMAS_REG_PDATA(ldo3),
647         PALMAS_REG_PDATA(ldo4),
648         NULL,
649         PALMAS_REG_PDATA(ldo6),
650         PALMAS_REG_PDATA(ldo7),
651         PALMAS_REG_PDATA(ldo8),
652         PALMAS_REG_PDATA(ldo9),
653         PALMAS_REG_PDATA(ldoln),
654         PALMAS_REG_PDATA(ldousb),
655         NULL,
656         NULL,
657         NULL,
658         NULL,
659         NULL,
660 };
661
662 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
663                 _tstep, _vsel)                                          \
664         static struct palmas_reg_init reg_init_data_##_name = {         \
665                 .warm_reset = _warm_reset,                              \
666                 .roof_floor =   _roof_floor,                            \
667                 .mode_sleep = _mode_sleep,                              \
668                 .tstep = _tstep,                                        \
669                 .vsel = _vsel,                                          \
670         }
671
672 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
673 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
674 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
675 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
676 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
677 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
678 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
679 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
680 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
681 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
682 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
683 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
684 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
685 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
686 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
687 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
688 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
689 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
690 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
691 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
692 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
693 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
694 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
695 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
696 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
697 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
698
699 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
700 static struct palmas_reg_init *dalmore_e1611_reg_init[PALMAS_NUM_REGS] = {
701         PALMAS_REG_INIT_DATA(smps12),
702         PALMAS_REG_INIT_DATA(smps123),
703         PALMAS_REG_INIT_DATA(smps3),
704         PALMAS_REG_INIT_DATA(smps45),
705         PALMAS_REG_INIT_DATA(smps457),
706         PALMAS_REG_INIT_DATA(smps6),
707         PALMAS_REG_INIT_DATA(smps7),
708         PALMAS_REG_INIT_DATA(smps8),
709         PALMAS_REG_INIT_DATA(smps9),
710         PALMAS_REG_INIT_DATA(smps10),
711         PALMAS_REG_INIT_DATA(ldo1),
712         PALMAS_REG_INIT_DATA(ldo2),
713         PALMAS_REG_INIT_DATA(ldo3),
714         PALMAS_REG_INIT_DATA(ldo4),
715         PALMAS_REG_INIT_DATA(ldo5),
716         PALMAS_REG_INIT_DATA(ldo6),
717         PALMAS_REG_INIT_DATA(ldo7),
718         PALMAS_REG_INIT_DATA(ldo8),
719         PALMAS_REG_INIT_DATA(ldo9),
720         PALMAS_REG_INIT_DATA(ldoln),
721         PALMAS_REG_INIT_DATA(ldousb),
722         PALMAS_REG_INIT_DATA(regen1),
723         PALMAS_REG_INIT_DATA(regen2),
724         PALMAS_REG_INIT_DATA(regen3),
725         PALMAS_REG_INIT_DATA(sysen1),
726         PALMAS_REG_INIT_DATA(sysen2),
727 };
728
729 static struct palmas_pmic_platform_data pmic_platform = {
730         .enable_ldo8_tracking = true,
731         .disabe_ldo8_tracking_suspend = true,
732 };
733
734 static struct palmas_platform_data palmas_pdata = {
735         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
736         .irq_base = PALMAS_TEGRA_IRQ_BASE,
737         .pmic_pdata = &pmic_platform,
738         .mux_from_pdata = true,
739         .pad1 = 0,
740         .pad2 = 0,
741         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
742         .use_power_off = true,
743 };
744
745 static struct i2c_board_info palma_device[] = {
746         {
747                 I2C_BOARD_INFO("tps65913", 0x58),
748                 .irq            = INT_EXTERNAL_PMU,
749                 .platform_data  = &palmas_pdata,
750         },
751 };
752
753 /* EN_AVDD_USB_HDMI From PMU GP1 */
754 static struct regulator_consumer_supply fixed_reg_avdd_usb_hdmi_supply[] = {
755         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
756         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
757         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
758         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
759         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
760         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
761 };
762
763 /* EN_CAM_1v8 From PMU GP5 */
764 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
765         REGULATOR_SUPPLY("dvdd_cam", NULL),
766         REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
767         REGULATOR_SUPPLY("vi2c", "2-0030"),
768         REGULATOR_SUPPLY("vif", "2-0036"),
769         REGULATOR_SUPPLY("dovdd", "2-0010"),
770         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
771 };
772
773 /* EN_CAM_1v8 on e1611 From PMU GP6 */
774 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_e1611_supply[] = {
775         REGULATOR_SUPPLY("dvdd_cam", NULL),
776         REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
777         REGULATOR_SUPPLY("vi2c", "2-0030"),
778         REGULATOR_SUPPLY("vif", "2-0036"),
779         REGULATOR_SUPPLY("dovdd", "2-0010"),
780         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
781 };
782
783 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
784         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
785 };
786
787 /* EN_USB1_VBUS From TEGRA GPIO PN4 PR3(T30) */
788 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
789         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
790 };
791
792 /* EN_3V3_FUSE From TEGRA GPIO PX4 */
793 static struct regulator_consumer_supply fixed_reg_vpp_fuse_supply[] = {
794         REGULATOR_SUPPLY("vpp_fuse", NULL),
795 };
796
797 /* EN_USB3_VBUS From TEGRA GPIO PM5 */
798 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
799         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
800 };
801
802 /* EN_1V8_TS From TEGRA_GPIO_PH5 */
803 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
804         REGULATOR_SUPPLY("dvdd", "spi3.2"),
805 };
806
807 /* Macro for defining fixed regulator sub device data */
808 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
809 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
810         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
811         static struct regulator_init_data ri_data_##_var =              \
812         {                                                               \
813                 .supply_regulator = _in_supply,                         \
814                 .num_consumer_supplies =                                \
815                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
816                 .consumer_supplies = fixed_reg_##_name##_supply,        \
817                 .constraints = {                                        \
818                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
819                                         REGULATOR_MODE_STANDBY),        \
820                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
821                                         REGULATOR_CHANGE_STATUS |       \
822                                         REGULATOR_CHANGE_VOLTAGE),      \
823                         .always_on = _always_on,                        \
824                         .boot_on = _boot_on,                            \
825                 },                                                      \
826         };                                                              \
827         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
828         {                                                               \
829                 .supply_name = FIXED_SUPPLY(_name),                     \
830                 .microvolts = _millivolts * 1000,                       \
831                 .gpio = _gpio_nr,                                       \
832                 .gpio_is_open_drain = _open_drain,                      \
833                 .enable_high = _active_high,                            \
834                 .enabled_at_boot = _boot_state,                         \
835                 .init_data = &ri_data_##_var,                           \
836         };                                                              \
837         static struct platform_device fixed_reg_##_var##_dev = {        \
838                 .name = "reg-fixed-voltage",                            \
839                 .id = _id,                                              \
840                 .dev = {                                                \
841                         .platform_data = &fixed_reg_##_var##_pdata,     \
842                 },                                                      \
843         }
844
845 FIXED_REG(1,    avdd_usb_hdmi,  avdd_usb_hdmi,
846         tps65090_rails(DCDC2),  0,      0,
847         MAX77663_GPIO_BASE + MAX77663_GPIO1,    true,   true,   1,      3300);
848
849 FIXED_REG(2,    en_1v8_cam,     en_1v8_cam,
850         max77663_rails(sd2),    0,      0,
851         MAX77663_GPIO_BASE + MAX77663_GPIO5,    false,  true,   0,      1800);
852
853 FIXED_REG(3,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
854         tps65090_rails(DCDC1),  0,      0,
855         TEGRA_GPIO_PK1, false,  true,   0,      5000);
856
857 FIXED_REG(4,    vpp_fuse,       vpp_fuse,
858         max77663_rails(sd2),    0,      0,
859         TEGRA_GPIO_PX4, false,  true,   0,      3300);
860
861 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
862 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
863         tps65090_rails(DCDC1),  0,      0,
864         TEGRA_GPIO_PN4, true,   true,   0,      5000);
865 #else
866 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
867         tps65090_rails(DCDC1),  0,      0,
868         TEGRA_GPIO_PR3, true,   true,   0,      5000);
869 #endif
870
871 FIXED_REG(6,    usb3_vbus,      usb3_vbus,
872         tps65090_rails(DCDC1),  0,      0,
873         TEGRA_GPIO_PK6, true,   true,   0,      5000);
874
875 FIXED_REG(7,    en_1v8_cam_e1611,       en_1v8_cam_e1611,
876         palmas_rails(smps3),    0,      0,
877         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
878
879 FIXED_REG(8,    dvdd_ts,        dvdd_ts,
880         palmas_rails(smps3),    0,      0,
881         TEGRA_GPIO_PH5, false,  false,  1,      1800);
882 /*
883  * Creating the fixed regulator device tables
884  */
885
886 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
887
888 #define DALMORE_COMMON_FIXED_REG                \
889         ADD_FIXED_REG(usb1_vbus),               \
890         ADD_FIXED_REG(usb3_vbus),               \
891         ADD_FIXED_REG(vdd_hdmi_5v0),
892
893 #define E1612_FIXED_REG                         \
894         ADD_FIXED_REG(avdd_usb_hdmi),           \
895         ADD_FIXED_REG(en_1v8_cam),              \
896         ADD_FIXED_REG(vpp_fuse),                \
897
898 #define E1611_FIXED_REG                         \
899         ADD_FIXED_REG(en_1v8_cam_e1611), \
900         ADD_FIXED_REG(dvdd_ts),
901
902 /* Gpio switch regulator platform data for Dalmore E1611 */
903 static struct platform_device *fixed_reg_devs_e1611_a00[] = {
904         DALMORE_COMMON_FIXED_REG
905         E1611_FIXED_REG
906 };
907
908 /* Gpio switch regulator platform data for Dalmore E1612 */
909 static struct platform_device *fixed_reg_devs_e1612_a00[] = {
910         DALMORE_COMMON_FIXED_REG
911         E1612_FIXED_REG
912 };
913
914 int __init dalmore_palmas_regulator_init(void)
915 {
916         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
917         u32 pmc_ctrl;
918         int i;
919 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
920         int ret;
921
922         ret = gpio_request(TEGRA_GPIO_PCC3, "pmic_nreswarm");
923         if (ret < 0)
924                 pr_err("%s: gpio_request failed for gpio %d\n",
925                                 __func__, TEGRA_GPIO_PCC3);
926         else
927                 gpio_direction_output(TEGRA_GPIO_PCC3, 1);
928 #endif
929         /* TPS65913: Normal state of INT request line is LOW.
930          * configure the power management controller to trigger PMU
931          * interrupts when HIGH.
932          */
933         pmc_ctrl = readl(pmc + PMC_CTRL);
934         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
935         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
936                 pmic_platform.reg_data[i] = dalmore_e1611_reg_data[i];
937                 pmic_platform.reg_init[i] = dalmore_e1611_reg_init[i];
938         }
939
940         i2c_register_board_info(4, palma_device,
941                         ARRAY_SIZE(palma_device));
942         return 0;
943 }
944
945 static int ac_online(void)
946 {
947         return 1;
948 }
949
950 static struct resource dalmore_pda_resources[] = {
951         [0] = {
952                 .name   = "ac",
953         },
954 };
955
956 static struct pda_power_pdata dalmore_pda_data = {
957         .is_ac_online   = ac_online,
958 };
959
960 static struct platform_device dalmore_pda_power_device = {
961         .name           = "pda-power",
962         .id             = -1,
963         .resource       = dalmore_pda_resources,
964         .num_resources  = ARRAY_SIZE(dalmore_pda_resources),
965         .dev    = {
966                 .platform_data  = &dalmore_pda_data,
967         },
968 };
969
970 static struct tegra_suspend_platform_data dalmore_suspend_data = {
971         .cpu_timer      = 300,
972         .cpu_off_timer  = 300,
973         .suspend_mode   = TEGRA_SUSPEND_LP0,
974         .core_timer     = 0x157e,
975         .core_off_timer = 2000,
976         .corereq_high   = true,
977         .sysclkreq_high = true,
978         .min_residency_noncpu = 600,
979         .min_residency_crail = 1000,
980 };
981 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
982 /* board parameters for cpu dfll */
983 static struct tegra_cl_dvfs_cfg_param dalmore_cl_dvfs_param = {
984         .sample_rate = 12500,
985
986         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
987         .cf = 10,
988         .ci = 0,
989         .cg = 2,
990
991         .droop_cut_value = 0xF,
992         .droop_restore_ramp = 0x0,
993         .scale_out_ramp = 0x0,
994 };
995 #endif
996
997 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
998 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
999 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
1000 static inline void fill_reg_map(void)
1001 {
1002         int i;
1003         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
1004                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
1005                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
1006         }
1007 }
1008
1009 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1010 static struct tegra_cl_dvfs_platform_data dalmore_cl_dvfs_data = {
1011         .dfll_clk_name = "dfll_cpu",
1012         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
1013         .u.pmu_i2c = {
1014                 .fs_rate = 400000,
1015                 .slave_addr = 0x86,
1016                 .reg = 0x00,
1017         },
1018         .vdd_map = pmu_cpu_vdd_map,
1019         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
1020
1021         .cfg_param = &dalmore_cl_dvfs_param,
1022 };
1023
1024 static int __init dalmore_cl_dvfs_init(void)
1025 {
1026         fill_reg_map();
1027         tegra_cl_dvfs_device.dev.platform_data = &dalmore_cl_dvfs_data;
1028         platform_device_register(&tegra_cl_dvfs_device);
1029
1030         return 0;
1031 }
1032 #endif
1033
1034 static int __init dalmore_max77663_regulator_init(void)
1035 {
1036         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
1037         u32 pmc_ctrl;
1038
1039         /* configure the power management controller to trigger PMU
1040          * interrupts when low */
1041         pmc_ctrl = readl(pmc + PMC_CTRL);
1042         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
1043
1044         i2c_register_board_info(4, max77663_regulators,
1045                                 ARRAY_SIZE(max77663_regulators));
1046
1047         return 0;
1048 }
1049
1050 static struct regulator_bulk_data dalmore_gps_regulator_supply[] = {
1051         [0] = {
1052                 .supply = "vdd_gps_3v3",
1053         },
1054         [1] = {
1055                 .supply = "vdd_gps_1v8",
1056         },
1057 };
1058
1059 static struct regulator_userspace_consumer_data dalmore_gps_regulator_pdata = {
1060         .num_supplies   = ARRAY_SIZE(dalmore_gps_regulator_supply),
1061         .supplies       = dalmore_gps_regulator_supply,
1062 };
1063
1064 static struct platform_device dalmore_gps_regulator_device = {
1065         .name   = "reg-userspace-consumer",
1066         .id     = 2,
1067         .dev    = {
1068                         .platform_data = &dalmore_gps_regulator_pdata,
1069         },
1070 };
1071
1072 static struct regulator_bulk_data dalmore_bt_regulator_supply[] = {
1073         [0] = {
1074                 .supply = "vdd_bt_3v3",
1075         },
1076         [1] = {
1077                 .supply = "vddio_bt_1v8",
1078         },
1079 };
1080
1081 static struct regulator_userspace_consumer_data dalmore_bt_regulator_pdata = {
1082         .num_supplies   = ARRAY_SIZE(dalmore_bt_regulator_supply),
1083         .supplies       = dalmore_bt_regulator_supply,
1084 };
1085
1086 static struct platform_device dalmore_bt_regulator_device = {
1087         .name   = "reg-userspace-consumer",
1088         .id     = 1,
1089         .dev    = {
1090                         .platform_data = &dalmore_bt_regulator_pdata,
1091         },
1092 };
1093
1094 static int __init dalmore_fixed_regulator_init(void)
1095 {
1096         struct board_info board_info;
1097
1098         if (!machine_is_dalmore())
1099                 return 0;
1100
1101         tegra_get_board_info(&board_info);
1102
1103         if (board_info.board_id == BOARD_E1611 ||
1104                 board_info.board_id == BOARD_P2454)
1105                 return platform_add_devices(fixed_reg_devs_e1611_a00,
1106                                 ARRAY_SIZE(fixed_reg_devs_e1611_a00));
1107         else
1108                 return platform_add_devices(fixed_reg_devs_e1612_a00,
1109                                 ARRAY_SIZE(fixed_reg_devs_e1612_a00));
1110 }
1111 subsys_initcall_sync(dalmore_fixed_regulator_init);
1112
1113 int __init dalmore_regulator_init(void)
1114 {
1115         struct board_info board_info;
1116         i2c_register_board_info(4, tps65090_regulators,
1117                         ARRAY_SIZE(tps65090_regulators));
1118 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1119         dalmore_cl_dvfs_init();
1120 #endif
1121         tegra_get_board_info(&board_info);
1122         if (board_info.board_id == BOARD_E1611 ||
1123                 board_info.board_id == BOARD_P2454)
1124                 dalmore_palmas_regulator_init();
1125         else
1126                 dalmore_max77663_regulator_init();
1127
1128         i2c_register_board_info(4, tps51632_boardinfo, 1);
1129         platform_device_register(&dalmore_pda_power_device);
1130         platform_device_register(&dalmore_bt_regulator_device);
1131         platform_device_register(&dalmore_gps_regulator_device);
1132         return 0;
1133 }
1134
1135 int __init dalmore_suspend_init(void)
1136 {
1137         tegra_init_suspend(&dalmore_suspend_data);
1138         return 0;
1139 }
1140
1141 int __init dalmore_edp_init(void)
1142 {
1143 #ifdef CONFIG_TEGRA_EDP_LIMITS
1144         unsigned int regulator_mA;
1145
1146         regulator_mA = get_maximum_cpu_current_supported();
1147         if (!regulator_mA)
1148                 regulator_mA = 15000;
1149
1150         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1151
1152         tegra_init_cpu_edp_limits(regulator_mA);
1153 #endif
1154         return 0;
1155 }
1156
1157 static struct soctherm_platform_data dalmore_soctherm_data = {
1158         .soctherm_clk_rate = 136000000,
1159         .tsensor_clk_rate = 500000,
1160         .sensor_data = {
1161                 [TSENSE_CPU0] = {
1162                         .enable = true,
1163                         .tall = 16300,
1164                         .tiddq = 1,
1165                         .ten_count = 1,
1166                         .tsample = 163,
1167                         .pdiv = 10,
1168                 },
1169                 [TSENSE_CPU1] = {
1170                         .enable = true,
1171                         .tall = 16300,
1172                         .tiddq = 1,
1173                         .ten_count = 1,
1174                         .tsample = 163,
1175                         .pdiv = 10,
1176                 },
1177                 [TSENSE_CPU2] = {
1178                         .enable = true,
1179                         .tall = 16300,
1180                         .tiddq = 1,
1181                         .ten_count = 1,
1182                         .tsample = 163,
1183                         .pdiv = 10,
1184                 },
1185                 [TSENSE_CPU3] = {
1186                         .enable = true,
1187                         .tall = 16300,
1188                         .tiddq = 1,
1189                         .ten_count = 1,
1190                         .tsample = 163,
1191                         .pdiv = 10,
1192                 },
1193                 /* MEM0/MEM1 won't be used */
1194                 [TSENSE_MEM0] = {
1195                         .enable = false,
1196                 },
1197                 [TSENSE_MEM1] = {
1198                         .enable = false,
1199                 },
1200                 [TSENSE_GPU] = {
1201                         .enable = true,
1202                         .tall = 16300,
1203                         .tiddq = 1,
1204                         .ten_count = 1,
1205                         .tsample = 163,
1206                         .pdiv = 10,
1207                 },
1208                 [TSENSE_PLLX] = {
1209                         .enable = true,
1210                         .tall = 16300,
1211                         .tiddq = 1,
1212                         .ten_count = 1,
1213                         .tsample = 163,
1214                         .pdiv = 10,
1215                 },
1216         },
1217 };
1218
1219 int __init dalmore_soctherm_init(void)
1220 {
1221         return tegra11_soctherm_init(&dalmore_soctherm_data);
1222 }