arm: tegra: dalmore: tps65090 charger platform data
[linux-3.10.git] / arch / arm / mach-tegra / board-dalmore-power.c
1 /*
2  * arch/arm/mach-tegra/board-dalmore-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/max77663-core.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/mfd/tps65090.h>
31 #include <linux/regulator/max77663-regulator.h>
32 #include <linux/regulator/tps65090-regulator.h>
33 #include <linux/regulator/tps51632-regulator.h>
34 #include <linux/gpio.h>
35 #include <linux/interrupt.h>
36 #include <linux/regulator/userspace-consumer.h>
37
38 #include <asm/mach-types.h>
39 #include <linux/power/sbs-battery.h>
40
41 #include <mach/iomap.h>
42 #include <mach/irqs.h>
43 #include <mach/edp.h>
44 #include <mach/gpio-tegra.h>
45
46 #include "cpu-tegra.h"
47 #include "pm.h"
48 #include "tegra-board-id.h"
49 #include "board.h"
50 #include "gpio-names.h"
51 #include "board-dalmore.h"
52 #include "tegra_cl_dvfs.h"
53 #include "devices.h"
54 #include "tegra11_soctherm.h"
55
56 #define PMC_CTRL                0x0
57 #define PMC_CTRL_INTR_LOW       (1 << 17)
58 #define TPS65090_CHARGER_INT    TEGRA_GPIO_PJ0
59 /*TPS65090 consumer rails */
60 static struct regulator_consumer_supply tps65090_dcdc1_supply[] = {
61         REGULATOR_SUPPLY("vdd_sys_5v0", NULL),
62         REGULATOR_SUPPLY("vdd_spk", NULL),
63         REGULATOR_SUPPLY("vdd_sys_modem_5v0", NULL),
64         REGULATOR_SUPPLY("vdd_sys_cam_5v0", NULL),
65 };
66
67 static struct regulator_consumer_supply tps65090_dcdc2_supply[] = {
68         REGULATOR_SUPPLY("vdd_sys_3v3", NULL),
69         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
70         REGULATOR_SUPPLY("pwrdet_hv", NULL),
71         REGULATOR_SUPPLY("vdd_sys_ds_3v3", NULL),
72         REGULATOR_SUPPLY("vdd_sys_nfc_3v3", NULL),
73         REGULATOR_SUPPLY("vdd_hv_nfc_3v3", NULL),
74         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
75         REGULATOR_SUPPLY("vdd_sys_sensor_3v3", NULL),
76         REGULATOR_SUPPLY("vdd_sys_audio_3v3", NULL),
77         REGULATOR_SUPPLY("vdd_sys_dtv_3v3", NULL),
78         REGULATOR_SUPPLY("vcc", "0-007c"),
79         REGULATOR_SUPPLY("vcc", "0-0030"),
80         REGULATOR_SUPPLY("vin", "2-0030"),
81 };
82
83 static struct regulator_consumer_supply tps65090_dcdc3_supply[] = {
84         REGULATOR_SUPPLY("vdd_ao", NULL),
85 };
86
87 static struct regulator_consumer_supply tps65090_ldo1_supply[] = {
88         REGULATOR_SUPPLY("vdd_sby_5v0", NULL),
89 };
90
91 static struct regulator_consumer_supply tps65090_ldo2_supply[] = {
92         REGULATOR_SUPPLY("vdd_sby_3v3", NULL),
93 };
94
95 static struct regulator_consumer_supply tps65090_fet1_supply[] = {
96         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
97 };
98
99 static struct regulator_consumer_supply tps65090_fet3_supply[] = {
100         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
101 };
102
103 static struct regulator_consumer_supply tps65090_fet4_supply[] = {
104         REGULATOR_SUPPLY("avdd_lcd", NULL),
105         REGULATOR_SUPPLY("avdd", "spi3.2"),
106 };
107
108 static struct regulator_consumer_supply tps65090_fet5_supply[] = {
109         REGULATOR_SUPPLY("vdd_lvds", NULL),
110 };
111
112 static struct regulator_consumer_supply tps65090_fet6_supply[] = {
113         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
114 };
115
116 static struct regulator_consumer_supply tps65090_fet7_supply[] = {
117         REGULATOR_SUPPLY("vdd_wifi_3v3", "bcm4329_wlan.1"),
118         REGULATOR_SUPPLY("vdd_gps_3v3", "reg-userspace-consumer.2"),
119         REGULATOR_SUPPLY("vdd_bt_3v3", "reg-userspace-consumer.1"),
120 };
121
122 #define TPS65090_PDATA_INIT(_id, _name, _supply_reg,                    \
123                 _always_on, _boot_on, _apply_uV, _en_ext_ctrl, _gpio)   \
124 static struct regulator_init_data ri_data_##_name =                     \
125 {                                                                       \
126         .supply_regulator = _supply_reg,                                \
127         .constraints = {                                                \
128                 .name = tps65090_rails(_id),                            \
129                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
130                                      REGULATOR_MODE_STANDBY),           \
131                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
132                                    REGULATOR_CHANGE_STATUS |            \
133                                    REGULATOR_CHANGE_VOLTAGE),           \
134                 .always_on = _always_on,                                \
135                 .boot_on = _boot_on,                                    \
136                 .apply_uV = _apply_uV,                                  \
137         },                                                              \
138         .num_consumer_supplies =                                        \
139                 ARRAY_SIZE(tps65090_##_name##_supply),                  \
140         .consumer_supplies = tps65090_##_name##_supply,                 \
141 };                                                                      \
142 static struct tps65090_regulator_platform_data                          \
143                         tps65090_regulator_pdata_##_name =              \
144 {                                                                       \
145         .id = TPS65090_REGULATOR_##_id,                                 \
146         .enable_ext_control = _en_ext_ctrl,                             \
147         .gpio = _gpio,                                                  \
148         .reg_init_data = &ri_data_##_name ,                             \
149 }
150
151 TPS65090_PDATA_INIT(DCDC1, dcdc1, NULL, 1, 1, 0, false, -1);
152 TPS65090_PDATA_INIT(DCDC2, dcdc2, NULL, 1, 1, 0, false, -1);
153 TPS65090_PDATA_INIT(DCDC3, dcdc3, NULL, 1, 1, 0, false, -1);
154 TPS65090_PDATA_INIT(LDO1, ldo1, NULL, 1, 1, 0, false, -1);
155 TPS65090_PDATA_INIT(LDO2, ldo2, NULL, 1, 1, 0, false, -1);
156 TPS65090_PDATA_INIT(FET1, fet1, NULL, 0, 0, 0, false, -1);
157 TPS65090_PDATA_INIT(FET3, fet3, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
158 TPS65090_PDATA_INIT(FET4, fet4, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
159 TPS65090_PDATA_INIT(FET5, fet5, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
160 TPS65090_PDATA_INIT(FET6, fet6, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
161 TPS65090_PDATA_INIT(FET7, fet7, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
162
163 #define ADD_TPS65090_REG(_name) (&tps65090_regulator_pdata_##_name)
164 static struct tps65090_regulator_platform_data *tps65090_reg_pdata[] = {
165         ADD_TPS65090_REG(dcdc1),
166         ADD_TPS65090_REG(dcdc2),
167         ADD_TPS65090_REG(dcdc3),
168         ADD_TPS65090_REG(ldo1),
169         ADD_TPS65090_REG(ldo2),
170         ADD_TPS65090_REG(fet1),
171         ADD_TPS65090_REG(fet3),
172         ADD_TPS65090_REG(fet4),
173         ADD_TPS65090_REG(fet5),
174         ADD_TPS65090_REG(fet6),
175         ADD_TPS65090_REG(fet7),
176 };
177
178 static struct tps65090_charger_data bcharger_pdata = {
179         .irq_base = TPS65090_TEGRA_IRQ_BASE,
180         .update_status = sbs_update,
181 };
182
183 static struct tps65090_platform_data tps65090_pdata = {
184         .irq_base = TPS65090_TEGRA_IRQ_BASE,
185         .irq_flag = IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
186         .num_reg_pdata =  ARRAY_SIZE(tps65090_reg_pdata),
187         .reg_pdata = tps65090_reg_pdata,
188         .charger_pdata = &bcharger_pdata,
189 };
190
191 /* MAX77663 consumer rails */
192 static struct regulator_consumer_supply max77663_sd0_supply[] = {
193         REGULATOR_SUPPLY("vdd_core", NULL),
194 };
195
196 static struct regulator_consumer_supply max77663_sd1_supply[] = {
197         REGULATOR_SUPPLY("vddio_ddr", NULL),
198         REGULATOR_SUPPLY("vddio_ddr0", NULL),
199         REGULATOR_SUPPLY("vddio_ddr1", NULL),
200 };
201
202 static struct regulator_consumer_supply max77663_sd2_supply[] = {
203         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
204         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
205         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
206         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
207         REGULATOR_SUPPLY("pwrdet_cam", NULL),
208         REGULATOR_SUPPLY("avdd_osc", NULL),
209         REGULATOR_SUPPLY("vddio_sys", NULL),
210         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
211         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
212         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
213         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
214         REGULATOR_SUPPLY("vdd_emmc", NULL),
215         REGULATOR_SUPPLY("vddio_audio", NULL),
216         REGULATOR_SUPPLY("pwrdet_audio", NULL),
217         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
218         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
219         REGULATOR_SUPPLY("vddio_modem", NULL),
220         REGULATOR_SUPPLY("vddio_modem_1v8", NULL),
221         REGULATOR_SUPPLY("vddio_bb", NULL),
222         REGULATOR_SUPPLY("pwrdet_bb", NULL),
223         REGULATOR_SUPPLY("vddio_bb_1v8", NULL),
224         REGULATOR_SUPPLY("vddio_uart", NULL),
225         REGULATOR_SUPPLY("pwrdet_uart", NULL),
226         REGULATOR_SUPPLY("vddio_gmi", NULL),
227         REGULATOR_SUPPLY("pwrdet_nand", NULL),
228         REGULATOR_SUPPLY("vdd_sensor_1v8", NULL),
229         REGULATOR_SUPPLY("vdd_mic_1v8", NULL),
230         REGULATOR_SUPPLY("vdd_nfc_1v8", NULL),
231         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
232         REGULATOR_SUPPLY("vdd_spi_1v8", NULL),
233         REGULATOR_SUPPLY("dvdd_lcd", NULL),
234         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
235         REGULATOR_SUPPLY("vddio_wifi_1v8", "bcm4329_wlan.1"),
236         REGULATOR_SUPPLY("vdd_gps_1v8", "reg-userspace-consumer.2"),
237         REGULATOR_SUPPLY("vddio_bt_1v8", "reg-userspace-consumer.1"),
238         REGULATOR_SUPPLY("vdd_dtv_1v8", NULL),
239         REGULATOR_SUPPLY("vlogic", "0-0069"),
240 };
241
242 static struct regulator_consumer_supply max77663_sd3_supply[] = {
243         REGULATOR_SUPPLY("vcore_emmc", NULL),
244 };
245
246 static struct regulator_consumer_supply max77663_ldo0_supply[] = {
247         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
248         REGULATOR_SUPPLY("avdd_pllx", NULL),
249         REGULATOR_SUPPLY("avdd_plle", NULL),
250         REGULATOR_SUPPLY("avdd_pllm", NULL),
251         REGULATOR_SUPPLY("avdd_pllu", NULL),
252         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
253         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
254         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
255 };
256
257 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
258         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
259 };
260
261 static struct regulator_consumer_supply max77663_ldo2_supply[] = {
262         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
263         REGULATOR_SUPPLY("vdd_als", NULL),
264         REGULATOR_SUPPLY("vdd", "0-004c"),
265         REGULATOR_SUPPLY("vdd", "0-0069"),
266 };
267
268 static struct regulator_consumer_supply max77663_ldo3_supply[] = {
269         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
270         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
271         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
272 };
273
274 static struct regulator_consumer_supply max77663_ldo4_supply[] = {
275         REGULATOR_SUPPLY("vdd_rtc", NULL),
276 };
277
278 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
279         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
280         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
281         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
282         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
283         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
284         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
285         REGULATOR_SUPPLY("vddio_bb_hsic", NULL),
286 };
287
288 static struct regulator_consumer_supply max77663_ldo6_supply[] = {
289         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
290         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
291 };
292
293 /* FIXME!! Put the device address of camera */
294 static struct regulator_consumer_supply max77663_ldo7_supply[] = {
295         REGULATOR_SUPPLY("avdd_cam1", NULL),
296         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
297         REGULATOR_SUPPLY("vana", "2-0036"),
298 };
299
300 /* FIXME!! Put the device address of camera */
301 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
302         REGULATOR_SUPPLY("avdd_cam2", NULL),
303         REGULATOR_SUPPLY("avdd", "2-0010"),
304 };
305
306 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
307         {
308                 .src = FPS_SRC_0,
309                 .en_src = FPS_EN_SRC_EN0,
310                 .time_period = FPS_TIME_PERIOD_DEF,
311         },
312         {
313                 .src = FPS_SRC_1,
314                 .en_src = FPS_EN_SRC_EN1,
315                 .time_period = FPS_TIME_PERIOD_DEF,
316         },
317         {
318                 .src = FPS_SRC_2,
319                 .en_src = FPS_EN_SRC_EN0,
320                 .time_period = FPS_TIME_PERIOD_DEF,
321         },
322 };
323
324 #define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg,   \
325                 _always_on, _boot_on, _apply_uV,                        \
326                 _fps_src, _fps_pu_period, _fps_pd_period, _flags)       \
327         static struct regulator_init_data max77663_regulator_idata_##_id = {   \
328                 .supply_regulator = _supply_reg,                        \
329                 .constraints = {                                        \
330                         .name = max77663_rails(_id),                    \
331                         .min_uV = _min_uV,                              \
332                         .max_uV = _max_uV,                              \
333                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
334                                              REGULATOR_MODE_STANDBY),   \
335                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
336                                            REGULATOR_CHANGE_STATUS |    \
337                                            REGULATOR_CHANGE_VOLTAGE),   \
338                         .always_on = _always_on,                        \
339                         .boot_on = _boot_on,                            \
340                         .apply_uV = _apply_uV,                          \
341                 },                                                      \
342                 .num_consumer_supplies =                                \
343                         ARRAY_SIZE(max77663_##_id##_supply),            \
344                 .consumer_supplies = max77663_##_id##_supply,           \
345         };                                                              \
346 static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id =\
347 {                                                                       \
348                 .reg_init_data = &max77663_regulator_idata_##_id,       \
349                 .id = MAX77663_REGULATOR_ID_##_rid,                     \
350                 .fps_src = _fps_src,                                    \
351                 .fps_pu_period = _fps_pu_period,                        \
352                 .fps_pd_period = _fps_pd_period,                        \
353                 .fps_cfgs = max77663_fps_cfgs,                          \
354                 .flags = _flags,                                        \
355         }
356
357 MAX77663_PDATA_INIT(SD0, sd0,  900000, 1400000, tps65090_rails(DCDC3), 1, 1, 0,
358                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
359
360 MAX77663_PDATA_INIT(SD1, sd1,  1200000, 1200000, tps65090_rails(DCDC3), 1, 1, 1,
361                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
362
363 MAX77663_PDATA_INIT(SD2, sd2,  1800000, 1800000, tps65090_rails(DCDC3), 1, 1, 1,
364                     FPS_SRC_0, -1, -1, 0);
365
366 MAX77663_PDATA_INIT(SD3, sd3,  2850000, 2850000, tps65090_rails(DCDC3), 1, 1, 1,
367                     FPS_SRC_NONE, -1, -1, 0);
368
369 MAX77663_PDATA_INIT(LDO0, ldo0, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
370                     FPS_SRC_1, -1, -1, 0);
371
372 MAX77663_PDATA_INIT(LDO1, ldo1, 1050000, 1050000, max77663_rails(sd2), 0, 0, 1,
373                     FPS_SRC_NONE, -1, -1, 0);
374
375 MAX77663_PDATA_INIT(LDO2, ldo2, 2850000, 2850000, tps65090_rails(DCDC2), 1, 1,
376                     1, FPS_SRC_1, -1, -1, 0);
377
378 MAX77663_PDATA_INIT(LDO3, ldo3, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
379                     FPS_SRC_NONE, -1, -1, 0);
380
381 MAX77663_PDATA_INIT(LDO4, ldo4, 1100000, 1100000, tps65090_rails(DCDC2), 1, 1,
382                     1, FPS_SRC_NONE, -1, -1, 0);
383
384 MAX77663_PDATA_INIT(LDO5, ldo5, 1200000, 1200000, max77663_rails(sd2), 0, 1, 1,
385                     FPS_SRC_NONE, -1, -1, 0);
386
387 MAX77663_PDATA_INIT(LDO6, ldo6, 1800000, 3300000, tps65090_rails(DCDC2), 0, 0, 0,
388                     FPS_SRC_NONE, -1, -1, 0);
389
390 MAX77663_PDATA_INIT(LDO7, ldo7, 2800000, 2800000, tps65090_rails(DCDC2), 0, 0, 1,
391                     FPS_SRC_NONE, -1, -1, 0);
392
393 MAX77663_PDATA_INIT(LDO8, ldo8, 2800000, 2800000, tps65090_rails(DCDC2), 0, 1, 1,
394                     FPS_SRC_1, -1, -1, 0);
395
396 #define MAX77663_REG(_id, _data) (&max77663_regulator_pdata_##_data)
397
398 static struct max77663_regulator_platform_data *max77663_reg_pdata[] = {
399         MAX77663_REG(SD0, sd0),
400         MAX77663_REG(SD1, sd1),
401         MAX77663_REG(SD2, sd2),
402         MAX77663_REG(SD3, sd3),
403         MAX77663_REG(LDO0, ldo0),
404         MAX77663_REG(LDO1, ldo1),
405         MAX77663_REG(LDO2, ldo2),
406         MAX77663_REG(LDO3, ldo3),
407         MAX77663_REG(LDO4, ldo4),
408         MAX77663_REG(LDO5, ldo5),
409         MAX77663_REG(LDO6, ldo6),
410         MAX77663_REG(LDO7, ldo7),
411         MAX77663_REG(LDO8, ldo8),
412 };
413
414 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
415         {
416                 .gpio = MAX77663_GPIO0,
417                 .dir = GPIO_DIR_OUT,
418                 .dout = GPIO_DOUT_LOW,
419                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
420                 .alternate = GPIO_ALT_DISABLE,
421         },
422         {
423                 .gpio = MAX77663_GPIO1,
424                 .dir = GPIO_DIR_IN,
425                 .dout = GPIO_DOUT_HIGH,
426                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
427                 .pull_up = GPIO_PU_ENABLE,
428                 .alternate = GPIO_ALT_DISABLE,
429         },
430         {
431                 .gpio = MAX77663_GPIO2,
432                 .dir = GPIO_DIR_OUT,
433                 .dout = GPIO_DOUT_HIGH,
434                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
435                 .pull_up = GPIO_PU_ENABLE,
436                 .alternate = GPIO_ALT_DISABLE,
437         },
438         {
439                 .gpio = MAX77663_GPIO3,
440                 .dir = GPIO_DIR_OUT,
441                 .dout = GPIO_DOUT_HIGH,
442                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
443                 .pull_up = GPIO_PU_ENABLE,
444                 .alternate = GPIO_ALT_DISABLE,
445         },
446         {
447                 .gpio = MAX77663_GPIO4,
448                 .dir = GPIO_DIR_OUT,
449                 .dout = GPIO_DOUT_HIGH,
450                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
451                 .alternate = GPIO_ALT_ENABLE,
452         },
453         {
454                 .gpio = MAX77663_GPIO5,
455                 .dir = GPIO_DIR_OUT,
456                 .dout = GPIO_DOUT_LOW,
457                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
458                 .alternate = GPIO_ALT_DISABLE,
459         },
460         {
461                 .gpio = MAX77663_GPIO6,
462                 .dir = GPIO_DIR_OUT,
463                 .dout = GPIO_DOUT_LOW,
464                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
465                 .alternate = GPIO_ALT_DISABLE,
466         },
467         {
468                 .gpio = MAX77663_GPIO7,
469                 .dir = GPIO_DIR_OUT,
470                 .dout = GPIO_DOUT_LOW,
471                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
472                 .alternate = GPIO_ALT_DISABLE,
473         },
474 };
475
476 static struct max77663_platform_data max77663_pdata = {
477         .irq_base       = MAX77663_IRQ_BASE,
478         .gpio_base      = MAX77663_GPIO_BASE,
479
480         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
481         .gpio_cfgs      = max77663_gpio_cfgs,
482
483         .regulator_pdata = max77663_reg_pdata,
484         .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata),
485
486         .rtc_i2c_addr   = 0x68,
487
488         .use_power_off  = false,
489 };
490
491 static struct i2c_board_info __initdata max77663_regulators[] = {
492         {
493                 /* The I2C address was determined by OTP factory setting */
494                 I2C_BOARD_INFO("max77663", 0x3c),
495                 .irq            = INT_EXTERNAL_PMU,
496                 .platform_data  = &max77663_pdata,
497         },
498 };
499
500 static struct i2c_board_info __initdata tps65090_regulators[] = {
501         {
502                 I2C_BOARD_INFO("tps65090", 0x48),
503                 .platform_data  = &tps65090_pdata,
504         },
505 };
506
507 /* TPS51632 DC-DC converter */
508 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
509         REGULATOR_SUPPLY("vdd_cpu", NULL),
510 };
511
512 static struct regulator_init_data tps51632_init_data = {
513         .constraints = {                                                \
514                 .min_uV = 500000,                                       \
515                 .max_uV = 1520000,                                      \
516                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
517                                         REGULATOR_MODE_STANDBY),        \
518                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
519                                         REGULATOR_CHANGE_STATUS |       \
520                                         REGULATOR_CHANGE_VOLTAGE),      \
521                 .always_on = 1,                                         \
522                 .boot_on =  1,                                          \
523                 .apply_uV = 0,                                          \
524         },                                                              \
525         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
526                 .consumer_supplies = tps51632_dcdc_supply,              \
527 };
528
529 static struct tps51632_regulator_platform_data tps51632_pdata = {
530         .reg_init_data = &tps51632_init_data,           \
531         .enable_pwm = false,                            \
532         .max_voltage_uV = 1520000,                      \
533         .base_voltage_uV = 500000,                      \
534         .slew_rate_uv_per_us = 6000,                    \
535 };
536
537 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
538         {
539                 I2C_BOARD_INFO("tps51632", 0x43),
540                 .platform_data  = &tps51632_pdata,
541         },
542 };
543
544 /************************ Palmas based regulator ****************/
545 static struct regulator_consumer_supply palmas_smps12_supply[] = {
546         REGULATOR_SUPPLY("vddio_ddr3l", NULL),
547         REGULATOR_SUPPLY("vcore_ddr3l", NULL),
548         REGULATOR_SUPPLY("vref2_ddr3l", NULL),
549 };
550
551 #define palmas_smps3_supply max77663_sd2_supply
552 #define palmas_smps45_supply max77663_sd0_supply
553 #define palmas_smps457_supply max77663_sd0_supply
554
555 static struct regulator_consumer_supply palmas_smps8_supply[] = {
556         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
557         REGULATOR_SUPPLY("avdd_pllm", NULL),
558         REGULATOR_SUPPLY("avdd_pllu", NULL),
559         REGULATOR_SUPPLY("avdd_pllx", NULL),
560         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
561         REGULATOR_SUPPLY("avdd_plle", NULL),
562         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
563         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
564         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
565         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
566         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
567         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
568
569 };
570
571 static struct regulator_consumer_supply palmas_smps9_supply[] = {
572         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
573 };
574
575 #define palmas_ldo1_supply max77663_ldo7_supply
576 #define palmas_ldo2_supply max77663_ldo8_supply
577 #define palmas_ldo3_supply max77663_ldo5_supply
578
579 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
580         REGULATOR_SUPPLY("vpp_fuse", NULL),
581 };
582
583 #define palmas_ldo6_supply max77663_ldo2_supply
584
585 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
586         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
587         REGULATOR_SUPPLY("vdd", "2-000e"),
588 };
589
590 #define palmas_ldo8_supply max77663_ldo4_supply
591 #define palmas_ldo9_supply max77663_ldo6_supply
592
593 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
594         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
595 };
596
597 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
598         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
599         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
600         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
601         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
602         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
603 };
604
605 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
606         _boot_on, _apply_uv)                                            \
607         static struct regulator_init_data reg_idata_##_name = {         \
608                 .constraints = {                                        \
609                         .name = palmas_rails(_name),                    \
610                         .min_uV = (_minmv)*1000,                        \
611                         .max_uV = (_maxmv)*1000,                        \
612                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
613                                         REGULATOR_MODE_STANDBY),        \
614                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
615                                         REGULATOR_CHANGE_STATUS |       \
616                                         REGULATOR_CHANGE_VOLTAGE),      \
617                         .always_on = _always_on,                        \
618                         .boot_on = _boot_on,                            \
619                         .apply_uV = _apply_uv,                          \
620                 },                                                      \
621                 .num_consumer_supplies =                                \
622                         ARRAY_SIZE(palmas_##_name##_supply),            \
623                 .consumer_supplies = palmas_##_name##_supply,           \
624                 .supply_regulator = _supply_reg,                        \
625         }
626
627 PALMAS_PDATA_INIT(smps12, 1350,  1350, tps65090_rails(DCDC3), 0, 0, 0);
628 PALMAS_PDATA_INIT(smps3, 1800,  1800, tps65090_rails(DCDC3), 0, 0, 0);
629 PALMAS_PDATA_INIT(smps45, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0);
630 PALMAS_PDATA_INIT(smps457, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0);
631 PALMAS_PDATA_INIT(smps8, 1050,  1050, tps65090_rails(DCDC2), 0, 1, 1);
632 PALMAS_PDATA_INIT(smps9, 2800,  2800, tps65090_rails(DCDC2), 1, 0, 0);
633 PALMAS_PDATA_INIT(ldo1, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
634 PALMAS_PDATA_INIT(ldo2, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
635 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps3), 0, 0, 1);
636 PALMAS_PDATA_INIT(ldo4, 1800,  1800, tps65090_rails(DCDC2), 0, 0, 0);
637 PALMAS_PDATA_INIT(ldo6, 2850,  2850, tps65090_rails(DCDC2), 0, 0, 1);
638 PALMAS_PDATA_INIT(ldo7, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
639 PALMAS_PDATA_INIT(ldo8, 900,  900, tps65090_rails(DCDC3), 1, 1, 1);
640 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
641 PALMAS_PDATA_INIT(ldoln, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1);
642 PALMAS_PDATA_INIT(ldousb, 3300,  3300, tps65090_rails(DCDC1), 0, 0, 1);
643
644 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
645
646 static struct regulator_init_data *dalmore_e1611_reg_data[PALMAS_NUM_REGS] = {
647         PALMAS_REG_PDATA(smps12),
648         NULL,
649         PALMAS_REG_PDATA(smps3),
650         PALMAS_REG_PDATA(smps45),
651         PALMAS_REG_PDATA(smps457),
652         NULL,
653         NULL,
654         PALMAS_REG_PDATA(smps8),
655         PALMAS_REG_PDATA(smps9),
656         NULL,
657         PALMAS_REG_PDATA(ldo1),
658         PALMAS_REG_PDATA(ldo2),
659         PALMAS_REG_PDATA(ldo3),
660         PALMAS_REG_PDATA(ldo4),
661         NULL,
662         PALMAS_REG_PDATA(ldo6),
663         PALMAS_REG_PDATA(ldo7),
664         PALMAS_REG_PDATA(ldo8),
665         PALMAS_REG_PDATA(ldo9),
666         PALMAS_REG_PDATA(ldoln),
667         PALMAS_REG_PDATA(ldousb),
668         NULL,
669         NULL,
670         NULL,
671         NULL,
672         NULL,
673 };
674
675 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
676                 _tstep, _vsel)                                          \
677         static struct palmas_reg_init reg_init_data_##_name = {         \
678                 .warm_reset = _warm_reset,                              \
679                 .roof_floor =   _roof_floor,                            \
680                 .mode_sleep = _mode_sleep,                              \
681                 .tstep = _tstep,                                        \
682                 .vsel = _vsel,                                          \
683         }
684
685 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
686 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
687 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
688 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
689 PALMAS_REG_INIT(smps457, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
690 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
691 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
692 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
693 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
694 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
695 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
696 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
697 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
698 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
699 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
700 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
701 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
702 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
703 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
704 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
705 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
706 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
707 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
708 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
709 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
710 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
711
712 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
713 static struct palmas_reg_init *dalmore_e1611_reg_init[PALMAS_NUM_REGS] = {
714         PALMAS_REG_INIT_DATA(smps12),
715         PALMAS_REG_INIT_DATA(smps123),
716         PALMAS_REG_INIT_DATA(smps3),
717         PALMAS_REG_INIT_DATA(smps45),
718         PALMAS_REG_INIT_DATA(smps457),
719         PALMAS_REG_INIT_DATA(smps6),
720         PALMAS_REG_INIT_DATA(smps7),
721         PALMAS_REG_INIT_DATA(smps8),
722         PALMAS_REG_INIT_DATA(smps9),
723         PALMAS_REG_INIT_DATA(smps10),
724         PALMAS_REG_INIT_DATA(ldo1),
725         PALMAS_REG_INIT_DATA(ldo2),
726         PALMAS_REG_INIT_DATA(ldo3),
727         PALMAS_REG_INIT_DATA(ldo4),
728         PALMAS_REG_INIT_DATA(ldo5),
729         PALMAS_REG_INIT_DATA(ldo6),
730         PALMAS_REG_INIT_DATA(ldo7),
731         PALMAS_REG_INIT_DATA(ldo8),
732         PALMAS_REG_INIT_DATA(ldo9),
733         PALMAS_REG_INIT_DATA(ldoln),
734         PALMAS_REG_INIT_DATA(ldousb),
735         PALMAS_REG_INIT_DATA(regen1),
736         PALMAS_REG_INIT_DATA(regen2),
737         PALMAS_REG_INIT_DATA(regen3),
738         PALMAS_REG_INIT_DATA(sysen1),
739         PALMAS_REG_INIT_DATA(sysen2),
740 };
741
742 static struct palmas_pmic_platform_data pmic_platform = {
743         .enable_ldo8_tracking = true,
744         .disabe_ldo8_tracking_suspend = true,
745 };
746
747 static struct palmas_platform_data palmas_pdata = {
748         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
749         .irq_base = PALMAS_TEGRA_IRQ_BASE,
750         .pmic_pdata = &pmic_platform,
751         .mux_from_pdata = true,
752         .pad1 = 0,
753         .pad2 = 0,
754         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
755         .use_power_off = true,
756 };
757
758 static struct i2c_board_info palma_device[] = {
759         {
760                 I2C_BOARD_INFO("tps65913", 0x58),
761                 .irq            = INT_EXTERNAL_PMU,
762                 .platform_data  = &palmas_pdata,
763         },
764 };
765
766 /* EN_AVDD_USB_HDMI From PMU GP1 */
767 static struct regulator_consumer_supply fixed_reg_avdd_usb_hdmi_supply[] = {
768         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
769         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
770         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
771         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
772         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
773         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
774 };
775
776 /* EN_CAM_1v8 From PMU GP5 */
777 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
778         REGULATOR_SUPPLY("dvdd_cam", NULL),
779         REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
780         REGULATOR_SUPPLY("vi2c", "2-0030"),
781         REGULATOR_SUPPLY("vif", "2-0036"),
782         REGULATOR_SUPPLY("dovdd", "2-0010"),
783         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
784 };
785
786 /* EN_CAM_1v8 on e1611 From PMU GP6 */
787 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_e1611_supply[] = {
788         REGULATOR_SUPPLY("dvdd_cam", NULL),
789         REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
790         REGULATOR_SUPPLY("vi2c", "2-0030"),
791         REGULATOR_SUPPLY("vif", "2-0036"),
792         REGULATOR_SUPPLY("dovdd", "2-0010"),
793         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
794 };
795
796 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
797         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
798 };
799
800 /* EN_USB1_VBUS From TEGRA GPIO PN4 PR3(T30) */
801 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
802         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
803 };
804
805 /* EN_3V3_FUSE From TEGRA GPIO PX4 */
806 static struct regulator_consumer_supply fixed_reg_vpp_fuse_supply[] = {
807         REGULATOR_SUPPLY("vpp_fuse", NULL),
808 };
809
810 /* EN_USB3_VBUS From TEGRA GPIO PM5 */
811 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
812         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
813 };
814
815 /* EN_1V8_TS From TEGRA_GPIO_PH5 */
816 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
817         REGULATOR_SUPPLY("dvdd", "spi3.2"),
818 };
819
820 /* Macro for defining fixed regulator sub device data */
821 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
822 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
823         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
824         static struct regulator_init_data ri_data_##_var =              \
825         {                                                               \
826                 .supply_regulator = _in_supply,                         \
827                 .num_consumer_supplies =                                \
828                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
829                 .consumer_supplies = fixed_reg_##_name##_supply,        \
830                 .constraints = {                                        \
831                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
832                                         REGULATOR_MODE_STANDBY),        \
833                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
834                                         REGULATOR_CHANGE_STATUS |       \
835                                         REGULATOR_CHANGE_VOLTAGE),      \
836                         .always_on = _always_on,                        \
837                         .boot_on = _boot_on,                            \
838                 },                                                      \
839         };                                                              \
840         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
841         {                                                               \
842                 .supply_name = FIXED_SUPPLY(_name),                     \
843                 .microvolts = _millivolts * 1000,                       \
844                 .gpio = _gpio_nr,                                       \
845                 .gpio_is_open_drain = _open_drain,                      \
846                 .enable_high = _active_high,                            \
847                 .enabled_at_boot = _boot_state,                         \
848                 .init_data = &ri_data_##_var,                           \
849         };                                                              \
850         static struct platform_device fixed_reg_##_var##_dev = {        \
851                 .name = "reg-fixed-voltage",                            \
852                 .id = _id,                                              \
853                 .dev = {                                                \
854                         .platform_data = &fixed_reg_##_var##_pdata,     \
855                 },                                                      \
856         }
857
858 FIXED_REG(1,    avdd_usb_hdmi,  avdd_usb_hdmi,
859         tps65090_rails(DCDC2),  0,      0,
860         MAX77663_GPIO_BASE + MAX77663_GPIO1,    true,   true,   1,      3300);
861
862 FIXED_REG(2,    en_1v8_cam,     en_1v8_cam,
863         max77663_rails(sd2),    0,      0,
864         MAX77663_GPIO_BASE + MAX77663_GPIO5,    false,  true,   0,      1800);
865
866 FIXED_REG(3,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
867         tps65090_rails(DCDC1),  0,      0,
868         TEGRA_GPIO_PK1, false,  true,   0,      5000);
869
870 FIXED_REG(4,    vpp_fuse,       vpp_fuse,
871         max77663_rails(sd2),    0,      0,
872         TEGRA_GPIO_PX4, false,  true,   0,      3300);
873
874 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
875 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
876         tps65090_rails(DCDC1),  0,      0,
877         TEGRA_GPIO_PN4, true,   true,   0,      5000);
878 #else
879 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
880         tps65090_rails(DCDC1),  0,      0,
881         TEGRA_GPIO_PR3, true,   true,   0,      5000);
882 #endif
883
884 FIXED_REG(6,    usb3_vbus,      usb3_vbus,
885         tps65090_rails(DCDC1),  0,      0,
886         TEGRA_GPIO_PK6, true,   true,   0,      5000);
887
888 FIXED_REG(7,    en_1v8_cam_e1611,       en_1v8_cam_e1611,
889         palmas_rails(smps3),    0,      0,
890         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
891
892 FIXED_REG(8,    dvdd_ts,        dvdd_ts,
893         palmas_rails(smps3),    0,      0,
894         TEGRA_GPIO_PH5, false,  false,  1,      1800);
895 /*
896  * Creating the fixed regulator device tables
897  */
898
899 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
900
901 #define DALMORE_COMMON_FIXED_REG                \
902         ADD_FIXED_REG(usb1_vbus),               \
903         ADD_FIXED_REG(usb3_vbus),               \
904         ADD_FIXED_REG(vdd_hdmi_5v0),
905
906 #define E1612_FIXED_REG                         \
907         ADD_FIXED_REG(avdd_usb_hdmi),           \
908         ADD_FIXED_REG(en_1v8_cam),              \
909         ADD_FIXED_REG(vpp_fuse),                \
910
911 #define E1611_FIXED_REG                         \
912         ADD_FIXED_REG(en_1v8_cam_e1611), \
913         ADD_FIXED_REG(dvdd_ts),
914
915 /* Gpio switch regulator platform data for Dalmore E1611 */
916 static struct platform_device *fixed_reg_devs_e1611_a00[] = {
917         DALMORE_COMMON_FIXED_REG
918         E1611_FIXED_REG
919 };
920
921 /* Gpio switch regulator platform data for Dalmore E1612 */
922 static struct platform_device *fixed_reg_devs_e1612_a00[] = {
923         DALMORE_COMMON_FIXED_REG
924         E1612_FIXED_REG
925 };
926
927 int __init dalmore_palmas_regulator_init(void)
928 {
929         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
930         u32 pmc_ctrl;
931         int i;
932 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
933         int ret;
934
935         ret = gpio_request(TEGRA_GPIO_PCC3, "pmic_nreswarm");
936         if (ret < 0)
937                 pr_err("%s: gpio_request failed for gpio %d\n",
938                                 __func__, TEGRA_GPIO_PCC3);
939         else
940                 gpio_direction_output(TEGRA_GPIO_PCC3, 1);
941 #endif
942         /* TPS65913: Normal state of INT request line is LOW.
943          * configure the power management controller to trigger PMU
944          * interrupts when HIGH.
945          */
946         pmc_ctrl = readl(pmc + PMC_CTRL);
947         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
948         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
949                 pmic_platform.reg_data[i] = dalmore_e1611_reg_data[i];
950                 pmic_platform.reg_init[i] = dalmore_e1611_reg_init[i];
951         }
952
953         i2c_register_board_info(4, palma_device,
954                         ARRAY_SIZE(palma_device));
955         return 0;
956 }
957
958 static int ac_online(void)
959 {
960         return 1;
961 }
962
963 static struct resource dalmore_pda_resources[] = {
964         [0] = {
965                 .name   = "ac",
966         },
967 };
968
969 static struct pda_power_pdata dalmore_pda_data = {
970         .is_ac_online   = ac_online,
971 };
972
973 static struct platform_device dalmore_pda_power_device = {
974         .name           = "pda-power",
975         .id             = -1,
976         .resource       = dalmore_pda_resources,
977         .num_resources  = ARRAY_SIZE(dalmore_pda_resources),
978         .dev    = {
979                 .platform_data  = &dalmore_pda_data,
980         },
981 };
982
983 static struct tegra_suspend_platform_data dalmore_suspend_data = {
984         .cpu_timer      = 300,
985         .cpu_off_timer  = 300,
986         .suspend_mode   = TEGRA_SUSPEND_LP0,
987         .core_timer     = 0x157e,
988         .core_off_timer = 2000,
989         .corereq_high   = true,
990         .sysclkreq_high = true,
991         .min_residency_noncpu = 600,
992         .min_residency_crail = 1000,
993 };
994 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
995 /* board parameters for cpu dfll */
996 static struct tegra_cl_dvfs_cfg_param dalmore_cl_dvfs_param = {
997         .sample_rate = 12500,
998
999         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
1000         .cf = 10,
1001         .ci = 0,
1002         .cg = 2,
1003
1004         .droop_cut_value = 0xF,
1005         .droop_restore_ramp = 0x0,
1006         .scale_out_ramp = 0x0,
1007 };
1008 #endif
1009
1010 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
1011 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
1012 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
1013 static inline void fill_reg_map(void)
1014 {
1015         int i;
1016         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
1017                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
1018                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
1019         }
1020 }
1021
1022 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1023 static struct tegra_cl_dvfs_platform_data dalmore_cl_dvfs_data = {
1024         .dfll_clk_name = "dfll_cpu",
1025         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
1026         .u.pmu_i2c = {
1027                 .fs_rate = 400000,
1028                 .slave_addr = 0x86,
1029                 .reg = 0x00,
1030         },
1031         .vdd_map = pmu_cpu_vdd_map,
1032         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
1033
1034         .cfg_param = &dalmore_cl_dvfs_param,
1035 };
1036
1037 static int __init dalmore_cl_dvfs_init(void)
1038 {
1039         fill_reg_map();
1040         tegra_cl_dvfs_device.dev.platform_data = &dalmore_cl_dvfs_data;
1041         platform_device_register(&tegra_cl_dvfs_device);
1042
1043         return 0;
1044 }
1045 #endif
1046
1047 static int __init dalmore_max77663_regulator_init(void)
1048 {
1049         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
1050         u32 pmc_ctrl;
1051
1052         /* configure the power management controller to trigger PMU
1053          * interrupts when low */
1054         pmc_ctrl = readl(pmc + PMC_CTRL);
1055         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
1056
1057         i2c_register_board_info(4, max77663_regulators,
1058                                 ARRAY_SIZE(max77663_regulators));
1059
1060         return 0;
1061 }
1062
1063 static struct regulator_bulk_data dalmore_gps_regulator_supply[] = {
1064         [0] = {
1065                 .supply = "vdd_gps_3v3",
1066         },
1067         [1] = {
1068                 .supply = "vdd_gps_1v8",
1069         },
1070 };
1071
1072 static struct regulator_userspace_consumer_data dalmore_gps_regulator_pdata = {
1073         .num_supplies   = ARRAY_SIZE(dalmore_gps_regulator_supply),
1074         .supplies       = dalmore_gps_regulator_supply,
1075 };
1076
1077 static struct platform_device dalmore_gps_regulator_device = {
1078         .name   = "reg-userspace-consumer",
1079         .id     = 2,
1080         .dev    = {
1081                         .platform_data = &dalmore_gps_regulator_pdata,
1082         },
1083 };
1084
1085 static struct regulator_bulk_data dalmore_bt_regulator_supply[] = {
1086         [0] = {
1087                 .supply = "vdd_bt_3v3",
1088         },
1089         [1] = {
1090                 .supply = "vddio_bt_1v8",
1091         },
1092 };
1093
1094 static struct regulator_userspace_consumer_data dalmore_bt_regulator_pdata = {
1095         .num_supplies   = ARRAY_SIZE(dalmore_bt_regulator_supply),
1096         .supplies       = dalmore_bt_regulator_supply,
1097 };
1098
1099 static struct platform_device dalmore_bt_regulator_device = {
1100         .name   = "reg-userspace-consumer",
1101         .id     = 1,
1102         .dev    = {
1103                         .platform_data = &dalmore_bt_regulator_pdata,
1104         },
1105 };
1106
1107 static int __init dalmore_fixed_regulator_init(void)
1108 {
1109         struct board_info board_info;
1110
1111         if (!machine_is_dalmore())
1112                 return 0;
1113
1114         tegra_get_board_info(&board_info);
1115
1116         if (board_info.board_id == BOARD_E1611 ||
1117                 board_info.board_id == BOARD_P2454)
1118                 return platform_add_devices(fixed_reg_devs_e1611_a00,
1119                                 ARRAY_SIZE(fixed_reg_devs_e1611_a00));
1120         else
1121                 return platform_add_devices(fixed_reg_devs_e1612_a00,
1122                                 ARRAY_SIZE(fixed_reg_devs_e1612_a00));
1123 }
1124 subsys_initcall_sync(dalmore_fixed_regulator_init);
1125
1126 static void dalmore_tps65090_init(void)
1127 {
1128         int err;
1129
1130         err = gpio_request(TPS65090_CHARGER_INT, "CHARGER_INT");
1131         if (err < 0) {
1132                 pr_err("%s: gpio_request failed %d\n", __func__, err);
1133                 goto fail_init_irq;
1134         }
1135
1136         err = gpio_direction_input(TPS65090_CHARGER_INT);
1137         if (err < 0) {
1138                 pr_err("%s: gpio_direction_input failed %d\n", __func__, err);
1139                 goto fail_init_irq;
1140         }
1141
1142         tps65090_regulators[0].irq = gpio_to_irq(TPS65090_CHARGER_INT);
1143 fail_init_irq:
1144         i2c_register_board_info(4, tps65090_regulators,
1145                         ARRAY_SIZE(tps65090_regulators));
1146         return;
1147 }
1148
1149 int __init dalmore_regulator_init(void)
1150 {
1151         struct board_info board_info;
1152
1153         dalmore_tps65090_init();
1154 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1155         dalmore_cl_dvfs_init();
1156 #endif
1157         tegra_get_board_info(&board_info);
1158         if (board_info.board_id == BOARD_E1611 ||
1159                 board_info.board_id == BOARD_P2454)
1160                 dalmore_palmas_regulator_init();
1161         else
1162                 dalmore_max77663_regulator_init();
1163
1164         i2c_register_board_info(4, tps51632_boardinfo, 1);
1165         platform_device_register(&dalmore_pda_power_device);
1166         platform_device_register(&dalmore_bt_regulator_device);
1167         platform_device_register(&dalmore_gps_regulator_device);
1168         return 0;
1169 }
1170
1171 int __init dalmore_suspend_init(void)
1172 {
1173         tegra_init_suspend(&dalmore_suspend_data);
1174         return 0;
1175 }
1176
1177 int __init dalmore_edp_init(void)
1178 {
1179         unsigned int regulator_mA;
1180
1181         regulator_mA = get_maximum_cpu_current_supported();
1182         if (!regulator_mA)
1183                 regulator_mA = 15000;
1184
1185         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1186         tegra_init_cpu_edp_limits(regulator_mA);
1187
1188         regulator_mA = get_maximum_core_current_supported();
1189         if (!regulator_mA)
1190                 regulator_mA = 4000;
1191
1192         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
1193         tegra_init_core_edp_limits(regulator_mA);
1194
1195         return 0;
1196 }
1197
1198 static struct soctherm_platform_data dalmore_soctherm_data = {
1199         .soctherm_clk_rate = 136000000,
1200         .tsensor_clk_rate = 500000,
1201         .sensor_data = {
1202                 [TSENSE_CPU0] = {
1203                         .enable = true,
1204                         .tall = 16300,
1205                         .tiddq = 1,
1206                         .ten_count = 1,
1207                         .tsample = 163,
1208                         .pdiv = 10,
1209                 },
1210                 [TSENSE_CPU1] = {
1211                         .enable = true,
1212                         .tall = 16300,
1213                         .tiddq = 1,
1214                         .ten_count = 1,
1215                         .tsample = 163,
1216                         .pdiv = 10,
1217                 },
1218                 [TSENSE_CPU2] = {
1219                         .enable = true,
1220                         .tall = 16300,
1221                         .tiddq = 1,
1222                         .ten_count = 1,
1223                         .tsample = 163,
1224                         .pdiv = 10,
1225                 },
1226                 [TSENSE_CPU3] = {
1227                         .enable = true,
1228                         .tall = 16300,
1229                         .tiddq = 1,
1230                         .ten_count = 1,
1231                         .tsample = 163,
1232                         .pdiv = 10,
1233                 },
1234                 /* MEM0/MEM1 won't be used */
1235                 [TSENSE_MEM0] = {
1236                         .enable = false,
1237                 },
1238                 [TSENSE_MEM1] = {
1239                         .enable = false,
1240                 },
1241                 [TSENSE_GPU] = {
1242                         .enable = true,
1243                         .tall = 16300,
1244                         .tiddq = 1,
1245                         .ten_count = 1,
1246                         .tsample = 163,
1247                         .pdiv = 10,
1248                 },
1249                 [TSENSE_PLLX] = {
1250                         .enable = true,
1251                         .tall = 16300,
1252                         .tiddq = 1,
1253                         .ten_count = 1,
1254                         .tsample = 163,
1255                         .pdiv = 10,
1256                 },
1257         },
1258 };
1259
1260 int __init dalmore_soctherm_init(void)
1261 {
1262         return tegra11_soctherm_init(&dalmore_soctherm_data);
1263 }