ARM: tegra11: dalmore: Add core EDP limits initialization
[linux-3.10.git] / arch / arm / mach-tegra / board-dalmore-power.c
1 /*
2  * arch/arm/mach-tegra/board-dalmore-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/max77663-core.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/mfd/tps65090.h>
31 #include <linux/regulator/max77663-regulator.h>
32 #include <linux/regulator/tps65090-regulator.h>
33 #include <linux/regulator/tps51632-regulator.h>
34 #include <linux/gpio.h>
35 #include <linux/interrupt.h>
36 #include <linux/regulator/userspace-consumer.h>
37
38 #include <asm/mach-types.h>
39
40 #include <mach/iomap.h>
41 #include <mach/irqs.h>
42 #include <mach/edp.h>
43 #include <mach/gpio-tegra.h>
44
45 #include "cpu-tegra.h"
46 #include "pm.h"
47 #include "tegra-board-id.h"
48 #include "board.h"
49 #include "gpio-names.h"
50 #include "board-dalmore.h"
51 #include "tegra_cl_dvfs.h"
52 #include "devices.h"
53 #include "tegra11_soctherm.h"
54
55 #define PMC_CTRL                0x0
56 #define PMC_CTRL_INTR_LOW       (1 << 17)
57 #define TPS65090_CHARGER_INT    TEGRA_GPIO_PJ0
58 /*TPS65090 consumer rails */
59 static struct regulator_consumer_supply tps65090_dcdc1_supply[] = {
60         REGULATOR_SUPPLY("vdd_sys_5v0", NULL),
61         REGULATOR_SUPPLY("vdd_spk", NULL),
62         REGULATOR_SUPPLY("vdd_sys_modem_5v0", NULL),
63         REGULATOR_SUPPLY("vdd_sys_cam_5v0", NULL),
64 };
65
66 static struct regulator_consumer_supply tps65090_dcdc2_supply[] = {
67         REGULATOR_SUPPLY("vdd_sys_3v3", NULL),
68         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
69         REGULATOR_SUPPLY("pwrdet_hv", NULL),
70         REGULATOR_SUPPLY("vdd_sys_ds_3v3", NULL),
71         REGULATOR_SUPPLY("vdd_sys_nfc_3v3", NULL),
72         REGULATOR_SUPPLY("vdd_hv_nfc_3v3", NULL),
73         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
74         REGULATOR_SUPPLY("vdd_sys_sensor_3v3", NULL),
75         REGULATOR_SUPPLY("vdd_sys_audio_3v3", NULL),
76         REGULATOR_SUPPLY("vdd_sys_dtv_3v3", NULL),
77         REGULATOR_SUPPLY("vcc", "0-007c"),
78         REGULATOR_SUPPLY("vcc", "0-0030"),
79         REGULATOR_SUPPLY("vin", "2-0030"),
80 };
81
82 static struct regulator_consumer_supply tps65090_dcdc3_supply[] = {
83         REGULATOR_SUPPLY("vdd_ao", NULL),
84 };
85
86 static struct regulator_consumer_supply tps65090_ldo1_supply[] = {
87         REGULATOR_SUPPLY("vdd_sby_5v0", NULL),
88 };
89
90 static struct regulator_consumer_supply tps65090_ldo2_supply[] = {
91         REGULATOR_SUPPLY("vdd_sby_3v3", NULL),
92 };
93
94 static struct regulator_consumer_supply tps65090_fet1_supply[] = {
95         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
96 };
97
98 static struct regulator_consumer_supply tps65090_fet3_supply[] = {
99         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
100 };
101
102 static struct regulator_consumer_supply tps65090_fet4_supply[] = {
103         REGULATOR_SUPPLY("avdd_lcd", NULL),
104         REGULATOR_SUPPLY("avdd", "spi3.2"),
105 };
106
107 static struct regulator_consumer_supply tps65090_fet5_supply[] = {
108         REGULATOR_SUPPLY("vdd_lvds", NULL),
109 };
110
111 static struct regulator_consumer_supply tps65090_fet6_supply[] = {
112         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
113 };
114
115 static struct regulator_consumer_supply tps65090_fet7_supply[] = {
116         REGULATOR_SUPPLY("vdd_wifi_3v3", "bcm4329_wlan.1"),
117         REGULATOR_SUPPLY("vdd_gps_3v3", "reg-userspace-consumer.2"),
118         REGULATOR_SUPPLY("vdd_bt_3v3", "reg-userspace-consumer.1"),
119 };
120
121 #define TPS65090_PDATA_INIT(_id, _name, _supply_reg,                    \
122                 _always_on, _boot_on, _apply_uV, _en_ext_ctrl, _gpio)   \
123 static struct regulator_init_data ri_data_##_name =                     \
124 {                                                                       \
125         .supply_regulator = _supply_reg,                                \
126         .constraints = {                                                \
127                 .name = tps65090_rails(_id),                            \
128                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
129                                      REGULATOR_MODE_STANDBY),           \
130                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
131                                    REGULATOR_CHANGE_STATUS |            \
132                                    REGULATOR_CHANGE_VOLTAGE),           \
133                 .always_on = _always_on,                                \
134                 .boot_on = _boot_on,                                    \
135                 .apply_uV = _apply_uV,                                  \
136         },                                                              \
137         .num_consumer_supplies =                                        \
138                 ARRAY_SIZE(tps65090_##_name##_supply),                  \
139         .consumer_supplies = tps65090_##_name##_supply,                 \
140 };                                                                      \
141 static struct tps65090_regulator_platform_data                          \
142                         tps65090_regulator_pdata_##_name =              \
143 {                                                                       \
144         .id = TPS65090_REGULATOR_##_id,                                 \
145         .enable_ext_control = _en_ext_ctrl,                             \
146         .gpio = _gpio,                                                  \
147         .reg_init_data = &ri_data_##_name ,                             \
148 }
149
150 TPS65090_PDATA_INIT(DCDC1, dcdc1, NULL, 1, 1, 0, false, -1);
151 TPS65090_PDATA_INIT(DCDC2, dcdc2, NULL, 1, 1, 0, false, -1);
152 TPS65090_PDATA_INIT(DCDC3, dcdc3, NULL, 1, 1, 0, false, -1);
153 TPS65090_PDATA_INIT(LDO1, ldo1, NULL, 1, 1, 0, false, -1);
154 TPS65090_PDATA_INIT(LDO2, ldo2, NULL, 1, 1, 0, false, -1);
155 TPS65090_PDATA_INIT(FET1, fet1, NULL, 0, 0, 0, false, -1);
156 TPS65090_PDATA_INIT(FET3, fet3, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
157 TPS65090_PDATA_INIT(FET4, fet4, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
158 TPS65090_PDATA_INIT(FET5, fet5, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
159 TPS65090_PDATA_INIT(FET6, fet6, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
160 TPS65090_PDATA_INIT(FET7, fet7, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
161
162 #define ADD_TPS65090_REG(_name) (&tps65090_regulator_pdata_##_name)
163 static struct tps65090_regulator_platform_data *tps65090_reg_pdata[] = {
164         ADD_TPS65090_REG(dcdc1),
165         ADD_TPS65090_REG(dcdc2),
166         ADD_TPS65090_REG(dcdc3),
167         ADD_TPS65090_REG(ldo1),
168         ADD_TPS65090_REG(ldo2),
169         ADD_TPS65090_REG(fet1),
170         ADD_TPS65090_REG(fet3),
171         ADD_TPS65090_REG(fet4),
172         ADD_TPS65090_REG(fet5),
173         ADD_TPS65090_REG(fet6),
174         ADD_TPS65090_REG(fet7),
175 };
176
177 static struct tps65090_platform_data tps65090_pdata = {
178         .irq_base = TPS65090_TEGRA_IRQ_BASE,
179         .irq_flag = IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
180         .num_reg_pdata =  ARRAY_SIZE(tps65090_reg_pdata),
181         .reg_pdata = tps65090_reg_pdata
182 };
183
184 /* MAX77663 consumer rails */
185 static struct regulator_consumer_supply max77663_sd0_supply[] = {
186         REGULATOR_SUPPLY("vdd_core", NULL),
187 };
188
189 static struct regulator_consumer_supply max77663_sd1_supply[] = {
190         REGULATOR_SUPPLY("vddio_ddr", NULL),
191         REGULATOR_SUPPLY("vddio_ddr0", NULL),
192         REGULATOR_SUPPLY("vddio_ddr1", NULL),
193 };
194
195 static struct regulator_consumer_supply max77663_sd2_supply[] = {
196         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
197         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
198         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
199         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
200         REGULATOR_SUPPLY("pwrdet_cam", NULL),
201         REGULATOR_SUPPLY("avdd_osc", NULL),
202         REGULATOR_SUPPLY("vddio_sys", NULL),
203         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
204         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
205         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
206         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
207         REGULATOR_SUPPLY("vdd_emmc", NULL),
208         REGULATOR_SUPPLY("vddio_audio", NULL),
209         REGULATOR_SUPPLY("pwrdet_audio", NULL),
210         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
211         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
212         REGULATOR_SUPPLY("vddio_modem", NULL),
213         REGULATOR_SUPPLY("vddio_modem_1v8", NULL),
214         REGULATOR_SUPPLY("vddio_bb", NULL),
215         REGULATOR_SUPPLY("pwrdet_bb", NULL),
216         REGULATOR_SUPPLY("vddio_bb_1v8", NULL),
217         REGULATOR_SUPPLY("vddio_uart", NULL),
218         REGULATOR_SUPPLY("pwrdet_uart", NULL),
219         REGULATOR_SUPPLY("vddio_gmi", NULL),
220         REGULATOR_SUPPLY("pwrdet_nand", NULL),
221         REGULATOR_SUPPLY("vdd_sensor_1v8", NULL),
222         REGULATOR_SUPPLY("vdd_mic_1v8", NULL),
223         REGULATOR_SUPPLY("vdd_nfc_1v8", NULL),
224         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
225         REGULATOR_SUPPLY("vdd_spi_1v8", NULL),
226         REGULATOR_SUPPLY("dvdd_lcd", NULL),
227         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
228         REGULATOR_SUPPLY("vddio_wifi_1v8", "bcm4329_wlan.1"),
229         REGULATOR_SUPPLY("vdd_gps_1v8", "reg-userspace-consumer.2"),
230         REGULATOR_SUPPLY("vddio_bt_1v8", "reg-userspace-consumer.1"),
231         REGULATOR_SUPPLY("vdd_dtv_1v8", NULL),
232         REGULATOR_SUPPLY("vlogic", "0-0069"),
233 };
234
235 static struct regulator_consumer_supply max77663_sd3_supply[] = {
236         REGULATOR_SUPPLY("vcore_emmc", NULL),
237 };
238
239 static struct regulator_consumer_supply max77663_ldo0_supply[] = {
240         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
241         REGULATOR_SUPPLY("avdd_pllx", NULL),
242         REGULATOR_SUPPLY("avdd_plle", NULL),
243         REGULATOR_SUPPLY("avdd_pllm", NULL),
244         REGULATOR_SUPPLY("avdd_pllu", NULL),
245         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
246         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
247         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
248 };
249
250 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
251         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
252 };
253
254 static struct regulator_consumer_supply max77663_ldo2_supply[] = {
255         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
256         REGULATOR_SUPPLY("vdd_als", NULL),
257         REGULATOR_SUPPLY("vdd", "0-004c"),
258         REGULATOR_SUPPLY("vdd", "0-0069"),
259 };
260
261 static struct regulator_consumer_supply max77663_ldo3_supply[] = {
262         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
263         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
264         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
265 };
266
267 static struct regulator_consumer_supply max77663_ldo4_supply[] = {
268         REGULATOR_SUPPLY("vdd_rtc", NULL),
269 };
270
271 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
272         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
273         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
274         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
275         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
276         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
277         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
278         REGULATOR_SUPPLY("vddio_bb_hsic", NULL),
279 };
280
281 static struct regulator_consumer_supply max77663_ldo6_supply[] = {
282         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
283         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
284 };
285
286 /* FIXME!! Put the device address of camera */
287 static struct regulator_consumer_supply max77663_ldo7_supply[] = {
288         REGULATOR_SUPPLY("avdd_cam1", NULL),
289         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
290         REGULATOR_SUPPLY("vana", "2-0036"),
291 };
292
293 /* FIXME!! Put the device address of camera */
294 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
295         REGULATOR_SUPPLY("avdd_cam2", NULL),
296         REGULATOR_SUPPLY("avdd", "2-0010"),
297 };
298
299 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
300         {
301                 .src = FPS_SRC_0,
302                 .en_src = FPS_EN_SRC_EN0,
303                 .time_period = FPS_TIME_PERIOD_DEF,
304         },
305         {
306                 .src = FPS_SRC_1,
307                 .en_src = FPS_EN_SRC_EN1,
308                 .time_period = FPS_TIME_PERIOD_DEF,
309         },
310         {
311                 .src = FPS_SRC_2,
312                 .en_src = FPS_EN_SRC_EN0,
313                 .time_period = FPS_TIME_PERIOD_DEF,
314         },
315 };
316
317 #define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg,   \
318                 _always_on, _boot_on, _apply_uV,                        \
319                 _fps_src, _fps_pu_period, _fps_pd_period, _flags)       \
320         static struct regulator_init_data max77663_regulator_idata_##_id = {   \
321                 .supply_regulator = _supply_reg,                        \
322                 .constraints = {                                        \
323                         .name = max77663_rails(_id),                    \
324                         .min_uV = _min_uV,                              \
325                         .max_uV = _max_uV,                              \
326                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
327                                              REGULATOR_MODE_STANDBY),   \
328                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
329                                            REGULATOR_CHANGE_STATUS |    \
330                                            REGULATOR_CHANGE_VOLTAGE),   \
331                         .always_on = _always_on,                        \
332                         .boot_on = _boot_on,                            \
333                         .apply_uV = _apply_uV,                          \
334                 },                                                      \
335                 .num_consumer_supplies =                                \
336                         ARRAY_SIZE(max77663_##_id##_supply),            \
337                 .consumer_supplies = max77663_##_id##_supply,           \
338         };                                                              \
339 static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id =\
340 {                                                                       \
341                 .reg_init_data = &max77663_regulator_idata_##_id,       \
342                 .id = MAX77663_REGULATOR_ID_##_rid,                     \
343                 .fps_src = _fps_src,                                    \
344                 .fps_pu_period = _fps_pu_period,                        \
345                 .fps_pd_period = _fps_pd_period,                        \
346                 .fps_cfgs = max77663_fps_cfgs,                          \
347                 .flags = _flags,                                        \
348         }
349
350 MAX77663_PDATA_INIT(SD0, sd0,  900000, 1400000, tps65090_rails(DCDC3), 1, 1, 0,
351                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
352
353 MAX77663_PDATA_INIT(SD1, sd1,  1200000, 1200000, tps65090_rails(DCDC3), 1, 1, 1,
354                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
355
356 MAX77663_PDATA_INIT(SD2, sd2,  1800000, 1800000, tps65090_rails(DCDC3), 1, 1, 1,
357                     FPS_SRC_0, -1, -1, 0);
358
359 MAX77663_PDATA_INIT(SD3, sd3,  2850000, 2850000, tps65090_rails(DCDC3), 1, 1, 1,
360                     FPS_SRC_NONE, -1, -1, 0);
361
362 MAX77663_PDATA_INIT(LDO0, ldo0, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
363                     FPS_SRC_1, -1, -1, 0);
364
365 MAX77663_PDATA_INIT(LDO1, ldo1, 1050000, 1050000, max77663_rails(sd2), 0, 0, 1,
366                     FPS_SRC_NONE, -1, -1, 0);
367
368 MAX77663_PDATA_INIT(LDO2, ldo2, 2850000, 2850000, tps65090_rails(DCDC2), 1, 1,
369                     1, FPS_SRC_1, -1, -1, 0);
370
371 MAX77663_PDATA_INIT(LDO3, ldo3, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
372                     FPS_SRC_NONE, -1, -1, 0);
373
374 MAX77663_PDATA_INIT(LDO4, ldo4, 1100000, 1100000, tps65090_rails(DCDC2), 1, 1,
375                     1, FPS_SRC_NONE, -1, -1, 0);
376
377 MAX77663_PDATA_INIT(LDO5, ldo5, 1200000, 1200000, max77663_rails(sd2), 0, 1, 1,
378                     FPS_SRC_NONE, -1, -1, 0);
379
380 MAX77663_PDATA_INIT(LDO6, ldo6, 1800000, 3300000, tps65090_rails(DCDC2), 0, 0, 0,
381                     FPS_SRC_NONE, -1, -1, 0);
382
383 MAX77663_PDATA_INIT(LDO7, ldo7, 2800000, 2800000, tps65090_rails(DCDC2), 0, 0, 1,
384                     FPS_SRC_NONE, -1, -1, 0);
385
386 MAX77663_PDATA_INIT(LDO8, ldo8, 2800000, 2800000, tps65090_rails(DCDC2), 0, 1, 1,
387                     FPS_SRC_1, -1, -1, 0);
388
389 #define MAX77663_REG(_id, _data) (&max77663_regulator_pdata_##_data)
390
391 static struct max77663_regulator_platform_data *max77663_reg_pdata[] = {
392         MAX77663_REG(SD0, sd0),
393         MAX77663_REG(SD1, sd1),
394         MAX77663_REG(SD2, sd2),
395         MAX77663_REG(SD3, sd3),
396         MAX77663_REG(LDO0, ldo0),
397         MAX77663_REG(LDO1, ldo1),
398         MAX77663_REG(LDO2, ldo2),
399         MAX77663_REG(LDO3, ldo3),
400         MAX77663_REG(LDO4, ldo4),
401         MAX77663_REG(LDO5, ldo5),
402         MAX77663_REG(LDO6, ldo6),
403         MAX77663_REG(LDO7, ldo7),
404         MAX77663_REG(LDO8, ldo8),
405 };
406
407 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
408         {
409                 .gpio = MAX77663_GPIO0,
410                 .dir = GPIO_DIR_OUT,
411                 .dout = GPIO_DOUT_LOW,
412                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
413                 .alternate = GPIO_ALT_DISABLE,
414         },
415         {
416                 .gpio = MAX77663_GPIO1,
417                 .dir = GPIO_DIR_IN,
418                 .dout = GPIO_DOUT_HIGH,
419                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
420                 .pull_up = GPIO_PU_ENABLE,
421                 .alternate = GPIO_ALT_DISABLE,
422         },
423         {
424                 .gpio = MAX77663_GPIO2,
425                 .dir = GPIO_DIR_OUT,
426                 .dout = GPIO_DOUT_HIGH,
427                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
428                 .pull_up = GPIO_PU_ENABLE,
429                 .alternate = GPIO_ALT_DISABLE,
430         },
431         {
432                 .gpio = MAX77663_GPIO3,
433                 .dir = GPIO_DIR_OUT,
434                 .dout = GPIO_DOUT_HIGH,
435                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
436                 .pull_up = GPIO_PU_ENABLE,
437                 .alternate = GPIO_ALT_DISABLE,
438         },
439         {
440                 .gpio = MAX77663_GPIO4,
441                 .dir = GPIO_DIR_OUT,
442                 .dout = GPIO_DOUT_HIGH,
443                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
444                 .alternate = GPIO_ALT_ENABLE,
445         },
446         {
447                 .gpio = MAX77663_GPIO5,
448                 .dir = GPIO_DIR_OUT,
449                 .dout = GPIO_DOUT_LOW,
450                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
451                 .alternate = GPIO_ALT_DISABLE,
452         },
453         {
454                 .gpio = MAX77663_GPIO6,
455                 .dir = GPIO_DIR_OUT,
456                 .dout = GPIO_DOUT_LOW,
457                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
458                 .alternate = GPIO_ALT_DISABLE,
459         },
460         {
461                 .gpio = MAX77663_GPIO7,
462                 .dir = GPIO_DIR_OUT,
463                 .dout = GPIO_DOUT_LOW,
464                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
465                 .alternate = GPIO_ALT_DISABLE,
466         },
467 };
468
469 static struct max77663_platform_data max77663_pdata = {
470         .irq_base       = MAX77663_IRQ_BASE,
471         .gpio_base      = MAX77663_GPIO_BASE,
472
473         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
474         .gpio_cfgs      = max77663_gpio_cfgs,
475
476         .regulator_pdata = max77663_reg_pdata,
477         .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata),
478
479         .rtc_i2c_addr   = 0x68,
480
481         .use_power_off  = false,
482 };
483
484 static struct i2c_board_info __initdata max77663_regulators[] = {
485         {
486                 /* The I2C address was determined by OTP factory setting */
487                 I2C_BOARD_INFO("max77663", 0x3c),
488                 .irq            = INT_EXTERNAL_PMU,
489                 .platform_data  = &max77663_pdata,
490         },
491 };
492
493 static struct i2c_board_info __initdata tps65090_regulators[] = {
494         {
495                 I2C_BOARD_INFO("tps65090", 0x48),
496                 .platform_data  = &tps65090_pdata,
497         },
498 };
499
500 /* TPS51632 DC-DC converter */
501 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
502         REGULATOR_SUPPLY("vdd_cpu", NULL),
503 };
504
505 static struct regulator_init_data tps51632_init_data = {
506         .constraints = {                                                \
507                 .min_uV = 500000,                                       \
508                 .max_uV = 1520000,                                      \
509                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
510                                         REGULATOR_MODE_STANDBY),        \
511                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
512                                         REGULATOR_CHANGE_STATUS |       \
513                                         REGULATOR_CHANGE_VOLTAGE),      \
514                 .always_on = 1,                                         \
515                 .boot_on =  1,                                          \
516                 .apply_uV = 0,                                          \
517         },                                                              \
518         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
519                 .consumer_supplies = tps51632_dcdc_supply,              \
520 };
521
522 static struct tps51632_regulator_platform_data tps51632_pdata = {
523         .reg_init_data = &tps51632_init_data,           \
524         .enable_pwm = false,                            \
525         .max_voltage_uV = 1520000,                      \
526         .base_voltage_uV = 500000,                      \
527         .slew_rate_uv_per_us = 6000,                    \
528 };
529
530 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
531         {
532                 I2C_BOARD_INFO("tps51632", 0x43),
533                 .platform_data  = &tps51632_pdata,
534         },
535 };
536
537 /************************ Palmas based regulator ****************/
538 static struct regulator_consumer_supply palmas_smps12_supply[] = {
539         REGULATOR_SUPPLY("vddio_ddr3l", NULL),
540         REGULATOR_SUPPLY("vcore_ddr3l", NULL),
541         REGULATOR_SUPPLY("vref2_ddr3l", NULL),
542 };
543
544 #define palmas_smps3_supply max77663_sd2_supply
545 #define palmas_smps45_supply max77663_sd0_supply
546 #define palmas_smps457_supply max77663_sd0_supply
547
548 static struct regulator_consumer_supply palmas_smps8_supply[] = {
549         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
550         REGULATOR_SUPPLY("avdd_pllm", NULL),
551         REGULATOR_SUPPLY("avdd_pllu", NULL),
552         REGULATOR_SUPPLY("avdd_pllx", NULL),
553         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
554         REGULATOR_SUPPLY("avdd_plle", NULL),
555         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
556         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
557         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
558         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
559         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
560         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
561
562 };
563
564 static struct regulator_consumer_supply palmas_smps9_supply[] = {
565         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
566 };
567
568 #define palmas_ldo1_supply max77663_ldo7_supply
569 #define palmas_ldo2_supply max77663_ldo8_supply
570 #define palmas_ldo3_supply max77663_ldo5_supply
571
572 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
573         REGULATOR_SUPPLY("vpp_fuse", NULL),
574 };
575
576 #define palmas_ldo6_supply max77663_ldo2_supply
577
578 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
579         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
580         REGULATOR_SUPPLY("vdd", "2-000e"),
581 };
582
583 #define palmas_ldo8_supply max77663_ldo4_supply
584 #define palmas_ldo9_supply max77663_ldo6_supply
585
586 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
587         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
588 };
589
590 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
591         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
592         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
593         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
594         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
595         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
596 };
597
598 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
599         _boot_on, _apply_uv)                                            \
600         static struct regulator_init_data reg_idata_##_name = {         \
601                 .constraints = {                                        \
602                         .name = palmas_rails(_name),                    \
603                         .min_uV = (_minmv)*1000,                        \
604                         .max_uV = (_maxmv)*1000,                        \
605                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
606                                         REGULATOR_MODE_STANDBY),        \
607                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
608                                         REGULATOR_CHANGE_STATUS |       \
609                                         REGULATOR_CHANGE_VOLTAGE),      \
610                         .always_on = _always_on,                        \
611                         .boot_on = _boot_on,                            \
612                         .apply_uV = _apply_uv,                          \
613                 },                                                      \
614                 .num_consumer_supplies =                                \
615                         ARRAY_SIZE(palmas_##_name##_supply),            \
616                 .consumer_supplies = palmas_##_name##_supply,           \
617                 .supply_regulator = _supply_reg,                        \
618         }
619
620 PALMAS_PDATA_INIT(smps12, 1350,  1350, tps65090_rails(DCDC3), 0, 0, 0);
621 PALMAS_PDATA_INIT(smps3, 1800,  1800, tps65090_rails(DCDC3), 0, 0, 0);
622 PALMAS_PDATA_INIT(smps45, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0);
623 PALMAS_PDATA_INIT(smps457, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0);
624 PALMAS_PDATA_INIT(smps8, 1050,  1050, tps65090_rails(DCDC2), 0, 1, 1);
625 PALMAS_PDATA_INIT(smps9, 2800,  2800, tps65090_rails(DCDC2), 1, 0, 0);
626 PALMAS_PDATA_INIT(ldo1, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
627 PALMAS_PDATA_INIT(ldo2, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
628 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps3), 0, 0, 1);
629 PALMAS_PDATA_INIT(ldo4, 1800,  1800, tps65090_rails(DCDC2), 0, 0, 0);
630 PALMAS_PDATA_INIT(ldo6, 2850,  2850, tps65090_rails(DCDC2), 0, 0, 1);
631 PALMAS_PDATA_INIT(ldo7, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
632 PALMAS_PDATA_INIT(ldo8, 900,  900, tps65090_rails(DCDC3), 1, 1, 1);
633 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
634 PALMAS_PDATA_INIT(ldoln, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1);
635 PALMAS_PDATA_INIT(ldousb, 3300,  3300, tps65090_rails(DCDC1), 0, 0, 1);
636
637 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
638
639 static struct regulator_init_data *dalmore_e1611_reg_data[PALMAS_NUM_REGS] = {
640         PALMAS_REG_PDATA(smps12),
641         NULL,
642         PALMAS_REG_PDATA(smps3),
643         PALMAS_REG_PDATA(smps45),
644         PALMAS_REG_PDATA(smps457),
645         NULL,
646         NULL,
647         PALMAS_REG_PDATA(smps8),
648         PALMAS_REG_PDATA(smps9),
649         NULL,
650         PALMAS_REG_PDATA(ldo1),
651         PALMAS_REG_PDATA(ldo2),
652         PALMAS_REG_PDATA(ldo3),
653         PALMAS_REG_PDATA(ldo4),
654         NULL,
655         PALMAS_REG_PDATA(ldo6),
656         PALMAS_REG_PDATA(ldo7),
657         PALMAS_REG_PDATA(ldo8),
658         PALMAS_REG_PDATA(ldo9),
659         PALMAS_REG_PDATA(ldoln),
660         PALMAS_REG_PDATA(ldousb),
661         NULL,
662         NULL,
663         NULL,
664         NULL,
665         NULL,
666 };
667
668 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
669                 _tstep, _vsel)                                          \
670         static struct palmas_reg_init reg_init_data_##_name = {         \
671                 .warm_reset = _warm_reset,                              \
672                 .roof_floor =   _roof_floor,                            \
673                 .mode_sleep = _mode_sleep,                              \
674                 .tstep = _tstep,                                        \
675                 .vsel = _vsel,                                          \
676         }
677
678 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
679 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
680 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
681 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
682 PALMAS_REG_INIT(smps457, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
683 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
684 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
685 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
686 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
687 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
688 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
689 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
690 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
691 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
692 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
693 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
694 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
695 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
696 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
697 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
698 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
699 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
700 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
701 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
702 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
703 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
704
705 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
706 static struct palmas_reg_init *dalmore_e1611_reg_init[PALMAS_NUM_REGS] = {
707         PALMAS_REG_INIT_DATA(smps12),
708         PALMAS_REG_INIT_DATA(smps123),
709         PALMAS_REG_INIT_DATA(smps3),
710         PALMAS_REG_INIT_DATA(smps45),
711         PALMAS_REG_INIT_DATA(smps457),
712         PALMAS_REG_INIT_DATA(smps6),
713         PALMAS_REG_INIT_DATA(smps7),
714         PALMAS_REG_INIT_DATA(smps8),
715         PALMAS_REG_INIT_DATA(smps9),
716         PALMAS_REG_INIT_DATA(smps10),
717         PALMAS_REG_INIT_DATA(ldo1),
718         PALMAS_REG_INIT_DATA(ldo2),
719         PALMAS_REG_INIT_DATA(ldo3),
720         PALMAS_REG_INIT_DATA(ldo4),
721         PALMAS_REG_INIT_DATA(ldo5),
722         PALMAS_REG_INIT_DATA(ldo6),
723         PALMAS_REG_INIT_DATA(ldo7),
724         PALMAS_REG_INIT_DATA(ldo8),
725         PALMAS_REG_INIT_DATA(ldo9),
726         PALMAS_REG_INIT_DATA(ldoln),
727         PALMAS_REG_INIT_DATA(ldousb),
728         PALMAS_REG_INIT_DATA(regen1),
729         PALMAS_REG_INIT_DATA(regen2),
730         PALMAS_REG_INIT_DATA(regen3),
731         PALMAS_REG_INIT_DATA(sysen1),
732         PALMAS_REG_INIT_DATA(sysen2),
733 };
734
735 static struct palmas_pmic_platform_data pmic_platform = {
736         .enable_ldo8_tracking = true,
737         .disabe_ldo8_tracking_suspend = true,
738 };
739
740 static struct palmas_platform_data palmas_pdata = {
741         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
742         .irq_base = PALMAS_TEGRA_IRQ_BASE,
743         .pmic_pdata = &pmic_platform,
744         .mux_from_pdata = true,
745         .pad1 = 0,
746         .pad2 = 0,
747         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
748         .use_power_off = true,
749 };
750
751 static struct i2c_board_info palma_device[] = {
752         {
753                 I2C_BOARD_INFO("tps65913", 0x58),
754                 .irq            = INT_EXTERNAL_PMU,
755                 .platform_data  = &palmas_pdata,
756         },
757 };
758
759 /* EN_AVDD_USB_HDMI From PMU GP1 */
760 static struct regulator_consumer_supply fixed_reg_avdd_usb_hdmi_supply[] = {
761         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
762         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
763         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
764         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
765         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
766         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
767 };
768
769 /* EN_CAM_1v8 From PMU GP5 */
770 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
771         REGULATOR_SUPPLY("dvdd_cam", NULL),
772         REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
773         REGULATOR_SUPPLY("vi2c", "2-0030"),
774         REGULATOR_SUPPLY("vif", "2-0036"),
775         REGULATOR_SUPPLY("dovdd", "2-0010"),
776         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
777 };
778
779 /* EN_CAM_1v8 on e1611 From PMU GP6 */
780 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_e1611_supply[] = {
781         REGULATOR_SUPPLY("dvdd_cam", NULL),
782         REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
783         REGULATOR_SUPPLY("vi2c", "2-0030"),
784         REGULATOR_SUPPLY("vif", "2-0036"),
785         REGULATOR_SUPPLY("dovdd", "2-0010"),
786         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
787 };
788
789 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
790         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
791 };
792
793 /* EN_USB1_VBUS From TEGRA GPIO PN4 PR3(T30) */
794 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
795         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
796 };
797
798 /* EN_3V3_FUSE From TEGRA GPIO PX4 */
799 static struct regulator_consumer_supply fixed_reg_vpp_fuse_supply[] = {
800         REGULATOR_SUPPLY("vpp_fuse", NULL),
801 };
802
803 /* EN_USB3_VBUS From TEGRA GPIO PM5 */
804 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
805         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
806 };
807
808 /* EN_1V8_TS From TEGRA_GPIO_PH5 */
809 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
810         REGULATOR_SUPPLY("dvdd", "spi3.2"),
811 };
812
813 /* Macro for defining fixed regulator sub device data */
814 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
815 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
816         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
817         static struct regulator_init_data ri_data_##_var =              \
818         {                                                               \
819                 .supply_regulator = _in_supply,                         \
820                 .num_consumer_supplies =                                \
821                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
822                 .consumer_supplies = fixed_reg_##_name##_supply,        \
823                 .constraints = {                                        \
824                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
825                                         REGULATOR_MODE_STANDBY),        \
826                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
827                                         REGULATOR_CHANGE_STATUS |       \
828                                         REGULATOR_CHANGE_VOLTAGE),      \
829                         .always_on = _always_on,                        \
830                         .boot_on = _boot_on,                            \
831                 },                                                      \
832         };                                                              \
833         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
834         {                                                               \
835                 .supply_name = FIXED_SUPPLY(_name),                     \
836                 .microvolts = _millivolts * 1000,                       \
837                 .gpio = _gpio_nr,                                       \
838                 .gpio_is_open_drain = _open_drain,                      \
839                 .enable_high = _active_high,                            \
840                 .enabled_at_boot = _boot_state,                         \
841                 .init_data = &ri_data_##_var,                           \
842         };                                                              \
843         static struct platform_device fixed_reg_##_var##_dev = {        \
844                 .name = "reg-fixed-voltage",                            \
845                 .id = _id,                                              \
846                 .dev = {                                                \
847                         .platform_data = &fixed_reg_##_var##_pdata,     \
848                 },                                                      \
849         }
850
851 FIXED_REG(1,    avdd_usb_hdmi,  avdd_usb_hdmi,
852         tps65090_rails(DCDC2),  0,      0,
853         MAX77663_GPIO_BASE + MAX77663_GPIO1,    true,   true,   1,      3300);
854
855 FIXED_REG(2,    en_1v8_cam,     en_1v8_cam,
856         max77663_rails(sd2),    0,      0,
857         MAX77663_GPIO_BASE + MAX77663_GPIO5,    false,  true,   0,      1800);
858
859 FIXED_REG(3,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
860         tps65090_rails(DCDC1),  0,      0,
861         TEGRA_GPIO_PK1, false,  true,   0,      5000);
862
863 FIXED_REG(4,    vpp_fuse,       vpp_fuse,
864         max77663_rails(sd2),    0,      0,
865         TEGRA_GPIO_PX4, false,  true,   0,      3300);
866
867 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
868 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
869         tps65090_rails(DCDC1),  0,      0,
870         TEGRA_GPIO_PN4, true,   true,   0,      5000);
871 #else
872 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
873         tps65090_rails(DCDC1),  0,      0,
874         TEGRA_GPIO_PR3, true,   true,   0,      5000);
875 #endif
876
877 FIXED_REG(6,    usb3_vbus,      usb3_vbus,
878         tps65090_rails(DCDC1),  0,      0,
879         TEGRA_GPIO_PK6, true,   true,   0,      5000);
880
881 FIXED_REG(7,    en_1v8_cam_e1611,       en_1v8_cam_e1611,
882         palmas_rails(smps3),    0,      0,
883         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
884
885 FIXED_REG(8,    dvdd_ts,        dvdd_ts,
886         palmas_rails(smps3),    0,      0,
887         TEGRA_GPIO_PH5, false,  false,  1,      1800);
888 /*
889  * Creating the fixed regulator device tables
890  */
891
892 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
893
894 #define DALMORE_COMMON_FIXED_REG                \
895         ADD_FIXED_REG(usb1_vbus),               \
896         ADD_FIXED_REG(usb3_vbus),               \
897         ADD_FIXED_REG(vdd_hdmi_5v0),
898
899 #define E1612_FIXED_REG                         \
900         ADD_FIXED_REG(avdd_usb_hdmi),           \
901         ADD_FIXED_REG(en_1v8_cam),              \
902         ADD_FIXED_REG(vpp_fuse),                \
903
904 #define E1611_FIXED_REG                         \
905         ADD_FIXED_REG(en_1v8_cam_e1611), \
906         ADD_FIXED_REG(dvdd_ts),
907
908 /* Gpio switch regulator platform data for Dalmore E1611 */
909 static struct platform_device *fixed_reg_devs_e1611_a00[] = {
910         DALMORE_COMMON_FIXED_REG
911         E1611_FIXED_REG
912 };
913
914 /* Gpio switch regulator platform data for Dalmore E1612 */
915 static struct platform_device *fixed_reg_devs_e1612_a00[] = {
916         DALMORE_COMMON_FIXED_REG
917         E1612_FIXED_REG
918 };
919
920 int __init dalmore_palmas_regulator_init(void)
921 {
922         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
923         u32 pmc_ctrl;
924         int i;
925 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
926         int ret;
927
928         ret = gpio_request(TEGRA_GPIO_PCC3, "pmic_nreswarm");
929         if (ret < 0)
930                 pr_err("%s: gpio_request failed for gpio %d\n",
931                                 __func__, TEGRA_GPIO_PCC3);
932         else
933                 gpio_direction_output(TEGRA_GPIO_PCC3, 1);
934 #endif
935         /* TPS65913: Normal state of INT request line is LOW.
936          * configure the power management controller to trigger PMU
937          * interrupts when HIGH.
938          */
939         pmc_ctrl = readl(pmc + PMC_CTRL);
940         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
941         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
942                 pmic_platform.reg_data[i] = dalmore_e1611_reg_data[i];
943                 pmic_platform.reg_init[i] = dalmore_e1611_reg_init[i];
944         }
945
946         i2c_register_board_info(4, palma_device,
947                         ARRAY_SIZE(palma_device));
948         return 0;
949 }
950
951 static int ac_online(void)
952 {
953         return 1;
954 }
955
956 static struct resource dalmore_pda_resources[] = {
957         [0] = {
958                 .name   = "ac",
959         },
960 };
961
962 static struct pda_power_pdata dalmore_pda_data = {
963         .is_ac_online   = ac_online,
964 };
965
966 static struct platform_device dalmore_pda_power_device = {
967         .name           = "pda-power",
968         .id             = -1,
969         .resource       = dalmore_pda_resources,
970         .num_resources  = ARRAY_SIZE(dalmore_pda_resources),
971         .dev    = {
972                 .platform_data  = &dalmore_pda_data,
973         },
974 };
975
976 static struct tegra_suspend_platform_data dalmore_suspend_data = {
977         .cpu_timer      = 300,
978         .cpu_off_timer  = 300,
979         .suspend_mode   = TEGRA_SUSPEND_LP0,
980         .core_timer     = 0x157e,
981         .core_off_timer = 2000,
982         .corereq_high   = true,
983         .sysclkreq_high = true,
984         .min_residency_noncpu = 600,
985         .min_residency_crail = 1000,
986 };
987 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
988 /* board parameters for cpu dfll */
989 static struct tegra_cl_dvfs_cfg_param dalmore_cl_dvfs_param = {
990         .sample_rate = 12500,
991
992         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
993         .cf = 10,
994         .ci = 0,
995         .cg = 2,
996
997         .droop_cut_value = 0xF,
998         .droop_restore_ramp = 0x0,
999         .scale_out_ramp = 0x0,
1000 };
1001 #endif
1002
1003 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
1004 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
1005 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
1006 static inline void fill_reg_map(void)
1007 {
1008         int i;
1009         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
1010                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
1011                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
1012         }
1013 }
1014
1015 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1016 static struct tegra_cl_dvfs_platform_data dalmore_cl_dvfs_data = {
1017         .dfll_clk_name = "dfll_cpu",
1018         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
1019         .u.pmu_i2c = {
1020                 .fs_rate = 400000,
1021                 .slave_addr = 0x86,
1022                 .reg = 0x00,
1023         },
1024         .vdd_map = pmu_cpu_vdd_map,
1025         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
1026
1027         .cfg_param = &dalmore_cl_dvfs_param,
1028 };
1029
1030 static int __init dalmore_cl_dvfs_init(void)
1031 {
1032         fill_reg_map();
1033         tegra_cl_dvfs_device.dev.platform_data = &dalmore_cl_dvfs_data;
1034         platform_device_register(&tegra_cl_dvfs_device);
1035
1036         return 0;
1037 }
1038 #endif
1039
1040 static int __init dalmore_max77663_regulator_init(void)
1041 {
1042         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
1043         u32 pmc_ctrl;
1044
1045         /* configure the power management controller to trigger PMU
1046          * interrupts when low */
1047         pmc_ctrl = readl(pmc + PMC_CTRL);
1048         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
1049
1050         i2c_register_board_info(4, max77663_regulators,
1051                                 ARRAY_SIZE(max77663_regulators));
1052
1053         return 0;
1054 }
1055
1056 static struct regulator_bulk_data dalmore_gps_regulator_supply[] = {
1057         [0] = {
1058                 .supply = "vdd_gps_3v3",
1059         },
1060         [1] = {
1061                 .supply = "vdd_gps_1v8",
1062         },
1063 };
1064
1065 static struct regulator_userspace_consumer_data dalmore_gps_regulator_pdata = {
1066         .num_supplies   = ARRAY_SIZE(dalmore_gps_regulator_supply),
1067         .supplies       = dalmore_gps_regulator_supply,
1068 };
1069
1070 static struct platform_device dalmore_gps_regulator_device = {
1071         .name   = "reg-userspace-consumer",
1072         .id     = 2,
1073         .dev    = {
1074                         .platform_data = &dalmore_gps_regulator_pdata,
1075         },
1076 };
1077
1078 static struct regulator_bulk_data dalmore_bt_regulator_supply[] = {
1079         [0] = {
1080                 .supply = "vdd_bt_3v3",
1081         },
1082         [1] = {
1083                 .supply = "vddio_bt_1v8",
1084         },
1085 };
1086
1087 static struct regulator_userspace_consumer_data dalmore_bt_regulator_pdata = {
1088         .num_supplies   = ARRAY_SIZE(dalmore_bt_regulator_supply),
1089         .supplies       = dalmore_bt_regulator_supply,
1090 };
1091
1092 static struct platform_device dalmore_bt_regulator_device = {
1093         .name   = "reg-userspace-consumer",
1094         .id     = 1,
1095         .dev    = {
1096                         .platform_data = &dalmore_bt_regulator_pdata,
1097         },
1098 };
1099
1100 static int __init dalmore_fixed_regulator_init(void)
1101 {
1102         struct board_info board_info;
1103
1104         if (!machine_is_dalmore())
1105                 return 0;
1106
1107         tegra_get_board_info(&board_info);
1108
1109         if (board_info.board_id == BOARD_E1611 ||
1110                 board_info.board_id == BOARD_P2454)
1111                 return platform_add_devices(fixed_reg_devs_e1611_a00,
1112                                 ARRAY_SIZE(fixed_reg_devs_e1611_a00));
1113         else
1114                 return platform_add_devices(fixed_reg_devs_e1612_a00,
1115                                 ARRAY_SIZE(fixed_reg_devs_e1612_a00));
1116 }
1117 subsys_initcall_sync(dalmore_fixed_regulator_init);
1118
1119 static void dalmore_tps65090_init(void)
1120 {
1121         int err;
1122
1123         err = gpio_request(TPS65090_CHARGER_INT, "CHARGER_INT");
1124         if (err < 0) {
1125                 pr_err("%s: gpio_request failed %d\n", __func__, err);
1126                 goto fail_init_irq;
1127         }
1128
1129         err = gpio_direction_input(TPS65090_CHARGER_INT);
1130         if (err < 0) {
1131                 pr_err("%s: gpio_direction_input failed %d\n", __func__, err);
1132                 goto fail_init_irq;
1133         }
1134
1135         tps65090_regulators[0].irq = gpio_to_irq(TPS65090_CHARGER_INT);
1136 fail_init_irq:
1137         i2c_register_board_info(4, tps65090_regulators,
1138                         ARRAY_SIZE(tps65090_regulators));
1139         return;
1140 }
1141
1142 int __init dalmore_regulator_init(void)
1143 {
1144         struct board_info board_info;
1145
1146         dalmore_tps65090_init();
1147 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1148         dalmore_cl_dvfs_init();
1149 #endif
1150         tegra_get_board_info(&board_info);
1151         if (board_info.board_id == BOARD_E1611 ||
1152                 board_info.board_id == BOARD_P2454)
1153                 dalmore_palmas_regulator_init();
1154         else
1155                 dalmore_max77663_regulator_init();
1156
1157         i2c_register_board_info(4, tps51632_boardinfo, 1);
1158         platform_device_register(&dalmore_pda_power_device);
1159         platform_device_register(&dalmore_bt_regulator_device);
1160         platform_device_register(&dalmore_gps_regulator_device);
1161         return 0;
1162 }
1163
1164 int __init dalmore_suspend_init(void)
1165 {
1166         tegra_init_suspend(&dalmore_suspend_data);
1167         return 0;
1168 }
1169
1170 int __init dalmore_edp_init(void)
1171 {
1172         unsigned int regulator_mA;
1173
1174         regulator_mA = get_maximum_cpu_current_supported();
1175         if (!regulator_mA)
1176                 regulator_mA = 15000;
1177
1178         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1179         tegra_init_cpu_edp_limits(regulator_mA);
1180
1181         regulator_mA = get_maximum_core_current_supported();
1182         if (!regulator_mA)
1183                 regulator_mA = 4000;
1184
1185         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
1186         tegra_init_core_edp_limits(regulator_mA);
1187
1188         return 0;
1189 }
1190
1191 static struct soctherm_platform_data dalmore_soctherm_data = {
1192         .soctherm_clk_rate = 136000000,
1193         .tsensor_clk_rate = 500000,
1194         .sensor_data = {
1195                 [TSENSE_CPU0] = {
1196                         .enable = true,
1197                         .tall = 16300,
1198                         .tiddq = 1,
1199                         .ten_count = 1,
1200                         .tsample = 163,
1201                         .pdiv = 10,
1202                 },
1203                 [TSENSE_CPU1] = {
1204                         .enable = true,
1205                         .tall = 16300,
1206                         .tiddq = 1,
1207                         .ten_count = 1,
1208                         .tsample = 163,
1209                         .pdiv = 10,
1210                 },
1211                 [TSENSE_CPU2] = {
1212                         .enable = true,
1213                         .tall = 16300,
1214                         .tiddq = 1,
1215                         .ten_count = 1,
1216                         .tsample = 163,
1217                         .pdiv = 10,
1218                 },
1219                 [TSENSE_CPU3] = {
1220                         .enable = true,
1221                         .tall = 16300,
1222                         .tiddq = 1,
1223                         .ten_count = 1,
1224                         .tsample = 163,
1225                         .pdiv = 10,
1226                 },
1227                 /* MEM0/MEM1 won't be used */
1228                 [TSENSE_MEM0] = {
1229                         .enable = false,
1230                 },
1231                 [TSENSE_MEM1] = {
1232                         .enable = false,
1233                 },
1234                 [TSENSE_GPU] = {
1235                         .enable = true,
1236                         .tall = 16300,
1237                         .tiddq = 1,
1238                         .ten_count = 1,
1239                         .tsample = 163,
1240                         .pdiv = 10,
1241                 },
1242                 [TSENSE_PLLX] = {
1243                         .enable = true,
1244                         .tall = 16300,
1245                         .tiddq = 1,
1246                         .ten_count = 1,
1247                         .tsample = 163,
1248                         .pdiv = 10,
1249                 },
1250         },
1251 };
1252
1253 int __init dalmore_soctherm_init(void)
1254 {
1255         return tegra11_soctherm_init(&dalmore_soctherm_data);
1256 }