ARM: tegra: dalmore: updating regulators sources for xusb
[linux-3.10.git] / arch / arm / mach-tegra / board-dalmore-power.c
1 /*
2  * arch/arm/mach-tegra/board-dalmore-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/max77663-core.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/mfd/tps65090.h>
31 #include <linux/regulator/max77663-regulator.h>
32 #include <linux/regulator/tps65090-regulator.h>
33 #include <linux/regulator/tps51632-regulator.h>
34 #include <linux/gpio.h>
35 #include <linux/interrupt.h>
36 #include <linux/regulator/userspace-consumer.h>
37
38 #include <asm/mach-types.h>
39 #include <linux/power/sbs-battery.h>
40
41 #include <mach/iomap.h>
42 #include <mach/irqs.h>
43 #include <mach/edp.h>
44 #include <mach/gpio-tegra.h>
45
46 #include "cpu-tegra.h"
47 #include "pm.h"
48 #include "tegra-board-id.h"
49 #include "board.h"
50 #include "gpio-names.h"
51 #include "board-dalmore.h"
52 #include "tegra_cl_dvfs.h"
53 #include "devices.h"
54 #include "tegra11_soctherm.h"
55
56 #define PMC_CTRL                0x0
57 #define PMC_CTRL_INTR_LOW       (1 << 17)
58 #define TPS65090_CHARGER_INT    TEGRA_GPIO_PJ0
59 /*TPS65090 consumer rails */
60 static struct regulator_consumer_supply tps65090_dcdc1_supply[] = {
61         REGULATOR_SUPPLY("vdd_sys_5v0", NULL),
62         REGULATOR_SUPPLY("vdd_spk", NULL),
63         REGULATOR_SUPPLY("vdd_sys_modem_5v0", NULL),
64         REGULATOR_SUPPLY("vdd_sys_cam_5v0", NULL),
65 };
66
67 static struct regulator_consumer_supply tps65090_dcdc2_supply[] = {
68         REGULATOR_SUPPLY("vdd_sys_3v3", NULL),
69         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
70         REGULATOR_SUPPLY("pwrdet_hv", NULL),
71         REGULATOR_SUPPLY("vdd_sys_ds_3v3", NULL),
72         REGULATOR_SUPPLY("vdd_sys_nfc_3v3", NULL),
73         REGULATOR_SUPPLY("vdd_hv_nfc_3v3", NULL),
74         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
75         REGULATOR_SUPPLY("vdd_sys_sensor_3v3", NULL),
76         REGULATOR_SUPPLY("vdd_sys_audio_3v3", NULL),
77         REGULATOR_SUPPLY("vdd_sys_dtv_3v3", NULL),
78         REGULATOR_SUPPLY("vcc", "0-007c"),
79         REGULATOR_SUPPLY("vcc", "0-0030"),
80         REGULATOR_SUPPLY("vin", "2-0030"),
81 };
82
83 static struct regulator_consumer_supply tps65090_dcdc3_supply[] = {
84         REGULATOR_SUPPLY("vdd_ao", NULL),
85 };
86
87 static struct regulator_consumer_supply tps65090_ldo1_supply[] = {
88         REGULATOR_SUPPLY("vdd_sby_5v0", NULL),
89 };
90
91 static struct regulator_consumer_supply tps65090_ldo2_supply[] = {
92         REGULATOR_SUPPLY("vdd_sby_3v3", NULL),
93 };
94
95 static struct regulator_consumer_supply tps65090_fet1_supply[] = {
96         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
97 };
98
99 static struct regulator_consumer_supply tps65090_fet3_supply[] = {
100         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
101 };
102
103 static struct regulator_consumer_supply tps65090_fet4_supply[] = {
104         REGULATOR_SUPPLY("avdd_lcd", NULL),
105         REGULATOR_SUPPLY("avdd", "spi3.2"),
106 };
107
108 static struct regulator_consumer_supply tps65090_fet5_supply[] = {
109         REGULATOR_SUPPLY("vdd_lvds", NULL),
110 };
111
112 static struct regulator_consumer_supply tps65090_fet6_supply[] = {
113         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
114 };
115
116 static struct regulator_consumer_supply tps65090_fet7_supply[] = {
117         REGULATOR_SUPPLY("vdd_wifi_3v3", "bcm4329_wlan.1"),
118         REGULATOR_SUPPLY("vdd_gps_3v3", "reg-userspace-consumer.2"),
119         REGULATOR_SUPPLY("vdd_bt_3v3", "bluedroid_pm.0"),
120 };
121
122 #define TPS65090_PDATA_INIT(_id, _name, _supply_reg,                    \
123         _always_on, _boot_on, _apply_uV, _en_ext_ctrl, _gpio, _wait_to) \
124 static struct regulator_init_data ri_data_##_name =                     \
125 {                                                                       \
126         .supply_regulator = _supply_reg,                                \
127         .constraints = {                                                \
128                 .name = tps65090_rails(_id),                            \
129                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
130                                      REGULATOR_MODE_STANDBY),           \
131                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
132                                    REGULATOR_CHANGE_STATUS |            \
133                                    REGULATOR_CHANGE_VOLTAGE),           \
134                 .always_on = _always_on,                                \
135                 .boot_on = _boot_on,                                    \
136                 .apply_uV = _apply_uV,                                  \
137         },                                                              \
138         .num_consumer_supplies =                                        \
139                 ARRAY_SIZE(tps65090_##_name##_supply),                  \
140         .consumer_supplies = tps65090_##_name##_supply,                 \
141 };                                                                      \
142 static struct tps65090_regulator_platform_data                          \
143                         tps65090_regulator_pdata_##_name =              \
144 {                                                                       \
145         .id = TPS65090_REGULATOR_##_id,                                 \
146         .enable_ext_control = _en_ext_ctrl,                             \
147         .gpio = _gpio,                                                  \
148         .reg_init_data = &ri_data_##_name ,                             \
149         .wait_timeout_us = _wait_to,                                    \
150 }
151
152 TPS65090_PDATA_INIT(DCDC1, dcdc1, NULL, 1, 1, 0, true, -1, -1);
153 TPS65090_PDATA_INIT(DCDC2, dcdc2, NULL, 1, 1, 0, true, -1, -1);
154 TPS65090_PDATA_INIT(DCDC3, dcdc3, NULL, 1, 1, 0, true, -1, -1);
155 TPS65090_PDATA_INIT(LDO1, ldo1, NULL, 1, 1, 0, false, -1, -1);
156 TPS65090_PDATA_INIT(LDO2, ldo2, NULL, 1, 1, 0, false, -1, -1);
157 TPS65090_PDATA_INIT(FET1, fet1, NULL, 0, 0, 0, false, -1, 800);
158 TPS65090_PDATA_INIT(FET3, fet3, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
159 TPS65090_PDATA_INIT(FET4, fet4, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
160 TPS65090_PDATA_INIT(FET5, fet5, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
161 TPS65090_PDATA_INIT(FET6, fet6, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
162 TPS65090_PDATA_INIT(FET7, fet7, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
163
164 #define ADD_TPS65090_REG(_name) (&tps65090_regulator_pdata_##_name)
165 static struct tps65090_regulator_platform_data *tps65090_reg_pdata[] = {
166         ADD_TPS65090_REG(dcdc1),
167         ADD_TPS65090_REG(dcdc2),
168         ADD_TPS65090_REG(dcdc3),
169         ADD_TPS65090_REG(ldo1),
170         ADD_TPS65090_REG(ldo2),
171         ADD_TPS65090_REG(fet1),
172         ADD_TPS65090_REG(fet3),
173         ADD_TPS65090_REG(fet4),
174         ADD_TPS65090_REG(fet5),
175         ADD_TPS65090_REG(fet6),
176         ADD_TPS65090_REG(fet7),
177 };
178
179 static struct tps65090_charger_data bcharger_pdata = {
180         .irq_base = TPS65090_TEGRA_IRQ_BASE,
181         .update_status = sbs_update,
182 };
183
184 static struct tps65090_platform_data tps65090_pdata = {
185         .irq_base = TPS65090_TEGRA_IRQ_BASE,
186         .irq_flag = IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
187         .num_reg_pdata =  ARRAY_SIZE(tps65090_reg_pdata),
188         .reg_pdata = tps65090_reg_pdata,
189         .charger_pdata = &bcharger_pdata,
190 };
191
192 /* MAX77663 consumer rails */
193 static struct regulator_consumer_supply max77663_sd0_supply[] = {
194         REGULATOR_SUPPLY("vdd_core", NULL),
195 };
196
197 static struct regulator_consumer_supply max77663_sd1_supply[] = {
198         REGULATOR_SUPPLY("vddio_ddr", NULL),
199         REGULATOR_SUPPLY("vddio_ddr0", NULL),
200         REGULATOR_SUPPLY("vddio_ddr1", NULL),
201 };
202
203 static struct regulator_consumer_supply max77663_sd2_supply[] = {
204         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
205         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
206         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
207         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
208         REGULATOR_SUPPLY("pwrdet_cam", NULL),
209         REGULATOR_SUPPLY("avdd_osc", NULL),
210         REGULATOR_SUPPLY("vddio_sys", NULL),
211         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
212         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
213         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
214         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
215         REGULATOR_SUPPLY("vdd_emmc", NULL),
216         REGULATOR_SUPPLY("vddio_audio", NULL),
217         REGULATOR_SUPPLY("pwrdet_audio", NULL),
218         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
219         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
220         REGULATOR_SUPPLY("vddio_modem", NULL),
221         REGULATOR_SUPPLY("vddio_modem_1v8", NULL),
222         REGULATOR_SUPPLY("vddio_bb", NULL),
223         REGULATOR_SUPPLY("pwrdet_bb", NULL),
224         REGULATOR_SUPPLY("vddio_bb_1v8", NULL),
225         REGULATOR_SUPPLY("vddio_uart", NULL),
226         REGULATOR_SUPPLY("pwrdet_uart", NULL),
227         REGULATOR_SUPPLY("vddio_gmi", NULL),
228         REGULATOR_SUPPLY("pwrdet_nand", NULL),
229         REGULATOR_SUPPLY("vdd_sensor_1v8", NULL),
230         REGULATOR_SUPPLY("vdd_mic_1v8", NULL),
231         REGULATOR_SUPPLY("vdd_nfc_1v8", NULL),
232         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
233         REGULATOR_SUPPLY("vdd_spi_1v8", NULL),
234         REGULATOR_SUPPLY("dvdd_lcd", NULL),
235         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
236         REGULATOR_SUPPLY("vddio_wifi_1v8", "bcm4329_wlan.1"),
237         REGULATOR_SUPPLY("vdd_gps_1v8", "reg-userspace-consumer.2"),
238         REGULATOR_SUPPLY("vddio_bt_1v8", "bluedroid_pm.0"),
239         REGULATOR_SUPPLY("vdd_dtv_1v8", NULL),
240         REGULATOR_SUPPLY("vlogic", "0-0069"),
241 };
242
243 static struct regulator_consumer_supply max77663_sd3_supply[] = {
244         REGULATOR_SUPPLY("vcore_emmc", NULL),
245 };
246
247 static struct regulator_consumer_supply max77663_ldo0_supply[] = {
248         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
249         REGULATOR_SUPPLY("avdd_pllx", NULL),
250         REGULATOR_SUPPLY("avdd_plle", NULL),
251         REGULATOR_SUPPLY("avdd_pllm", NULL),
252         REGULATOR_SUPPLY("avdd_pllu", NULL),
253         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
254         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
255         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
256 };
257
258 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
259         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
260 };
261
262 static struct regulator_consumer_supply max77663_ldo2_supply[] = {
263         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
264         REGULATOR_SUPPLY("vdd_als", NULL),
265         REGULATOR_SUPPLY("vdd", "0-004c"),
266         REGULATOR_SUPPLY("vdd", "0-0069"),
267 };
268
269 static struct regulator_consumer_supply max77663_ldo3_supply[] = {
270         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
271         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
272         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
273 };
274
275 static struct regulator_consumer_supply max77663_ldo4_supply[] = {
276         REGULATOR_SUPPLY("vdd_rtc", NULL),
277 };
278
279 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
280         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
281         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
282         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
283         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
284         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
285         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
286         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
287         REGULATOR_SUPPLY("vddio_bb_hsic", NULL),
288 };
289
290 static struct regulator_consumer_supply max77663_ldo6_supply[] = {
291         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
292         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
293 };
294
295 /* FIXME!! Put the device address of camera */
296 static struct regulator_consumer_supply max77663_ldo7_supply[] = {
297         REGULATOR_SUPPLY("avdd_cam1", NULL),
298         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
299         REGULATOR_SUPPLY("vana", "2-0036"),
300 };
301
302 /* FIXME!! Put the device address of camera */
303 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
304         REGULATOR_SUPPLY("avdd_cam2", NULL),
305         REGULATOR_SUPPLY("avdd", "2-0010"),
306 };
307
308 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
309         {
310                 .src = FPS_SRC_0,
311                 .en_src = FPS_EN_SRC_EN0,
312                 .time_period = FPS_TIME_PERIOD_DEF,
313         },
314         {
315                 .src = FPS_SRC_1,
316                 .en_src = FPS_EN_SRC_EN1,
317                 .time_period = FPS_TIME_PERIOD_DEF,
318         },
319         {
320                 .src = FPS_SRC_2,
321                 .en_src = FPS_EN_SRC_EN0,
322                 .time_period = FPS_TIME_PERIOD_DEF,
323         },
324 };
325
326 #define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg,   \
327                 _always_on, _boot_on, _apply_uV,                        \
328                 _fps_src, _fps_pu_period, _fps_pd_period, _flags)       \
329         static struct regulator_init_data max77663_regulator_idata_##_id = {   \
330                 .supply_regulator = _supply_reg,                        \
331                 .constraints = {                                        \
332                         .name = max77663_rails(_id),                    \
333                         .min_uV = _min_uV,                              \
334                         .max_uV = _max_uV,                              \
335                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
336                                              REGULATOR_MODE_STANDBY),   \
337                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
338                                            REGULATOR_CHANGE_STATUS |    \
339                                            REGULATOR_CHANGE_VOLTAGE),   \
340                         .always_on = _always_on,                        \
341                         .boot_on = _boot_on,                            \
342                         .apply_uV = _apply_uV,                          \
343                 },                                                      \
344                 .num_consumer_supplies =                                \
345                         ARRAY_SIZE(max77663_##_id##_supply),            \
346                 .consumer_supplies = max77663_##_id##_supply,           \
347         };                                                              \
348 static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id =\
349 {                                                                       \
350                 .reg_init_data = &max77663_regulator_idata_##_id,       \
351                 .id = MAX77663_REGULATOR_ID_##_rid,                     \
352                 .fps_src = _fps_src,                                    \
353                 .fps_pu_period = _fps_pu_period,                        \
354                 .fps_pd_period = _fps_pd_period,                        \
355                 .fps_cfgs = max77663_fps_cfgs,                          \
356                 .flags = _flags,                                        \
357         }
358
359 MAX77663_PDATA_INIT(SD0, sd0,  900000, 1400000, tps65090_rails(DCDC3), 1, 1, 0,
360                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
361
362 MAX77663_PDATA_INIT(SD1, sd1,  1200000, 1200000, tps65090_rails(DCDC3), 1, 1, 1,
363                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
364
365 MAX77663_PDATA_INIT(SD2, sd2,  1800000, 1800000, tps65090_rails(DCDC3), 1, 1, 1,
366                     FPS_SRC_0, -1, -1, 0);
367
368 MAX77663_PDATA_INIT(SD3, sd3,  2850000, 2850000, tps65090_rails(DCDC3), 1, 1, 1,
369                     FPS_SRC_NONE, -1, -1, 0);
370
371 MAX77663_PDATA_INIT(LDO0, ldo0, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
372                     FPS_SRC_1, -1, -1, 0);
373
374 MAX77663_PDATA_INIT(LDO1, ldo1, 1050000, 1050000, max77663_rails(sd2), 0, 0, 1,
375                     FPS_SRC_NONE, -1, -1, 0);
376
377 MAX77663_PDATA_INIT(LDO2, ldo2, 2850000, 2850000, tps65090_rails(DCDC2), 1, 1,
378                     1, FPS_SRC_1, -1, -1, 0);
379
380 MAX77663_PDATA_INIT(LDO3, ldo3, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
381                     FPS_SRC_NONE, -1, -1, 0);
382
383 MAX77663_PDATA_INIT(LDO4, ldo4, 1100000, 1100000, tps65090_rails(DCDC2), 1, 1,
384                     1, FPS_SRC_NONE, -1, -1, 0);
385
386 MAX77663_PDATA_INIT(LDO5, ldo5, 1200000, 1200000, max77663_rails(sd2), 0, 1, 1,
387                     FPS_SRC_NONE, -1, -1, 0);
388
389 MAX77663_PDATA_INIT(LDO6, ldo6, 1800000, 3300000, tps65090_rails(DCDC2), 0, 0, 0,
390                     FPS_SRC_NONE, -1, -1, 0);
391
392 MAX77663_PDATA_INIT(LDO7, ldo7, 2800000, 2800000, tps65090_rails(DCDC2), 0, 0, 1,
393                     FPS_SRC_NONE, -1, -1, 0);
394
395 MAX77663_PDATA_INIT(LDO8, ldo8, 2800000, 2800000, tps65090_rails(DCDC2), 0, 1, 1,
396                     FPS_SRC_1, -1, -1, 0);
397
398 #define MAX77663_REG(_id, _data) (&max77663_regulator_pdata_##_data)
399
400 static struct max77663_regulator_platform_data *max77663_reg_pdata[] = {
401         MAX77663_REG(SD0, sd0),
402         MAX77663_REG(SD1, sd1),
403         MAX77663_REG(SD2, sd2),
404         MAX77663_REG(SD3, sd3),
405         MAX77663_REG(LDO0, ldo0),
406         MAX77663_REG(LDO1, ldo1),
407         MAX77663_REG(LDO2, ldo2),
408         MAX77663_REG(LDO3, ldo3),
409         MAX77663_REG(LDO4, ldo4),
410         MAX77663_REG(LDO5, ldo5),
411         MAX77663_REG(LDO6, ldo6),
412         MAX77663_REG(LDO7, ldo7),
413         MAX77663_REG(LDO8, ldo8),
414 };
415
416 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
417         {
418                 .gpio = MAX77663_GPIO0,
419                 .dir = GPIO_DIR_OUT,
420                 .dout = GPIO_DOUT_LOW,
421                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
422                 .alternate = GPIO_ALT_DISABLE,
423         },
424         {
425                 .gpio = MAX77663_GPIO1,
426                 .dir = GPIO_DIR_IN,
427                 .dout = GPIO_DOUT_HIGH,
428                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
429                 .pull_up = GPIO_PU_ENABLE,
430                 .alternate = GPIO_ALT_DISABLE,
431         },
432         {
433                 .gpio = MAX77663_GPIO2,
434                 .dir = GPIO_DIR_OUT,
435                 .dout = GPIO_DOUT_HIGH,
436                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
437                 .pull_up = GPIO_PU_ENABLE,
438                 .alternate = GPIO_ALT_DISABLE,
439         },
440         {
441                 .gpio = MAX77663_GPIO3,
442                 .dir = GPIO_DIR_OUT,
443                 .dout = GPIO_DOUT_HIGH,
444                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
445                 .pull_up = GPIO_PU_ENABLE,
446                 .alternate = GPIO_ALT_DISABLE,
447         },
448         {
449                 .gpio = MAX77663_GPIO4,
450                 .dir = GPIO_DIR_OUT,
451                 .dout = GPIO_DOUT_HIGH,
452                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
453                 .alternate = GPIO_ALT_ENABLE,
454         },
455         {
456                 .gpio = MAX77663_GPIO5,
457                 .dir = GPIO_DIR_OUT,
458                 .dout = GPIO_DOUT_LOW,
459                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
460                 .alternate = GPIO_ALT_DISABLE,
461         },
462         {
463                 .gpio = MAX77663_GPIO6,
464                 .dir = GPIO_DIR_OUT,
465                 .dout = GPIO_DOUT_LOW,
466                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
467                 .alternate = GPIO_ALT_DISABLE,
468         },
469         {
470                 .gpio = MAX77663_GPIO7,
471                 .dir = GPIO_DIR_OUT,
472                 .dout = GPIO_DOUT_LOW,
473                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
474                 .alternate = GPIO_ALT_DISABLE,
475         },
476 };
477
478 static struct max77663_platform_data max77663_pdata = {
479         .irq_base       = MAX77663_IRQ_BASE,
480         .gpio_base      = MAX77663_GPIO_BASE,
481
482         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
483         .gpio_cfgs      = max77663_gpio_cfgs,
484
485         .regulator_pdata = max77663_reg_pdata,
486         .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata),
487
488         .rtc_i2c_addr   = 0x68,
489
490         .use_power_off  = false,
491 };
492
493 static struct i2c_board_info __initdata max77663_regulators[] = {
494         {
495                 /* The I2C address was determined by OTP factory setting */
496                 I2C_BOARD_INFO("max77663", 0x3c),
497                 .irq            = INT_EXTERNAL_PMU,
498                 .platform_data  = &max77663_pdata,
499         },
500 };
501
502 static struct i2c_board_info __initdata tps65090_regulators[] = {
503         {
504                 I2C_BOARD_INFO("tps65090", 0x48),
505                 .platform_data  = &tps65090_pdata,
506         },
507 };
508
509 /* TPS51632 DC-DC converter */
510 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
511         REGULATOR_SUPPLY("vdd_cpu", NULL),
512 };
513
514 static struct regulator_init_data tps51632_init_data = {
515         .constraints = {                                                \
516                 .min_uV = 500000,                                       \
517                 .max_uV = 1520000,                                      \
518                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
519                                         REGULATOR_MODE_STANDBY),        \
520                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
521                                         REGULATOR_CHANGE_STATUS |       \
522                                          REGULATOR_CHANGE_CONTROL |     \
523                                         REGULATOR_CHANGE_VOLTAGE),      \
524                 .always_on = 1,                                         \
525                 .boot_on =  1,                                          \
526                 .apply_uV = 0,                                          \
527         },                                                              \
528         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
529                 .consumer_supplies = tps51632_dcdc_supply,              \
530 };
531
532 static struct tps51632_regulator_platform_data tps51632_pdata = {
533         .reg_init_data = &tps51632_init_data,           \
534         .enable_pwm = false,                            \
535         .max_voltage_uV = 1520000,                      \
536         .base_voltage_uV = 500000,                      \
537         .slew_rate_uv_per_us = 6000,                    \
538 };
539
540 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
541         {
542                 I2C_BOARD_INFO("tps51632", 0x43),
543                 .platform_data  = &tps51632_pdata,
544         },
545 };
546
547 /************************ Palmas based regulator ****************/
548 static struct regulator_consumer_supply palmas_smps12_supply[] = {
549         REGULATOR_SUPPLY("vddio_ddr3l", NULL),
550         REGULATOR_SUPPLY("vcore_ddr3l", NULL),
551         REGULATOR_SUPPLY("vref2_ddr3l", NULL),
552 };
553
554 #define palmas_smps3_supply max77663_sd2_supply
555 #define palmas_smps45_supply max77663_sd0_supply
556 #define palmas_smps457_supply max77663_sd0_supply
557
558 static struct regulator_consumer_supply palmas_smps8_supply[] = {
559         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
560         REGULATOR_SUPPLY("avdd_pllm", NULL),
561         REGULATOR_SUPPLY("avdd_pllu", NULL),
562         REGULATOR_SUPPLY("avdd_pllx", NULL),
563         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
564         REGULATOR_SUPPLY("avdd_plle", NULL),
565         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
566         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
567         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
568         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
569         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
570         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
571         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
572         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
573 };
574
575 static struct regulator_consumer_supply palmas_smps9_supply[] = {
576         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
577 };
578
579 #define palmas_ldo1_supply max77663_ldo7_supply
580 #define palmas_ldo2_supply max77663_ldo8_supply
581 #define palmas_ldo3_supply max77663_ldo5_supply
582
583 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
584         REGULATOR_SUPPLY("vpp_fuse", NULL),
585 };
586
587 #define palmas_ldo6_supply max77663_ldo2_supply
588
589 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
590         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
591         REGULATOR_SUPPLY("vdd", "2-000e"),
592 };
593
594 #define palmas_ldo8_supply max77663_ldo4_supply
595 #define palmas_ldo9_supply max77663_ldo6_supply
596
597 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
598         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
599         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
600 };
601
602 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
603         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
604         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
605         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
606         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
607         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
608 };
609
610 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
611         _boot_on, _apply_uv)                                            \
612         static struct regulator_init_data reg_idata_##_name = {         \
613                 .constraints = {                                        \
614                         .name = palmas_rails(_name),                    \
615                         .min_uV = (_minmv)*1000,                        \
616                         .max_uV = (_maxmv)*1000,                        \
617                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
618                                         REGULATOR_MODE_STANDBY),        \
619                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
620                                         REGULATOR_CHANGE_STATUS |       \
621                                         REGULATOR_CHANGE_VOLTAGE),      \
622                         .always_on = _always_on,                        \
623                         .boot_on = _boot_on,                            \
624                         .apply_uV = _apply_uv,                          \
625                 },                                                      \
626                 .num_consumer_supplies =                                \
627                         ARRAY_SIZE(palmas_##_name##_supply),            \
628                 .consumer_supplies = palmas_##_name##_supply,           \
629                 .supply_regulator = _supply_reg,                        \
630         }
631
632 PALMAS_PDATA_INIT(smps12, 1350,  1350, tps65090_rails(DCDC3), 0, 0, 0);
633 PALMAS_PDATA_INIT(smps3, 1800,  1800, tps65090_rails(DCDC3), 0, 0, 0);
634 PALMAS_PDATA_INIT(smps45, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0);
635 PALMAS_PDATA_INIT(smps457, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0);
636 PALMAS_PDATA_INIT(smps8, 1050,  1050, tps65090_rails(DCDC2), 0, 1, 1);
637 PALMAS_PDATA_INIT(smps9, 2800,  2800, tps65090_rails(DCDC2), 1, 0, 0);
638 PALMAS_PDATA_INIT(ldo1, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
639 PALMAS_PDATA_INIT(ldo2, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
640 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps3), 0, 0, 1);
641 PALMAS_PDATA_INIT(ldo4, 1800,  1800, tps65090_rails(DCDC2), 0, 0, 0);
642 PALMAS_PDATA_INIT(ldo6, 2850,  2850, tps65090_rails(DCDC2), 0, 0, 1);
643 PALMAS_PDATA_INIT(ldo7, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
644 PALMAS_PDATA_INIT(ldo8, 900,  900, tps65090_rails(DCDC3), 1, 1, 1);
645 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
646 PALMAS_PDATA_INIT(ldoln, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1);
647 PALMAS_PDATA_INIT(ldousb, 3300,  3300, tps65090_rails(DCDC1), 0, 0, 1);
648
649 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
650
651 static struct regulator_init_data *dalmore_e1611_reg_data[PALMAS_NUM_REGS] = {
652         PALMAS_REG_PDATA(smps12),
653         NULL,
654         PALMAS_REG_PDATA(smps3),
655         PALMAS_REG_PDATA(smps45),
656         PALMAS_REG_PDATA(smps457),
657         NULL,
658         NULL,
659         PALMAS_REG_PDATA(smps8),
660         PALMAS_REG_PDATA(smps9),
661         NULL,
662         PALMAS_REG_PDATA(ldo1),
663         PALMAS_REG_PDATA(ldo2),
664         PALMAS_REG_PDATA(ldo3),
665         PALMAS_REG_PDATA(ldo4),
666         NULL,
667         PALMAS_REG_PDATA(ldo6),
668         PALMAS_REG_PDATA(ldo7),
669         PALMAS_REG_PDATA(ldo8),
670         PALMAS_REG_PDATA(ldo9),
671         PALMAS_REG_PDATA(ldoln),
672         PALMAS_REG_PDATA(ldousb),
673         NULL,
674         NULL,
675         NULL,
676         NULL,
677         NULL,
678 };
679
680 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
681                 _tstep, _vsel)                                          \
682         static struct palmas_reg_init reg_init_data_##_name = {         \
683                 .warm_reset = _warm_reset,                              \
684                 .roof_floor =   _roof_floor,                            \
685                 .mode_sleep = _mode_sleep,                              \
686                 .tstep = _tstep,                                        \
687                 .vsel = _vsel,                                          \
688         }
689
690 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
691 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
692 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
693 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
694 PALMAS_REG_INIT(smps457, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
695 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
696 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
697 PALMAS_REG_INIT(smps8, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
698 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
699 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
700 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
701 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
702 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
703 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
704 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
705 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
706 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
707 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
708 PALMAS_REG_INIT(ldo9, 1, 0, 0, 0, 0);
709 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
710 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
711 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
712 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
713 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
714 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
715 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
716
717 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
718 static struct palmas_reg_init *dalmore_e1611_reg_init[PALMAS_NUM_REGS] = {
719         PALMAS_REG_INIT_DATA(smps12),
720         PALMAS_REG_INIT_DATA(smps123),
721         PALMAS_REG_INIT_DATA(smps3),
722         PALMAS_REG_INIT_DATA(smps45),
723         PALMAS_REG_INIT_DATA(smps457),
724         PALMAS_REG_INIT_DATA(smps6),
725         PALMAS_REG_INIT_DATA(smps7),
726         PALMAS_REG_INIT_DATA(smps8),
727         PALMAS_REG_INIT_DATA(smps9),
728         PALMAS_REG_INIT_DATA(smps10),
729         PALMAS_REG_INIT_DATA(ldo1),
730         PALMAS_REG_INIT_DATA(ldo2),
731         PALMAS_REG_INIT_DATA(ldo3),
732         PALMAS_REG_INIT_DATA(ldo4),
733         PALMAS_REG_INIT_DATA(ldo5),
734         PALMAS_REG_INIT_DATA(ldo6),
735         PALMAS_REG_INIT_DATA(ldo7),
736         PALMAS_REG_INIT_DATA(ldo8),
737         PALMAS_REG_INIT_DATA(ldo9),
738         PALMAS_REG_INIT_DATA(ldoln),
739         PALMAS_REG_INIT_DATA(ldousb),
740         PALMAS_REG_INIT_DATA(regen1),
741         PALMAS_REG_INIT_DATA(regen2),
742         PALMAS_REG_INIT_DATA(regen3),
743         PALMAS_REG_INIT_DATA(sysen1),
744         PALMAS_REG_INIT_DATA(sysen2),
745 };
746
747 static struct palmas_pmic_platform_data pmic_platform = {
748         .enable_ldo8_tracking = true,
749         .disabe_ldo8_tracking_suspend = true,
750 };
751
752 static struct palmas_rtc_platform_data rtc_platform = {
753         .enable_charging = 1,
754         .charging_current_ua = 100,
755 };
756
757 static struct palmas_platform_data palmas_pdata = {
758         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
759         .irq_base = PALMAS_TEGRA_IRQ_BASE,
760         .pmic_pdata = &pmic_platform,
761         .rtc_pdata = &rtc_platform,
762         .mux_from_pdata = true,
763         .pad1 = 0,
764         .pad2 = 0,
765         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
766         .use_power_off = true,
767 };
768
769 static struct i2c_board_info palma_device[] = {
770         {
771                 I2C_BOARD_INFO("tps65913", 0x58),
772                 .irq            = INT_EXTERNAL_PMU,
773                 .platform_data  = &palmas_pdata,
774         },
775 };
776
777 /* EN_AVDD_USB_HDMI From PMU GP1 */
778 static struct regulator_consumer_supply fixed_reg_avdd_usb_hdmi_supply[] = {
779         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
780         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
781         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
782         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
783         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
784         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
785 };
786
787 /* EN_CAM_1v8 From PMU GP5 */
788 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
789         REGULATOR_SUPPLY("vi2c", "2-0030"),
790         REGULATOR_SUPPLY("vif", "2-0036"),
791         REGULATOR_SUPPLY("dovdd", "2-0010"),
792         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
793 };
794
795 /* EN_CAM_1v8 on e1611 From PMU GP6 */
796 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_e1611_supply[] = {
797         REGULATOR_SUPPLY("vi2c", "2-0030"),
798         REGULATOR_SUPPLY("vif", "2-0036"),
799         REGULATOR_SUPPLY("dovdd", "2-0010"),
800         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
801 };
802
803 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
804         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
805 };
806
807 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
808         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
809 };
810
811 /* EN_USB1_VBUS From TEGRA GPIO PN4 PR3(T30) */
812 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
813         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
814 };
815
816 /* EN_3V3_FUSE From TEGRA GPIO PX4 */
817 static struct regulator_consumer_supply fixed_reg_vpp_fuse_supply[] = {
818         REGULATOR_SUPPLY("vpp_fuse", NULL),
819 };
820
821 /* EN_USB3_VBUS From TEGRA GPIO PM5 */
822 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
823         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
824         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci"),
825 };
826
827 /* EN_1V8_TS From TEGRA_GPIO_PH5 */
828 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
829         REGULATOR_SUPPLY("dvdd", "spi3.2"),
830 };
831
832 /* Macro for defining fixed regulator sub device data */
833 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
834 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
835         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
836         static struct regulator_init_data ri_data_##_var =              \
837         {                                                               \
838                 .supply_regulator = _in_supply,                         \
839                 .num_consumer_supplies =                                \
840                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
841                 .consumer_supplies = fixed_reg_##_name##_supply,        \
842                 .constraints = {                                        \
843                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
844                                         REGULATOR_MODE_STANDBY),        \
845                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
846                                         REGULATOR_CHANGE_STATUS |       \
847                                         REGULATOR_CHANGE_VOLTAGE),      \
848                         .always_on = _always_on,                        \
849                         .boot_on = _boot_on,                            \
850                 },                                                      \
851         };                                                              \
852         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
853         {                                                               \
854                 .supply_name = FIXED_SUPPLY(_name),                     \
855                 .microvolts = _millivolts * 1000,                       \
856                 .gpio = _gpio_nr,                                       \
857                 .gpio_is_open_drain = _open_drain,                      \
858                 .enable_high = _active_high,                            \
859                 .enabled_at_boot = _boot_state,                         \
860                 .init_data = &ri_data_##_var,                           \
861         };                                                              \
862         static struct platform_device fixed_reg_##_var##_dev = {        \
863                 .name = "reg-fixed-voltage",                            \
864                 .id = _id,                                              \
865                 .dev = {                                                \
866                         .platform_data = &fixed_reg_##_var##_pdata,     \
867                 },                                                      \
868         }
869
870 FIXED_REG(1,    avdd_usb_hdmi,  avdd_usb_hdmi,
871         tps65090_rails(DCDC2),  0,      0,
872         MAX77663_GPIO_BASE + MAX77663_GPIO1,    true,   true,   1,      3300);
873
874 FIXED_REG(2,    en_1v8_cam,     en_1v8_cam,
875         max77663_rails(sd2),    0,      0,
876         MAX77663_GPIO_BASE + MAX77663_GPIO5,    false,  true,   0,      1800);
877
878 FIXED_REG(3,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
879         tps65090_rails(DCDC1),  0,      0,
880         TEGRA_GPIO_PK1, false,  true,   0,      5000);
881
882 FIXED_REG(4,    vpp_fuse,       vpp_fuse,
883         max77663_rails(sd2),    0,      0,
884         TEGRA_GPIO_PX4, false,  true,   0,      3300);
885
886 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
887         tps65090_rails(DCDC1),  0,      0,
888         TEGRA_GPIO_PN4, true,   true,   0,      5000);
889
890 FIXED_REG(6,    usb3_vbus,      usb3_vbus,
891         tps65090_rails(DCDC1),  0,      0,
892         TEGRA_GPIO_PK6, true,   true,   0,      5000);
893
894 FIXED_REG(7,    en_1v8_cam_e1611,       en_1v8_cam_e1611,
895         palmas_rails(smps3),    0,      0,
896         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
897
898 FIXED_REG(8,    dvdd_ts,        dvdd_ts,
899         palmas_rails(smps3),    0,      0,
900         TEGRA_GPIO_PH5, false,  false,  1,      1800);
901
902 FIXED_REG(9,    lcd_bl_en,      lcd_bl_en,
903         NULL,   0,      0,
904         TEGRA_GPIO_PH2, false,  true,   0,      5000);
905 /*
906  * Creating the fixed regulator device tables
907  */
908
909 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
910
911 #define DALMORE_COMMON_FIXED_REG                \
912         ADD_FIXED_REG(usb1_vbus),               \
913         ADD_FIXED_REG(usb3_vbus),               \
914         ADD_FIXED_REG(vdd_hdmi_5v0),            \
915         ADD_FIXED_REG(lcd_bl_en),
916
917 #define E1612_FIXED_REG                         \
918         ADD_FIXED_REG(avdd_usb_hdmi),           \
919         ADD_FIXED_REG(en_1v8_cam),              \
920         ADD_FIXED_REG(vpp_fuse),                \
921
922 #define E1611_FIXED_REG                         \
923         ADD_FIXED_REG(en_1v8_cam_e1611), \
924         ADD_FIXED_REG(dvdd_ts),
925
926 /* Gpio switch regulator platform data for Dalmore E1611 */
927 static struct platform_device *fixed_reg_devs_e1611_a00[] = {
928         DALMORE_COMMON_FIXED_REG
929         E1611_FIXED_REG
930 };
931
932 /* Gpio switch regulator platform data for Dalmore E1612 */
933 static struct platform_device *fixed_reg_devs_e1612_a00[] = {
934         DALMORE_COMMON_FIXED_REG
935         E1612_FIXED_REG
936 };
937
938 int __init dalmore_palmas_regulator_init(void)
939 {
940         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
941         u32 pmc_ctrl;
942         int i;
943
944         /* TPS65913: Normal state of INT request line is LOW.
945          * configure the power management controller to trigger PMU
946          * interrupts when HIGH.
947          */
948         pmc_ctrl = readl(pmc + PMC_CTRL);
949         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
950         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
951                 pmic_platform.reg_data[i] = dalmore_e1611_reg_data[i];
952                 pmic_platform.reg_init[i] = dalmore_e1611_reg_init[i];
953         }
954
955         i2c_register_board_info(4, palma_device,
956                         ARRAY_SIZE(palma_device));
957         return 0;
958 }
959
960 static int ac_online(void)
961 {
962         return 1;
963 }
964
965 static struct resource dalmore_pda_resources[] = {
966         [0] = {
967                 .name   = "ac",
968         },
969 };
970
971 static struct pda_power_pdata dalmore_pda_data = {
972         .is_ac_online   = ac_online,
973 };
974
975 static struct platform_device dalmore_pda_power_device = {
976         .name           = "pda-power",
977         .id             = -1,
978         .resource       = dalmore_pda_resources,
979         .num_resources  = ARRAY_SIZE(dalmore_pda_resources),
980         .dev    = {
981                 .platform_data  = &dalmore_pda_data,
982         },
983 };
984
985 static struct tegra_suspend_platform_data dalmore_suspend_data = {
986         .cpu_timer      = 300,
987         .cpu_off_timer  = 300,
988         .suspend_mode   = TEGRA_SUSPEND_LP0,
989         .core_timer     = 0x157e,
990         .core_off_timer = 2000,
991         .corereq_high   = true,
992         .sysclkreq_high = true,
993         .min_residency_noncpu = 600,
994         .min_residency_crail = 1000,
995 };
996 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
997 /* board parameters for cpu dfll */
998 static struct tegra_cl_dvfs_cfg_param dalmore_cl_dvfs_param = {
999         .sample_rate = 12500,
1000
1001         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
1002         .cf = 10,
1003         .ci = 0,
1004         .cg = 2,
1005
1006         .droop_cut_value = 0xF,
1007         .droop_restore_ramp = 0x0,
1008         .scale_out_ramp = 0x0,
1009 };
1010 #endif
1011
1012 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
1013 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
1014 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
1015 static inline void fill_reg_map(void)
1016 {
1017         int i;
1018         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
1019                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
1020                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
1021         }
1022 }
1023
1024 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1025 static struct tegra_cl_dvfs_platform_data dalmore_cl_dvfs_data = {
1026         .dfll_clk_name = "dfll_cpu",
1027         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
1028         .u.pmu_i2c = {
1029                 .fs_rate = 400000,
1030                 .slave_addr = 0x86,
1031                 .reg = 0x00,
1032         },
1033         .vdd_map = pmu_cpu_vdd_map,
1034         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
1035
1036         .cfg_param = &dalmore_cl_dvfs_param,
1037 };
1038
1039 static int __init dalmore_cl_dvfs_init(void)
1040 {
1041         fill_reg_map();
1042         tegra_cl_dvfs_device.dev.platform_data = &dalmore_cl_dvfs_data;
1043         platform_device_register(&tegra_cl_dvfs_device);
1044
1045         return 0;
1046 }
1047 #endif
1048
1049 static int __init dalmore_max77663_regulator_init(void)
1050 {
1051         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
1052         u32 pmc_ctrl;
1053
1054         /* configure the power management controller to trigger PMU
1055          * interrupts when low */
1056         pmc_ctrl = readl(pmc + PMC_CTRL);
1057         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
1058
1059         i2c_register_board_info(4, max77663_regulators,
1060                                 ARRAY_SIZE(max77663_regulators));
1061
1062         return 0;
1063 }
1064
1065 static struct regulator_bulk_data dalmore_gps_regulator_supply[] = {
1066         [0] = {
1067                 .supply = "vdd_gps_3v3",
1068         },
1069         [1] = {
1070                 .supply = "vdd_gps_1v8",
1071         },
1072 };
1073
1074 static struct regulator_userspace_consumer_data dalmore_gps_regulator_pdata = {
1075         .num_supplies   = ARRAY_SIZE(dalmore_gps_regulator_supply),
1076         .supplies       = dalmore_gps_regulator_supply,
1077 };
1078
1079 static struct platform_device dalmore_gps_regulator_device = {
1080         .name   = "reg-userspace-consumer",
1081         .id     = 2,
1082         .dev    = {
1083                         .platform_data = &dalmore_gps_regulator_pdata,
1084         },
1085 };
1086
1087 static int __init dalmore_fixed_regulator_init(void)
1088 {
1089         struct board_info board_info;
1090
1091         if (!machine_is_dalmore())
1092                 return 0;
1093
1094         tegra_get_board_info(&board_info);
1095
1096         if (board_info.board_id == BOARD_E1611 ||
1097                 board_info.board_id == BOARD_P2454)
1098                 return platform_add_devices(fixed_reg_devs_e1611_a00,
1099                                 ARRAY_SIZE(fixed_reg_devs_e1611_a00));
1100         else
1101                 return platform_add_devices(fixed_reg_devs_e1612_a00,
1102                                 ARRAY_SIZE(fixed_reg_devs_e1612_a00));
1103 }
1104 subsys_initcall_sync(dalmore_fixed_regulator_init);
1105
1106 static void dalmore_tps65090_init(void)
1107 {
1108         int err;
1109
1110         err = gpio_request(TPS65090_CHARGER_INT, "CHARGER_INT");
1111         if (err < 0) {
1112                 pr_err("%s: gpio_request failed %d\n", __func__, err);
1113                 goto fail_init_irq;
1114         }
1115
1116         err = gpio_direction_input(TPS65090_CHARGER_INT);
1117         if (err < 0) {
1118                 pr_err("%s: gpio_direction_input failed %d\n", __func__, err);
1119                 goto fail_init_irq;
1120         }
1121
1122         tps65090_regulators[0].irq = gpio_to_irq(TPS65090_CHARGER_INT);
1123 fail_init_irq:
1124         i2c_register_board_info(4, tps65090_regulators,
1125                         ARRAY_SIZE(tps65090_regulators));
1126         return;
1127 }
1128
1129 int __init dalmore_regulator_init(void)
1130 {
1131         struct board_info board_info;
1132
1133         dalmore_tps65090_init();
1134 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1135         dalmore_cl_dvfs_init();
1136 #endif
1137         tegra_get_board_info(&board_info);
1138         if (board_info.board_id == BOARD_E1611 ||
1139                 board_info.board_id == BOARD_P2454)
1140                 dalmore_palmas_regulator_init();
1141         else
1142                 dalmore_max77663_regulator_init();
1143
1144         i2c_register_board_info(4, tps51632_boardinfo, 1);
1145         platform_device_register(&dalmore_pda_power_device);
1146         platform_device_register(&dalmore_gps_regulator_device);
1147         return 0;
1148 }
1149
1150 int __init dalmore_suspend_init(void)
1151 {
1152         tegra_init_suspend(&dalmore_suspend_data);
1153         return 0;
1154 }
1155
1156 int __init dalmore_edp_init(void)
1157 {
1158         unsigned int regulator_mA;
1159
1160         regulator_mA = get_maximum_cpu_current_supported();
1161         if (!regulator_mA)
1162                 regulator_mA = 15000;
1163
1164         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1165         tegra_init_cpu_edp_limits(regulator_mA);
1166
1167         regulator_mA = get_maximum_core_current_supported();
1168         if (!regulator_mA)
1169                 regulator_mA = 4000;
1170
1171         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
1172         tegra_init_core_edp_limits(regulator_mA);
1173
1174         return 0;
1175 }
1176
1177 static struct soctherm_platform_data dalmore_soctherm_data = {
1178         .soctherm_clk_rate = 136000000,
1179         .tsensor_clk_rate = 500000,
1180         .sensor_data = {
1181                 [TSENSE_CPU0] = {
1182                         .sensor_enable = true,
1183                         .zone_enable = false,
1184                         .tall = 16300,
1185                         .tiddq = 1,
1186                         .ten_count = 1,
1187                         .tsample = 163,
1188                         .pdiv = 10,
1189                 },
1190                 [TSENSE_CPU1] = {
1191                         .sensor_enable = true,
1192                         .zone_enable = false,
1193                         .tall = 16300,
1194                         .tiddq = 1,
1195                         .ten_count = 1,
1196                         .tsample = 163,
1197                         .pdiv = 10,
1198                 },
1199                 [TSENSE_CPU2] = {
1200                         .sensor_enable = true,
1201                         .zone_enable = false,
1202                         .tall = 16300,
1203                         .tiddq = 1,
1204                         .ten_count = 1,
1205                         .tsample = 163,
1206                         .pdiv = 10,
1207                 },
1208                 [TSENSE_CPU3] = {
1209                         .sensor_enable = true,
1210                         .zone_enable = false,
1211                         .tall = 16300,
1212                         .tiddq = 1,
1213                         .ten_count = 1,
1214                         .tsample = 163,
1215                         .pdiv = 10,
1216                 },
1217                 [TSENSE_GPU] = {
1218                         .sensor_enable = true,
1219                         .zone_enable = false,
1220                         .tall = 16300,
1221                         .tiddq = 1,
1222                         .ten_count = 1,
1223                         .tsample = 163,
1224                         .pdiv = 10,
1225                 },
1226                 [TSENSE_PLLX] = {
1227                         .sensor_enable = true,
1228                         .zone_enable = false,
1229                         .tall = 16300,
1230                         .tiddq = 1,
1231                         .ten_count = 1,
1232                         .tsample = 163,
1233                         .pdiv = 10,
1234                 },
1235         },
1236         .therm = {
1237                 [THERM_CPU] = {
1238                         .zone_enable = true,
1239                         .cdev_type = "tegra-balanced",
1240                         .thermtrip = 115,
1241                         .trip_temp = 85000,
1242                         .passive_delay = 1000,
1243                         .hysteresis = 3000,
1244                 },
1245                 [THERM_GPU] = {
1246                         .zone_enable = true,
1247                 },
1248                 [THERM_PLL] = {
1249                         .zone_enable = true,
1250                 },
1251         },
1252 };
1253
1254 int __init dalmore_soctherm_init(void)
1255 {
1256         return tegra11_soctherm_init(&dalmore_soctherm_data);
1257 }