arm: tegra: t11x: cpu rail power good timer
[linux-3.10.git] / arch / arm / mach-tegra / board-dalmore-power.c
1 /*
2  * arch/arm/mach-tegra/board-dalmore-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/max77663-core.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/mfd/tps65090.h>
31 #include <linux/regulator/max77663-regulator.h>
32 #include <linux/regulator/tps65090-regulator.h>
33 #include <linux/regulator/tps51632-regulator.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/userspace-consumer.h>
36
37 #include <asm/mach-types.h>
38
39 #include <mach/iomap.h>
40 #include <mach/irqs.h>
41 #include <mach/edp.h>
42 #include <mach/gpio-tegra.h>
43
44 #include "cpu-tegra.h"
45 #include "pm.h"
46 #include "tegra-board-id.h"
47 #include "board.h"
48 #include "gpio-names.h"
49 #include "board-dalmore.h"
50 #include "tegra_cl_dvfs.h"
51 #include "devices.h"
52 #include "tegra11_soctherm.h"
53
54 #define PMC_CTRL                0x0
55 #define PMC_CTRL_INTR_LOW       (1 << 17)
56
57 /*TPS65090 consumer rails */
58 static struct regulator_consumer_supply tps65090_dcdc1_supply[] = {
59         REGULATOR_SUPPLY("vdd_sys_5v0", NULL),
60         REGULATOR_SUPPLY("vdd_spk", NULL),
61         REGULATOR_SUPPLY("vdd_sys_modem_5v0", NULL),
62         REGULATOR_SUPPLY("vdd_sys_cam_5v0", NULL),
63 };
64
65 static struct regulator_consumer_supply tps65090_dcdc2_supply[] = {
66         REGULATOR_SUPPLY("vdd_sys_3v3", NULL),
67         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
68         REGULATOR_SUPPLY("pwrdet_hv", NULL),
69         REGULATOR_SUPPLY("vdd_sys_ds_3v3", NULL),
70         REGULATOR_SUPPLY("vdd_sys_nfc_3v3", NULL),
71         REGULATOR_SUPPLY("vdd_hv_nfc_3v3", NULL),
72         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
73         REGULATOR_SUPPLY("vdd_sys_sensor_3v3", NULL),
74         REGULATOR_SUPPLY("vdd_sys_audio_3v3", NULL),
75         REGULATOR_SUPPLY("vdd_sys_dtv_3v3", NULL),
76         REGULATOR_SUPPLY("vcc", "0-007c"),
77         REGULATOR_SUPPLY("vcc", "0-0030"),
78 };
79
80 static struct regulator_consumer_supply tps65090_dcdc3_supply[] = {
81         REGULATOR_SUPPLY("vdd_ao", NULL),
82 };
83
84 static struct regulator_consumer_supply tps65090_ldo1_supply[] = {
85         REGULATOR_SUPPLY("vdd_sby_5v0", NULL),
86 };
87
88 static struct regulator_consumer_supply tps65090_ldo2_supply[] = {
89         REGULATOR_SUPPLY("vdd_sby_3v3", NULL),
90 };
91
92 static struct regulator_consumer_supply tps65090_fet1_supply[] = {
93         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
94 };
95
96 static struct regulator_consumer_supply tps65090_fet3_supply[] = {
97         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
98 };
99
100 static struct regulator_consumer_supply tps65090_fet4_supply[] = {
101         REGULATOR_SUPPLY("avdd_lcd", NULL),
102         REGULATOR_SUPPLY("vdd_ts_3v3", NULL),
103 };
104
105 static struct regulator_consumer_supply tps65090_fet5_supply[] = {
106         REGULATOR_SUPPLY("vdd_lvds", NULL),
107 };
108
109 static struct regulator_consumer_supply tps65090_fet6_supply[] = {
110         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
111 };
112
113 static struct regulator_consumer_supply tps65090_fet7_supply[] = {
114         REGULATOR_SUPPLY("vdd_wifi_3v3", NULL),
115         REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
116         REGULATOR_SUPPLY("vdd_bt_3v3", NULL),
117 };
118
119 #define TPS65090_PDATA_INIT(_id, _name, _supply_reg,                    \
120                 _always_on, _boot_on, _apply_uV, _en_ext_ctrl, _gpio)   \
121 static struct regulator_init_data ri_data_##_name =                     \
122 {                                                                       \
123         .supply_regulator = _supply_reg,                                \
124         .constraints = {                                                \
125                 .name = tps65090_rails(_id),                            \
126                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
127                                      REGULATOR_MODE_STANDBY),           \
128                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
129                                    REGULATOR_CHANGE_STATUS |            \
130                                    REGULATOR_CHANGE_VOLTAGE),           \
131                 .always_on = _always_on,                                \
132                 .boot_on = _boot_on,                                    \
133                 .apply_uV = _apply_uV,                                  \
134         },                                                              \
135         .num_consumer_supplies =                                        \
136                 ARRAY_SIZE(tps65090_##_name##_supply),                  \
137         .consumer_supplies = tps65090_##_name##_supply,                 \
138 };                                                                      \
139 static struct tps65090_regulator_platform_data                          \
140                         tps65090_regulator_pdata_##_name =              \
141 {                                                                       \
142         .id = TPS65090_REGULATOR_##_id,                                 \
143         .enable_ext_control = _en_ext_ctrl,                             \
144         .gpio = _gpio,                                                  \
145         .reg_init_data = &ri_data_##_name ,                             \
146 }
147
148 TPS65090_PDATA_INIT(DCDC1, dcdc1, NULL, 1, 1, 0, false, -1);
149 TPS65090_PDATA_INIT(DCDC2, dcdc2, NULL, 1, 1, 0, false, -1);
150 TPS65090_PDATA_INIT(DCDC3, dcdc3, NULL, 1, 1, 0, false, -1);
151 TPS65090_PDATA_INIT(LDO1, ldo1, NULL, 1, 1, 0, false, -1);
152 TPS65090_PDATA_INIT(LDO2, ldo2, NULL, 1, 1, 0, false, -1);
153 TPS65090_PDATA_INIT(FET1, fet1, NULL, 0, 0, 0, false, -1);
154 TPS65090_PDATA_INIT(FET3, fet3, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
155 TPS65090_PDATA_INIT(FET4, fet4, tps65090_rails(DCDC2), 1, 1, 0, false, -1); /* always_on and boot_on */
156 TPS65090_PDATA_INIT(FET5, fet5, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
157 TPS65090_PDATA_INIT(FET6, fet6, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
158 TPS65090_PDATA_INIT(FET7, fet7, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
159
160 #define ADD_TPS65090_REG(_name) (&tps65090_regulator_pdata_##_name)
161 static struct tps65090_regulator_platform_data *tps65090_reg_pdata[] = {
162         ADD_TPS65090_REG(dcdc1),
163         ADD_TPS65090_REG(dcdc2),
164         ADD_TPS65090_REG(dcdc3),
165         ADD_TPS65090_REG(ldo1),
166         ADD_TPS65090_REG(ldo2),
167         ADD_TPS65090_REG(fet1),
168         ADD_TPS65090_REG(fet3),
169         ADD_TPS65090_REG(fet4),
170         ADD_TPS65090_REG(fet5),
171         ADD_TPS65090_REG(fet6),
172         ADD_TPS65090_REG(fet7),
173 };
174
175 static struct tps65090_platform_data tps65090_pdata = {
176         .irq_base = -1,
177         .num_reg_pdata =  ARRAY_SIZE(tps65090_reg_pdata),
178         .reg_pdata = tps65090_reg_pdata
179 };
180
181 /* MAX77663 consumer rails */
182 static struct regulator_consumer_supply max77663_sd0_supply[] = {
183         REGULATOR_SUPPLY("vdd_core", NULL),
184 };
185
186 static struct regulator_consumer_supply max77663_sd1_supply[] = {
187         REGULATOR_SUPPLY("vddio_ddr", NULL),
188         REGULATOR_SUPPLY("vddio_ddr0", NULL),
189         REGULATOR_SUPPLY("vddio_ddr1", NULL),
190 };
191
192 static struct regulator_consumer_supply max77663_sd2_supply[] = {
193         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
194         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
195         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
196         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
197         REGULATOR_SUPPLY("pwrdet_cam", NULL),
198         REGULATOR_SUPPLY("avdd_osc", NULL),
199         REGULATOR_SUPPLY("vddio_sys", NULL),
200         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
201         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
202         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
203         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
204         REGULATOR_SUPPLY("vdd_emmc", NULL),
205         REGULATOR_SUPPLY("vddio_audio", NULL),
206         REGULATOR_SUPPLY("pwrdet_audio", NULL),
207         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
208         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
209         REGULATOR_SUPPLY("vddio_modem", NULL),
210         REGULATOR_SUPPLY("vddio_modem_1v8", NULL),
211         REGULATOR_SUPPLY("vddio_bb", NULL),
212         REGULATOR_SUPPLY("pwrdet_bb", NULL),
213         REGULATOR_SUPPLY("vddio_bb_1v8", NULL),
214         REGULATOR_SUPPLY("vddio_uart", NULL),
215         REGULATOR_SUPPLY("pwrdet_uart", NULL),
216         REGULATOR_SUPPLY("vddio_gmi", NULL),
217         REGULATOR_SUPPLY("pwrdet_nand", NULL),
218         REGULATOR_SUPPLY("vdd_sensor_1v8", NULL),
219         REGULATOR_SUPPLY("vdd_mic_1v8", NULL),
220         REGULATOR_SUPPLY("vdd_nfc_1v8", NULL),
221         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
222         REGULATOR_SUPPLY("vdd_ts_1v8", NULL),
223         REGULATOR_SUPPLY("vdd_spi_1v8", NULL),
224         REGULATOR_SUPPLY("dvdd_lcd", NULL),
225         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
226         REGULATOR_SUPPLY("vddio_wifi_1v8", NULL),
227         REGULATOR_SUPPLY("vdd_gps_1v8", NULL),
228         REGULATOR_SUPPLY("vddio_bt_1v8", NULL),
229         REGULATOR_SUPPLY("vdd_dtv_1v8", NULL),
230 };
231
232 static struct regulator_consumer_supply max77663_sd3_supply[] = {
233         REGULATOR_SUPPLY("vcore_emmc", NULL),
234 };
235
236 static struct regulator_consumer_supply max77663_ldo0_supply[] = {
237         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
238         REGULATOR_SUPPLY("avdd_pllx", NULL),
239         REGULATOR_SUPPLY("avdd_plle", NULL),
240         REGULATOR_SUPPLY("avdd_pllm", NULL),
241         REGULATOR_SUPPLY("avdd_pllu", NULL),
242         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
243         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
244         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
245 };
246
247 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
248         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
249 };
250
251 static struct regulator_consumer_supply max77663_ldo2_supply[] = {
252         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
253         REGULATOR_SUPPLY("vdd_als", NULL),
254         REGULATOR_SUPPLY("vdd", "0-004c"),
255 };
256
257 static struct regulator_consumer_supply max77663_ldo3_supply[] = {
258         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
259         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
260         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
261 };
262
263 static struct regulator_consumer_supply max77663_ldo4_supply[] = {
264         REGULATOR_SUPPLY("vdd_rtc", NULL),
265 };
266
267 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
268         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
269         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
270         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
271         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
272         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
273         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
274         REGULATOR_SUPPLY("vddio_bb_hsic", NULL),
275 };
276
277 static struct regulator_consumer_supply max77663_ldo6_supply[] = {
278         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
279         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
280 };
281
282 /* FIXME!! Put the device address of camera */
283 static struct regulator_consumer_supply max77663_ldo7_supply[] = {
284         REGULATOR_SUPPLY("avdd_cam1", NULL),
285         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
286 };
287
288 /* FIXME!! Put the device address of camera */
289 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
290         REGULATOR_SUPPLY("avdd_cam2", NULL),
291 };
292
293 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
294         {
295                 .src = FPS_SRC_0,
296                 .en_src = FPS_EN_SRC_EN0,
297                 .time_period = FPS_TIME_PERIOD_DEF,
298         },
299         {
300                 .src = FPS_SRC_1,
301                 .en_src = FPS_EN_SRC_EN1,
302                 .time_period = FPS_TIME_PERIOD_DEF,
303         },
304         {
305                 .src = FPS_SRC_2,
306                 .en_src = FPS_EN_SRC_EN0,
307                 .time_period = FPS_TIME_PERIOD_DEF,
308         },
309 };
310
311 #define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg,   \
312                 _always_on, _boot_on, _apply_uV,                        \
313                 _fps_src, _fps_pu_period, _fps_pd_period, _flags)       \
314         static struct regulator_init_data max77663_regulator_idata_##_id = {   \
315                 .supply_regulator = _supply_reg,                        \
316                 .constraints = {                                        \
317                         .name = max77663_rails(_id),                    \
318                         .min_uV = _min_uV,                              \
319                         .max_uV = _max_uV,                              \
320                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
321                                              REGULATOR_MODE_STANDBY),   \
322                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
323                                            REGULATOR_CHANGE_STATUS |    \
324                                            REGULATOR_CHANGE_VOLTAGE),   \
325                         .always_on = _always_on,                        \
326                         .boot_on = _boot_on,                            \
327                         .apply_uV = _apply_uV,                          \
328                 },                                                      \
329                 .num_consumer_supplies =                                \
330                         ARRAY_SIZE(max77663_##_id##_supply),            \
331                 .consumer_supplies = max77663_##_id##_supply,           \
332         };                                                              \
333 static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id =\
334 {                                                                       \
335                 .reg_init_data = &max77663_regulator_idata_##_id,       \
336                 .id = MAX77663_REGULATOR_ID_##_rid,                     \
337                 .fps_src = _fps_src,                                    \
338                 .fps_pu_period = _fps_pu_period,                        \
339                 .fps_pd_period = _fps_pd_period,                        \
340                 .fps_cfgs = max77663_fps_cfgs,                          \
341                 .flags = _flags,                                        \
342         }
343
344 MAX77663_PDATA_INIT(SD0, sd0,  900000, 1400000, tps65090_rails(DCDC3), 1, 1, 0,
345                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
346
347 MAX77663_PDATA_INIT(SD1, sd1,  1200000, 1200000, tps65090_rails(DCDC3), 1, 1, 1,
348                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
349
350 MAX77663_PDATA_INIT(SD2, sd2,  1800000, 1800000, tps65090_rails(DCDC3), 1, 1, 1,
351                     FPS_SRC_0, -1, -1, 0);
352
353 MAX77663_PDATA_INIT(SD3, sd3,  2850000, 2850000, tps65090_rails(DCDC3), 1, 1, 1,
354                     FPS_SRC_NONE, -1, -1, 0);
355
356 MAX77663_PDATA_INIT(LDO0, ldo0, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
357                     FPS_SRC_1, -1, -1, 0);
358
359 MAX77663_PDATA_INIT(LDO1, ldo1, 1050000, 1050000, max77663_rails(sd2), 0, 0, 1,
360                     FPS_SRC_NONE, -1, -1, 0);
361
362 MAX77663_PDATA_INIT(LDO2, ldo2, 2850000, 2850000, tps65090_rails(DCDC2), 1, 1,
363                     1, FPS_SRC_1, -1, -1, 0);
364
365 MAX77663_PDATA_INIT(LDO3, ldo3, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
366                     FPS_SRC_NONE, -1, -1, 0);
367
368 MAX77663_PDATA_INIT(LDO4, ldo4, 1100000, 1100000, tps65090_rails(DCDC2), 1, 1,
369                     1, FPS_SRC_NONE, -1, -1, 0);
370
371 MAX77663_PDATA_INIT(LDO5, ldo5, 1200000, 1200000, max77663_rails(sd2), 0, 1, 1,
372                     FPS_SRC_NONE, -1, -1, 0);
373
374 MAX77663_PDATA_INIT(LDO6, ldo6, 1800000, 3300000, tps65090_rails(DCDC2), 0, 0, 0,
375                     FPS_SRC_NONE, -1, -1, 0);
376
377 MAX77663_PDATA_INIT(LDO7, ldo7, 2800000, 2800000, tps65090_rails(DCDC2), 0, 0, 1,
378                     FPS_SRC_NONE, -1, -1, 0);
379
380 MAX77663_PDATA_INIT(LDO8, ldo8, 2800000, 2800000, tps65090_rails(DCDC2), 0, 1, 1,
381                     FPS_SRC_1, -1, -1, 0);
382
383 #define MAX77663_REG(_id, _data) (&max77663_regulator_pdata_##_data)
384
385 static struct max77663_regulator_platform_data *max77663_reg_pdata[] = {
386         MAX77663_REG(SD0, sd0),
387         MAX77663_REG(SD1, sd1),
388         MAX77663_REG(SD2, sd2),
389         MAX77663_REG(SD3, sd3),
390         MAX77663_REG(LDO0, ldo0),
391         MAX77663_REG(LDO1, ldo1),
392         MAX77663_REG(LDO2, ldo2),
393         MAX77663_REG(LDO3, ldo3),
394         MAX77663_REG(LDO4, ldo4),
395         MAX77663_REG(LDO5, ldo5),
396         MAX77663_REG(LDO6, ldo6),
397         MAX77663_REG(LDO7, ldo7),
398         MAX77663_REG(LDO8, ldo8),
399 };
400
401 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
402         {
403                 .gpio = MAX77663_GPIO0,
404                 .dir = GPIO_DIR_OUT,
405                 .dout = GPIO_DOUT_LOW,
406                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
407                 .alternate = GPIO_ALT_DISABLE,
408         },
409         {
410                 .gpio = MAX77663_GPIO1,
411                 .dir = GPIO_DIR_IN,
412                 .dout = GPIO_DOUT_HIGH,
413                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
414                 .pull_up = GPIO_PU_ENABLE,
415                 .alternate = GPIO_ALT_DISABLE,
416         },
417         {
418                 .gpio = MAX77663_GPIO2,
419                 .dir = GPIO_DIR_OUT,
420                 .dout = GPIO_DOUT_HIGH,
421                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
422                 .pull_up = GPIO_PU_ENABLE,
423                 .alternate = GPIO_ALT_DISABLE,
424         },
425         {
426                 .gpio = MAX77663_GPIO3,
427                 .dir = GPIO_DIR_OUT,
428                 .dout = GPIO_DOUT_HIGH,
429                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
430                 .pull_up = GPIO_PU_ENABLE,
431                 .alternate = GPIO_ALT_DISABLE,
432         },
433         {
434                 .gpio = MAX77663_GPIO4,
435                 .dir = GPIO_DIR_OUT,
436                 .dout = GPIO_DOUT_HIGH,
437                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
438                 .alternate = GPIO_ALT_ENABLE,
439         },
440         {
441                 .gpio = MAX77663_GPIO5,
442                 .dir = GPIO_DIR_OUT,
443                 .dout = GPIO_DOUT_LOW,
444                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
445                 .alternate = GPIO_ALT_DISABLE,
446         },
447         {
448                 .gpio = MAX77663_GPIO6,
449                 .dir = GPIO_DIR_OUT,
450                 .dout = GPIO_DOUT_LOW,
451                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
452                 .alternate = GPIO_ALT_DISABLE,
453         },
454         {
455                 .gpio = MAX77663_GPIO7,
456                 .dir = GPIO_DIR_OUT,
457                 .dout = GPIO_DOUT_LOW,
458                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
459                 .alternate = GPIO_ALT_DISABLE,
460         },
461 };
462
463 static struct max77663_platform_data max77663_pdata = {
464         .irq_base       = MAX77663_IRQ_BASE,
465         .gpio_base      = MAX77663_GPIO_BASE,
466
467         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
468         .gpio_cfgs      = max77663_gpio_cfgs,
469
470         .regulator_pdata = max77663_reg_pdata,
471         .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata),
472
473         .rtc_i2c_addr   = 0x68,
474
475         .use_power_off  = false,
476 };
477
478 static struct i2c_board_info __initdata max77663_regulators[] = {
479         {
480                 /* The I2C address was determined by OTP factory setting */
481                 I2C_BOARD_INFO("max77663", 0x3c),
482                 .irq            = INT_EXTERNAL_PMU,
483                 .platform_data  = &max77663_pdata,
484         },
485 };
486
487 static struct i2c_board_info __initdata tps65090_regulators[] = {
488         {
489                 I2C_BOARD_INFO("tps65090", 0x48),
490                 .platform_data  = &tps65090_pdata,
491         },
492 };
493
494 /* TPS51632 DC-DC converter */
495 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
496         REGULATOR_SUPPLY("vdd_cpu", NULL),
497 };
498
499 static struct regulator_init_data tps51632_init_data = {
500         .constraints = {                                                \
501                 .min_uV = 500000,                                       \
502                 .max_uV = 1520000,                                      \
503                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
504                                         REGULATOR_MODE_STANDBY),        \
505                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
506                                         REGULATOR_CHANGE_STATUS |       \
507                                         REGULATOR_CHANGE_VOLTAGE),      \
508                 .always_on = 1,                                         \
509                 .boot_on =  1,                                          \
510                 .apply_uV = 0,                                          \
511         },                                                              \
512         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
513                 .consumer_supplies = tps51632_dcdc_supply,              \
514 };
515
516 static struct tps51632_regulator_platform_data tps51632_pdata = {
517         .reg_init_data = &tps51632_init_data,           \
518         .enable_pwm = false,                            \
519         .max_voltage_uV = 1520000,                      \
520         .base_voltage_uV = 500000,                      \
521         .slew_rate_uv_per_us = 6000,                    \
522 };
523
524 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
525         {
526                 I2C_BOARD_INFO("tps51632", 0x43),
527                 .platform_data  = &tps51632_pdata,
528         },
529 };
530
531 /************************ Palmas based regulator ****************/
532 static struct regulator_consumer_supply palmas_smps12_supply[] = {
533         REGULATOR_SUPPLY("vddio_ddr3l", NULL),
534         REGULATOR_SUPPLY("vcore_ddr3l", NULL),
535         REGULATOR_SUPPLY("vref2_ddr3l", NULL),
536 };
537
538 #define palmas_smps3_supply max77663_sd2_supply
539 #define palmas_smps45_supply max77663_sd0_supply
540
541 static struct regulator_consumer_supply palmas_smps8_supply[] = {
542         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
543         REGULATOR_SUPPLY("avdd_pllm", NULL),
544         REGULATOR_SUPPLY("avdd_pllu", NULL),
545         REGULATOR_SUPPLY("avdd_pllx", NULL),
546         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
547         REGULATOR_SUPPLY("avdd_plle", NULL),
548         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
549         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
550         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
551         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
552         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
553         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
554
555 };
556
557 static struct regulator_consumer_supply palmas_smps9_supply[] = {
558         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
559 };
560
561 #define palmas_ldo1_supply max77663_ldo7_supply
562 #define palmas_ldo2_supply max77663_ldo8_supply
563 #define palmas_ldo3_supply max77663_ldo5_supply
564
565 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
566         REGULATOR_SUPPLY("vpp_fuse", NULL),
567 };
568
569 #define palmas_ldo6_supply max77663_ldo2_supply
570
571 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
572         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
573 };
574
575 #define palmas_ldo8_supply max77663_ldo4_supply
576 #define palmas_ldo9_supply max77663_ldo6_supply
577
578 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
579         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
580 };
581
582 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
583         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
584         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
585         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
586         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
587         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
588 };
589
590 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
591         _boot_on, _apply_uv)                                            \
592         static struct regulator_init_data reg_idata_##_name = {         \
593                 .constraints = {                                        \
594                         .name = palmas_rails(_name),                    \
595                         .min_uV = (_minmv)*1000,                        \
596                         .max_uV = (_maxmv)*1000,                        \
597                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
598                                         REGULATOR_MODE_STANDBY),        \
599                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
600                                         REGULATOR_CHANGE_STATUS |       \
601                                         REGULATOR_CHANGE_VOLTAGE),      \
602                         .always_on = _always_on,                        \
603                         .boot_on = _boot_on,                            \
604                         .apply_uV = _apply_uv,                          \
605                 },                                                      \
606                 .num_consumer_supplies =                                \
607                         ARRAY_SIZE(palmas_##_name##_supply),            \
608                 .consumer_supplies = palmas_##_name##_supply,           \
609                 .supply_regulator = _supply_reg,                        \
610         }
611
612 PALMAS_PDATA_INIT(smps12, 1350,  1350, tps65090_rails(DCDC3), 0, 0, 0);
613 PALMAS_PDATA_INIT(smps3, 1800,  1800, tps65090_rails(DCDC3), 0, 0, 0);
614 PALMAS_PDATA_INIT(smps45, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0);
615 PALMAS_PDATA_INIT(smps8, 1050,  1050, tps65090_rails(DCDC2), 0, 1, 1);
616 PALMAS_PDATA_INIT(smps9, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 0);
617 PALMAS_PDATA_INIT(ldo1, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
618 PALMAS_PDATA_INIT(ldo2, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
619 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps3), 0, 0, 1);
620 PALMAS_PDATA_INIT(ldo4, 1800,  1800, tps65090_rails(DCDC2), 0, 0, 0);
621 PALMAS_PDATA_INIT(ldo6, 2850,  2850, tps65090_rails(DCDC2), 0, 0, 1);
622 PALMAS_PDATA_INIT(ldo7, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
623 PALMAS_PDATA_INIT(ldo8, 900,  900, tps65090_rails(DCDC3), 1, 1, 1);
624 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
625 PALMAS_PDATA_INIT(ldoln, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1);
626 PALMAS_PDATA_INIT(ldousb, 3300,  3300, tps65090_rails(DCDC1), 0, 0, 1);
627
628 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
629
630 static struct regulator_init_data *dalmore_e1611_reg_data[PALMAS_NUM_REGS] = {
631         PALMAS_REG_PDATA(smps12),
632         NULL,
633         PALMAS_REG_PDATA(smps3),
634         PALMAS_REG_PDATA(smps45),
635         NULL,
636         NULL,
637         NULL,
638         PALMAS_REG_PDATA(smps8),
639         PALMAS_REG_PDATA(smps9),
640         NULL,
641         PALMAS_REG_PDATA(ldo1),
642         PALMAS_REG_PDATA(ldo2),
643         PALMAS_REG_PDATA(ldo3),
644         PALMAS_REG_PDATA(ldo4),
645         NULL,
646         PALMAS_REG_PDATA(ldo6),
647         PALMAS_REG_PDATA(ldo7),
648         PALMAS_REG_PDATA(ldo8),
649         PALMAS_REG_PDATA(ldo9),
650         PALMAS_REG_PDATA(ldoln),
651         PALMAS_REG_PDATA(ldousb),
652         NULL,
653         NULL,
654         NULL,
655         NULL,
656         NULL,
657 };
658
659 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
660                 _tstep, _vsel)                                          \
661         static struct palmas_reg_init reg_init_data_##_name = {         \
662                 .warm_reset = _warm_reset,                              \
663                 .roof_floor =   _roof_floor,                            \
664                 .mode_sleep = _mode_sleep,                              \
665                 .tstep = _tstep,                                        \
666                 .vsel = _vsel,                                          \
667         }
668
669 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
670 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
671 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
672 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
673 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
674 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
675 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
676 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
677 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
678 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
679 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
680 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
681 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
682 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
683 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
684 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
685 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
686 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
687 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
688 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
689 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
690 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
691 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
692 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
693 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
694 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
695
696 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
697 static struct palmas_reg_init *dalmore_e1611_reg_init[PALMAS_NUM_REGS] = {
698         PALMAS_REG_INIT_DATA(smps12),
699         PALMAS_REG_INIT_DATA(smps123),
700         PALMAS_REG_INIT_DATA(smps3),
701         PALMAS_REG_INIT_DATA(smps45),
702         PALMAS_REG_INIT_DATA(smps457),
703         PALMAS_REG_INIT_DATA(smps6),
704         PALMAS_REG_INIT_DATA(smps7),
705         PALMAS_REG_INIT_DATA(smps8),
706         PALMAS_REG_INIT_DATA(smps9),
707         PALMAS_REG_INIT_DATA(smps10),
708         PALMAS_REG_INIT_DATA(ldo1),
709         PALMAS_REG_INIT_DATA(ldo2),
710         PALMAS_REG_INIT_DATA(ldo3),
711         PALMAS_REG_INIT_DATA(ldo4),
712         PALMAS_REG_INIT_DATA(ldo5),
713         PALMAS_REG_INIT_DATA(ldo6),
714         PALMAS_REG_INIT_DATA(ldo7),
715         PALMAS_REG_INIT_DATA(ldo8),
716         PALMAS_REG_INIT_DATA(ldo9),
717         PALMAS_REG_INIT_DATA(ldoln),
718         PALMAS_REG_INIT_DATA(ldousb),
719         PALMAS_REG_INIT_DATA(regen1),
720         PALMAS_REG_INIT_DATA(regen2),
721         PALMAS_REG_INIT_DATA(regen3),
722         PALMAS_REG_INIT_DATA(sysen1),
723         PALMAS_REG_INIT_DATA(sysen2),
724 };
725
726 static struct palmas_pmic_platform_data pmic_platform = {
727         .enable_ldo8_tracking = true,
728         .disabe_ldo8_tracking_suspend = true,
729 };
730
731 static struct palmas_platform_data palmas_pdata = {
732         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
733         .irq_base = PALMAS_TEGRA_IRQ_BASE,
734         .pmic_pdata = &pmic_platform,
735         .mux_from_pdata = true,
736         .pad1 = 0,
737         .pad2 = 0,
738         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
739 };
740
741 static struct i2c_board_info palma_device[] = {
742         {
743                 I2C_BOARD_INFO("tps65913", 0x58),
744                 .irq            = INT_EXTERNAL_PMU,
745                 .platform_data  = &palmas_pdata,
746         },
747 };
748
749 /* EN_AVDD_USB_HDMI From PMU GP1 */
750 static struct regulator_consumer_supply fixed_reg_avdd_usb_hdmi_supply[] = {
751         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
752         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
753         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
754         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
755         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
756         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
757 };
758
759 /* EN_CAM_1v8 From PMU GP5 */
760 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
761         REGULATOR_SUPPLY("dvdd_cam", NULL),
762         REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
763 };
764
765 /* EN_CAM_1v8 on e1611 From PMU GP6 */
766 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_e1611_supply[] = {
767         REGULATOR_SUPPLY("dvdd_cam", NULL),
768         REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
769 };
770
771 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
772         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
773 };
774
775 /* EN_USB1_VBUS From TEGRA GPIO PN4 PR3(T30) */
776 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
777         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
778 };
779
780 /* EN_3V3_FUSE From TEGRA GPIO PX4 */
781 static struct regulator_consumer_supply fixed_reg_vpp_fuse_supply[] = {
782         REGULATOR_SUPPLY("vpp_fuse", NULL),
783 };
784
785 /* EN_USB3_VBUS From TEGRA GPIO PM5 */
786 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
787         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
788 };
789
790 /* Macro for defining fixed regulator sub device data */
791 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
792 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
793         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
794         static struct regulator_init_data ri_data_##_var =              \
795         {                                                               \
796                 .supply_regulator = _in_supply,                         \
797                 .num_consumer_supplies =                                \
798                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
799                 .consumer_supplies = fixed_reg_##_name##_supply,        \
800                 .constraints = {                                        \
801                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
802                                         REGULATOR_MODE_STANDBY),        \
803                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
804                                         REGULATOR_CHANGE_STATUS |       \
805                                         REGULATOR_CHANGE_VOLTAGE),      \
806                         .always_on = _always_on,                        \
807                         .boot_on = _boot_on,                            \
808                 },                                                      \
809         };                                                              \
810         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
811         {                                                               \
812                 .supply_name = FIXED_SUPPLY(_name),                     \
813                 .microvolts = _millivolts * 1000,                       \
814                 .gpio = _gpio_nr,                                       \
815                 .gpio_is_open_drain = _open_drain,                      \
816                 .enable_high = _active_high,                            \
817                 .enabled_at_boot = _boot_state,                         \
818                 .init_data = &ri_data_##_var,                           \
819         };                                                              \
820         static struct platform_device fixed_reg_##_var##_dev = {        \
821                 .name = "reg-fixed-voltage",                            \
822                 .id = _id,                                              \
823                 .dev = {                                                \
824                         .platform_data = &fixed_reg_##_var##_pdata,     \
825                 },                                                      \
826         }
827
828 FIXED_REG(1,    avdd_usb_hdmi,  avdd_usb_hdmi,
829         tps65090_rails(DCDC2),  0,      0,
830         MAX77663_GPIO_BASE + MAX77663_GPIO1,    true,   true,   1,      3300);
831
832 FIXED_REG(2,    en_1v8_cam,     en_1v8_cam,
833         max77663_rails(sd2),    0,      0,
834         MAX77663_GPIO_BASE + MAX77663_GPIO5,    false,  true,   0,      1800);
835
836 FIXED_REG(3,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
837         tps65090_rails(DCDC1),  0,      0,
838         TEGRA_GPIO_PK1, false,  true,   0,      5000);
839
840 FIXED_REG(4,    vpp_fuse,       vpp_fuse,
841         max77663_rails(sd2),    0,      0,
842         TEGRA_GPIO_PX4, false,  true,   0,      3300);
843
844 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
845 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
846         tps65090_rails(DCDC1),  0,      0,
847         TEGRA_GPIO_PN4, true,   true,   0,      5000);
848 #else
849 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
850         tps65090_rails(DCDC1),  0,      0,
851         TEGRA_GPIO_PR3, true,   true,   0,      5000);
852 #endif
853
854 FIXED_REG(6,    usb3_vbus,      usb3_vbus,
855         tps65090_rails(DCDC1),  0,      0,
856         TEGRA_GPIO_PK6, true,   true,   0,      5000);
857
858 FIXED_REG(7,    en_1v8_cam_e1611,       en_1v8_cam_e1611,
859         palmas_rails(smps3),    0,      0,
860         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
861
862 /*
863  * Creating the fixed regulator device tables
864  */
865
866 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
867
868 #define DALMORE_COMMON_FIXED_REG                \
869         ADD_FIXED_REG(usb1_vbus),               \
870         ADD_FIXED_REG(usb3_vbus),               \
871         ADD_FIXED_REG(vdd_hdmi_5v0),
872
873 #define E1612_FIXED_REG                         \
874         ADD_FIXED_REG(avdd_usb_hdmi),           \
875         ADD_FIXED_REG(en_1v8_cam),              \
876         ADD_FIXED_REG(vpp_fuse),                \
877
878 #define E1611_FIXED_REG                         \
879         ADD_FIXED_REG(en_1v8_cam_e1611),
880
881 /* Gpio switch regulator platform data for Dalmore E1611 */
882 static struct platform_device *fixed_reg_devs_e1611_a00[] = {
883         DALMORE_COMMON_FIXED_REG
884         E1611_FIXED_REG
885 };
886
887 /* Gpio switch regulator platform data for Dalmore E1612 */
888 static struct platform_device *fixed_reg_devs_e1612_a00[] = {
889         DALMORE_COMMON_FIXED_REG
890         E1612_FIXED_REG
891 };
892
893 int __init dalmore_palmas_regulator_init(void)
894 {
895         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
896         u32 pmc_ctrl;
897         int i;
898 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
899         int ret;
900
901         ret = gpio_request(TEGRA_GPIO_PCC3, "pmic_nreswarm");
902         if (ret < 0)
903                 pr_err("%s: gpio_request failed for gpio %d\n",
904                                 __func__, TEGRA_GPIO_PCC3);
905         else
906                 gpio_direction_output(TEGRA_GPIO_PCC3, 1);
907 #endif
908         /* TPS65913: Normal state of INT request line is LOW.
909          * configure the power management controller to trigger PMU
910          * interrupts when HIGH.
911          */
912         pmc_ctrl = readl(pmc + PMC_CTRL);
913         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
914         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
915                 pmic_platform.reg_data[i] = dalmore_e1611_reg_data[i];
916                 pmic_platform.reg_init[i] = dalmore_e1611_reg_init[i];
917         }
918
919         i2c_register_board_info(4, palma_device,
920                         ARRAY_SIZE(palma_device));
921         return 0;
922 }
923
924 static int ac_online(void)
925 {
926         return 1;
927 }
928
929 static struct resource dalmore_pda_resources[] = {
930         [0] = {
931                 .name   = "ac",
932         },
933 };
934
935 static struct pda_power_pdata dalmore_pda_data = {
936         .is_ac_online   = ac_online,
937 };
938
939 static struct platform_device dalmore_pda_power_device = {
940         .name           = "pda-power",
941         .id             = -1,
942         .resource       = dalmore_pda_resources,
943         .num_resources  = ARRAY_SIZE(dalmore_pda_resources),
944         .dev    = {
945                 .platform_data  = &dalmore_pda_data,
946         },
947 };
948
949 static struct tegra_suspend_platform_data dalmore_suspend_data = {
950         .cpu_timer      = 300,
951         .cpu_off_timer  = 300,
952         .suspend_mode   = TEGRA_SUSPEND_LP0,
953         .core_timer     = 0x157e,
954         .core_off_timer = 2000,
955         .corereq_high   = true,
956         .sysclkreq_high = true,
957         .min_residency_noncpu = 600,
958         .min_residency_crail = 1000,
959 };
960 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
961 /* board parameters for cpu dfll */
962 static struct tegra_cl_dvfs_cfg_param dalmore_cl_dvfs_param = {
963         .sample_rate = 12500,
964
965         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
966         .cf = 10,
967         .ci = 0,
968         .cg = 2,
969
970         .droop_cut_value = 0xF,
971         .droop_restore_ramp = 0x0,
972         .scale_out_ramp = 0x0,
973 };
974 #endif
975
976 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
977 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
978 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
979 static inline void fill_reg_map(void)
980 {
981         int i;
982         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
983                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
984                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
985         }
986 }
987
988 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
989 static struct tegra_cl_dvfs_platform_data dalmore_cl_dvfs_data = {
990         .dfll_clk_name = "dfll_cpu",
991         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
992         .u.pmu_i2c = {
993                 .fs_rate = 400000,
994                 .slave_addr = 0x86,
995                 .reg = 0x00,
996         },
997         .vdd_map = pmu_cpu_vdd_map,
998         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
999
1000         .cfg_param = &dalmore_cl_dvfs_param,
1001 };
1002
1003 static int __init dalmore_cl_dvfs_init(void)
1004 {
1005         fill_reg_map();
1006         tegra_cl_dvfs_device.dev.platform_data = &dalmore_cl_dvfs_data;
1007         platform_device_register(&tegra_cl_dvfs_device);
1008
1009         return 0;
1010 }
1011 #endif
1012
1013 static int __init dalmore_max77663_regulator_init(void)
1014 {
1015         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
1016         u32 pmc_ctrl;
1017
1018         /* configure the power management controller to trigger PMU
1019          * interrupts when low */
1020         pmc_ctrl = readl(pmc + PMC_CTRL);
1021         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
1022
1023         i2c_register_board_info(4, max77663_regulators,
1024                                 ARRAY_SIZE(max77663_regulators));
1025
1026         return 0;
1027 }
1028
1029 static struct regulator_bulk_data dalmore_gps_regulator_supply[] = {
1030         [0] = {
1031                 .supply = "vdd_gps_3v3",
1032         },
1033         [1] = {
1034                 .supply = "vdd_gps_1v8",
1035         },
1036 };
1037
1038 static struct regulator_userspace_consumer_data dalmore_gps_regulator_pdata = {
1039         .num_supplies   = ARRAY_SIZE(dalmore_gps_regulator_supply),
1040         .supplies       = dalmore_gps_regulator_supply,
1041 };
1042
1043 static struct platform_device dalmore_gps_regulator_device = {
1044         .name   = "reg-userspace-consumer",
1045         .id     = 2,
1046         .dev    = {
1047                         .platform_data = &dalmore_gps_regulator_pdata,
1048         },
1049 };
1050
1051 static struct regulator_bulk_data dalmore_bt_regulator_supply[] = {
1052         [0] = {
1053                 .supply = "vdd_bt_3v3",
1054         },
1055         [1] = {
1056                 .supply = "vddio_bt_1v8",
1057         },
1058 };
1059
1060 static struct regulator_userspace_consumer_data dalmore_bt_regulator_pdata = {
1061         .num_supplies   = ARRAY_SIZE(dalmore_bt_regulator_supply),
1062         .supplies       = dalmore_bt_regulator_supply,
1063 };
1064
1065 static struct platform_device dalmore_bt_regulator_device = {
1066         .name   = "reg-userspace-consumer",
1067         .id     = 1,
1068         .dev    = {
1069                         .platform_data = &dalmore_bt_regulator_pdata,
1070         },
1071 };
1072
1073 static int __init dalmore_fixed_regulator_init(void)
1074 {
1075         struct board_info board_info;
1076
1077         if (!machine_is_dalmore())
1078                 return 0;
1079
1080         tegra_get_board_info(&board_info);
1081
1082         if (board_info.board_id == BOARD_E1611)
1083                 return platform_add_devices(fixed_reg_devs_e1611_a00,
1084                                 ARRAY_SIZE(fixed_reg_devs_e1611_a00));
1085         else
1086                 return platform_add_devices(fixed_reg_devs_e1612_a00,
1087                                 ARRAY_SIZE(fixed_reg_devs_e1612_a00));
1088 }
1089 subsys_initcall_sync(dalmore_fixed_regulator_init);
1090
1091 int __init dalmore_regulator_init(void)
1092 {
1093         struct board_info board_info;
1094         i2c_register_board_info(4, tps65090_regulators,
1095                         ARRAY_SIZE(tps65090_regulators));
1096 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1097         dalmore_cl_dvfs_init();
1098 #endif
1099         tegra_get_board_info(&board_info);
1100         if (board_info.board_id == BOARD_E1611)
1101                 dalmore_palmas_regulator_init();
1102         else
1103                 dalmore_max77663_regulator_init();
1104
1105         i2c_register_board_info(4, tps51632_boardinfo, 1);
1106         platform_device_register(&dalmore_pda_power_device);
1107         platform_device_register(&dalmore_bt_regulator_device);
1108         platform_device_register(&dalmore_gps_regulator_device);
1109         return 0;
1110 }
1111
1112 int __init dalmore_suspend_init(void)
1113 {
1114         tegra_init_suspend(&dalmore_suspend_data);
1115         return 0;
1116 }
1117
1118 int __init dalmore_edp_init(void)
1119 {
1120 #ifdef CONFIG_TEGRA_EDP_LIMITS
1121         unsigned int regulator_mA;
1122
1123         regulator_mA = get_maximum_cpu_current_supported();
1124         if (!regulator_mA)
1125                 regulator_mA = 15000;
1126
1127         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1128
1129         tegra_init_cpu_edp_limits(regulator_mA);
1130 #endif
1131         return 0;
1132 }
1133
1134 static struct soctherm_platform_data dalmore_soctherm_data = {
1135         .soctherm_clk_rate = 136000000,
1136         .tsensor_clk_rate = 500000,
1137         .sensor_data = {
1138                 [TSENSE_CPU0] = {
1139                         .enable = true,
1140                         .therm_a = 570,
1141                         .therm_b = -744,
1142                         .tall = 16300,
1143                         .tiddq = 1,
1144                         .ten_count = 1,
1145                         .tsample = 163,
1146                         .pdiv = 10,
1147                 },
1148                 [TSENSE_CPU1] = {
1149                         .enable = true,
1150                         .therm_a = 570,
1151                         .therm_b = -744,
1152                         .tall = 16300,
1153                         .tiddq = 1,
1154                         .ten_count = 1,
1155                         .tsample = 163,
1156                         .pdiv = 10,
1157                 },
1158                 [TSENSE_CPU2] = {
1159                         .enable = true,
1160                         .therm_a = 570,
1161                         .therm_b = -744,
1162                         .tall = 16300,
1163                         .tiddq = 1,
1164                         .ten_count = 1,
1165                         .tsample = 163,
1166                         .pdiv = 10,
1167                 },
1168                 [TSENSE_CPU3] = {
1169                         .enable = true,
1170                         .therm_a = 570,
1171                         .therm_b = -744,
1172                         .tall = 16300,
1173                         .tiddq = 1,
1174                         .ten_count = 1,
1175                         .tsample = 163,
1176                         .pdiv = 10,
1177                 },
1178                 [TSENSE_MEM0] = {
1179                         .enable = true,
1180                         .therm_a = 570,
1181                         .therm_b = -744,
1182                         .tall = 16300,
1183                         .tiddq = 1,
1184                         .ten_count = 1,
1185                         .tsample = 163,
1186                         .pdiv = 10,
1187                 },
1188                 [TSENSE_MEM1] = {
1189                         .enable = true,
1190                         .therm_a = 570,
1191                         .therm_b = -744,
1192                         .tall = 16300,
1193                         .tiddq = 1,
1194                         .ten_count = 1,
1195                         .tsample = 163,
1196                         .pdiv = 10,
1197                 },
1198                 [TSENSE_GPU] = {
1199                         .enable = true,
1200                         .therm_a = 570,
1201                         .therm_b = -744,
1202                         .tall = 16300,
1203                         .tiddq = 1,
1204                         .ten_count = 1,
1205                         .tsample = 163,
1206                         .pdiv = 10,
1207                 },
1208                 [TSENSE_PLLX] = {
1209                         .enable = true,
1210                         .therm_a = 570,
1211                         .therm_b = -744,
1212                         .tall = 16300,
1213                         .tiddq = 1,
1214                         .ten_count = 1,
1215                         .tsample = 163,
1216                         .pdiv = 10,
1217                 },
1218         },
1219
1220         .therm = {
1221                 [THERM_CPU] = {
1222                         .thermtrip = 90, /* in C */
1223                         .hw_backstop = 37, /* in C */
1224
1225                         .trip_temp = 68000, /* in mC */
1226                         .tc1 = 0,
1227                         .tc2 = 1,
1228                         .passive_delay = 2000,
1229                 },
1230         },
1231
1232         .throttle = {
1233                 [THROTTLE_HEAVY] = {
1234                         .priority = 1,
1235                         .devs = {
1236                                 [THROTTLE_DEV_CPU] = {
1237                                         .enable = true,
1238                                         .dividend = 1,
1239                                         .divisor = 255,
1240                                         .step = 0,
1241                                         .duration = 65535,
1242                                 },
1243                         },
1244                 },
1245         },
1246 };
1247
1248 static struct balanced_throttle tj_throttle = {
1249         .throt_tab_size = 10,
1250         .throt_tab = {
1251                 {      0, 1000 },
1252                 { 640000, 1000 },
1253                 { 640000, 1000 },
1254                 { 640000, 1000 },
1255                 { 640000, 1000 },
1256                 { 640000, 1000 },
1257                 { 760000, 1000 },
1258                 { 760000, 1050 },
1259                 {1000000, 1050 },
1260                 {1000000, 1100 },
1261         },
1262 };
1263
1264 static int __init dalmore_soctherm_init(void)
1265 {
1266         dalmore_soctherm_data.therm[THERM_CPU].cdev =
1267                         balanced_throttle_register(&tj_throttle);
1268
1269         return tegra11_soctherm_init(&dalmore_soctherm_data);
1270 }
1271 module_init(dalmore_soctherm_init);