ARM: tegra: soctherm: Enable THERMTRIP
[linux-3.10.git] / arch / arm / mach-tegra / board-dalmore-power.c
1 /*
2  * arch/arm/mach-tegra/board-dalmore-power.c
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/max77663-core.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/mfd/tps65090.h>
31 #include <linux/regulator/max77663-regulator.h>
32 #include <linux/regulator/tps65090-regulator.h>
33 #include <linux/regulator/tps51632-regulator.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/userspace-consumer.h>
36
37 #include <asm/mach-types.h>
38
39 #include <mach/iomap.h>
40 #include <mach/irqs.h>
41 #include <mach/edp.h>
42 #include <mach/gpio-tegra.h>
43
44 #include "pm.h"
45 #include "tegra-board-id.h"
46 #include "board.h"
47 #include "gpio-names.h"
48 #include "board-dalmore.h"
49 #include "tegra_cl_dvfs.h"
50 #include "devices.h"
51 #include "tegra11_soctherm.h"
52
53 #define PMC_CTRL                0x0
54 #define PMC_CTRL_INTR_LOW       (1 << 17)
55
56 /*TPS65090 consumer rails */
57 static struct regulator_consumer_supply tps65090_dcdc1_supply[] = {
58         REGULATOR_SUPPLY("vdd_sys_5v0", NULL),
59         REGULATOR_SUPPLY("vdd_spk", NULL),
60         REGULATOR_SUPPLY("vdd_sys_modem_5v0", NULL),
61         REGULATOR_SUPPLY("vdd_sys_cam_5v0", NULL),
62 };
63
64 static struct regulator_consumer_supply tps65090_dcdc2_supply[] = {
65         REGULATOR_SUPPLY("vdd_sys_3v3", NULL),
66         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
67         REGULATOR_SUPPLY("pwrdet_hv", NULL),
68         REGULATOR_SUPPLY("vdd_sys_ds_3v3", NULL),
69         REGULATOR_SUPPLY("vdd_sys_nfc_3v3", NULL),
70         REGULATOR_SUPPLY("vdd_hv_nfc_3v3", NULL),
71         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
72         REGULATOR_SUPPLY("vdd_sys_sensor_3v3", NULL),
73         REGULATOR_SUPPLY("vdd_sys_audio_3v3", NULL),
74         REGULATOR_SUPPLY("vdd_sys_dtv_3v3", NULL),
75         REGULATOR_SUPPLY("vcc", "0-007c"),
76         REGULATOR_SUPPLY("vcc", "0-0030"),
77 };
78
79 static struct regulator_consumer_supply tps65090_dcdc3_supply[] = {
80         REGULATOR_SUPPLY("vdd_ao", NULL),
81 };
82
83 static struct regulator_consumer_supply tps65090_ldo1_supply[] = {
84         REGULATOR_SUPPLY("vdd_sby_5v0", NULL),
85 };
86
87 static struct regulator_consumer_supply tps65090_ldo2_supply[] = {
88         REGULATOR_SUPPLY("vdd_sby_3v3", NULL),
89 };
90
91 static struct regulator_consumer_supply tps65090_fet1_supply[] = {
92         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
93 };
94
95 static struct regulator_consumer_supply tps65090_fet3_supply[] = {
96         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
97 };
98
99 static struct regulator_consumer_supply tps65090_fet4_supply[] = {
100         REGULATOR_SUPPLY("avdd_lcd", NULL),
101         REGULATOR_SUPPLY("vdd_ts_3v3", NULL),
102 };
103
104 static struct regulator_consumer_supply tps65090_fet5_supply[] = {
105         REGULATOR_SUPPLY("vdd_lvds", NULL),
106 };
107
108 static struct regulator_consumer_supply tps65090_fet6_supply[] = {
109         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
110 };
111
112 static struct regulator_consumer_supply tps65090_fet7_supply[] = {
113         REGULATOR_SUPPLY("vdd_wifi_3v3", NULL),
114         REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
115         REGULATOR_SUPPLY("vdd_bt_3v3", NULL),
116 };
117
118 #define TPS65090_PDATA_INIT(_id, _name, _supply_reg,                    \
119                 _always_on, _boot_on, _apply_uV, _en_ext_ctrl, _gpio)   \
120 static struct regulator_init_data ri_data_##_name =                     \
121 {                                                                       \
122         .supply_regulator = _supply_reg,                                \
123         .constraints = {                                                \
124                 .name = tps65090_rails(_id),                            \
125                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
126                                      REGULATOR_MODE_STANDBY),           \
127                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
128                                    REGULATOR_CHANGE_STATUS |            \
129                                    REGULATOR_CHANGE_VOLTAGE),           \
130                 .always_on = _always_on,                                \
131                 .boot_on = _boot_on,                                    \
132                 .apply_uV = _apply_uV,                                  \
133         },                                                              \
134         .num_consumer_supplies =                                        \
135                 ARRAY_SIZE(tps65090_##_name##_supply),                  \
136         .consumer_supplies = tps65090_##_name##_supply,                 \
137 };                                                                      \
138 static struct tps65090_regulator_platform_data                          \
139                         tps65090_regulator_pdata_##_name =              \
140 {                                                                       \
141         .id = TPS65090_REGULATOR_##_id,                                 \
142         .enable_ext_control = _en_ext_ctrl,                             \
143         .gpio = _gpio,                                                  \
144         .reg_init_data = &ri_data_##_name ,                             \
145 }
146
147 TPS65090_PDATA_INIT(DCDC1, dcdc1, NULL, 1, 1, 0, false, -1);
148 TPS65090_PDATA_INIT(DCDC2, dcdc2, NULL, 1, 1, 0, false, -1);
149 TPS65090_PDATA_INIT(DCDC3, dcdc3, NULL, 1, 1, 0, false, -1);
150 TPS65090_PDATA_INIT(LDO1, ldo1, NULL, 1, 1, 0, false, -1);
151 TPS65090_PDATA_INIT(LDO2, ldo2, NULL, 1, 1, 0, false, -1);
152 TPS65090_PDATA_INIT(FET1, fet1, NULL, 0, 0, 0, false, -1);
153 TPS65090_PDATA_INIT(FET3, fet3, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
154 TPS65090_PDATA_INIT(FET4, fet4, tps65090_rails(DCDC2), 1, 1, 0, false, -1); /* always_on and boot_on */
155 TPS65090_PDATA_INIT(FET5, fet5, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
156 TPS65090_PDATA_INIT(FET6, fet6, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
157 TPS65090_PDATA_INIT(FET7, fet7, tps65090_rails(DCDC2), 0, 0, 0, false, -1);
158
159 #define ADD_TPS65090_REG(_name) (&tps65090_regulator_pdata_##_name)
160 static struct tps65090_regulator_platform_data *tps65090_reg_pdata[] = {
161         ADD_TPS65090_REG(dcdc1),
162         ADD_TPS65090_REG(dcdc2),
163         ADD_TPS65090_REG(dcdc3),
164         ADD_TPS65090_REG(ldo1),
165         ADD_TPS65090_REG(ldo2),
166         ADD_TPS65090_REG(fet1),
167         ADD_TPS65090_REG(fet3),
168         ADD_TPS65090_REG(fet4),
169         ADD_TPS65090_REG(fet5),
170         ADD_TPS65090_REG(fet6),
171         ADD_TPS65090_REG(fet7),
172 };
173
174 static struct tps65090_platform_data tps65090_pdata = {
175         .irq_base = -1,
176         .num_reg_pdata =  ARRAY_SIZE(tps65090_reg_pdata),
177         .reg_pdata = tps65090_reg_pdata
178 };
179
180 /* MAX77663 consumer rails */
181 static struct regulator_consumer_supply max77663_sd0_supply[] = {
182         REGULATOR_SUPPLY("vdd_core", NULL),
183 };
184
185 static struct regulator_consumer_supply max77663_sd1_supply[] = {
186         REGULATOR_SUPPLY("vddio_ddr", NULL),
187         REGULATOR_SUPPLY("vddio_ddr0", NULL),
188         REGULATOR_SUPPLY("vddio_ddr1", NULL),
189 };
190
191 static struct regulator_consumer_supply max77663_sd2_supply[] = {
192         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
193         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
194         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
195         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
196         REGULATOR_SUPPLY("pwrdet_cam", NULL),
197         REGULATOR_SUPPLY("avdd_osc", NULL),
198         REGULATOR_SUPPLY("vddio_sys", NULL),
199         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
200         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
201         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
202         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
203         REGULATOR_SUPPLY("vdd_emmc", NULL),
204         REGULATOR_SUPPLY("vddio_audio", NULL),
205         REGULATOR_SUPPLY("pwrdet_audio", NULL),
206         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
207         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
208         REGULATOR_SUPPLY("vddio_modem", NULL),
209         REGULATOR_SUPPLY("vddio_modem_1v8", NULL),
210         REGULATOR_SUPPLY("vddio_bb", NULL),
211         REGULATOR_SUPPLY("pwrdet_bb", NULL),
212         REGULATOR_SUPPLY("vddio_bb_1v8", NULL),
213         REGULATOR_SUPPLY("vddio_uart", NULL),
214         REGULATOR_SUPPLY("pwrdet_uart", NULL),
215         REGULATOR_SUPPLY("vddio_gmi", NULL),
216         REGULATOR_SUPPLY("pwrdet_nand", NULL),
217         REGULATOR_SUPPLY("vdd_sensor_1v8", NULL),
218         REGULATOR_SUPPLY("vdd_mic_1v8", NULL),
219         REGULATOR_SUPPLY("vdd_nfc_1v8", NULL),
220         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
221         REGULATOR_SUPPLY("vdd_ts_1v8", NULL),
222         REGULATOR_SUPPLY("vdd_spi_1v8", NULL),
223         REGULATOR_SUPPLY("dvdd_lcd", NULL),
224         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
225         REGULATOR_SUPPLY("vddio_wifi_1v8", NULL),
226         REGULATOR_SUPPLY("vdd_gps_1v8", NULL),
227         REGULATOR_SUPPLY("vddio_bt_1v8", NULL),
228         REGULATOR_SUPPLY("vdd_dtv_1v8", NULL),
229 };
230
231 static struct regulator_consumer_supply max77663_sd3_supply[] = {
232         REGULATOR_SUPPLY("vcore_emmc", NULL),
233 };
234
235 static struct regulator_consumer_supply max77663_ldo0_supply[] = {
236         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
237         REGULATOR_SUPPLY("avdd_pllx", NULL),
238         REGULATOR_SUPPLY("avdd_plle", NULL),
239         REGULATOR_SUPPLY("avdd_pllm", NULL),
240         REGULATOR_SUPPLY("avdd_pllu", NULL),
241         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
242         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
243         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
244 };
245
246 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
247         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
248 };
249
250 static struct regulator_consumer_supply max77663_ldo2_supply[] = {
251         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
252         REGULATOR_SUPPLY("vdd_als", NULL),
253         REGULATOR_SUPPLY("vdd", "0-004c"),
254 };
255
256 static struct regulator_consumer_supply max77663_ldo3_supply[] = {
257         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
258         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
259         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
260 };
261
262 static struct regulator_consumer_supply max77663_ldo4_supply[] = {
263         REGULATOR_SUPPLY("vdd_rtc", NULL),
264 };
265
266 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
267         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
268         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
269         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
270         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
271         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
272         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
273         REGULATOR_SUPPLY("vddio_bb_hsic", NULL),
274 };
275
276 static struct regulator_consumer_supply max77663_ldo6_supply[] = {
277         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
278         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
279 };
280
281 /* FIXME!! Put the device address of camera */
282 static struct regulator_consumer_supply max77663_ldo7_supply[] = {
283         REGULATOR_SUPPLY("avdd_cam1", NULL),
284         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
285 };
286
287 /* FIXME!! Put the device address of camera */
288 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
289         REGULATOR_SUPPLY("avdd_cam2", NULL),
290 };
291
292 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
293         {
294                 .src = FPS_SRC_0,
295                 .en_src = FPS_EN_SRC_EN0,
296                 .time_period = FPS_TIME_PERIOD_DEF,
297         },
298         {
299                 .src = FPS_SRC_1,
300                 .en_src = FPS_EN_SRC_EN1,
301                 .time_period = FPS_TIME_PERIOD_DEF,
302         },
303         {
304                 .src = FPS_SRC_2,
305                 .en_src = FPS_EN_SRC_EN0,
306                 .time_period = FPS_TIME_PERIOD_DEF,
307         },
308 };
309
310 #define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg,   \
311                 _always_on, _boot_on, _apply_uV,                        \
312                 _fps_src, _fps_pu_period, _fps_pd_period, _flags)       \
313         static struct regulator_init_data max77663_regulator_idata_##_id = {   \
314                 .supply_regulator = _supply_reg,                        \
315                 .constraints = {                                        \
316                         .name = max77663_rails(_id),                    \
317                         .min_uV = _min_uV,                              \
318                         .max_uV = _max_uV,                              \
319                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
320                                              REGULATOR_MODE_STANDBY),   \
321                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
322                                            REGULATOR_CHANGE_STATUS |    \
323                                            REGULATOR_CHANGE_VOLTAGE),   \
324                         .always_on = _always_on,                        \
325                         .boot_on = _boot_on,                            \
326                         .apply_uV = _apply_uV,                          \
327                 },                                                      \
328                 .num_consumer_supplies =                                \
329                         ARRAY_SIZE(max77663_##_id##_supply),            \
330                 .consumer_supplies = max77663_##_id##_supply,           \
331         };                                                              \
332 static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id =\
333 {                                                                       \
334                 .reg_init_data = &max77663_regulator_idata_##_id,       \
335                 .id = MAX77663_REGULATOR_ID_##_rid,                     \
336                 .fps_src = _fps_src,                                    \
337                 .fps_pu_period = _fps_pu_period,                        \
338                 .fps_pd_period = _fps_pd_period,                        \
339                 .fps_cfgs = max77663_fps_cfgs,                          \
340                 .flags = _flags,                                        \
341         }
342
343 MAX77663_PDATA_INIT(SD0, sd0,  900000, 1400000, tps65090_rails(DCDC3), 1, 1, 0,
344                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
345
346 MAX77663_PDATA_INIT(SD1, sd1,  1200000, 1200000, tps65090_rails(DCDC3), 1, 1, 1,
347                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
348
349 MAX77663_PDATA_INIT(SD2, sd2,  1800000, 1800000, tps65090_rails(DCDC3), 1, 1, 1,
350                     FPS_SRC_0, -1, -1, 0);
351
352 MAX77663_PDATA_INIT(SD3, sd3,  2850000, 2850000, tps65090_rails(DCDC3), 1, 1, 1,
353                     FPS_SRC_NONE, -1, -1, 0);
354
355 MAX77663_PDATA_INIT(LDO0, ldo0, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
356                     FPS_SRC_1, -1, -1, 0);
357
358 MAX77663_PDATA_INIT(LDO1, ldo1, 1050000, 1050000, max77663_rails(sd2), 0, 0, 1,
359                     FPS_SRC_NONE, -1, -1, 0);
360
361 MAX77663_PDATA_INIT(LDO2, ldo2, 2850000, 2850000, tps65090_rails(DCDC2), 1, 1,
362                     1, FPS_SRC_1, -1, -1, 0);
363
364 MAX77663_PDATA_INIT(LDO3, ldo3, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
365                     FPS_SRC_NONE, -1, -1, 0);
366
367 MAX77663_PDATA_INIT(LDO4, ldo4, 1100000, 1100000, tps65090_rails(DCDC2), 1, 1,
368                     1, FPS_SRC_NONE, -1, -1, 0);
369
370 MAX77663_PDATA_INIT(LDO5, ldo5, 1200000, 1200000, max77663_rails(sd2), 0, 1, 1,
371                     FPS_SRC_NONE, -1, -1, 0);
372
373 MAX77663_PDATA_INIT(LDO6, ldo6, 1800000, 3300000, tps65090_rails(DCDC2), 0, 0, 0,
374                     FPS_SRC_NONE, -1, -1, 0);
375
376 MAX77663_PDATA_INIT(LDO7, ldo7, 2800000, 2800000, tps65090_rails(DCDC2), 0, 0, 1,
377                     FPS_SRC_NONE, -1, -1, 0);
378
379 MAX77663_PDATA_INIT(LDO8, ldo8, 2800000, 2800000, tps65090_rails(DCDC2), 0, 1, 1,
380                     FPS_SRC_1, -1, -1, 0);
381
382 #define MAX77663_REG(_id, _data) (&max77663_regulator_pdata_##_data)
383
384 static struct max77663_regulator_platform_data *max77663_reg_pdata[] = {
385         MAX77663_REG(SD0, sd0),
386         MAX77663_REG(SD1, sd1),
387         MAX77663_REG(SD2, sd2),
388         MAX77663_REG(SD3, sd3),
389         MAX77663_REG(LDO0, ldo0),
390         MAX77663_REG(LDO1, ldo1),
391         MAX77663_REG(LDO2, ldo2),
392         MAX77663_REG(LDO3, ldo3),
393         MAX77663_REG(LDO4, ldo4),
394         MAX77663_REG(LDO5, ldo5),
395         MAX77663_REG(LDO6, ldo6),
396         MAX77663_REG(LDO7, ldo7),
397         MAX77663_REG(LDO8, ldo8),
398 };
399
400 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
401         {
402                 .gpio = MAX77663_GPIO0,
403                 .dir = GPIO_DIR_OUT,
404                 .dout = GPIO_DOUT_LOW,
405                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
406                 .alternate = GPIO_ALT_DISABLE,
407         },
408         {
409                 .gpio = MAX77663_GPIO1,
410                 .dir = GPIO_DIR_IN,
411                 .dout = GPIO_DOUT_HIGH,
412                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
413                 .pull_up = GPIO_PU_ENABLE,
414                 .alternate = GPIO_ALT_DISABLE,
415         },
416         {
417                 .gpio = MAX77663_GPIO2,
418                 .dir = GPIO_DIR_OUT,
419                 .dout = GPIO_DOUT_HIGH,
420                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
421                 .pull_up = GPIO_PU_ENABLE,
422                 .alternate = GPIO_ALT_DISABLE,
423         },
424         {
425                 .gpio = MAX77663_GPIO3,
426                 .dir = GPIO_DIR_OUT,
427                 .dout = GPIO_DOUT_HIGH,
428                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
429                 .pull_up = GPIO_PU_ENABLE,
430                 .alternate = GPIO_ALT_DISABLE,
431         },
432         {
433                 .gpio = MAX77663_GPIO4,
434                 .dir = GPIO_DIR_OUT,
435                 .dout = GPIO_DOUT_HIGH,
436                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
437                 .alternate = GPIO_ALT_ENABLE,
438         },
439         {
440                 .gpio = MAX77663_GPIO5,
441                 .dir = GPIO_DIR_OUT,
442                 .dout = GPIO_DOUT_LOW,
443                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
444                 .alternate = GPIO_ALT_DISABLE,
445         },
446         {
447                 .gpio = MAX77663_GPIO6,
448                 .dir = GPIO_DIR_OUT,
449                 .dout = GPIO_DOUT_LOW,
450                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
451                 .alternate = GPIO_ALT_DISABLE,
452         },
453         {
454                 .gpio = MAX77663_GPIO7,
455                 .dir = GPIO_DIR_OUT,
456                 .dout = GPIO_DOUT_LOW,
457                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
458                 .alternate = GPIO_ALT_DISABLE,
459         },
460 };
461
462 static struct max77663_platform_data max77663_pdata = {
463         .irq_base       = MAX77663_IRQ_BASE,
464         .gpio_base      = MAX77663_GPIO_BASE,
465
466         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
467         .gpio_cfgs      = max77663_gpio_cfgs,
468
469         .regulator_pdata = max77663_reg_pdata,
470         .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata),
471
472         .rtc_i2c_addr   = 0x68,
473
474         .use_power_off  = false,
475 };
476
477 static struct i2c_board_info __initdata max77663_regulators[] = {
478         {
479                 /* The I2C address was determined by OTP factory setting */
480                 I2C_BOARD_INFO("max77663", 0x3c),
481                 .irq            = INT_EXTERNAL_PMU,
482                 .platform_data  = &max77663_pdata,
483         },
484 };
485
486 static struct i2c_board_info __initdata tps65090_regulators[] = {
487         {
488                 I2C_BOARD_INFO("tps65090", 0x48),
489                 .platform_data  = &tps65090_pdata,
490         },
491 };
492
493 /* TPS51632 DC-DC converter */
494 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
495         REGULATOR_SUPPLY("vdd_cpu", NULL),
496 };
497
498 static struct regulator_init_data tps51632_init_data = {
499         .constraints = {                                                \
500                 .min_uV = 500000,                                       \
501                 .max_uV = 1520000,                                      \
502                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
503                                         REGULATOR_MODE_STANDBY),        \
504                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
505                                         REGULATOR_CHANGE_STATUS |       \
506                                         REGULATOR_CHANGE_VOLTAGE),      \
507                 .always_on = 1,                                         \
508                 .boot_on =  1,                                          \
509                 .apply_uV = 0,                                          \
510         },                                                              \
511         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
512                 .consumer_supplies = tps51632_dcdc_supply,              \
513 };
514
515 static struct tps51632_regulator_platform_data tps51632_pdata = {
516         .reg_init_data = &tps51632_init_data,           \
517         .enable_pwm = false,                            \
518         .max_voltage_uV = 1520000,                      \
519         .base_voltage_uV = 500000,                      \
520         .slew_rate_uv_per_us = 6000,                    \
521 };
522
523 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
524         {
525                 I2C_BOARD_INFO("tps51632", 0x43),
526                 .platform_data  = &tps51632_pdata,
527         },
528 };
529
530 /************************ Palmas based regulator ****************/
531 static struct regulator_consumer_supply palmas_smps12_supply[] = {
532         REGULATOR_SUPPLY("vddio_ddr3l", NULL),
533         REGULATOR_SUPPLY("vcore_ddr3l", NULL),
534         REGULATOR_SUPPLY("vref2_ddr3l", NULL),
535 };
536
537 #define palmas_smps3_supply max77663_sd2_supply
538 #define palmas_smps45_supply max77663_sd0_supply
539
540 static struct regulator_consumer_supply palmas_smps8_supply[] = {
541         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
542         REGULATOR_SUPPLY("avdd_pllm", NULL),
543         REGULATOR_SUPPLY("avdd_pllu", NULL),
544         REGULATOR_SUPPLY("avdd_pllx", NULL),
545         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
546         REGULATOR_SUPPLY("avdd_plle", NULL),
547         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
548         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
549         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
550         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
551         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
552         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
553
554 };
555
556 static struct regulator_consumer_supply palmas_smps9_supply[] = {
557         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
558 };
559
560 #define palmas_ldo1_supply max77663_ldo7_supply
561 #define palmas_ldo2_supply max77663_ldo8_supply
562 #define palmas_ldo3_supply max77663_ldo5_supply
563
564 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
565         REGULATOR_SUPPLY("vpp_fuse", NULL),
566 };
567
568 #define palmas_ldo6_supply max77663_ldo2_supply
569
570 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
571         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
572 };
573
574 #define palmas_ldo8_supply max77663_ldo4_supply
575 #define palmas_ldo9_supply max77663_ldo6_supply
576
577 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
578         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
579 };
580
581 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
582         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
583         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
584         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
585         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
586         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
587 };
588
589 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
590         _boot_on, _apply_uv)                                            \
591         static struct regulator_init_data reg_idata_##_name = {         \
592                 .constraints = {                                        \
593                         .name = palmas_rails(_name),                    \
594                         .min_uV = (_minmv)*1000,                        \
595                         .max_uV = (_maxmv)*1000,                        \
596                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
597                                         REGULATOR_MODE_STANDBY),        \
598                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
599                                         REGULATOR_CHANGE_STATUS |       \
600                                         REGULATOR_CHANGE_VOLTAGE),      \
601                         .always_on = _always_on,                        \
602                         .boot_on = _boot_on,                            \
603                         .apply_uV = _apply_uv,                          \
604                 },                                                      \
605                 .num_consumer_supplies =                                \
606                         ARRAY_SIZE(palmas_##_name##_supply),            \
607                 .consumer_supplies = palmas_##_name##_supply,           \
608                 .supply_regulator = _supply_reg,                        \
609         }
610
611 PALMAS_PDATA_INIT(smps12, 1350,  1350, tps65090_rails(DCDC3), 0, 0, 0);
612 PALMAS_PDATA_INIT(smps3, 1800,  1800, tps65090_rails(DCDC3), 0, 0, 0);
613 PALMAS_PDATA_INIT(smps45, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0);
614 PALMAS_PDATA_INIT(smps8, 1050,  1050, tps65090_rails(DCDC2), 0, 1, 1);
615 PALMAS_PDATA_INIT(smps9, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 0);
616 PALMAS_PDATA_INIT(ldo1, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
617 PALMAS_PDATA_INIT(ldo2, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
618 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps3), 0, 0, 1);
619 PALMAS_PDATA_INIT(ldo4, 1800,  1800, tps65090_rails(DCDC2), 0, 0, 0);
620 PALMAS_PDATA_INIT(ldo6, 2850,  2850, tps65090_rails(DCDC2), 0, 0, 1);
621 PALMAS_PDATA_INIT(ldo7, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
622 PALMAS_PDATA_INIT(ldo8, 900,  900, tps65090_rails(DCDC3), 1, 1, 1);
623 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
624 PALMAS_PDATA_INIT(ldoln, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1);
625 PALMAS_PDATA_INIT(ldousb, 3300,  3300, tps65090_rails(DCDC1), 0, 0, 1);
626
627 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
628
629 static struct regulator_init_data *dalmore_e1611_reg_data[PALMAS_NUM_REGS] = {
630         PALMAS_REG_PDATA(smps12),
631         NULL,
632         PALMAS_REG_PDATA(smps3),
633         PALMAS_REG_PDATA(smps45),
634         NULL,
635         NULL,
636         NULL,
637         PALMAS_REG_PDATA(smps8),
638         PALMAS_REG_PDATA(smps9),
639         NULL,
640         PALMAS_REG_PDATA(ldo1),
641         PALMAS_REG_PDATA(ldo2),
642         PALMAS_REG_PDATA(ldo3),
643         PALMAS_REG_PDATA(ldo4),
644         NULL,
645         PALMAS_REG_PDATA(ldo6),
646         PALMAS_REG_PDATA(ldo7),
647         PALMAS_REG_PDATA(ldo8),
648         PALMAS_REG_PDATA(ldo9),
649         PALMAS_REG_PDATA(ldoln),
650         PALMAS_REG_PDATA(ldousb),
651         NULL,
652         NULL,
653         NULL,
654         NULL,
655         NULL,
656 };
657
658 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
659                 _tstep, _vsel)                                          \
660         static struct palmas_reg_init reg_init_data_##_name = {         \
661                 .warm_reset = _warm_reset,                              \
662                 .roof_floor =   _roof_floor,                            \
663                 .mode_sleep = _mode_sleep,                              \
664                 .tstep = _tstep,                                        \
665                 .vsel = _vsel,                                          \
666         }
667
668 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
669 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
670 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
671 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
672 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
673 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
674 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
675 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
676 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
677 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
678 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
679 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
680 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
681 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
682 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
683 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
684 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
685 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
686 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
687 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
688 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
689 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
690 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
691 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
692 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
693 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
694
695 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
696 static struct palmas_reg_init *dalmore_e1611_reg_init[PALMAS_NUM_REGS] = {
697         PALMAS_REG_INIT_DATA(smps12),
698         PALMAS_REG_INIT_DATA(smps123),
699         PALMAS_REG_INIT_DATA(smps3),
700         PALMAS_REG_INIT_DATA(smps45),
701         PALMAS_REG_INIT_DATA(smps457),
702         PALMAS_REG_INIT_DATA(smps6),
703         PALMAS_REG_INIT_DATA(smps7),
704         PALMAS_REG_INIT_DATA(smps8),
705         PALMAS_REG_INIT_DATA(smps9),
706         PALMAS_REG_INIT_DATA(smps10),
707         PALMAS_REG_INIT_DATA(ldo1),
708         PALMAS_REG_INIT_DATA(ldo2),
709         PALMAS_REG_INIT_DATA(ldo3),
710         PALMAS_REG_INIT_DATA(ldo4),
711         PALMAS_REG_INIT_DATA(ldo5),
712         PALMAS_REG_INIT_DATA(ldo6),
713         PALMAS_REG_INIT_DATA(ldo7),
714         PALMAS_REG_INIT_DATA(ldo8),
715         PALMAS_REG_INIT_DATA(ldo9),
716         PALMAS_REG_INIT_DATA(ldoln),
717         PALMAS_REG_INIT_DATA(ldousb),
718         PALMAS_REG_INIT_DATA(regen1),
719         PALMAS_REG_INIT_DATA(regen2),
720         PALMAS_REG_INIT_DATA(regen3),
721         PALMAS_REG_INIT_DATA(sysen1),
722         PALMAS_REG_INIT_DATA(sysen2),
723 };
724
725 static struct palmas_pmic_platform_data pmic_platform = {
726         .enable_ldo8_tracking = true,
727         .disabe_ldo8_tracking_suspend = true,
728 };
729
730 static struct palmas_platform_data palmas_pdata = {
731         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
732         .irq_base = PALMAS_TEGRA_IRQ_BASE,
733         .pmic_pdata = &pmic_platform,
734         .mux_from_pdata = true,
735         .pad1 = 0,
736         .pad2 = 0,
737         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
738 };
739
740 static struct i2c_board_info palma_device[] = {
741         {
742                 I2C_BOARD_INFO("tps65913", 0x58),
743                 .irq            = INT_EXTERNAL_PMU,
744                 .platform_data  = &palmas_pdata,
745         },
746 };
747
748 /* EN_AVDD_USB_HDMI From PMU GP1 */
749 static struct regulator_consumer_supply fixed_reg_avdd_usb_hdmi_supply[] = {
750         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
751         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
752         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
753         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
754         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
755         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
756 };
757
758 /* EN_CAM_1v8 From PMU GP5 */
759 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
760         REGULATOR_SUPPLY("dvdd_cam", NULL),
761         REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
762 };
763
764 /* EN_CAM_1v8 on e1611 From PMU GP6 */
765 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_e1611_supply[] = {
766         REGULATOR_SUPPLY("dvdd_cam", NULL),
767         REGULATOR_SUPPLY("vdd_cam_1v8", NULL),
768 };
769
770 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
771         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
772 };
773
774 /* EN_USB1_VBUS From TEGRA GPIO PN4 PR3(T30) */
775 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
776         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
777 };
778
779 /* EN_3V3_FUSE From TEGRA GPIO PX4 */
780 static struct regulator_consumer_supply fixed_reg_vpp_fuse_supply[] = {
781         REGULATOR_SUPPLY("vpp_fuse", NULL),
782 };
783
784 /* EN_USB3_VBUS From TEGRA GPIO PM5 */
785 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
786         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
787 };
788
789 /* Macro for defining fixed regulator sub device data */
790 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
791 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
792         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
793         static struct regulator_init_data ri_data_##_var =              \
794         {                                                               \
795                 .supply_regulator = _in_supply,                         \
796                 .num_consumer_supplies =                                \
797                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
798                 .consumer_supplies = fixed_reg_##_name##_supply,        \
799                 .constraints = {                                        \
800                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
801                                         REGULATOR_MODE_STANDBY),        \
802                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
803                                         REGULATOR_CHANGE_STATUS |       \
804                                         REGULATOR_CHANGE_VOLTAGE),      \
805                         .always_on = _always_on,                        \
806                         .boot_on = _boot_on,                            \
807                 },                                                      \
808         };                                                              \
809         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
810         {                                                               \
811                 .supply_name = FIXED_SUPPLY(_name),                     \
812                 .microvolts = _millivolts * 1000,                       \
813                 .gpio = _gpio_nr,                                       \
814                 .gpio_is_open_drain = _open_drain,                      \
815                 .enable_high = _active_high,                            \
816                 .enabled_at_boot = _boot_state,                         \
817                 .init_data = &ri_data_##_var,                           \
818         };                                                              \
819         static struct platform_device fixed_reg_##_var##_dev = {        \
820                 .name = "reg-fixed-voltage",                            \
821                 .id = _id,                                              \
822                 .dev = {                                                \
823                         .platform_data = &fixed_reg_##_var##_pdata,     \
824                 },                                                      \
825         }
826
827 FIXED_REG(1,    avdd_usb_hdmi,  avdd_usb_hdmi,
828         tps65090_rails(DCDC2),  0,      0,
829         MAX77663_GPIO_BASE + MAX77663_GPIO1,    true,   true,   1,      3300);
830
831 FIXED_REG(2,    en_1v8_cam,     en_1v8_cam,
832         max77663_rails(sd2),    0,      0,
833         MAX77663_GPIO_BASE + MAX77663_GPIO5,    false,  true,   0,      1800);
834
835 FIXED_REG(3,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
836         tps65090_rails(DCDC1),  0,      0,
837         TEGRA_GPIO_PK1, false,  true,   0,      5000);
838
839 FIXED_REG(4,    vpp_fuse,       vpp_fuse,
840         max77663_rails(sd2),    0,      0,
841         TEGRA_GPIO_PX4, false,  true,   0,      3300);
842
843 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
844 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
845         tps65090_rails(DCDC1),  0,      0,
846         TEGRA_GPIO_PN4, true,   true,   0,      5000);
847 #else
848 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
849         tps65090_rails(DCDC1),  0,      0,
850         TEGRA_GPIO_PR3, true,   true,   0,      5000);
851 #endif
852
853 FIXED_REG(6,    usb3_vbus,      usb3_vbus,
854         tps65090_rails(DCDC1),  0,      0,
855         TEGRA_GPIO_PK6, true,   true,   0,      5000);
856
857 FIXED_REG(7,    en_1v8_cam_e1611,       en_1v8_cam_e1611,
858         palmas_rails(smps3),    0,      0,
859         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
860
861 /*
862  * Creating the fixed regulator device tables
863  */
864
865 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
866
867 #define DALMORE_COMMON_FIXED_REG                \
868         ADD_FIXED_REG(usb1_vbus),               \
869         ADD_FIXED_REG(usb3_vbus),               \
870         ADD_FIXED_REG(vdd_hdmi_5v0),
871
872 #define E1612_FIXED_REG                         \
873         ADD_FIXED_REG(avdd_usb_hdmi),           \
874         ADD_FIXED_REG(en_1v8_cam),              \
875         ADD_FIXED_REG(vpp_fuse),                \
876
877 #define E1611_FIXED_REG                         \
878         ADD_FIXED_REG(en_1v8_cam_e1611),
879
880 /* Gpio switch regulator platform data for Dalmore E1611 */
881 static struct platform_device *fixed_reg_devs_e1611_a00[] = {
882         DALMORE_COMMON_FIXED_REG
883         E1611_FIXED_REG
884 };
885
886 /* Gpio switch regulator platform data for Dalmore E1612 */
887 static struct platform_device *fixed_reg_devs_e1612_a00[] = {
888         DALMORE_COMMON_FIXED_REG
889         E1612_FIXED_REG
890 };
891
892 int __init dalmore_palmas_regulator_init(void)
893 {
894         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
895         u32 pmc_ctrl;
896         int i;
897 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
898         int ret;
899
900         ret = gpio_request(TEGRA_GPIO_PCC3, "pmic_nreswarm");
901         if (ret < 0)
902                 pr_err("%s: gpio_request failed for gpio %d\n",
903                                 __func__, TEGRA_GPIO_PCC3);
904         else
905                 gpio_direction_output(TEGRA_GPIO_PCC3, 1);
906 #endif
907         /* TPS65913: Normal state of INT request line is LOW.
908          * configure the power management controller to trigger PMU
909          * interrupts when HIGH.
910          */
911         pmc_ctrl = readl(pmc + PMC_CTRL);
912         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
913         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
914                 pmic_platform.reg_data[i] = dalmore_e1611_reg_data[i];
915                 pmic_platform.reg_init[i] = dalmore_e1611_reg_init[i];
916         }
917
918         i2c_register_board_info(4, palma_device,
919                         ARRAY_SIZE(palma_device));
920         return 0;
921 }
922
923 static int ac_online(void)
924 {
925         return 1;
926 }
927
928 static struct resource dalmore_pda_resources[] = {
929         [0] = {
930                 .name   = "ac",
931         },
932 };
933
934 static struct pda_power_pdata dalmore_pda_data = {
935         .is_ac_online   = ac_online,
936 };
937
938 static struct platform_device dalmore_pda_power_device = {
939         .name           = "pda-power",
940         .id             = -1,
941         .resource       = dalmore_pda_resources,
942         .num_resources  = ARRAY_SIZE(dalmore_pda_resources),
943         .dev    = {
944                 .platform_data  = &dalmore_pda_data,
945         },
946 };
947
948 static struct tegra_suspend_platform_data dalmore_suspend_data = {
949         .cpu_timer      = 2000,
950         .cpu_off_timer  = 2000,
951         .suspend_mode   = TEGRA_SUSPEND_LP0,
952         .core_timer     = 0x157e,
953         .core_off_timer = 2000,
954         .corereq_high   = true,
955         .sysclkreq_high = true,
956         .min_residency_noncpu = 600,
957         .min_residency_crail = 1000,
958 };
959 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
960 /* board parameters for cpu dfll */
961 static struct tegra_cl_dvfs_cfg_param dalmore_cl_dvfs_param = {
962         .sample_rate = 12500,
963
964         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
965         .cf = 10,
966         .ci = 0,
967         .cg = 2,
968
969         .droop_cut_value = 0xF,
970         .droop_restore_ramp = 0x0,
971         .scale_out_ramp = 0x0,
972 };
973 #endif
974
975 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
976 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
977 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
978 static inline void fill_reg_map(void)
979 {
980         int i;
981         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
982                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
983                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
984         }
985 }
986
987 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
988 static struct tegra_cl_dvfs_platform_data dalmore_cl_dvfs_data = {
989         .dfll_clk_name = "dfll_cpu",
990         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
991         .u.pmu_i2c = {
992                 .fs_rate = 400000,
993                 .slave_addr = 0x86,
994                 .reg = 0x00,
995         },
996         .vdd_map = pmu_cpu_vdd_map,
997         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
998
999         .cfg_param = &dalmore_cl_dvfs_param,
1000 };
1001
1002 static int __init dalmore_cl_dvfs_init(void)
1003 {
1004         fill_reg_map();
1005         tegra_cl_dvfs_device.dev.platform_data = &dalmore_cl_dvfs_data;
1006         platform_device_register(&tegra_cl_dvfs_device);
1007
1008         return 0;
1009 }
1010 #endif
1011
1012 static int __init dalmore_max77663_regulator_init(void)
1013 {
1014         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
1015         u32 pmc_ctrl;
1016
1017         /* configure the power management controller to trigger PMU
1018          * interrupts when low */
1019         pmc_ctrl = readl(pmc + PMC_CTRL);
1020         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
1021
1022         i2c_register_board_info(4, max77663_regulators,
1023                                 ARRAY_SIZE(max77663_regulators));
1024
1025         return 0;
1026 }
1027
1028 static struct regulator_bulk_data dalmore_bt_regulator_supply[] = {
1029         [0] = {
1030                 .supply = "vdd_bt_3v3",
1031         },
1032         [1] = {
1033                 .supply = "vddio_bt_1v8",
1034         },
1035 };
1036
1037 static struct regulator_userspace_consumer_data dalmore_bt_regulator_pdata = {
1038         .num_supplies   = ARRAY_SIZE(dalmore_bt_regulator_supply),
1039         .supplies       = dalmore_bt_regulator_supply,
1040 };
1041
1042 static struct platform_device dalmore_bt_regulator_device = {
1043         .name   = "reg-userspace-consumer",
1044         .id     = 1,
1045         .dev    = {
1046                         .platform_data = &dalmore_bt_regulator_pdata,
1047         },
1048 };
1049
1050 static int __init dalmore_fixed_regulator_init(void)
1051 {
1052         struct board_info board_info;
1053
1054         if (!machine_is_dalmore())
1055                 return 0;
1056
1057         tegra_get_board_info(&board_info);
1058
1059         if (board_info.board_id == BOARD_E1611)
1060                 return platform_add_devices(fixed_reg_devs_e1611_a00,
1061                                 ARRAY_SIZE(fixed_reg_devs_e1611_a00));
1062         else
1063                 return platform_add_devices(fixed_reg_devs_e1612_a00,
1064                                 ARRAY_SIZE(fixed_reg_devs_e1612_a00));
1065 }
1066 subsys_initcall_sync(dalmore_fixed_regulator_init);
1067
1068 int __init dalmore_regulator_init(void)
1069 {
1070         struct board_info board_info;
1071         i2c_register_board_info(4, tps65090_regulators,
1072                         ARRAY_SIZE(tps65090_regulators));
1073 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1074         dalmore_cl_dvfs_init();
1075 #endif
1076         tegra_get_board_info(&board_info);
1077         if (board_info.board_id == BOARD_E1611)
1078                 dalmore_palmas_regulator_init();
1079         else
1080                 dalmore_max77663_regulator_init();
1081
1082         i2c_register_board_info(4, tps51632_boardinfo, 1);
1083         platform_device_register(&dalmore_pda_power_device);
1084         platform_device_register(&dalmore_bt_regulator_device);
1085         return 0;
1086 }
1087
1088 int __init dalmore_suspend_init(void)
1089 {
1090         tegra_init_suspend(&dalmore_suspend_data);
1091         return 0;
1092 }
1093
1094 int __init dalmore_edp_init(void)
1095 {
1096 #ifdef CONFIG_TEGRA_EDP_LIMITS
1097         unsigned int regulator_mA;
1098
1099         regulator_mA = get_maximum_cpu_current_supported();
1100         if (!regulator_mA)
1101                 regulator_mA = 15000;
1102
1103         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1104
1105         tegra_init_cpu_edp_limits(regulator_mA);
1106 #endif
1107         return 0;
1108 }
1109
1110 static struct soctherm_platform_data dalmore_soctherm_data = {
1111         .thermtrip = {
1112                 [THERM_CPU] = 90,
1113                 [THERM_GPU] = 0, /* Not enabled */
1114                 [THERM_MEM] = 0, /* Not enabled */
1115                 [THERM_PLL] = 0, /* Not enabled */
1116         },
1117
1118         .hw_backstop = 60,
1119         .dividend = 1,
1120         .divisor = 2,
1121         .duration = 1,
1122         .step = 1,
1123         .sensor_data = {
1124                 [TSENSE_CPU0] = {
1125                         .enable = true,
1126                         .therm_a = 570,
1127                         .therm_b = -744,
1128                         .tall = 16300,
1129                         .tiddq = 1,
1130                         .ten_count = 1,
1131                         .tsample = 163,
1132                         .pdiv = 10,
1133                 },
1134                 [TSENSE_CPU1] = {
1135                         .enable = true,
1136                         .therm_a = 570,
1137                         .therm_b = -744,
1138                         .tall = 16300,
1139                         .tiddq = 1,
1140                         .ten_count = 1,
1141                         .tsample = 163,
1142                         .pdiv = 10,
1143                 },
1144                 [TSENSE_CPU2] = {
1145                         .enable = true,
1146                         .therm_a = 570,
1147                         .therm_b = -744,
1148                         .tall = 16300,
1149                         .tiddq = 1,
1150                         .ten_count = 1,
1151                         .tsample = 163,
1152                         .pdiv = 10,
1153                 },
1154                 [TSENSE_CPU3] = {
1155                         .enable = true,
1156                         .therm_a = 570,
1157                         .therm_b = -744,
1158                         .tall = 16300,
1159                         .tiddq = 1,
1160                         .ten_count = 1,
1161                         .tsample = 163,
1162                         .pdiv = 10,
1163                 },
1164                 [TSENSE_MEM0] = {
1165                         .enable = true,
1166                         .therm_a = 570,
1167                         .therm_b = -744,
1168                         .tall = 16300,
1169                         .tiddq = 1,
1170                         .ten_count = 1,
1171                         .tsample = 163,
1172                         .pdiv = 10,
1173                 },
1174                 [TSENSE_MEM1] = {
1175                         .enable = true,
1176                         .therm_a = 570,
1177                         .therm_b = -744,
1178                         .tall = 16300,
1179                         .tiddq = 1,
1180                         .ten_count = 1,
1181                         .tsample = 163,
1182                         .pdiv = 10,
1183                 },
1184                 [TSENSE_GPU] = {
1185                         .enable = true,
1186                         .therm_a = 570,
1187                         .therm_b = -744,
1188                         .tall = 16300,
1189                         .tiddq = 1,
1190                         .ten_count = 1,
1191                         .tsample = 163,
1192                         .pdiv = 10,
1193                 },
1194                 [TSENSE_PLLX] = {
1195                         .enable = true,
1196                         .therm_a = 570,
1197                         .therm_b = -744,
1198                         .tall = 16300,
1199                         .tiddq = 1,
1200                         .ten_count = 1,
1201                         .tsample = 163,
1202                         .pdiv = 10,
1203                 },
1204         },
1205 };
1206
1207 static int __init dalmore_soctherm_init(void)
1208 {
1209         return tegra11_soctherm_init(&dalmore_soctherm_data);
1210 }
1211 module_init(dalmore_soctherm_init);