fe6084a31ceb63ff0542f4f4310a3080e7513544
[linux-3.10.git] / arch / arm / mach-tegra / board-dalmore-power.c
1 /*
2  * arch/arm/mach-tegra/board-dalmore-power.c
3  *
4  * Copyright (C) 2012-2013 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/max77663-core.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/mfd/tps65090.h>
31 #include <linux/regulator/max77663-regulator.h>
32 #include <linux/regulator/tps65090-regulator.h>
33 #include <linux/regulator/tps51632-regulator.h>
34 #include <linux/gpio.h>
35 #include <linux/interrupt.h>
36 #include <linux/regulator/userspace-consumer.h>
37
38 #include <asm/mach-types.h>
39 #include <linux/power/sbs-battery.h>
40
41 #include <mach/irqs.h>
42 #include <mach/edp.h>
43 #include <mach/gpio-tegra.h>
44
45 #include "cpu-tegra.h"
46 #include "pm.h"
47 #include "tegra-board-id.h"
48 #include "board.h"
49 #include "gpio-names.h"
50 #include "board-common.h"
51 #include "board-dalmore.h"
52 #include "tegra_cl_dvfs.h"
53 #include "devices.h"
54 #include "tegra11_soctherm.h"
55 #include "iomap.h"
56 #include "tegra3_tsensor.h"
57
58 #define PMC_CTRL                0x0
59 #define PMC_CTRL_INTR_LOW       (1 << 17)
60 #define TPS65090_CHARGER_INT    TEGRA_GPIO_PJ0
61 /*TPS65090 consumer rails */
62 static struct regulator_consumer_supply tps65090_dcdc1_supply[] = {
63         REGULATOR_SUPPLY("vdd_sys_5v0", NULL),
64         REGULATOR_SUPPLY("vdd_spk", NULL),
65         REGULATOR_SUPPLY("vdd_sys_modem_5v0", NULL),
66         REGULATOR_SUPPLY("vdd_sys_cam_5v0", NULL),
67 };
68
69 static struct regulator_consumer_supply tps65090_dcdc2_supply[] = {
70         REGULATOR_SUPPLY("vdd_sys_3v3", NULL),
71         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
72         REGULATOR_SUPPLY("pwrdet_hv", NULL),
73         REGULATOR_SUPPLY("vdd_sys_ds_3v3", NULL),
74         REGULATOR_SUPPLY("vdd_sys_nfc_3v3", NULL),
75         REGULATOR_SUPPLY("vdd_hv_nfc_3v3", NULL),
76         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
77         REGULATOR_SUPPLY("vdd_sys_sensor_3v3", NULL),
78         REGULATOR_SUPPLY("vdd_sys_audio_3v3", NULL),
79         REGULATOR_SUPPLY("vdd_sys_dtv_3v3", NULL),
80         REGULATOR_SUPPLY("vcc", "0-007c"),
81         REGULATOR_SUPPLY("vcc", "0-0030"),
82         REGULATOR_SUPPLY("vin", "2-0030"),
83 };
84
85 static struct regulator_consumer_supply tps65090_dcdc3_supply[] = {
86         REGULATOR_SUPPLY("vdd_ao", NULL),
87 };
88
89 static struct regulator_consumer_supply tps65090_ldo1_supply[] = {
90         REGULATOR_SUPPLY("vdd_sby_5v0", NULL),
91 };
92
93 static struct regulator_consumer_supply tps65090_ldo2_supply[] = {
94         REGULATOR_SUPPLY("vdd_sby_3v3", NULL),
95 };
96
97 static struct regulator_consumer_supply tps65090_fet1_supply[] = {
98         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
99 };
100
101 static struct regulator_consumer_supply tps65090_fet3_supply[] = {
102         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
103 };
104
105 static struct regulator_consumer_supply tps65090_fet4_supply[] = {
106         REGULATOR_SUPPLY("avdd_lcd", NULL),
107         REGULATOR_SUPPLY("avdd", "spi3.2"),
108 };
109
110 static struct regulator_consumer_supply tps65090_fet5_supply[] = {
111         REGULATOR_SUPPLY("vdd_lvds", NULL),
112 };
113
114 static struct regulator_consumer_supply tps65090_fet6_supply[] = {
115         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
116 };
117
118 static struct regulator_consumer_supply tps65090_fet7_supply[] = {
119         REGULATOR_SUPPLY("vdd_wifi_3v3", "bcm4329_wlan.1"),
120         REGULATOR_SUPPLY("vdd_gps_3v3", "reg-userspace-consumer.2"),
121         REGULATOR_SUPPLY("vdd_bt_3v3", "bluedroid_pm.0"),
122 };
123
124 #define TPS65090_PDATA_INIT(_id, _name, _supply_reg,                    \
125         _always_on, _boot_on, _apply_uV, _en_ext_ctrl, _gpio, _wait_to) \
126 static struct regulator_init_data ri_data_##_name =                     \
127 {                                                                       \
128         .supply_regulator = _supply_reg,                                \
129         .constraints = {                                                \
130                 .name = tps65090_rails(_id),                            \
131                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
132                                      REGULATOR_MODE_STANDBY),           \
133                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
134                                    REGULATOR_CHANGE_STATUS |            \
135                                    REGULATOR_CHANGE_VOLTAGE),           \
136                 .always_on = _always_on,                                \
137                 .boot_on = _boot_on,                                    \
138                 .apply_uV = _apply_uV,                                  \
139         },                                                              \
140         .num_consumer_supplies =                                        \
141                 ARRAY_SIZE(tps65090_##_name##_supply),                  \
142         .consumer_supplies = tps65090_##_name##_supply,                 \
143 };                                                                      \
144 static struct tps65090_regulator_platform_data                          \
145                         tps65090_regulator_pdata_##_name =              \
146 {                                                                       \
147         .id = TPS65090_REGULATOR_##_id,                                 \
148         .enable_ext_control = _en_ext_ctrl,                             \
149         .gpio = _gpio,                                                  \
150         .reg_init_data = &ri_data_##_name ,                             \
151         .wait_timeout_us = _wait_to,                                    \
152 }
153
154 TPS65090_PDATA_INIT(DCDC1, dcdc1, NULL, 1, 1, 0, true, -1, -1);
155 TPS65090_PDATA_INIT(DCDC2, dcdc2, NULL, 1, 1, 0, true, -1, -1);
156 TPS65090_PDATA_INIT(DCDC3, dcdc3, NULL, 1, 1, 0, true, -1, -1);
157 TPS65090_PDATA_INIT(LDO1, ldo1, NULL, 1, 1, 0, false, -1, -1);
158 TPS65090_PDATA_INIT(LDO2, ldo2, NULL, 1, 1, 0, false, -1, -1);
159 TPS65090_PDATA_INIT(FET1, fet1, NULL, 0, 0, 0, false, -1, 800);
160 TPS65090_PDATA_INIT(FET3, fet3, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
161 TPS65090_PDATA_INIT(FET4, fet4, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
162 TPS65090_PDATA_INIT(FET5, fet5, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
163 TPS65090_PDATA_INIT(FET6, fet6, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
164 TPS65090_PDATA_INIT(FET7, fet7, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
165
166 #define ADD_TPS65090_REG(_name) (&tps65090_regulator_pdata_##_name)
167 static struct tps65090_regulator_platform_data *tps65090_reg_pdata[] = {
168         ADD_TPS65090_REG(dcdc1),
169         ADD_TPS65090_REG(dcdc2),
170         ADD_TPS65090_REG(dcdc3),
171         ADD_TPS65090_REG(ldo1),
172         ADD_TPS65090_REG(ldo2),
173         ADD_TPS65090_REG(fet1),
174         ADD_TPS65090_REG(fet3),
175         ADD_TPS65090_REG(fet4),
176         ADD_TPS65090_REG(fet5),
177         ADD_TPS65090_REG(fet6),
178         ADD_TPS65090_REG(fet7),
179 };
180
181 static struct tps65090_charger_data bcharger_pdata = {
182         .irq_base = TPS65090_TEGRA_IRQ_BASE,
183         .update_status = sbs_update,
184 };
185
186 static struct tps65090_platform_data tps65090_pdata = {
187         .irq_base = TPS65090_TEGRA_IRQ_BASE,
188         .irq_flag = IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
189         .num_reg_pdata =  ARRAY_SIZE(tps65090_reg_pdata),
190         .reg_pdata = tps65090_reg_pdata,
191         .charger_pdata = &bcharger_pdata,
192 };
193
194 /* MAX77663 consumer rails */
195 static struct regulator_consumer_supply max77663_sd0_supply[] = {
196         REGULATOR_SUPPLY("vdd_core", NULL),
197 };
198
199 static struct regulator_consumer_supply max77663_sd1_supply[] = {
200         REGULATOR_SUPPLY("vddio_ddr", NULL),
201         REGULATOR_SUPPLY("vddio_ddr0", NULL),
202         REGULATOR_SUPPLY("vddio_ddr1", NULL),
203 };
204
205 static struct regulator_consumer_supply max77663_sd2_supply[] = {
206         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
207         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
208         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
209         REGULATOR_SUPPLY("vddio_cam", "vi"),
210         REGULATOR_SUPPLY("pwrdet_cam", NULL),
211         REGULATOR_SUPPLY("avdd_osc", NULL),
212         REGULATOR_SUPPLY("vddio_sys", NULL),
213         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
214         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
215         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
216         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
217         REGULATOR_SUPPLY("vdd_emmc", NULL),
218         REGULATOR_SUPPLY("vddio_audio", NULL),
219         REGULATOR_SUPPLY("pwrdet_audio", NULL),
220         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
221         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
222         REGULATOR_SUPPLY("vddio_modem", NULL),
223         REGULATOR_SUPPLY("vddio_modem_1v8", NULL),
224         REGULATOR_SUPPLY("vddio_bb", NULL),
225         REGULATOR_SUPPLY("pwrdet_bb", NULL),
226         REGULATOR_SUPPLY("vddio_bb_1v8", NULL),
227         REGULATOR_SUPPLY("vddio_uart", NULL),
228         REGULATOR_SUPPLY("pwrdet_uart", NULL),
229         REGULATOR_SUPPLY("vddio_gmi", NULL),
230         REGULATOR_SUPPLY("pwrdet_nand", NULL),
231         REGULATOR_SUPPLY("vdd_sensor_1v8", NULL),
232         REGULATOR_SUPPLY("vdd_mic_1v8", NULL),
233         REGULATOR_SUPPLY("vdd_nfc_1v8", NULL),
234         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
235         REGULATOR_SUPPLY("vdd_spi_1v8", NULL),
236         REGULATOR_SUPPLY("dvdd_lcd", NULL),
237         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
238         REGULATOR_SUPPLY("vddio_wifi_1v8", "bcm4329_wlan.1"),
239         REGULATOR_SUPPLY("vdd_gps_1v8", "reg-userspace-consumer.2"),
240         REGULATOR_SUPPLY("vddio_bt_1v8", "bluedroid_pm.0"),
241         REGULATOR_SUPPLY("vdd_dtv_1v8", NULL),
242         REGULATOR_SUPPLY("vlogic", "0-0069"),
243 };
244
245 static struct regulator_consumer_supply max77663_sd3_supply[] = {
246         REGULATOR_SUPPLY("vcore_emmc", NULL),
247 };
248
249 static struct regulator_consumer_supply max77663_ldo0_supply[] = {
250         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
251         REGULATOR_SUPPLY("avdd_pllx", NULL),
252         REGULATOR_SUPPLY("avdd_plle", NULL),
253         REGULATOR_SUPPLY("avdd_pllm", NULL),
254         REGULATOR_SUPPLY("avdd_pllu", NULL),
255         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
256         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
257         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
258 };
259
260 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
261         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
262 };
263
264 static struct regulator_consumer_supply max77663_ldo2_supply[] = {
265         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
266         REGULATOR_SUPPLY("vdd_als", NULL),
267         REGULATOR_SUPPLY("vdd", "0-004c"),
268         REGULATOR_SUPPLY("vdd", "0-0069"),
269 };
270
271 static struct regulator_consumer_supply max77663_ldo3_supply[] = {
272         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
273         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
274         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
275 };
276
277 static struct regulator_consumer_supply max77663_ldo4_supply[] = {
278         REGULATOR_SUPPLY("vdd_rtc", NULL),
279 };
280
281 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
282         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
283         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
284         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
285         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
286         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
287         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
288         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
289         REGULATOR_SUPPLY("vddio_bb_hsic", NULL),
290 };
291
292 static struct regulator_consumer_supply max77663_ldo6_supply[] = {
293         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
294         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
295 };
296
297 /* FIXME!! Put the device address of camera */
298 static struct regulator_consumer_supply max77663_ldo7_supply[] = {
299         REGULATOR_SUPPLY("avdd_cam1", NULL),
300         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
301         REGULATOR_SUPPLY("vana", "2-0036"),
302 };
303
304 /* FIXME!! Put the device address of camera */
305 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
306         REGULATOR_SUPPLY("avdd_cam2", NULL),
307         REGULATOR_SUPPLY("avdd", "2-0010"),
308 };
309
310 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
311         {
312                 .src = FPS_SRC_0,
313                 .en_src = FPS_EN_SRC_EN0,
314                 .time_period = FPS_TIME_PERIOD_DEF,
315         },
316         {
317                 .src = FPS_SRC_1,
318                 .en_src = FPS_EN_SRC_EN1,
319                 .time_period = FPS_TIME_PERIOD_DEF,
320         },
321         {
322                 .src = FPS_SRC_2,
323                 .en_src = FPS_EN_SRC_EN0,
324                 .time_period = FPS_TIME_PERIOD_DEF,
325         },
326 };
327
328 #define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg,   \
329                 _always_on, _boot_on, _apply_uV,                        \
330                 _fps_src, _fps_pu_period, _fps_pd_period, _flags)       \
331         static struct regulator_init_data max77663_regulator_idata_##_id = {   \
332                 .supply_regulator = _supply_reg,                        \
333                 .constraints = {                                        \
334                         .name = max77663_rails(_id),                    \
335                         .min_uV = _min_uV,                              \
336                         .max_uV = _max_uV,                              \
337                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
338                                              REGULATOR_MODE_STANDBY),   \
339                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
340                                            REGULATOR_CHANGE_STATUS |    \
341                                            REGULATOR_CHANGE_VOLTAGE),   \
342                         .always_on = _always_on,                        \
343                         .boot_on = _boot_on,                            \
344                         .apply_uV = _apply_uV,                          \
345                 },                                                      \
346                 .num_consumer_supplies =                                \
347                         ARRAY_SIZE(max77663_##_id##_supply),            \
348                 .consumer_supplies = max77663_##_id##_supply,           \
349         };                                                              \
350 static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id =\
351 {                                                                       \
352                 .reg_init_data = &max77663_regulator_idata_##_id,       \
353                 .id = MAX77663_REGULATOR_ID_##_rid,                     \
354                 .fps_src = _fps_src,                                    \
355                 .fps_pu_period = _fps_pu_period,                        \
356                 .fps_pd_period = _fps_pd_period,                        \
357                 .fps_cfgs = max77663_fps_cfgs,                          \
358                 .flags = _flags,                                        \
359         }
360
361 MAX77663_PDATA_INIT(SD0, sd0,  900000, 1400000, tps65090_rails(DCDC3), 1, 1, 0,
362                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
363
364 MAX77663_PDATA_INIT(SD1, sd1,  1200000, 1200000, tps65090_rails(DCDC3), 1, 1, 1,
365                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
366
367 MAX77663_PDATA_INIT(SD2, sd2,  1800000, 1800000, tps65090_rails(DCDC3), 1, 1, 1,
368                     FPS_SRC_0, -1, -1, 0);
369
370 MAX77663_PDATA_INIT(SD3, sd3,  2850000, 2850000, tps65090_rails(DCDC3), 1, 1, 1,
371                     FPS_SRC_NONE, -1, -1, 0);
372
373 MAX77663_PDATA_INIT(LDO0, ldo0, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
374                     FPS_SRC_1, -1, -1, 0);
375
376 MAX77663_PDATA_INIT(LDO1, ldo1, 1050000, 1050000, max77663_rails(sd2), 0, 0, 1,
377                     FPS_SRC_NONE, -1, -1, 0);
378
379 MAX77663_PDATA_INIT(LDO2, ldo2, 2850000, 2850000, tps65090_rails(DCDC2), 1, 1,
380                     1, FPS_SRC_1, -1, -1, 0);
381
382 MAX77663_PDATA_INIT(LDO3, ldo3, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
383                     FPS_SRC_NONE, -1, -1, 0);
384
385 MAX77663_PDATA_INIT(LDO4, ldo4, 1100000, 1100000, tps65090_rails(DCDC2), 1, 1,
386                     1, FPS_SRC_NONE, -1, -1, 0);
387
388 MAX77663_PDATA_INIT(LDO5, ldo5, 1200000, 1200000, max77663_rails(sd2), 0, 1, 1,
389                     FPS_SRC_NONE, -1, -1, 0);
390
391 MAX77663_PDATA_INIT(LDO6, ldo6, 1800000, 3300000, tps65090_rails(DCDC2), 0, 0, 0,
392                     FPS_SRC_NONE, -1, -1, 0);
393
394 MAX77663_PDATA_INIT(LDO7, ldo7, 2800000, 2800000, tps65090_rails(DCDC2), 0, 0, 1,
395                     FPS_SRC_NONE, -1, -1, 0);
396
397 MAX77663_PDATA_INIT(LDO8, ldo8, 2800000, 2800000, tps65090_rails(DCDC2), 0, 1, 1,
398                     FPS_SRC_1, -1, -1, 0);
399
400 #define MAX77663_REG(_id, _data) (&max77663_regulator_pdata_##_data)
401
402 static struct max77663_regulator_platform_data *max77663_reg_pdata[] = {
403         MAX77663_REG(SD0, sd0),
404         MAX77663_REG(SD1, sd1),
405         MAX77663_REG(SD2, sd2),
406         MAX77663_REG(SD3, sd3),
407         MAX77663_REG(LDO0, ldo0),
408         MAX77663_REG(LDO1, ldo1),
409         MAX77663_REG(LDO2, ldo2),
410         MAX77663_REG(LDO3, ldo3),
411         MAX77663_REG(LDO4, ldo4),
412         MAX77663_REG(LDO5, ldo5),
413         MAX77663_REG(LDO6, ldo6),
414         MAX77663_REG(LDO7, ldo7),
415         MAX77663_REG(LDO8, ldo8),
416 };
417
418 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
419         {
420                 .gpio = MAX77663_GPIO0,
421                 .dir = GPIO_DIR_OUT,
422                 .dout = GPIO_DOUT_LOW,
423                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
424                 .alternate = GPIO_ALT_DISABLE,
425         },
426         {
427                 .gpio = MAX77663_GPIO1,
428                 .dir = GPIO_DIR_IN,
429                 .dout = GPIO_DOUT_HIGH,
430                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
431                 .pull_up = GPIO_PU_ENABLE,
432                 .alternate = GPIO_ALT_DISABLE,
433         },
434         {
435                 .gpio = MAX77663_GPIO2,
436                 .dir = GPIO_DIR_OUT,
437                 .dout = GPIO_DOUT_HIGH,
438                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
439                 .pull_up = GPIO_PU_ENABLE,
440                 .alternate = GPIO_ALT_DISABLE,
441         },
442         {
443                 .gpio = MAX77663_GPIO3,
444                 .dir = GPIO_DIR_OUT,
445                 .dout = GPIO_DOUT_HIGH,
446                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
447                 .pull_up = GPIO_PU_ENABLE,
448                 .alternate = GPIO_ALT_DISABLE,
449         },
450         {
451                 .gpio = MAX77663_GPIO4,
452                 .dir = GPIO_DIR_OUT,
453                 .dout = GPIO_DOUT_HIGH,
454                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
455                 .alternate = GPIO_ALT_ENABLE,
456         },
457         {
458                 .gpio = MAX77663_GPIO5,
459                 .dir = GPIO_DIR_OUT,
460                 .dout = GPIO_DOUT_LOW,
461                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
462                 .alternate = GPIO_ALT_DISABLE,
463         },
464         {
465                 .gpio = MAX77663_GPIO6,
466                 .dir = GPIO_DIR_OUT,
467                 .dout = GPIO_DOUT_LOW,
468                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
469                 .alternate = GPIO_ALT_DISABLE,
470         },
471         {
472                 .gpio = MAX77663_GPIO7,
473                 .dir = GPIO_DIR_OUT,
474                 .dout = GPIO_DOUT_LOW,
475                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
476                 .alternate = GPIO_ALT_DISABLE,
477         },
478 };
479
480 static struct max77663_platform_data max77663_pdata = {
481         .irq_base       = MAX77663_IRQ_BASE,
482         .gpio_base      = MAX77663_GPIO_BASE,
483
484         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
485         .gpio_cfgs      = max77663_gpio_cfgs,
486
487         .regulator_pdata = max77663_reg_pdata,
488         .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata),
489
490         .rtc_i2c_addr   = 0x68,
491
492         .use_power_off  = false,
493 };
494
495 static struct i2c_board_info __initdata max77663_regulators[] = {
496         {
497                 /* The I2C address was determined by OTP factory setting */
498                 I2C_BOARD_INFO("max77663", 0x3c),
499                 .irq            = INT_EXTERNAL_PMU,
500                 .platform_data  = &max77663_pdata,
501         },
502 };
503
504 static struct i2c_board_info __initdata tps65090_regulators[] = {
505         {
506                 I2C_BOARD_INFO("tps65090", 0x48),
507                 .platform_data  = &tps65090_pdata,
508         },
509 };
510
511 /* TPS51632 DC-DC converter */
512 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
513         REGULATOR_SUPPLY("vdd_cpu", NULL),
514 };
515
516 static struct regulator_init_data tps51632_init_data = {
517         .constraints = {                                                \
518                 .min_uV = 500000,                                       \
519                 .max_uV = 1520000,                                      \
520                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
521                                         REGULATOR_MODE_STANDBY),        \
522                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
523                                         REGULATOR_CHANGE_STATUS |       \
524                                          REGULATOR_CHANGE_CONTROL |     \
525                                         REGULATOR_CHANGE_VOLTAGE),      \
526                 .always_on = 1,                                         \
527                 .boot_on =  1,                                          \
528                 .apply_uV = 0,                                          \
529         },                                                              \
530         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
531                 .consumer_supplies = tps51632_dcdc_supply,              \
532 };
533
534 static struct tps51632_regulator_platform_data tps51632_pdata = {
535         .reg_init_data = &tps51632_init_data,           \
536         .enable_pwm = false,                            \
537         .max_voltage_uV = 1520000,                      \
538         .base_voltage_uV = 500000,                      \
539         .slew_rate_uv_per_us = 6000,                    \
540 };
541
542 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
543         {
544                 I2C_BOARD_INFO("tps51632", 0x43),
545                 .platform_data  = &tps51632_pdata,
546         },
547 };
548
549 /************************ Palmas based regulator ****************/
550 static struct regulator_consumer_supply palmas_smps12_supply[] = {
551         REGULATOR_SUPPLY("vddio_ddr3l", NULL),
552         REGULATOR_SUPPLY("vcore_ddr3l", NULL),
553         REGULATOR_SUPPLY("vref2_ddr3l", NULL),
554 };
555
556 #define palmas_smps3_supply max77663_sd2_supply
557 #define palmas_smps45_supply max77663_sd0_supply
558 #define palmas_smps457_supply max77663_sd0_supply
559
560 static struct regulator_consumer_supply palmas_smps8_supply[] = {
561         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
562         REGULATOR_SUPPLY("avdd_pllm", NULL),
563         REGULATOR_SUPPLY("avdd_pllu", NULL),
564         REGULATOR_SUPPLY("avdd_pllx", NULL),
565         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
566         REGULATOR_SUPPLY("avdd_plle", NULL),
567         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
568         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
569         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
570         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
571         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
572         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
573         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
574         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
575 };
576
577 static struct regulator_consumer_supply palmas_smps9_supply[] = {
578         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
579 };
580
581 #define palmas_ldo1_supply max77663_ldo7_supply
582 #define palmas_ldo2_supply max77663_ldo8_supply
583 #define palmas_ldo3_supply max77663_ldo5_supply
584
585 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
586         REGULATOR_SUPPLY("vpp_fuse", NULL),
587 };
588
589 #define palmas_ldo6_supply max77663_ldo2_supply
590
591 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
592         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
593         REGULATOR_SUPPLY("vdd", "2-000e"),
594 };
595
596 #define palmas_ldo8_supply max77663_ldo4_supply
597 #define palmas_ldo9_supply max77663_ldo6_supply
598
599 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
600         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
601         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
602 };
603
604 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
605         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
606         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
607         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
608         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
609         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
610 };
611
612 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
613         _boot_on, _apply_uv)                                            \
614         static struct regulator_init_data reg_idata_##_name = {         \
615                 .constraints = {                                        \
616                         .name = palmas_rails(_name),                    \
617                         .min_uV = (_minmv)*1000,                        \
618                         .max_uV = (_maxmv)*1000,                        \
619                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
620                                         REGULATOR_MODE_STANDBY),        \
621                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
622                                         REGULATOR_CHANGE_STATUS |       \
623                                         REGULATOR_CHANGE_VOLTAGE),      \
624                         .always_on = _always_on,                        \
625                         .boot_on = _boot_on,                            \
626                         .apply_uV = _apply_uv,                          \
627                 },                                                      \
628                 .num_consumer_supplies =                                \
629                         ARRAY_SIZE(palmas_##_name##_supply),            \
630                 .consumer_supplies = palmas_##_name##_supply,           \
631                 .supply_regulator = _supply_reg,                        \
632         }
633
634 PALMAS_PDATA_INIT(smps12, 1350,  1350, tps65090_rails(DCDC3), 0, 0, 0);
635 PALMAS_PDATA_INIT(smps3, 1800,  1800, tps65090_rails(DCDC3), 0, 0, 0);
636 PALMAS_PDATA_INIT(smps45, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0);
637 PALMAS_PDATA_INIT(smps457, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0);
638 PALMAS_PDATA_INIT(smps8, 1050,  1050, tps65090_rails(DCDC2), 0, 1, 1);
639 PALMAS_PDATA_INIT(smps9, 2800,  2800, tps65090_rails(DCDC2), 1, 0, 0);
640 PALMAS_PDATA_INIT(ldo1, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
641 PALMAS_PDATA_INIT(ldo2, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
642 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps3), 0, 0, 1);
643 PALMAS_PDATA_INIT(ldo4, 1800,  1800, tps65090_rails(DCDC2), 0, 0, 0);
644 PALMAS_PDATA_INIT(ldo6, 2850,  2850, tps65090_rails(DCDC2), 0, 0, 1);
645 PALMAS_PDATA_INIT(ldo7, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
646 PALMAS_PDATA_INIT(ldo8, 900,  900, tps65090_rails(DCDC3), 1, 1, 1);
647 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
648 PALMAS_PDATA_INIT(ldoln, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1);
649 PALMAS_PDATA_INIT(ldousb, 3300,  3300, tps65090_rails(DCDC1), 0, 0, 1);
650
651 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
652
653 static struct regulator_init_data *dalmore_e1611_reg_data[PALMAS_NUM_REGS] = {
654         PALMAS_REG_PDATA(smps12),
655         NULL,
656         PALMAS_REG_PDATA(smps3),
657         PALMAS_REG_PDATA(smps45),
658         PALMAS_REG_PDATA(smps457),
659         NULL,
660         NULL,
661         PALMAS_REG_PDATA(smps8),
662         PALMAS_REG_PDATA(smps9),
663         NULL,
664         PALMAS_REG_PDATA(ldo1),
665         PALMAS_REG_PDATA(ldo2),
666         PALMAS_REG_PDATA(ldo3),
667         PALMAS_REG_PDATA(ldo4),
668         NULL,
669         PALMAS_REG_PDATA(ldo6),
670         PALMAS_REG_PDATA(ldo7),
671         PALMAS_REG_PDATA(ldo8),
672         PALMAS_REG_PDATA(ldo9),
673         PALMAS_REG_PDATA(ldoln),
674         PALMAS_REG_PDATA(ldousb),
675         NULL,
676         NULL,
677         NULL,
678         NULL,
679         NULL,
680 };
681
682 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
683                 _tstep, _vsel)                                          \
684         static struct palmas_reg_init reg_init_data_##_name = {         \
685                 .warm_reset = _warm_reset,                              \
686                 .roof_floor =   _roof_floor,                            \
687                 .mode_sleep = _mode_sleep,                              \
688                 .tstep = _tstep,                                        \
689                 .vsel = _vsel,                                          \
690         }
691
692 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
693 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
694 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
695 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
696 PALMAS_REG_INIT(smps457, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
697 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
698 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
699 PALMAS_REG_INIT(smps8, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
700 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
701 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
702 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
703 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
704 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
705 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
706 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
707 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
708 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
709 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
710 PALMAS_REG_INIT(ldo9, 1, 0, 0, 0, 0);
711 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
712 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
713 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
714 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
715 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
716 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
717 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
718
719 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
720 static struct palmas_reg_init *dalmore_e1611_reg_init[PALMAS_NUM_REGS] = {
721         PALMAS_REG_INIT_DATA(smps12),
722         PALMAS_REG_INIT_DATA(smps123),
723         PALMAS_REG_INIT_DATA(smps3),
724         PALMAS_REG_INIT_DATA(smps45),
725         PALMAS_REG_INIT_DATA(smps457),
726         PALMAS_REG_INIT_DATA(smps6),
727         PALMAS_REG_INIT_DATA(smps7),
728         PALMAS_REG_INIT_DATA(smps8),
729         PALMAS_REG_INIT_DATA(smps9),
730         PALMAS_REG_INIT_DATA(smps10),
731         PALMAS_REG_INIT_DATA(ldo1),
732         PALMAS_REG_INIT_DATA(ldo2),
733         PALMAS_REG_INIT_DATA(ldo3),
734         PALMAS_REG_INIT_DATA(ldo4),
735         PALMAS_REG_INIT_DATA(ldo5),
736         PALMAS_REG_INIT_DATA(ldo6),
737         PALMAS_REG_INIT_DATA(ldo7),
738         PALMAS_REG_INIT_DATA(ldo8),
739         PALMAS_REG_INIT_DATA(ldo9),
740         PALMAS_REG_INIT_DATA(ldoln),
741         PALMAS_REG_INIT_DATA(ldousb),
742         PALMAS_REG_INIT_DATA(regen1),
743         PALMAS_REG_INIT_DATA(regen2),
744         PALMAS_REG_INIT_DATA(regen3),
745         PALMAS_REG_INIT_DATA(sysen1),
746         PALMAS_REG_INIT_DATA(sysen2),
747 };
748
749 static struct palmas_pmic_platform_data pmic_platform = {
750         .enable_ldo8_tracking = true,
751         .disabe_ldo8_tracking_suspend = true,
752 };
753
754 static struct palmas_rtc_platform_data rtc_platform = {
755         .enable_charging = 1,
756         .charging_current_ua = 100,
757 };
758
759 static struct palmas_platform_data palmas_pdata = {
760         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
761         .irq_base = PALMAS_TEGRA_IRQ_BASE,
762         .pmic_pdata = &pmic_platform,
763         .rtc_pdata = &rtc_platform,
764         .mux_from_pdata = true,
765         .pad1 = 0,
766         .pad2 = 0,
767         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
768         .use_power_off = true,
769 };
770
771 static struct i2c_board_info palma_device[] = {
772         {
773                 I2C_BOARD_INFO("tps65913", 0x58),
774                 .irq            = INT_EXTERNAL_PMU,
775                 .platform_data  = &palmas_pdata,
776         },
777 };
778
779 /* EN_AVDD_USB_HDMI From PMU GP1 */
780 static struct regulator_consumer_supply fixed_reg_avdd_usb_hdmi_supply[] = {
781         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
782         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
783         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
784         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
785         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
786         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
787 };
788
789 /* EN_CAM_1v8 From PMU GP5 */
790 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
791         REGULATOR_SUPPLY("vi2c", "2-0030"),
792         REGULATOR_SUPPLY("vif", "2-0036"),
793         REGULATOR_SUPPLY("dovdd", "2-0010"),
794         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
795 };
796
797 /* EN_CAM_1v8 on e1611 From PMU GP6 */
798 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_e1611_supply[] = {
799         REGULATOR_SUPPLY("vi2c", "2-0030"),
800         REGULATOR_SUPPLY("vif", "2-0036"),
801         REGULATOR_SUPPLY("dovdd", "2-0010"),
802         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
803 };
804
805 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
806         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
807 };
808
809 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
810         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
811 };
812
813 /* EN_USB1_VBUS From TEGRA GPIO PN4 PR3(T30) */
814 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
815         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
816 };
817
818 /* EN_3V3_FUSE From TEGRA GPIO PX4 */
819 static struct regulator_consumer_supply fixed_reg_vpp_fuse_supply[] = {
820         REGULATOR_SUPPLY("vpp_fuse", NULL),
821 };
822
823 /* EN_USB3_VBUS From TEGRA GPIO PM5 */
824 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
825         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
826         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci"),
827 };
828
829 /* EN_1V8_TS From TEGRA_GPIO_PH5 */
830 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
831         REGULATOR_SUPPLY("dvdd", "spi3.2"),
832 };
833
834 /* Macro for defining fixed regulator sub device data */
835 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
836 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
837         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
838         static struct regulator_init_data ri_data_##_var =              \
839         {                                                               \
840                 .supply_regulator = _in_supply,                         \
841                 .num_consumer_supplies =                                \
842                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
843                 .consumer_supplies = fixed_reg_##_name##_supply,        \
844                 .constraints = {                                        \
845                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
846                                         REGULATOR_MODE_STANDBY),        \
847                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
848                                         REGULATOR_CHANGE_STATUS |       \
849                                         REGULATOR_CHANGE_VOLTAGE),      \
850                         .always_on = _always_on,                        \
851                         .boot_on = _boot_on,                            \
852                 },                                                      \
853         };                                                              \
854         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
855         {                                                               \
856                 .supply_name = FIXED_SUPPLY(_name),                     \
857                 .microvolts = _millivolts * 1000,                       \
858                 .gpio = _gpio_nr,                                       \
859                 .gpio_is_open_drain = _open_drain,                      \
860                 .enable_high = _active_high,                            \
861                 .enabled_at_boot = _boot_state,                         \
862                 .init_data = &ri_data_##_var,                           \
863         };                                                              \
864         static struct platform_device fixed_reg_##_var##_dev = {        \
865                 .name = "reg-fixed-voltage",                            \
866                 .id = _id,                                              \
867                 .dev = {                                                \
868                         .platform_data = &fixed_reg_##_var##_pdata,     \
869                 },                                                      \
870         }
871
872 FIXED_REG(1,    avdd_usb_hdmi,  avdd_usb_hdmi,
873         tps65090_rails(DCDC2),  0,      0,
874         MAX77663_GPIO_BASE + MAX77663_GPIO1,    true,   true,   1,      3300);
875
876 FIXED_REG(2,    en_1v8_cam,     en_1v8_cam,
877         max77663_rails(sd2),    0,      0,
878         MAX77663_GPIO_BASE + MAX77663_GPIO5,    false,  true,   0,      1800);
879
880 FIXED_REG(3,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
881         tps65090_rails(DCDC1),  0,      0,
882         TEGRA_GPIO_PK1, false,  true,   0,      5000);
883
884 FIXED_REG(4,    vpp_fuse,       vpp_fuse,
885         max77663_rails(sd2),    0,      0,
886         TEGRA_GPIO_PX4, false,  true,   0,      3300);
887
888 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
889         tps65090_rails(DCDC1),  0,      0,
890         TEGRA_GPIO_PN4, true,   true,   0,      5000);
891
892 FIXED_REG(6,    usb3_vbus,      usb3_vbus,
893         tps65090_rails(DCDC1),  0,      0,
894         TEGRA_GPIO_PK6, true,   true,   0,      5000);
895
896 FIXED_REG(7,    en_1v8_cam_e1611,       en_1v8_cam_e1611,
897         palmas_rails(smps3),    0,      0,
898         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
899
900 FIXED_REG(8,    dvdd_ts,        dvdd_ts,
901         palmas_rails(smps3),    0,      0,
902         TEGRA_GPIO_PH5, false,  false,  1,      1800);
903
904 FIXED_REG(9,    lcd_bl_en,      lcd_bl_en,
905         NULL,   0,      0,
906         TEGRA_GPIO_PH2, false,  true,   0,      5000);
907 /*
908  * Creating the fixed regulator device tables
909  */
910
911 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
912
913 #define DALMORE_COMMON_FIXED_REG                \
914         ADD_FIXED_REG(usb1_vbus),               \
915         ADD_FIXED_REG(usb3_vbus),               \
916         ADD_FIXED_REG(vdd_hdmi_5v0),            \
917         ADD_FIXED_REG(lcd_bl_en),
918
919 #define E1612_FIXED_REG                         \
920         ADD_FIXED_REG(avdd_usb_hdmi),           \
921         ADD_FIXED_REG(en_1v8_cam),              \
922         ADD_FIXED_REG(vpp_fuse),                \
923
924 #define E1611_FIXED_REG                         \
925         ADD_FIXED_REG(en_1v8_cam_e1611), \
926         ADD_FIXED_REG(dvdd_ts),
927
928 /* Gpio switch regulator platform data for Dalmore E1611 */
929 static struct platform_device *fixed_reg_devs_e1611_a00[] = {
930         DALMORE_COMMON_FIXED_REG
931         E1611_FIXED_REG
932 };
933
934 /* Gpio switch regulator platform data for Dalmore E1612 */
935 static struct platform_device *fixed_reg_devs_e1612_a00[] = {
936         DALMORE_COMMON_FIXED_REG
937         E1612_FIXED_REG
938 };
939
940 int __init dalmore_palmas_regulator_init(void)
941 {
942         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
943         u32 pmc_ctrl;
944         int i;
945
946         /* TPS65913: Normal state of INT request line is LOW.
947          * configure the power management controller to trigger PMU
948          * interrupts when HIGH.
949          */
950         pmc_ctrl = readl(pmc + PMC_CTRL);
951         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
952         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
953                 pmic_platform.reg_data[i] = dalmore_e1611_reg_data[i];
954                 pmic_platform.reg_init[i] = dalmore_e1611_reg_init[i];
955         }
956
957         i2c_register_board_info(4, palma_device,
958                         ARRAY_SIZE(palma_device));
959         return 0;
960 }
961
962 static int ac_online(void)
963 {
964         return 1;
965 }
966
967 static struct resource dalmore_pda_resources[] = {
968         [0] = {
969                 .name   = "ac",
970         },
971 };
972
973 static struct pda_power_pdata dalmore_pda_data = {
974         .is_ac_online   = ac_online,
975 };
976
977 static struct platform_device dalmore_pda_power_device = {
978         .name           = "pda-power",
979         .id             = -1,
980         .resource       = dalmore_pda_resources,
981         .num_resources  = ARRAY_SIZE(dalmore_pda_resources),
982         .dev    = {
983                 .platform_data  = &dalmore_pda_data,
984         },
985 };
986
987 static struct tegra_suspend_platform_data dalmore_suspend_data = {
988         .cpu_timer      = 300,
989         .cpu_off_timer  = 300,
990         .suspend_mode   = TEGRA_SUSPEND_LP0,
991         .core_timer     = 0x157e,
992         .core_off_timer = 2000,
993         .corereq_high   = true,
994         .sysclkreq_high = true,
995         .cpu_lp2_min_residency = 1000,
996         .min_residency_crail = 20000,
997 };
998 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
999 /* board parameters for cpu dfll */
1000 static struct tegra_cl_dvfs_cfg_param dalmore_cl_dvfs_param = {
1001         .sample_rate = 12500,
1002
1003         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
1004         .cf = 10,
1005         .ci = 0,
1006         .cg = 2,
1007
1008         .droop_cut_value = 0xF,
1009         .droop_restore_ramp = 0x0,
1010         .scale_out_ramp = 0x0,
1011 };
1012 #endif
1013
1014 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
1015 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
1016 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
1017 static inline void fill_reg_map(void)
1018 {
1019         int i;
1020         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
1021                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
1022                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
1023         }
1024 }
1025
1026 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1027 static struct tegra_cl_dvfs_platform_data dalmore_cl_dvfs_data = {
1028         .dfll_clk_name = "dfll_cpu",
1029         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
1030         .u.pmu_i2c = {
1031                 .fs_rate = 400000,
1032                 .slave_addr = 0x86,
1033                 .reg = 0x00,
1034         },
1035         .vdd_map = pmu_cpu_vdd_map,
1036         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
1037
1038         .cfg_param = &dalmore_cl_dvfs_param,
1039 };
1040
1041 static int __init dalmore_cl_dvfs_init(void)
1042 {
1043         fill_reg_map();
1044         tegra_cl_dvfs_device.dev.platform_data = &dalmore_cl_dvfs_data;
1045         platform_device_register(&tegra_cl_dvfs_device);
1046
1047         return 0;
1048 }
1049 #endif
1050
1051 static int __init dalmore_max77663_regulator_init(void)
1052 {
1053         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
1054         u32 pmc_ctrl;
1055
1056         /* configure the power management controller to trigger PMU
1057          * interrupts when low */
1058         pmc_ctrl = readl(pmc + PMC_CTRL);
1059         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
1060
1061         i2c_register_board_info(4, max77663_regulators,
1062                                 ARRAY_SIZE(max77663_regulators));
1063
1064         return 0;
1065 }
1066
1067 static struct regulator_bulk_data dalmore_gps_regulator_supply[] = {
1068         [0] = {
1069                 .supply = "vdd_gps_3v3",
1070         },
1071         [1] = {
1072                 .supply = "vdd_gps_1v8",
1073         },
1074 };
1075
1076 static struct regulator_userspace_consumer_data dalmore_gps_regulator_pdata = {
1077         .num_supplies   = ARRAY_SIZE(dalmore_gps_regulator_supply),
1078         .supplies       = dalmore_gps_regulator_supply,
1079 };
1080
1081 static struct platform_device dalmore_gps_regulator_device = {
1082         .name   = "reg-userspace-consumer",
1083         .id     = 2,
1084         .dev    = {
1085                         .platform_data = &dalmore_gps_regulator_pdata,
1086         },
1087 };
1088
1089 static int __init dalmore_fixed_regulator_init(void)
1090 {
1091         struct board_info board_info;
1092
1093         if (!machine_is_dalmore())
1094                 return 0;
1095
1096         tegra_get_board_info(&board_info);
1097
1098         if (board_info.board_id == BOARD_E1611 ||
1099                 board_info.board_id == BOARD_P2454)
1100                 return platform_add_devices(fixed_reg_devs_e1611_a00,
1101                                 ARRAY_SIZE(fixed_reg_devs_e1611_a00));
1102         else
1103                 return platform_add_devices(fixed_reg_devs_e1612_a00,
1104                                 ARRAY_SIZE(fixed_reg_devs_e1612_a00));
1105 }
1106 subsys_initcall_sync(dalmore_fixed_regulator_init);
1107
1108 static void dalmore_tps65090_init(void)
1109 {
1110         int err;
1111
1112         err = gpio_request(TPS65090_CHARGER_INT, "CHARGER_INT");
1113         if (err < 0) {
1114                 pr_err("%s: gpio_request failed %d\n", __func__, err);
1115                 goto fail_init_irq;
1116         }
1117
1118         err = gpio_direction_input(TPS65090_CHARGER_INT);
1119         if (err < 0) {
1120                 pr_err("%s: gpio_direction_input failed %d\n", __func__, err);
1121                 goto fail_init_irq;
1122         }
1123
1124         tps65090_regulators[0].irq = gpio_to_irq(TPS65090_CHARGER_INT);
1125 fail_init_irq:
1126         i2c_register_board_info(4, tps65090_regulators,
1127                         ARRAY_SIZE(tps65090_regulators));
1128         return;
1129 }
1130
1131 int __init dalmore_regulator_init(void)
1132 {
1133         struct board_info board_info;
1134
1135         dalmore_tps65090_init();
1136 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1137         dalmore_cl_dvfs_init();
1138 #endif
1139         tegra_get_board_info(&board_info);
1140         if (board_info.board_id == BOARD_E1611 ||
1141                 board_info.board_id == BOARD_P2454)
1142                 dalmore_palmas_regulator_init();
1143         else
1144                 dalmore_max77663_regulator_init();
1145
1146         i2c_register_board_info(4, tps51632_boardinfo, 1);
1147         platform_device_register(&dalmore_pda_power_device);
1148         platform_device_register(&dalmore_gps_regulator_device);
1149         return 0;
1150 }
1151
1152 int __init dalmore_suspend_init(void)
1153 {
1154         tegra_init_suspend(&dalmore_suspend_data);
1155         return 0;
1156 }
1157
1158 int __init dalmore_edp_init(void)
1159 {
1160         unsigned int regulator_mA;
1161
1162         regulator_mA = get_maximum_cpu_current_supported();
1163         if (!regulator_mA)
1164                 regulator_mA = 15000;
1165
1166         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1167         tegra_init_cpu_edp_limits(regulator_mA);
1168
1169         regulator_mA = get_maximum_core_current_supported();
1170         if (!regulator_mA)
1171                 regulator_mA = 4000;
1172
1173         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
1174         tegra_init_core_edp_limits(regulator_mA);
1175
1176         return 0;
1177 }
1178
1179 static struct tegra_tsensor_pmu_data tpdata_palmas = {
1180         .reset_tegra = 1,
1181         .pmu_16bit_ops = 0,
1182         .controller_type = 0,
1183         .pmu_i2c_addr = 0x58,
1184         .i2c_controller_id = 4,
1185         .poweroff_reg_addr = 0xa0,
1186         .poweroff_reg_data = 0x0,
1187 };
1188
1189 static struct tegra_tsensor_pmu_data tpdata_max77663 = {
1190         .reset_tegra = 1,
1191         .pmu_16bit_ops = 0,
1192         .controller_type = 0,
1193         .pmu_i2c_addr = 0x3c,
1194         .i2c_controller_id = 4,
1195         .poweroff_reg_addr = 0x41,
1196         .poweroff_reg_data = 0x80,
1197 };
1198
1199 static struct soctherm_platform_data dalmore_soctherm_data = {
1200         .therm = {
1201                 [THERM_CPU] = {
1202                         .zone_enable = true,
1203                         .passive_delay = 1000,
1204                         .num_trips = 3,
1205                         .trips = {
1206                                 {
1207                                         .cdev_type = "tegra-balanced",
1208                                         .trip_temp = 84000,
1209                                         .trip_type = THERMAL_TRIP_PASSIVE,
1210                                         .upper = THERMAL_NO_LIMIT,
1211                                         .lower = THERMAL_NO_LIMIT,
1212                                 },
1213                                 {
1214                                         .cdev_type = "tegra-heavy",
1215                                         .trip_temp = 94000,
1216                                         .trip_type = THERMAL_TRIP_HOT,
1217                                         .upper = THERMAL_NO_LIMIT,
1218                                         .lower = THERMAL_NO_LIMIT,
1219                                 },
1220                                 {
1221                                         .cdev_type = "tegra-shutdown",
1222                                         .trip_temp = 104000,
1223                                         .trip_type = THERMAL_TRIP_CRITICAL,
1224                                         .upper = THERMAL_NO_LIMIT,
1225                                         .lower = THERMAL_NO_LIMIT,
1226                                 },
1227                         },
1228                 },
1229                 [THERM_GPU] = {
1230                         .zone_enable = true,
1231                 },
1232                 [THERM_PLL] = {
1233                         .zone_enable = true,
1234                 },
1235         },
1236         .throttle = {
1237                 [THROTTLE_HEAVY] = {
1238                         .devs = {
1239                                 [THROTTLE_DEV_CPU] = {
1240                                         .enable = 1,
1241                                 },
1242                         },
1243                 },
1244         },
1245         .tshut_pmu_trip_data = &tpdata_palmas,
1246 };
1247
1248 int __init dalmore_soctherm_init(void)
1249 {
1250         struct board_info board_info;
1251
1252         tegra_get_board_info(&board_info);
1253         if (!(board_info.board_id == BOARD_E1611 ||
1254                 board_info.board_id == BOARD_P2454))
1255                 dalmore_soctherm_data.tshut_pmu_trip_data = &tpdata_max77663;
1256
1257         tegra_platform_edp_init(dalmore_soctherm_data.therm[THERM_CPU].trips,
1258                         &dalmore_soctherm_data.therm[THERM_CPU].num_trips);
1259         tegra_add_tj_trips(dalmore_soctherm_data.therm[THERM_CPU].trips,
1260                         &dalmore_soctherm_data.therm[THERM_CPU].num_trips);
1261
1262         return tegra11_soctherm_init(&dalmore_soctherm_data);
1263 }