c322f3639b44225e757a329f7488900498d01c90
[linux-3.10.git] / arch / arm / mach-tegra / board-dalmore-power.c
1 /*
2  * arch/arm/mach-tegra/board-dalmore-power.c
3  *
4  * Copyright (C) 2012-2013 NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/max77663-core.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/mfd/tps65090.h>
31 #include <linux/regulator/max77663-regulator.h>
32 #include <linux/regulator/tps65090-regulator.h>
33 #include <linux/regulator/tps51632-regulator.h>
34 #include <linux/gpio.h>
35 #include <linux/interrupt.h>
36 #include <linux/regulator/userspace-consumer.h>
37
38 #include <asm/mach-types.h>
39 #include <linux/power/sbs-battery.h>
40
41 #include <mach/irqs.h>
42 #include <mach/edp.h>
43 #include <mach/gpio-tegra.h>
44
45 #include "cpu-tegra.h"
46 #include "pm.h"
47 #include "tegra-board-id.h"
48 #include "board.h"
49 #include "gpio-names.h"
50 #include "board-common.h"
51 #include "board-dalmore.h"
52 #include "tegra_cl_dvfs.h"
53 #include "devices.h"
54 #include "tegra11_soctherm.h"
55 #include "iomap.h"
56
57 #define PMC_CTRL                0x0
58 #define PMC_CTRL_INTR_LOW       (1 << 17)
59 #define TPS65090_CHARGER_INT    TEGRA_GPIO_PJ0
60 /*TPS65090 consumer rails */
61 static struct regulator_consumer_supply tps65090_dcdc1_supply[] = {
62         REGULATOR_SUPPLY("vdd_sys_5v0", NULL),
63         REGULATOR_SUPPLY("vdd_spk", NULL),
64         REGULATOR_SUPPLY("vdd_sys_modem_5v0", NULL),
65         REGULATOR_SUPPLY("vdd_sys_cam_5v0", NULL),
66 };
67
68 static struct regulator_consumer_supply tps65090_dcdc2_supply[] = {
69         REGULATOR_SUPPLY("vdd_sys_3v3", NULL),
70         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
71         REGULATOR_SUPPLY("pwrdet_hv", NULL),
72         REGULATOR_SUPPLY("vdd_sys_ds_3v3", NULL),
73         REGULATOR_SUPPLY("vdd_sys_nfc_3v3", NULL),
74         REGULATOR_SUPPLY("vdd_hv_nfc_3v3", NULL),
75         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
76         REGULATOR_SUPPLY("vdd_sys_sensor_3v3", NULL),
77         REGULATOR_SUPPLY("vdd_sys_audio_3v3", NULL),
78         REGULATOR_SUPPLY("vdd_sys_dtv_3v3", NULL),
79         REGULATOR_SUPPLY("vcc", "0-007c"),
80         REGULATOR_SUPPLY("vcc", "0-0030"),
81         REGULATOR_SUPPLY("vin", "2-0030"),
82 };
83
84 static struct regulator_consumer_supply tps65090_dcdc3_supply[] = {
85         REGULATOR_SUPPLY("vdd_ao", NULL),
86 };
87
88 static struct regulator_consumer_supply tps65090_ldo1_supply[] = {
89         REGULATOR_SUPPLY("vdd_sby_5v0", NULL),
90 };
91
92 static struct regulator_consumer_supply tps65090_ldo2_supply[] = {
93         REGULATOR_SUPPLY("vdd_sby_3v3", NULL),
94 };
95
96 static struct regulator_consumer_supply tps65090_fet1_supply[] = {
97         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
98 };
99
100 static struct regulator_consumer_supply tps65090_fet3_supply[] = {
101         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
102 };
103
104 static struct regulator_consumer_supply tps65090_fet4_supply[] = {
105         REGULATOR_SUPPLY("avdd_lcd", NULL),
106         REGULATOR_SUPPLY("avdd", "spi3.2"),
107 };
108
109 static struct regulator_consumer_supply tps65090_fet5_supply[] = {
110         REGULATOR_SUPPLY("vdd_lvds", NULL),
111 };
112
113 static struct regulator_consumer_supply tps65090_fet6_supply[] = {
114         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
115 };
116
117 static struct regulator_consumer_supply tps65090_fet7_supply[] = {
118         REGULATOR_SUPPLY("vdd_wifi_3v3", "bcm4329_wlan.1"),
119         REGULATOR_SUPPLY("vdd_gps_3v3", "reg-userspace-consumer.2"),
120         REGULATOR_SUPPLY("vdd_bt_3v3", "bluedroid_pm.0"),
121 };
122
123 #define TPS65090_PDATA_INIT(_id, _name, _supply_reg,                    \
124         _always_on, _boot_on, _apply_uV, _en_ext_ctrl, _gpio, _wait_to) \
125 static struct regulator_init_data ri_data_##_name =                     \
126 {                                                                       \
127         .supply_regulator = _supply_reg,                                \
128         .constraints = {                                                \
129                 .name = tps65090_rails(_id),                            \
130                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
131                                      REGULATOR_MODE_STANDBY),           \
132                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
133                                    REGULATOR_CHANGE_STATUS |            \
134                                    REGULATOR_CHANGE_VOLTAGE),           \
135                 .always_on = _always_on,                                \
136                 .boot_on = _boot_on,                                    \
137                 .apply_uV = _apply_uV,                                  \
138         },                                                              \
139         .num_consumer_supplies =                                        \
140                 ARRAY_SIZE(tps65090_##_name##_supply),                  \
141         .consumer_supplies = tps65090_##_name##_supply,                 \
142 };                                                                      \
143 static struct tps65090_regulator_platform_data                          \
144                         tps65090_regulator_pdata_##_name =              \
145 {                                                                       \
146         .id = TPS65090_REGULATOR_##_id,                                 \
147         .enable_ext_control = _en_ext_ctrl,                             \
148         .gpio = _gpio,                                                  \
149         .reg_init_data = &ri_data_##_name ,                             \
150         .wait_timeout_us = _wait_to,                                    \
151 }
152
153 TPS65090_PDATA_INIT(DCDC1, dcdc1, NULL, 1, 1, 0, true, -1, -1);
154 TPS65090_PDATA_INIT(DCDC2, dcdc2, NULL, 1, 1, 0, true, -1, -1);
155 TPS65090_PDATA_INIT(DCDC3, dcdc3, NULL, 1, 1, 0, true, -1, -1);
156 TPS65090_PDATA_INIT(LDO1, ldo1, NULL, 1, 1, 0, false, -1, -1);
157 TPS65090_PDATA_INIT(LDO2, ldo2, NULL, 1, 1, 0, false, -1, -1);
158 TPS65090_PDATA_INIT(FET1, fet1, NULL, 0, 0, 0, false, -1, 800);
159 TPS65090_PDATA_INIT(FET3, fet3, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
160 TPS65090_PDATA_INIT(FET4, fet4, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
161 TPS65090_PDATA_INIT(FET5, fet5, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
162 TPS65090_PDATA_INIT(FET6, fet6, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
163 TPS65090_PDATA_INIT(FET7, fet7, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
164
165 #define ADD_TPS65090_REG(_name) (&tps65090_regulator_pdata_##_name)
166 static struct tps65090_regulator_platform_data *tps65090_reg_pdata[] = {
167         ADD_TPS65090_REG(dcdc1),
168         ADD_TPS65090_REG(dcdc2),
169         ADD_TPS65090_REG(dcdc3),
170         ADD_TPS65090_REG(ldo1),
171         ADD_TPS65090_REG(ldo2),
172         ADD_TPS65090_REG(fet1),
173         ADD_TPS65090_REG(fet3),
174         ADD_TPS65090_REG(fet4),
175         ADD_TPS65090_REG(fet5),
176         ADD_TPS65090_REG(fet6),
177         ADD_TPS65090_REG(fet7),
178 };
179
180 static struct tps65090_charger_data bcharger_pdata = {
181         .irq_base = TPS65090_TEGRA_IRQ_BASE,
182         .update_status = sbs_update,
183 };
184
185 static struct tps65090_platform_data tps65090_pdata = {
186         .irq_base = TPS65090_TEGRA_IRQ_BASE,
187         .irq_flag = IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
188         .num_reg_pdata =  ARRAY_SIZE(tps65090_reg_pdata),
189         .reg_pdata = tps65090_reg_pdata,
190         .charger_pdata = &bcharger_pdata,
191 };
192
193 /* MAX77663 consumer rails */
194 static struct regulator_consumer_supply max77663_sd0_supply[] = {
195         REGULATOR_SUPPLY("vdd_core", NULL),
196 };
197
198 static struct regulator_consumer_supply max77663_sd1_supply[] = {
199         REGULATOR_SUPPLY("vddio_ddr", NULL),
200         REGULATOR_SUPPLY("vddio_ddr0", NULL),
201         REGULATOR_SUPPLY("vddio_ddr1", NULL),
202 };
203
204 static struct regulator_consumer_supply max77663_sd2_supply[] = {
205         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
206         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
207         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
208         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
209         REGULATOR_SUPPLY("pwrdet_cam", NULL),
210         REGULATOR_SUPPLY("avdd_osc", NULL),
211         REGULATOR_SUPPLY("vddio_sys", NULL),
212         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
213         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
214         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
215         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
216         REGULATOR_SUPPLY("vdd_emmc", NULL),
217         REGULATOR_SUPPLY("vddio_audio", NULL),
218         REGULATOR_SUPPLY("pwrdet_audio", NULL),
219         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
220         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
221         REGULATOR_SUPPLY("vddio_modem", NULL),
222         REGULATOR_SUPPLY("vddio_modem_1v8", NULL),
223         REGULATOR_SUPPLY("vddio_bb", NULL),
224         REGULATOR_SUPPLY("pwrdet_bb", NULL),
225         REGULATOR_SUPPLY("vddio_bb_1v8", NULL),
226         REGULATOR_SUPPLY("vddio_uart", NULL),
227         REGULATOR_SUPPLY("pwrdet_uart", NULL),
228         REGULATOR_SUPPLY("vddio_gmi", NULL),
229         REGULATOR_SUPPLY("pwrdet_nand", NULL),
230         REGULATOR_SUPPLY("vdd_sensor_1v8", NULL),
231         REGULATOR_SUPPLY("vdd_mic_1v8", NULL),
232         REGULATOR_SUPPLY("vdd_nfc_1v8", NULL),
233         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
234         REGULATOR_SUPPLY("vdd_spi_1v8", NULL),
235         REGULATOR_SUPPLY("dvdd_lcd", NULL),
236         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
237         REGULATOR_SUPPLY("vddio_wifi_1v8", "bcm4329_wlan.1"),
238         REGULATOR_SUPPLY("vdd_gps_1v8", "reg-userspace-consumer.2"),
239         REGULATOR_SUPPLY("vddio_bt_1v8", "bluedroid_pm.0"),
240         REGULATOR_SUPPLY("vdd_dtv_1v8", NULL),
241         REGULATOR_SUPPLY("vlogic", "0-0069"),
242 };
243
244 static struct regulator_consumer_supply max77663_sd3_supply[] = {
245         REGULATOR_SUPPLY("vcore_emmc", NULL),
246 };
247
248 static struct regulator_consumer_supply max77663_ldo0_supply[] = {
249         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
250         REGULATOR_SUPPLY("avdd_pllx", NULL),
251         REGULATOR_SUPPLY("avdd_plle", NULL),
252         REGULATOR_SUPPLY("avdd_pllm", NULL),
253         REGULATOR_SUPPLY("avdd_pllu", NULL),
254         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
255         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
256         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
257 };
258
259 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
260         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
261 };
262
263 static struct regulator_consumer_supply max77663_ldo2_supply[] = {
264         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
265         REGULATOR_SUPPLY("vdd_als", NULL),
266         REGULATOR_SUPPLY("vdd", "0-004c"),
267         REGULATOR_SUPPLY("vdd", "0-0069"),
268 };
269
270 static struct regulator_consumer_supply max77663_ldo3_supply[] = {
271         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
272         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
273         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
274 };
275
276 static struct regulator_consumer_supply max77663_ldo4_supply[] = {
277         REGULATOR_SUPPLY("vdd_rtc", NULL),
278 };
279
280 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
281         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
282         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
283         REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"),
284         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
285         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
286         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
287         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
288         REGULATOR_SUPPLY("vddio_bb_hsic", NULL),
289 };
290
291 static struct regulator_consumer_supply max77663_ldo6_supply[] = {
292         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
293         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
294 };
295
296 /* FIXME!! Put the device address of camera */
297 static struct regulator_consumer_supply max77663_ldo7_supply[] = {
298         REGULATOR_SUPPLY("avdd_cam1", NULL),
299         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
300         REGULATOR_SUPPLY("vana", "2-0036"),
301 };
302
303 /* FIXME!! Put the device address of camera */
304 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
305         REGULATOR_SUPPLY("avdd_cam2", NULL),
306         REGULATOR_SUPPLY("avdd", "2-0010"),
307 };
308
309 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
310         {
311                 .src = FPS_SRC_0,
312                 .en_src = FPS_EN_SRC_EN0,
313                 .time_period = FPS_TIME_PERIOD_DEF,
314         },
315         {
316                 .src = FPS_SRC_1,
317                 .en_src = FPS_EN_SRC_EN1,
318                 .time_period = FPS_TIME_PERIOD_DEF,
319         },
320         {
321                 .src = FPS_SRC_2,
322                 .en_src = FPS_EN_SRC_EN0,
323                 .time_period = FPS_TIME_PERIOD_DEF,
324         },
325 };
326
327 #define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg,   \
328                 _always_on, _boot_on, _apply_uV,                        \
329                 _fps_src, _fps_pu_period, _fps_pd_period, _flags)       \
330         static struct regulator_init_data max77663_regulator_idata_##_id = {   \
331                 .supply_regulator = _supply_reg,                        \
332                 .constraints = {                                        \
333                         .name = max77663_rails(_id),                    \
334                         .min_uV = _min_uV,                              \
335                         .max_uV = _max_uV,                              \
336                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
337                                              REGULATOR_MODE_STANDBY),   \
338                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
339                                            REGULATOR_CHANGE_STATUS |    \
340                                            REGULATOR_CHANGE_VOLTAGE),   \
341                         .always_on = _always_on,                        \
342                         .boot_on = _boot_on,                            \
343                         .apply_uV = _apply_uV,                          \
344                 },                                                      \
345                 .num_consumer_supplies =                                \
346                         ARRAY_SIZE(max77663_##_id##_supply),            \
347                 .consumer_supplies = max77663_##_id##_supply,           \
348         };                                                              \
349 static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id =\
350 {                                                                       \
351                 .reg_init_data = &max77663_regulator_idata_##_id,       \
352                 .id = MAX77663_REGULATOR_ID_##_rid,                     \
353                 .fps_src = _fps_src,                                    \
354                 .fps_pu_period = _fps_pu_period,                        \
355                 .fps_pd_period = _fps_pd_period,                        \
356                 .fps_cfgs = max77663_fps_cfgs,                          \
357                 .flags = _flags,                                        \
358         }
359
360 MAX77663_PDATA_INIT(SD0, sd0,  900000, 1400000, tps65090_rails(DCDC3), 1, 1, 0,
361                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
362
363 MAX77663_PDATA_INIT(SD1, sd1,  1200000, 1200000, tps65090_rails(DCDC3), 1, 1, 1,
364                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
365
366 MAX77663_PDATA_INIT(SD2, sd2,  1800000, 1800000, tps65090_rails(DCDC3), 1, 1, 1,
367                     FPS_SRC_0, -1, -1, 0);
368
369 MAX77663_PDATA_INIT(SD3, sd3,  2850000, 2850000, tps65090_rails(DCDC3), 1, 1, 1,
370                     FPS_SRC_NONE, -1, -1, 0);
371
372 MAX77663_PDATA_INIT(LDO0, ldo0, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
373                     FPS_SRC_1, -1, -1, 0);
374
375 MAX77663_PDATA_INIT(LDO1, ldo1, 1050000, 1050000, max77663_rails(sd2), 0, 0, 1,
376                     FPS_SRC_NONE, -1, -1, 0);
377
378 MAX77663_PDATA_INIT(LDO2, ldo2, 2850000, 2850000, tps65090_rails(DCDC2), 1, 1,
379                     1, FPS_SRC_1, -1, -1, 0);
380
381 MAX77663_PDATA_INIT(LDO3, ldo3, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
382                     FPS_SRC_NONE, -1, -1, 0);
383
384 MAX77663_PDATA_INIT(LDO4, ldo4, 1100000, 1100000, tps65090_rails(DCDC2), 1, 1,
385                     1, FPS_SRC_NONE, -1, -1, 0);
386
387 MAX77663_PDATA_INIT(LDO5, ldo5, 1200000, 1200000, max77663_rails(sd2), 0, 1, 1,
388                     FPS_SRC_NONE, -1, -1, 0);
389
390 MAX77663_PDATA_INIT(LDO6, ldo6, 1800000, 3300000, tps65090_rails(DCDC2), 0, 0, 0,
391                     FPS_SRC_NONE, -1, -1, 0);
392
393 MAX77663_PDATA_INIT(LDO7, ldo7, 2800000, 2800000, tps65090_rails(DCDC2), 0, 0, 1,
394                     FPS_SRC_NONE, -1, -1, 0);
395
396 MAX77663_PDATA_INIT(LDO8, ldo8, 2800000, 2800000, tps65090_rails(DCDC2), 0, 1, 1,
397                     FPS_SRC_1, -1, -1, 0);
398
399 #define MAX77663_REG(_id, _data) (&max77663_regulator_pdata_##_data)
400
401 static struct max77663_regulator_platform_data *max77663_reg_pdata[] = {
402         MAX77663_REG(SD0, sd0),
403         MAX77663_REG(SD1, sd1),
404         MAX77663_REG(SD2, sd2),
405         MAX77663_REG(SD3, sd3),
406         MAX77663_REG(LDO0, ldo0),
407         MAX77663_REG(LDO1, ldo1),
408         MAX77663_REG(LDO2, ldo2),
409         MAX77663_REG(LDO3, ldo3),
410         MAX77663_REG(LDO4, ldo4),
411         MAX77663_REG(LDO5, ldo5),
412         MAX77663_REG(LDO6, ldo6),
413         MAX77663_REG(LDO7, ldo7),
414         MAX77663_REG(LDO8, ldo8),
415 };
416
417 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
418         {
419                 .gpio = MAX77663_GPIO0,
420                 .dir = GPIO_DIR_OUT,
421                 .dout = GPIO_DOUT_LOW,
422                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
423                 .alternate = GPIO_ALT_DISABLE,
424         },
425         {
426                 .gpio = MAX77663_GPIO1,
427                 .dir = GPIO_DIR_IN,
428                 .dout = GPIO_DOUT_HIGH,
429                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
430                 .pull_up = GPIO_PU_ENABLE,
431                 .alternate = GPIO_ALT_DISABLE,
432         },
433         {
434                 .gpio = MAX77663_GPIO2,
435                 .dir = GPIO_DIR_OUT,
436                 .dout = GPIO_DOUT_HIGH,
437                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
438                 .pull_up = GPIO_PU_ENABLE,
439                 .alternate = GPIO_ALT_DISABLE,
440         },
441         {
442                 .gpio = MAX77663_GPIO3,
443                 .dir = GPIO_DIR_OUT,
444                 .dout = GPIO_DOUT_HIGH,
445                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
446                 .pull_up = GPIO_PU_ENABLE,
447                 .alternate = GPIO_ALT_DISABLE,
448         },
449         {
450                 .gpio = MAX77663_GPIO4,
451                 .dir = GPIO_DIR_OUT,
452                 .dout = GPIO_DOUT_HIGH,
453                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
454                 .alternate = GPIO_ALT_ENABLE,
455         },
456         {
457                 .gpio = MAX77663_GPIO5,
458                 .dir = GPIO_DIR_OUT,
459                 .dout = GPIO_DOUT_LOW,
460                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
461                 .alternate = GPIO_ALT_DISABLE,
462         },
463         {
464                 .gpio = MAX77663_GPIO6,
465                 .dir = GPIO_DIR_OUT,
466                 .dout = GPIO_DOUT_LOW,
467                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
468                 .alternate = GPIO_ALT_DISABLE,
469         },
470         {
471                 .gpio = MAX77663_GPIO7,
472                 .dir = GPIO_DIR_OUT,
473                 .dout = GPIO_DOUT_LOW,
474                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
475                 .alternate = GPIO_ALT_DISABLE,
476         },
477 };
478
479 static struct max77663_platform_data max77663_pdata = {
480         .irq_base       = MAX77663_IRQ_BASE,
481         .gpio_base      = MAX77663_GPIO_BASE,
482
483         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
484         .gpio_cfgs      = max77663_gpio_cfgs,
485
486         .regulator_pdata = max77663_reg_pdata,
487         .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata),
488
489         .rtc_i2c_addr   = 0x68,
490
491         .use_power_off  = false,
492 };
493
494 static struct i2c_board_info __initdata max77663_regulators[] = {
495         {
496                 /* The I2C address was determined by OTP factory setting */
497                 I2C_BOARD_INFO("max77663", 0x3c),
498                 .irq            = INT_EXTERNAL_PMU,
499                 .platform_data  = &max77663_pdata,
500         },
501 };
502
503 static struct i2c_board_info __initdata tps65090_regulators[] = {
504         {
505                 I2C_BOARD_INFO("tps65090", 0x48),
506                 .platform_data  = &tps65090_pdata,
507         },
508 };
509
510 /* TPS51632 DC-DC converter */
511 static struct regulator_consumer_supply tps51632_dcdc_supply[] = {
512         REGULATOR_SUPPLY("vdd_cpu", NULL),
513 };
514
515 static struct regulator_init_data tps51632_init_data = {
516         .constraints = {                                                \
517                 .min_uV = 500000,                                       \
518                 .max_uV = 1520000,                                      \
519                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
520                                         REGULATOR_MODE_STANDBY),        \
521                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
522                                         REGULATOR_CHANGE_STATUS |       \
523                                          REGULATOR_CHANGE_CONTROL |     \
524                                         REGULATOR_CHANGE_VOLTAGE),      \
525                 .always_on = 1,                                         \
526                 .boot_on =  1,                                          \
527                 .apply_uV = 0,                                          \
528         },                                                              \
529         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply),      \
530                 .consumer_supplies = tps51632_dcdc_supply,              \
531 };
532
533 static struct tps51632_regulator_platform_data tps51632_pdata = {
534         .reg_init_data = &tps51632_init_data,           \
535         .enable_pwm = false,                            \
536         .max_voltage_uV = 1520000,                      \
537         .base_voltage_uV = 500000,                      \
538         .slew_rate_uv_per_us = 6000,                    \
539 };
540
541 static struct i2c_board_info __initdata tps51632_boardinfo[] = {
542         {
543                 I2C_BOARD_INFO("tps51632", 0x43),
544                 .platform_data  = &tps51632_pdata,
545         },
546 };
547
548 /************************ Palmas based regulator ****************/
549 static struct regulator_consumer_supply palmas_smps12_supply[] = {
550         REGULATOR_SUPPLY("vddio_ddr3l", NULL),
551         REGULATOR_SUPPLY("vcore_ddr3l", NULL),
552         REGULATOR_SUPPLY("vref2_ddr3l", NULL),
553 };
554
555 #define palmas_smps3_supply max77663_sd2_supply
556 #define palmas_smps45_supply max77663_sd0_supply
557 #define palmas_smps457_supply max77663_sd0_supply
558
559 static struct regulator_consumer_supply palmas_smps8_supply[] = {
560         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
561         REGULATOR_SUPPLY("avdd_pllm", NULL),
562         REGULATOR_SUPPLY("avdd_pllu", NULL),
563         REGULATOR_SUPPLY("avdd_pllx", NULL),
564         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
565         REGULATOR_SUPPLY("avdd_plle", NULL),
566         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
567         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
568         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"),
569         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
570         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
571         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
572         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
573         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
574 };
575
576 static struct regulator_consumer_supply palmas_smps9_supply[] = {
577         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
578 };
579
580 #define palmas_ldo1_supply max77663_ldo7_supply
581 #define palmas_ldo2_supply max77663_ldo8_supply
582 #define palmas_ldo3_supply max77663_ldo5_supply
583
584 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
585         REGULATOR_SUPPLY("vpp_fuse", NULL),
586 };
587
588 #define palmas_ldo6_supply max77663_ldo2_supply
589
590 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
591         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
592         REGULATOR_SUPPLY("vdd", "2-000e"),
593 };
594
595 #define palmas_ldo8_supply max77663_ldo4_supply
596 #define palmas_ldo9_supply max77663_ldo6_supply
597
598 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
599         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
600         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
601 };
602
603 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
604         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
605         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
606         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
607         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
608         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
609 };
610
611 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
612         _boot_on, _apply_uv)                                            \
613         static struct regulator_init_data reg_idata_##_name = {         \
614                 .constraints = {                                        \
615                         .name = palmas_rails(_name),                    \
616                         .min_uV = (_minmv)*1000,                        \
617                         .max_uV = (_maxmv)*1000,                        \
618                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
619                                         REGULATOR_MODE_STANDBY),        \
620                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
621                                         REGULATOR_CHANGE_STATUS |       \
622                                         REGULATOR_CHANGE_VOLTAGE),      \
623                         .always_on = _always_on,                        \
624                         .boot_on = _boot_on,                            \
625                         .apply_uV = _apply_uv,                          \
626                 },                                                      \
627                 .num_consumer_supplies =                                \
628                         ARRAY_SIZE(palmas_##_name##_supply),            \
629                 .consumer_supplies = palmas_##_name##_supply,           \
630                 .supply_regulator = _supply_reg,                        \
631         }
632
633 PALMAS_PDATA_INIT(smps12, 1350,  1350, tps65090_rails(DCDC3), 0, 0, 0);
634 PALMAS_PDATA_INIT(smps3, 1800,  1800, tps65090_rails(DCDC3), 0, 0, 0);
635 PALMAS_PDATA_INIT(smps45, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0);
636 PALMAS_PDATA_INIT(smps457, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0);
637 PALMAS_PDATA_INIT(smps8, 1050,  1050, tps65090_rails(DCDC2), 0, 1, 1);
638 PALMAS_PDATA_INIT(smps9, 2800,  2800, tps65090_rails(DCDC2), 1, 0, 0);
639 PALMAS_PDATA_INIT(ldo1, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
640 PALMAS_PDATA_INIT(ldo2, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
641 PALMAS_PDATA_INIT(ldo3, 1200,  1200, palmas_rails(smps3), 0, 0, 1);
642 PALMAS_PDATA_INIT(ldo4, 1800,  1800, tps65090_rails(DCDC2), 0, 0, 0);
643 PALMAS_PDATA_INIT(ldo6, 2850,  2850, tps65090_rails(DCDC2), 0, 0, 1);
644 PALMAS_PDATA_INIT(ldo7, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1);
645 PALMAS_PDATA_INIT(ldo8, 900,  900, tps65090_rails(DCDC3), 1, 1, 1);
646 PALMAS_PDATA_INIT(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1);
647 PALMAS_PDATA_INIT(ldoln, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1);
648 PALMAS_PDATA_INIT(ldousb, 3300,  3300, tps65090_rails(DCDC1), 0, 0, 1);
649
650 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
651
652 static struct regulator_init_data *dalmore_e1611_reg_data[PALMAS_NUM_REGS] = {
653         PALMAS_REG_PDATA(smps12),
654         NULL,
655         PALMAS_REG_PDATA(smps3),
656         PALMAS_REG_PDATA(smps45),
657         PALMAS_REG_PDATA(smps457),
658         NULL,
659         NULL,
660         PALMAS_REG_PDATA(smps8),
661         PALMAS_REG_PDATA(smps9),
662         NULL,
663         PALMAS_REG_PDATA(ldo1),
664         PALMAS_REG_PDATA(ldo2),
665         PALMAS_REG_PDATA(ldo3),
666         PALMAS_REG_PDATA(ldo4),
667         NULL,
668         PALMAS_REG_PDATA(ldo6),
669         PALMAS_REG_PDATA(ldo7),
670         PALMAS_REG_PDATA(ldo8),
671         PALMAS_REG_PDATA(ldo9),
672         PALMAS_REG_PDATA(ldoln),
673         PALMAS_REG_PDATA(ldousb),
674         NULL,
675         NULL,
676         NULL,
677         NULL,
678         NULL,
679 };
680
681 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
682                 _tstep, _vsel)                                          \
683         static struct palmas_reg_init reg_init_data_##_name = {         \
684                 .warm_reset = _warm_reset,                              \
685                 .roof_floor =   _roof_floor,                            \
686                 .mode_sleep = _mode_sleep,                              \
687                 .tstep = _tstep,                                        \
688                 .vsel = _vsel,                                          \
689         }
690
691 PALMAS_REG_INIT(smps12, 0, 0, 0, 0, 0);
692 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
693 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
694 PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
695 PALMAS_REG_INIT(smps457, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
696 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
697 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
698 PALMAS_REG_INIT(smps8, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
699 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
700 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
701 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
702 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
703 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
704 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
705 PALMAS_REG_INIT(ldo5, 0, 0, 0, 0, 0);
706 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
707 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
708 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
709 PALMAS_REG_INIT(ldo9, 1, 0, 0, 0, 0);
710 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
711 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
712 PALMAS_REG_INIT(regen1, 0, 0, 0, 0, 0);
713 PALMAS_REG_INIT(regen2, 0, 0, 0, 0, 0);
714 PALMAS_REG_INIT(regen3, 0, 0, 0, 0, 0);
715 PALMAS_REG_INIT(sysen1, 0, 0, 0, 0, 0);
716 PALMAS_REG_INIT(sysen2, 0, 0, 0, 0, 0);
717
718 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
719 static struct palmas_reg_init *dalmore_e1611_reg_init[PALMAS_NUM_REGS] = {
720         PALMAS_REG_INIT_DATA(smps12),
721         PALMAS_REG_INIT_DATA(smps123),
722         PALMAS_REG_INIT_DATA(smps3),
723         PALMAS_REG_INIT_DATA(smps45),
724         PALMAS_REG_INIT_DATA(smps457),
725         PALMAS_REG_INIT_DATA(smps6),
726         PALMAS_REG_INIT_DATA(smps7),
727         PALMAS_REG_INIT_DATA(smps8),
728         PALMAS_REG_INIT_DATA(smps9),
729         PALMAS_REG_INIT_DATA(smps10),
730         PALMAS_REG_INIT_DATA(ldo1),
731         PALMAS_REG_INIT_DATA(ldo2),
732         PALMAS_REG_INIT_DATA(ldo3),
733         PALMAS_REG_INIT_DATA(ldo4),
734         PALMAS_REG_INIT_DATA(ldo5),
735         PALMAS_REG_INIT_DATA(ldo6),
736         PALMAS_REG_INIT_DATA(ldo7),
737         PALMAS_REG_INIT_DATA(ldo8),
738         PALMAS_REG_INIT_DATA(ldo9),
739         PALMAS_REG_INIT_DATA(ldoln),
740         PALMAS_REG_INIT_DATA(ldousb),
741         PALMAS_REG_INIT_DATA(regen1),
742         PALMAS_REG_INIT_DATA(regen2),
743         PALMAS_REG_INIT_DATA(regen3),
744         PALMAS_REG_INIT_DATA(sysen1),
745         PALMAS_REG_INIT_DATA(sysen2),
746 };
747
748 static struct palmas_pmic_platform_data pmic_platform = {
749         .enable_ldo8_tracking = true,
750         .disabe_ldo8_tracking_suspend = true,
751 };
752
753 static struct palmas_rtc_platform_data rtc_platform = {
754         .enable_charging = 1,
755         .charging_current_ua = 100,
756 };
757
758 static struct palmas_platform_data palmas_pdata = {
759         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
760         .irq_base = PALMAS_TEGRA_IRQ_BASE,
761         .pmic_pdata = &pmic_platform,
762         .rtc_pdata = &rtc_platform,
763         .mux_from_pdata = true,
764         .pad1 = 0,
765         .pad2 = 0,
766         .pad3 = PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1,
767         .use_power_off = true,
768 };
769
770 static struct i2c_board_info palma_device[] = {
771         {
772                 I2C_BOARD_INFO("tps65913", 0x58),
773                 .irq            = INT_EXTERNAL_PMU,
774                 .platform_data  = &palmas_pdata,
775         },
776 };
777
778 /* EN_AVDD_USB_HDMI From PMU GP1 */
779 static struct regulator_consumer_supply fixed_reg_avdd_usb_hdmi_supply[] = {
780         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
781         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
782         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
783         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
784         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
785         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
786 };
787
788 /* EN_CAM_1v8 From PMU GP5 */
789 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
790         REGULATOR_SUPPLY("vi2c", "2-0030"),
791         REGULATOR_SUPPLY("vif", "2-0036"),
792         REGULATOR_SUPPLY("dovdd", "2-0010"),
793         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
794 };
795
796 /* EN_CAM_1v8 on e1611 From PMU GP6 */
797 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_e1611_supply[] = {
798         REGULATOR_SUPPLY("vi2c", "2-0030"),
799         REGULATOR_SUPPLY("vif", "2-0036"),
800         REGULATOR_SUPPLY("dovdd", "2-0010"),
801         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
802 };
803
804 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
805         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
806 };
807
808 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
809         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
810 };
811
812 /* EN_USB1_VBUS From TEGRA GPIO PN4 PR3(T30) */
813 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
814         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
815 };
816
817 /* EN_3V3_FUSE From TEGRA GPIO PX4 */
818 static struct regulator_consumer_supply fixed_reg_vpp_fuse_supply[] = {
819         REGULATOR_SUPPLY("vpp_fuse", NULL),
820 };
821
822 /* EN_USB3_VBUS From TEGRA GPIO PM5 */
823 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
824         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
825         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci"),
826 };
827
828 /* EN_1V8_TS From TEGRA_GPIO_PH5 */
829 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
830         REGULATOR_SUPPLY("dvdd", "spi3.2"),
831 };
832
833 /* Macro for defining fixed regulator sub device data */
834 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
835 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
836         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
837         static struct regulator_init_data ri_data_##_var =              \
838         {                                                               \
839                 .supply_regulator = _in_supply,                         \
840                 .num_consumer_supplies =                                \
841                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
842                 .consumer_supplies = fixed_reg_##_name##_supply,        \
843                 .constraints = {                                        \
844                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
845                                         REGULATOR_MODE_STANDBY),        \
846                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
847                                         REGULATOR_CHANGE_STATUS |       \
848                                         REGULATOR_CHANGE_VOLTAGE),      \
849                         .always_on = _always_on,                        \
850                         .boot_on = _boot_on,                            \
851                 },                                                      \
852         };                                                              \
853         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
854         {                                                               \
855                 .supply_name = FIXED_SUPPLY(_name),                     \
856                 .microvolts = _millivolts * 1000,                       \
857                 .gpio = _gpio_nr,                                       \
858                 .gpio_is_open_drain = _open_drain,                      \
859                 .enable_high = _active_high,                            \
860                 .enabled_at_boot = _boot_state,                         \
861                 .init_data = &ri_data_##_var,                           \
862         };                                                              \
863         static struct platform_device fixed_reg_##_var##_dev = {        \
864                 .name = "reg-fixed-voltage",                            \
865                 .id = _id,                                              \
866                 .dev = {                                                \
867                         .platform_data = &fixed_reg_##_var##_pdata,     \
868                 },                                                      \
869         }
870
871 FIXED_REG(1,    avdd_usb_hdmi,  avdd_usb_hdmi,
872         tps65090_rails(DCDC2),  0,      0,
873         MAX77663_GPIO_BASE + MAX77663_GPIO1,    true,   true,   1,      3300);
874
875 FIXED_REG(2,    en_1v8_cam,     en_1v8_cam,
876         max77663_rails(sd2),    0,      0,
877         MAX77663_GPIO_BASE + MAX77663_GPIO5,    false,  true,   0,      1800);
878
879 FIXED_REG(3,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
880         tps65090_rails(DCDC1),  0,      0,
881         TEGRA_GPIO_PK1, false,  true,   0,      5000);
882
883 FIXED_REG(4,    vpp_fuse,       vpp_fuse,
884         max77663_rails(sd2),    0,      0,
885         TEGRA_GPIO_PX4, false,  true,   0,      3300);
886
887 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
888         tps65090_rails(DCDC1),  0,      0,
889         TEGRA_GPIO_PN4, true,   true,   0,      5000);
890
891 FIXED_REG(6,    usb3_vbus,      usb3_vbus,
892         tps65090_rails(DCDC1),  0,      0,
893         TEGRA_GPIO_PK6, true,   true,   0,      5000);
894
895 FIXED_REG(7,    en_1v8_cam_e1611,       en_1v8_cam_e1611,
896         palmas_rails(smps3),    0,      0,
897         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
898
899 FIXED_REG(8,    dvdd_ts,        dvdd_ts,
900         palmas_rails(smps3),    0,      0,
901         TEGRA_GPIO_PH5, false,  false,  1,      1800);
902
903 FIXED_REG(9,    lcd_bl_en,      lcd_bl_en,
904         NULL,   0,      0,
905         TEGRA_GPIO_PH2, false,  true,   0,      5000);
906 /*
907  * Creating the fixed regulator device tables
908  */
909
910 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
911
912 #define DALMORE_COMMON_FIXED_REG                \
913         ADD_FIXED_REG(usb1_vbus),               \
914         ADD_FIXED_REG(usb3_vbus),               \
915         ADD_FIXED_REG(vdd_hdmi_5v0),            \
916         ADD_FIXED_REG(lcd_bl_en),
917
918 #define E1612_FIXED_REG                         \
919         ADD_FIXED_REG(avdd_usb_hdmi),           \
920         ADD_FIXED_REG(en_1v8_cam),              \
921         ADD_FIXED_REG(vpp_fuse),                \
922
923 #define E1611_FIXED_REG                         \
924         ADD_FIXED_REG(en_1v8_cam_e1611), \
925         ADD_FIXED_REG(dvdd_ts),
926
927 /* Gpio switch regulator platform data for Dalmore E1611 */
928 static struct platform_device *fixed_reg_devs_e1611_a00[] = {
929         DALMORE_COMMON_FIXED_REG
930         E1611_FIXED_REG
931 };
932
933 /* Gpio switch regulator platform data for Dalmore E1612 */
934 static struct platform_device *fixed_reg_devs_e1612_a00[] = {
935         DALMORE_COMMON_FIXED_REG
936         E1612_FIXED_REG
937 };
938
939 int __init dalmore_palmas_regulator_init(void)
940 {
941         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
942         u32 pmc_ctrl;
943         int i;
944
945         /* TPS65913: Normal state of INT request line is LOW.
946          * configure the power management controller to trigger PMU
947          * interrupts when HIGH.
948          */
949         pmc_ctrl = readl(pmc + PMC_CTRL);
950         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
951         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
952                 pmic_platform.reg_data[i] = dalmore_e1611_reg_data[i];
953                 pmic_platform.reg_init[i] = dalmore_e1611_reg_init[i];
954         }
955
956         i2c_register_board_info(4, palma_device,
957                         ARRAY_SIZE(palma_device));
958         return 0;
959 }
960
961 static int ac_online(void)
962 {
963         return 1;
964 }
965
966 static struct resource dalmore_pda_resources[] = {
967         [0] = {
968                 .name   = "ac",
969         },
970 };
971
972 static struct pda_power_pdata dalmore_pda_data = {
973         .is_ac_online   = ac_online,
974 };
975
976 static struct platform_device dalmore_pda_power_device = {
977         .name           = "pda-power",
978         .id             = -1,
979         .resource       = dalmore_pda_resources,
980         .num_resources  = ARRAY_SIZE(dalmore_pda_resources),
981         .dev    = {
982                 .platform_data  = &dalmore_pda_data,
983         },
984 };
985
986 static struct tegra_suspend_platform_data dalmore_suspend_data = {
987         .cpu_timer      = 300,
988         .cpu_off_timer  = 300,
989         .suspend_mode   = TEGRA_SUSPEND_LP0,
990         .core_timer     = 0x157e,
991         .core_off_timer = 2000,
992         .corereq_high   = true,
993         .sysclkreq_high = true,
994         .cpu_lp2_min_residency = 1000,
995         .min_residency_noncpu = 2000,
996         .min_residency_crail = 8000,
997 };
998 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
999 /* board parameters for cpu dfll */
1000 static struct tegra_cl_dvfs_cfg_param dalmore_cl_dvfs_param = {
1001         .sample_rate = 12500,
1002
1003         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
1004         .cf = 10,
1005         .ci = 0,
1006         .cg = 2,
1007
1008         .droop_cut_value = 0xF,
1009         .droop_restore_ramp = 0x0,
1010         .scale_out_ramp = 0x0,
1011 };
1012 #endif
1013
1014 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
1015 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
1016 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
1017 static inline void fill_reg_map(void)
1018 {
1019         int i;
1020         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
1021                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
1022                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
1023         }
1024 }
1025
1026 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1027 static struct tegra_cl_dvfs_platform_data dalmore_cl_dvfs_data = {
1028         .dfll_clk_name = "dfll_cpu",
1029         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
1030         .u.pmu_i2c = {
1031                 .fs_rate = 400000,
1032                 .slave_addr = 0x86,
1033                 .reg = 0x00,
1034         },
1035         .vdd_map = pmu_cpu_vdd_map,
1036         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
1037
1038         .cfg_param = &dalmore_cl_dvfs_param,
1039 };
1040
1041 static int __init dalmore_cl_dvfs_init(void)
1042 {
1043         fill_reg_map();
1044         tegra_cl_dvfs_device.dev.platform_data = &dalmore_cl_dvfs_data;
1045         platform_device_register(&tegra_cl_dvfs_device);
1046
1047         return 0;
1048 }
1049 #endif
1050
1051 static int __init dalmore_max77663_regulator_init(void)
1052 {
1053         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
1054         u32 pmc_ctrl;
1055
1056         /* configure the power management controller to trigger PMU
1057          * interrupts when low */
1058         pmc_ctrl = readl(pmc + PMC_CTRL);
1059         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
1060
1061         i2c_register_board_info(4, max77663_regulators,
1062                                 ARRAY_SIZE(max77663_regulators));
1063
1064         return 0;
1065 }
1066
1067 static struct regulator_bulk_data dalmore_gps_regulator_supply[] = {
1068         [0] = {
1069                 .supply = "vdd_gps_3v3",
1070         },
1071         [1] = {
1072                 .supply = "vdd_gps_1v8",
1073         },
1074 };
1075
1076 static struct regulator_userspace_consumer_data dalmore_gps_regulator_pdata = {
1077         .num_supplies   = ARRAY_SIZE(dalmore_gps_regulator_supply),
1078         .supplies       = dalmore_gps_regulator_supply,
1079 };
1080
1081 static struct platform_device dalmore_gps_regulator_device = {
1082         .name   = "reg-userspace-consumer",
1083         .id     = 2,
1084         .dev    = {
1085                         .platform_data = &dalmore_gps_regulator_pdata,
1086         },
1087 };
1088
1089 static int __init dalmore_fixed_regulator_init(void)
1090 {
1091         struct board_info board_info;
1092
1093         if (!machine_is_dalmore())
1094                 return 0;
1095
1096         tegra_get_board_info(&board_info);
1097
1098         if (board_info.board_id == BOARD_E1611 ||
1099                 board_info.board_id == BOARD_P2454)
1100                 return platform_add_devices(fixed_reg_devs_e1611_a00,
1101                                 ARRAY_SIZE(fixed_reg_devs_e1611_a00));
1102         else
1103                 return platform_add_devices(fixed_reg_devs_e1612_a00,
1104                                 ARRAY_SIZE(fixed_reg_devs_e1612_a00));
1105 }
1106 subsys_initcall_sync(dalmore_fixed_regulator_init);
1107
1108 static void dalmore_tps65090_init(void)
1109 {
1110         int err;
1111
1112         err = gpio_request(TPS65090_CHARGER_INT, "CHARGER_INT");
1113         if (err < 0) {
1114                 pr_err("%s: gpio_request failed %d\n", __func__, err);
1115                 goto fail_init_irq;
1116         }
1117
1118         err = gpio_direction_input(TPS65090_CHARGER_INT);
1119         if (err < 0) {
1120                 pr_err("%s: gpio_direction_input failed %d\n", __func__, err);
1121                 goto fail_init_irq;
1122         }
1123
1124         tps65090_regulators[0].irq = gpio_to_irq(TPS65090_CHARGER_INT);
1125 fail_init_irq:
1126         i2c_register_board_info(4, tps65090_regulators,
1127                         ARRAY_SIZE(tps65090_regulators));
1128         return;
1129 }
1130
1131 int __init dalmore_regulator_init(void)
1132 {
1133         struct board_info board_info;
1134
1135         dalmore_tps65090_init();
1136 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1137         dalmore_cl_dvfs_init();
1138 #endif
1139         tegra_get_board_info(&board_info);
1140         if (board_info.board_id == BOARD_E1611 ||
1141                 board_info.board_id == BOARD_P2454)
1142                 dalmore_palmas_regulator_init();
1143         else
1144                 dalmore_max77663_regulator_init();
1145
1146         i2c_register_board_info(4, tps51632_boardinfo, 1);
1147         platform_device_register(&dalmore_pda_power_device);
1148         platform_device_register(&dalmore_gps_regulator_device);
1149         return 0;
1150 }
1151
1152 int __init dalmore_suspend_init(void)
1153 {
1154         tegra_init_suspend(&dalmore_suspend_data);
1155         return 0;
1156 }
1157
1158 int __init dalmore_edp_init(void)
1159 {
1160         unsigned int regulator_mA;
1161
1162         regulator_mA = get_maximum_cpu_current_supported();
1163         if (!regulator_mA)
1164                 regulator_mA = 15000;
1165
1166         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1167         tegra_init_cpu_edp_limits(regulator_mA);
1168
1169         regulator_mA = get_maximum_core_current_supported();
1170         if (!regulator_mA)
1171                 regulator_mA = 4000;
1172
1173         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
1174         tegra_init_core_edp_limits(regulator_mA);
1175
1176         return 0;
1177 }
1178
1179 static struct soctherm_platform_data dalmore_soctherm_data = {
1180         .therm = {
1181                 [THERM_CPU] = {
1182                         .zone_enable = true,
1183                         .passive_delay = 1000,
1184                         .num_trips = 3,
1185                         .trips = {
1186                                 {
1187                                         .cdev_type = "tegra-balanced",
1188                                         .trip_temp = 84000,
1189                                         .trip_type = THERMAL_TRIP_PASSIVE,
1190                                         .upper = THERMAL_NO_LIMIT,
1191                                         .lower = THERMAL_NO_LIMIT,
1192                                 },
1193                                 {
1194                                         .cdev_type = "tegra-heavy",
1195                                         .trip_temp = 94000,
1196                                         .trip_type = THERMAL_TRIP_HOT,
1197                                         .upper = THERMAL_NO_LIMIT,
1198                                         .lower = THERMAL_NO_LIMIT,
1199                                 },
1200                                 {
1201                                         .cdev_type = "tegra-shutdown",
1202                                         .trip_temp = 104000,
1203                                         .trip_type = THERMAL_TRIP_CRITICAL,
1204                                         .upper = THERMAL_NO_LIMIT,
1205                                         .lower = THERMAL_NO_LIMIT,
1206                                 },
1207                         },
1208                 },
1209                 [THERM_GPU] = {
1210                         .zone_enable = true,
1211                 },
1212                 [THERM_PLL] = {
1213                         .zone_enable = true,
1214                 },
1215         },
1216         .throttle = {
1217                 [THROTTLE_HEAVY] = {
1218                         .devs = {
1219                                 [THROTTLE_DEV_CPU] = {
1220                                         .enable = 1,
1221                                 },
1222                         },
1223                 },
1224         },
1225 };
1226
1227 int __init dalmore_soctherm_init(void)
1228 {
1229         tegra_platform_edp_init(dalmore_soctherm_data.therm[THERM_CPU].trips,
1230                         &dalmore_soctherm_data.therm[THERM_CPU].num_trips);
1231         tegra_add_tj_trips(dalmore_soctherm_data.therm[THERM_CPU].trips,
1232                         &dalmore_soctherm_data.therm[THERM_CPU].num_trips);
1233
1234         return tegra11_soctherm_init(&dalmore_soctherm_data);
1235 }