ARM: tegra: powermon: Fix copyrights from GPLv3 to GPLv2
[linux-3.10.git] / arch / arm / mach-tegra / board-dalmore-power.c
1 /*
2  * arch/arm/mach-tegra/board-dalmore-power.c
3  *
4  * Copyright (c) 2012-2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/max77663-core.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/mfd/tps65090.h>
31 #include <linux/regulator/max77663-regulator.h>
32 #include <linux/regulator/tps51632-regulator.h>
33 #include <linux/gpio.h>
34 #include <linux/interrupt.h>
35 #include <linux/regulator/userspace-consumer.h>
36 #include <linux/pid_thermal_gov.h>
37
38 #include <asm/mach-types.h>
39 #include <linux/power/sbs-battery.h>
40
41 #include <mach/irqs.h>
42 #include <mach/edp.h>
43 #include <mach/gpio-tegra.h>
44 #include <mach/hardware.h>
45
46 #include "cpu-tegra.h"
47 #include "pm.h"
48 #include "tegra-board-id.h"
49 #include "board-pmu-defines.h"
50 #include "board.h"
51 #include "gpio-names.h"
52 #include "board-common.h"
53 #include "board-dalmore.h"
54 #include "tegra_cl_dvfs.h"
55 #include "devices.h"
56 #include "tegra11_soctherm.h"
57 #include "iomap.h"
58 #include "tegra3_tsensor.h"
59
60 #define PMC_CTRL                0x0
61 #define PMC_CTRL_INTR_LOW       (1 << 17)
62 #define TPS65090_CHARGER_INT    TEGRA_GPIO_PJ0
63 #define POWER_CONFIG2   0x02
64
65 /*TPS65090 consumer rails */
66 static struct regulator_consumer_supply tps65090_dcdc1_supply[] = {
67         REGULATOR_SUPPLY("vdd_sys_5v0", NULL),
68         REGULATOR_SUPPLY("vdd_spk", NULL),
69         REGULATOR_SUPPLY("vdd_sys_modem_5v0", NULL),
70         REGULATOR_SUPPLY("vdd_sys_cam_5v0", NULL),
71 };
72
73 static struct regulator_consumer_supply tps65090_dcdc2_supply[] = {
74         REGULATOR_SUPPLY("vdd_sys_3v3", NULL),
75         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
76         REGULATOR_SUPPLY("pwrdet_hv", NULL),
77         REGULATOR_SUPPLY("vdd_sys_ds_3v3", NULL),
78         REGULATOR_SUPPLY("avdd", "0-0028"),
79         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
80         REGULATOR_SUPPLY("vdd_sys_sensor_3v3", NULL),
81         REGULATOR_SUPPLY("vdd_sys_audio_3v3", NULL),
82         REGULATOR_SUPPLY("vdd_sys_dtv_3v3", NULL),
83         REGULATOR_SUPPLY("vcc", "0-007c"),
84         REGULATOR_SUPPLY("vcc", "0-0030"),
85         REGULATOR_SUPPLY("vin", "2-0030"),
86 };
87
88 static struct regulator_consumer_supply tps65090_dcdc3_supply[] = {
89         REGULATOR_SUPPLY("vdd_ao", NULL),
90 };
91
92 static struct regulator_consumer_supply tps65090_ldo1_supply[] = {
93         REGULATOR_SUPPLY("vdd_sby_5v0", NULL),
94 };
95
96 static struct regulator_consumer_supply tps65090_ldo2_supply[] = {
97         REGULATOR_SUPPLY("vdd_sby_3v3", NULL),
98 };
99
100 static struct regulator_consumer_supply tps65090_fet1_supply[] = {
101         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
102 };
103
104 static struct regulator_consumer_supply tps65090_fet3_supply[] = {
105         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
106 };
107
108 static struct regulator_consumer_supply tps65090_fet4_supply[] = {
109         REGULATOR_SUPPLY("avdd_lcd", NULL),
110         REGULATOR_SUPPLY("avdd", "spi3.2"),
111 };
112
113 static struct regulator_consumer_supply tps65090_fet5_supply[] = {
114         REGULATOR_SUPPLY("vdd_lvds", NULL),
115 };
116
117 static struct regulator_consumer_supply tps65090_fet6_supply[] = {
118         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
119 };
120
121 static struct regulator_consumer_supply tps65090_fet7_supply[] = {
122         REGULATOR_SUPPLY("avdd", "bcm4329_wlan.1"),
123         REGULATOR_SUPPLY("avdd", "reg-userspace-consumer.2"),
124         REGULATOR_SUPPLY("avdd", "bluedroid_pm.0"),
125 };
126
127 #define tps65090_rails(id) "tps65090-"#id
128 #define TPS65090_PDATA_INIT(_id, _name, _supply_reg,                    \
129         _always_on, _boot_on, _apply_uV, _en_ext_ctrl, _gpio, _wait_to) \
130 static struct regulator_init_data ri_data_##_name =                     \
131 {                                                                       \
132         .supply_regulator = _supply_reg,                                \
133         .constraints = {                                                \
134                 .name = tps65090_rails(_id),                            \
135                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
136                                      REGULATOR_MODE_STANDBY),           \
137                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
138                                    REGULATOR_CHANGE_STATUS |            \
139                                    REGULATOR_CHANGE_VOLTAGE),           \
140                 .always_on = _always_on,                                \
141                 .boot_on = _boot_on,                                    \
142                 .apply_uV = _apply_uV,                                  \
143         },                                                              \
144         .num_consumer_supplies =                                        \
145                 ARRAY_SIZE(tps65090_##_name##_supply),                  \
146         .consumer_supplies = tps65090_##_name##_supply,                 \
147 };                                                                      \
148 static struct tps65090_regulator_plat_data                              \
149                         tps65090_regulator_pdata_##_name =              \
150 {                                                                       \
151         .enable_ext_control = _en_ext_ctrl,                             \
152         .gpio = _gpio,                                                  \
153         .reg_init_data = &ri_data_##_name ,                             \
154         .wait_timeout_us = _wait_to,                                    \
155 }
156
157 TPS65090_PDATA_INIT(DCDC1, dcdc1, NULL, 1, 1, 0, true, -1, -1);
158 TPS65090_PDATA_INIT(DCDC2, dcdc2, NULL, 1, 1, 0, true, -1, -1);
159 TPS65090_PDATA_INIT(DCDC3, dcdc3, NULL, 1, 1, 0, true, -1, -1);
160 TPS65090_PDATA_INIT(LDO1, ldo1, NULL, 1, 1, 0, false, -1, -1);
161 TPS65090_PDATA_INIT(LDO2, ldo2, NULL, 1, 1, 0, false, -1, -1);
162 TPS65090_PDATA_INIT(FET1, fet1, NULL, 0, 0, 0, false, -1, 800);
163 TPS65090_PDATA_INIT(FET3, fet3, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
164 TPS65090_PDATA_INIT(FET4, fet4, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
165 TPS65090_PDATA_INIT(FET5, fet5, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
166 TPS65090_PDATA_INIT(FET6, fet6, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
167 TPS65090_PDATA_INIT(FET7, fet7, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
168
169 static struct tps65090_charger_data bcharger_pdata = {
170         .irq_base = TPS65090_TEGRA_IRQ_BASE,
171 };
172
173 #define ADD_TPS65090_REG(_name) (&tps65090_regulator_pdata_##_name)
174 static struct tps65090_platform_data tps65090_pdata = {
175         .irq_base = TPS65090_TEGRA_IRQ_BASE,
176         .reg_pdata = {
177                         ADD_TPS65090_REG(dcdc1),
178                         ADD_TPS65090_REG(dcdc2),
179                         ADD_TPS65090_REG(dcdc3),
180                         ADD_TPS65090_REG(fet1),
181                         NULL,
182                         ADD_TPS65090_REG(fet3),
183                         ADD_TPS65090_REG(fet4),
184                         ADD_TPS65090_REG(fet5),
185                         ADD_TPS65090_REG(fet6),
186                         ADD_TPS65090_REG(fet7),
187                         ADD_TPS65090_REG(ldo1),
188                         ADD_TPS65090_REG(ldo2),
189                 },
190         .charger_pdata = &bcharger_pdata,
191 };
192
193 /* MAX77663 consumer rails */
194 static struct regulator_consumer_supply max77663_sd0_supply[] = {
195         REGULATOR_SUPPLY("vdd_core", NULL),
196         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"),
197         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.2"),
198         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"),
199 };
200
201 static struct regulator_consumer_supply max77663_sd1_supply[] = {
202         REGULATOR_SUPPLY("vddio_ddr", NULL),
203         REGULATOR_SUPPLY("vddio_ddr0", NULL),
204         REGULATOR_SUPPLY("vddio_ddr1", NULL),
205 };
206
207 static struct regulator_consumer_supply max77663_sd2_supply[] = {
208         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
209         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
210         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
211         REGULATOR_SUPPLY("vddio_cam", "vi"),
212         REGULATOR_SUPPLY("pwrdet_cam", NULL),
213         REGULATOR_SUPPLY("avdd_osc", NULL),
214         REGULATOR_SUPPLY("vddio_sys", NULL),
215         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
216         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
217         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
218         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
219         REGULATOR_SUPPLY("vdd_emmc", NULL),
220         REGULATOR_SUPPLY("vddio_audio", NULL),
221         REGULATOR_SUPPLY("pwrdet_audio", NULL),
222         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
223         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
224         REGULATOR_SUPPLY("vddio_modem", NULL),
225         REGULATOR_SUPPLY("vddio_modem_1v8", NULL),
226         REGULATOR_SUPPLY("vddio_bb", NULL),
227         REGULATOR_SUPPLY("pwrdet_bb", NULL),
228         REGULATOR_SUPPLY("vddio_bb_1v8", NULL),
229         REGULATOR_SUPPLY("vddio_uart", NULL),
230         REGULATOR_SUPPLY("pwrdet_uart", NULL),
231         REGULATOR_SUPPLY("vddio_gmi", NULL),
232         REGULATOR_SUPPLY("pwrdet_nand", NULL),
233         REGULATOR_SUPPLY("vdd_sensor_1v8", NULL),
234         REGULATOR_SUPPLY("vdd_mic_1v8", NULL),
235         REGULATOR_SUPPLY("dvdd", "0-0028"),
236         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
237         REGULATOR_SUPPLY("vdd_spi_1v8", NULL),
238         REGULATOR_SUPPLY("dvdd_lcd", NULL),
239         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
240         REGULATOR_SUPPLY("dvdd", "bcm4329_wlan.1"),
241         REGULATOR_SUPPLY("dvdd", "reg-userspace-consumer.2"),
242         REGULATOR_SUPPLY("dvdd", "bluedroid_pm.0"),
243         REGULATOR_SUPPLY("vdd_dtv_1v8", NULL),
244         REGULATOR_SUPPLY("vlogic", "0-0069"),
245         REGULATOR_SUPPLY("vid", "0-000d"),
246         REGULATOR_SUPPLY("vddio", "0-0078"),
247 };
248
249 static struct regulator_consumer_supply max77663_sd3_supply[] = {
250         REGULATOR_SUPPLY("vcore_emmc", NULL),
251 };
252
253 static struct regulator_consumer_supply max77663_ldo0_supply[] = {
254         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
255         REGULATOR_SUPPLY("avdd_pllx", NULL),
256         REGULATOR_SUPPLY("avdd_plle", NULL),
257         REGULATOR_SUPPLY("avdd_pllm", NULL),
258         REGULATOR_SUPPLY("avdd_pllu", NULL),
259         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
260         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
261         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
262 };
263
264 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
265         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
266 };
267
268 static struct regulator_consumer_supply max77663_ldo2_supply[] = {
269         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
270         REGULATOR_SUPPLY("vdd_als", NULL),
271         REGULATOR_SUPPLY("vdd", "0-0048"),
272         REGULATOR_SUPPLY("vdd", "0-004c"),
273         REGULATOR_SUPPLY("vdd", "0-0069"),
274         REGULATOR_SUPPLY("vdd", "0-000d"),
275         REGULATOR_SUPPLY("vdd", "0-0078"),
276 };
277
278 static struct regulator_consumer_supply max77663_ldo3_supply[] = {
279         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
280         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
281         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
282 };
283
284 static struct regulator_consumer_supply max77663_ldo4_supply[] = {
285         REGULATOR_SUPPLY("vdd_rtc", NULL),
286 };
287
288 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
289         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
290         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
291         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
292         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
293         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
294         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
295         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
296         REGULATOR_SUPPLY("vddio_bb_hsic", NULL),
297 };
298
299 static struct regulator_consumer_supply max77663_ldo6_supply[] = {
300         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
301         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
302 };
303
304 /* FIXME!! Put the device address of camera */
305 static struct regulator_consumer_supply max77663_ldo7_supply[] = {
306         REGULATOR_SUPPLY("avdd_cam1", NULL),
307         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
308         REGULATOR_SUPPLY("vana", "2-0036"),
309 };
310
311 /* FIXME!! Put the device address of camera */
312 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
313         REGULATOR_SUPPLY("avdd_cam2", NULL),
314         REGULATOR_SUPPLY("avdd", "2-0010"),
315 };
316
317 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
318         {
319                 .src = FPS_SRC_0,
320                 .en_src = FPS_EN_SRC_EN0,
321                 .time_period = FPS_TIME_PERIOD_DEF,
322         },
323         {
324                 .src = FPS_SRC_1,
325                 .en_src = FPS_EN_SRC_EN1,
326                 .time_period = FPS_TIME_PERIOD_DEF,
327         },
328         {
329                 .src = FPS_SRC_2,
330                 .en_src = FPS_EN_SRC_EN0,
331                 .time_period = FPS_TIME_PERIOD_DEF,
332         },
333 };
334
335 #define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg,   \
336                 _always_on, _boot_on, _apply_uV,                        \
337                 _fps_src, _fps_pu_period, _fps_pd_period, _flags)       \
338         static struct regulator_init_data max77663_regulator_idata_##_id = {   \
339                 .supply_regulator = _supply_reg,                        \
340                 .constraints = {                                        \
341                         .name = max77663_rails(_id),                    \
342                         .min_uV = _min_uV,                              \
343                         .max_uV = _max_uV,                              \
344                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
345                                              REGULATOR_MODE_STANDBY),   \
346                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
347                                            REGULATOR_CHANGE_STATUS |    \
348                                            REGULATOR_CHANGE_VOLTAGE),   \
349                         .always_on = _always_on,                        \
350                         .boot_on = _boot_on,                            \
351                         .apply_uV = _apply_uV,                          \
352                 },                                                      \
353                 .num_consumer_supplies =                                \
354                         ARRAY_SIZE(max77663_##_id##_supply),            \
355                 .consumer_supplies = max77663_##_id##_supply,           \
356         };                                                              \
357 static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id =\
358 {                                                                       \
359                 .reg_init_data = &max77663_regulator_idata_##_id,       \
360                 .id = MAX77663_REGULATOR_ID_##_rid,                     \
361                 .fps_src = _fps_src,                                    \
362                 .fps_pu_period = _fps_pu_period,                        \
363                 .fps_pd_period = _fps_pd_period,                        \
364                 .fps_cfgs = max77663_fps_cfgs,                          \
365                 .flags = _flags,                                        \
366         }
367
368 MAX77663_PDATA_INIT(SD0, sd0,  900000, 1400000, tps65090_rails(DCDC3), 1, 1, 0,
369                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
370
371 MAX77663_PDATA_INIT(SD1, sd1,  1200000, 1200000, tps65090_rails(DCDC3), 1, 1, 1,
372                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
373
374 MAX77663_PDATA_INIT(SD2, sd2,  1800000, 1800000, tps65090_rails(DCDC3), 1, 1, 1,
375                     FPS_SRC_0, -1, -1, 0);
376
377 MAX77663_PDATA_INIT(SD3, sd3,  2850000, 2850000, tps65090_rails(DCDC3), 1, 1, 1,
378                     FPS_SRC_NONE, -1, -1, 0);
379
380 MAX77663_PDATA_INIT(LDO0, ldo0, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
381                     FPS_SRC_1, -1, -1, 0);
382
383 MAX77663_PDATA_INIT(LDO1, ldo1, 1050000, 1050000, max77663_rails(sd2), 0, 0, 1,
384                     FPS_SRC_NONE, -1, -1, 0);
385
386 MAX77663_PDATA_INIT(LDO2, ldo2, 2850000, 2850000, tps65090_rails(DCDC2), 1, 1,
387                     1, FPS_SRC_1, -1, -1, 0);
388
389 MAX77663_PDATA_INIT(LDO3, ldo3, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
390                     FPS_SRC_NONE, -1, -1, 0);
391
392 MAX77663_PDATA_INIT(LDO4, ldo4, 1100000, 1100000, tps65090_rails(DCDC2), 1, 1,
393                     1, FPS_SRC_NONE, -1, -1, LDO4_EN_TRACKING);
394
395 MAX77663_PDATA_INIT(LDO5, ldo5, 1200000, 1200000, max77663_rails(sd2), 0, 1, 1,
396                     FPS_SRC_NONE, -1, -1, 0);
397
398 MAX77663_PDATA_INIT(LDO6, ldo6, 1800000, 3300000, tps65090_rails(DCDC2), 0, 0, 0,
399                     FPS_SRC_NONE, -1, -1, 0);
400
401 MAX77663_PDATA_INIT(LDO7, ldo7, 2800000, 2800000, tps65090_rails(DCDC2), 0, 0, 1,
402                     FPS_SRC_NONE, -1, -1, 0);
403
404 MAX77663_PDATA_INIT(LDO8, ldo8, 2800000, 2800000, tps65090_rails(DCDC2), 0, 1, 1,
405                     FPS_SRC_1, -1, -1, 0);
406
407 #define MAX77663_REG(_id, _data) (&max77663_regulator_pdata_##_data)
408
409 static struct max77663_regulator_platform_data *max77663_reg_pdata[] = {
410         MAX77663_REG(SD0, sd0),
411         MAX77663_REG(SD1, sd1),
412         MAX77663_REG(SD2, sd2),
413         MAX77663_REG(SD3, sd3),
414         MAX77663_REG(LDO0, ldo0),
415         MAX77663_REG(LDO1, ldo1),
416         MAX77663_REG(LDO2, ldo2),
417         MAX77663_REG(LDO3, ldo3),
418         MAX77663_REG(LDO4, ldo4),
419         MAX77663_REG(LDO5, ldo5),
420         MAX77663_REG(LDO6, ldo6),
421         MAX77663_REG(LDO7, ldo7),
422         MAX77663_REG(LDO8, ldo8),
423 };
424
425 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
426         {
427                 .gpio = MAX77663_GPIO0,
428                 .dir = GPIO_DIR_OUT,
429                 .dout = GPIO_DOUT_LOW,
430                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
431                 .alternate = GPIO_ALT_DISABLE,
432         },
433         {
434                 .gpio = MAX77663_GPIO1,
435                 .dir = GPIO_DIR_IN,
436                 .dout = GPIO_DOUT_HIGH,
437                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
438                 .pull_up = GPIO_PU_ENABLE,
439                 .alternate = GPIO_ALT_DISABLE,
440         },
441         {
442                 .gpio = MAX77663_GPIO2,
443                 .dir = GPIO_DIR_OUT,
444                 .dout = GPIO_DOUT_HIGH,
445                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
446                 .pull_up = GPIO_PU_ENABLE,
447                 .alternate = GPIO_ALT_DISABLE,
448         },
449         {
450                 .gpio = MAX77663_GPIO3,
451                 .dir = GPIO_DIR_OUT,
452                 .dout = GPIO_DOUT_HIGH,
453                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
454                 .pull_up = GPIO_PU_ENABLE,
455                 .alternate = GPIO_ALT_DISABLE,
456         },
457         {
458                 .gpio = MAX77663_GPIO4,
459                 .dir = GPIO_DIR_OUT,
460                 .dout = GPIO_DOUT_HIGH,
461                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
462                 .alternate = GPIO_ALT_ENABLE,
463         },
464         {
465                 .gpio = MAX77663_GPIO5,
466                 .dir = GPIO_DIR_OUT,
467                 .dout = GPIO_DOUT_LOW,
468                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
469                 .alternate = GPIO_ALT_DISABLE,
470         },
471         {
472                 .gpio = MAX77663_GPIO6,
473                 .dir = GPIO_DIR_OUT,
474                 .dout = GPIO_DOUT_LOW,
475                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
476                 .alternate = GPIO_ALT_DISABLE,
477         },
478         {
479                 .gpio = MAX77663_GPIO7,
480                 .dir = GPIO_DIR_OUT,
481                 .dout = GPIO_DOUT_LOW,
482                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
483                 .alternate = GPIO_ALT_DISABLE,
484         },
485 };
486
487 static struct max77663_platform_data max77663_pdata = {
488         .irq_base       = MAX77663_IRQ_BASE,
489         .gpio_base      = MAX77663_GPIO_BASE,
490
491         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
492         .gpio_cfgs      = max77663_gpio_cfgs,
493
494         .regulator_pdata = max77663_reg_pdata,
495         .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata),
496
497         .rtc_i2c_addr   = 0x68,
498
499         .use_power_off  = false,
500 };
501
502 static struct i2c_board_info __initdata max77663_regulators[] = {
503         {
504                 /* The I2C address was determined by OTP factory setting */
505                 I2C_BOARD_INFO("max77663", 0x3c),
506                 .irq            = INT_EXTERNAL_PMU,
507                 .platform_data  = &max77663_pdata,
508         },
509 };
510
511 static struct i2c_board_info __initdata tps65090_regulators[] = {
512         {
513                 I2C_BOARD_INFO("tps65090", 0x48),
514                 .platform_data  = &tps65090_pdata,
515         },
516 };
517
518 /************************ Palmas based regulator ****************/
519 static struct regulator_consumer_supply palmas_smps12_supply[] = {
520         REGULATOR_SUPPLY("vddio_ddr3l", NULL),
521         REGULATOR_SUPPLY("vcore_ddr3l", NULL),
522         REGULATOR_SUPPLY("vref2_ddr3l", NULL),
523 };
524
525 #define palmas_smps3_supply max77663_sd2_supply
526 #define palmas_smps45_supply max77663_sd0_supply
527 #define palmas_smps457_supply max77663_sd0_supply
528
529 static struct regulator_consumer_supply palmas_smps8_supply[] = {
530         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
531         REGULATOR_SUPPLY("avdd_pllm", NULL),
532         REGULATOR_SUPPLY("avdd_pllu", NULL),
533         REGULATOR_SUPPLY("avdd_pllx", NULL),
534         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
535         REGULATOR_SUPPLY("avdd_plle", NULL),
536         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
537         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
538         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
539         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
540         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
541         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
542         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
543         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
544 };
545
546 static struct regulator_consumer_supply palmas_smps8_config2_supply[] = {
547         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
548         REGULATOR_SUPPLY("avdd_pllm", NULL),
549         REGULATOR_SUPPLY("avdd_pllu", NULL),
550         REGULATOR_SUPPLY("avdd_pllx", NULL),
551         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
552         REGULATOR_SUPPLY("avdd_plle", NULL),
553         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
554         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
555         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
556 };
557
558 static struct regulator_consumer_supply palmas_smps9_supply[] = {
559         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
560 };
561
562 #define palmas_ldo1_supply max77663_ldo7_supply
563
564 static struct regulator_consumer_supply palmas_ldo1_config2_supply[] = {
565         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
566         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
567 };
568
569 #define palmas_ldo2_supply max77663_ldo8_supply
570
571 /* FIXME!! Put the device address of camera */
572 static struct regulator_consumer_supply palmas_ldo2_config2_supply[] = {
573         REGULATOR_SUPPLY("avdd_cam1", NULL),
574         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
575         REGULATOR_SUPPLY("avdd_cam2", NULL),
576         REGULATOR_SUPPLY("vana", "2-0036"),
577         REGULATOR_SUPPLY("vana", "2-0010"),
578         REGULATOR_SUPPLY("vana_imx132", "2-0036"),
579         REGULATOR_SUPPLY("avdd", "2-0010"),
580 };
581
582 #define palmas_ldo3_supply max77663_ldo5_supply
583
584 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
585         REGULATOR_SUPPLY("vpp_fuse", NULL),
586 };
587
588 static struct regulator_consumer_supply palmas_ldo4_config2_supply[] = {
589         REGULATOR_SUPPLY("vpp_fuse", NULL),
590         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
591         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
592 };
593
594 #define palmas_ldo6_supply max77663_ldo2_supply
595
596 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
597         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
598         REGULATOR_SUPPLY("vdd", "2-000e"),
599 };
600
601 #define palmas_ldo8_supply max77663_ldo4_supply
602 #define palmas_ldo9_supply max77663_ldo6_supply
603
604 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
605         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
606         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
607 };
608
609 static struct regulator_consumer_supply palmas_ldoln_fab05_supply[] = {
610         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
611 };
612
613 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
614         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
615         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
616         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
617         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
618         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
619 };
620
621 static struct regulator_consumer_supply palmas_ldousb_fab05_supply[] = {
622         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
623         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
624         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
625         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
626         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
627         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
628 };
629
630 PALMAS_REGS_PDATA(smps12, 1350,  1350, tps65090_rails(DCDC3), 0, 0, 0, NORMAL,
631         0, 0, 0, 0, 0);
632 PALMAS_REGS_PDATA(smps3, 1800,  1800, tps65090_rails(DCDC3), 0, 0, 0, NORMAL,
633         0, 0, 0, 0, 0);
634 PALMAS_REGS_PDATA(smps45, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0, NORMAL,
635         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
636 PALMAS_REGS_PDATA(smps457, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0, NORMAL,
637         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
638 PALMAS_REGS_PDATA(smps8, 1050,  1050, tps65090_rails(DCDC2), 0, 1, 1, NORMAL,
639         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
640 PALMAS_REGS_PDATA(smps8_config2, 1050,  1050, tps65090_rails(DCDC2), 0, 1, 1,
641         NORMAL, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
642 PALMAS_REGS_PDATA(smps9, 2800,  2800, tps65090_rails(DCDC2), 1, 0, 0, NORMAL,
643         0, 0, 0, 0, 0);
644 PALMAS_REGS_PDATA(ldo1, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1, 0,
645         0, 0, 0, 0, 0);
646 PALMAS_REGS_PDATA(ldo1_config2, 1200,  1200, tps65090_rails(DCDC2), 0, 0, 1, 0,
647         1, 0, 0, 0, 0);
648 PALMAS_REGS_PDATA(ldo2, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1, 0,
649         0, 0, 0, 0, 0);
650 PALMAS_REGS_PDATA(ldo2_config2, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1, 0,
651         0, 0, 0, 0, 0);
652 PALMAS_REGS_PDATA(ldo3, 1200,  1200, palmas_rails(smps3), 0, 0, 1, 0,
653         0, 0, 0, 0, 0);
654 PALMAS_REGS_PDATA(ldo4_config2, 1200,  1200, tps65090_rails(DCDC2), 0, 0, 1, 0,
655         0, 0, 0, 0, 0);
656 PALMAS_REGS_PDATA(ldo4, 1800,  1800, tps65090_rails(DCDC2), 0, 0, 0, 0,
657         0, 0, 0, 0, 0);
658 PALMAS_REGS_PDATA(ldo6, 2850,  2850, tps65090_rails(DCDC2), 0, 0, 1, 0,
659         0, 0, 0, 0, 0);
660 PALMAS_REGS_PDATA(ldo7, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1, 0,
661         0, 0, 0, 0, 0);
662 PALMAS_REGS_PDATA(ldo8, 900,  900, tps65090_rails(DCDC3), 1, 1, 1, 0,
663         0, 0, 0, 0, 0);
664 PALMAS_REGS_PDATA(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1, 0,
665         1, 0, 0, 0, 0);
666 PALMAS_REGS_PDATA(ldoln, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1, 0,
667         0, 0, 0, 0, 0);
668 PALMAS_REGS_PDATA(ldoln_fab05, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1, 0,
669         0, 0, 0, 0, 0);
670 PALMAS_REGS_PDATA(ldousb, 3300,  3300, tps65090_rails(DCDC1), 0, 0, 1, 0,
671         0, 0, 0, 0, 0);
672 PALMAS_REGS_PDATA(ldousb_fab05, 3300,  3300, tps65090_rails(DCDC1), 0, 0, 1, 0,
673         0, 0, 0, 0, 0);
674
675 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
676
677 static struct regulator_init_data *dalmore_e1611_reg_data[PALMAS_NUM_REGS] = {
678         PALMAS_REG_PDATA(smps12),
679         NULL,
680         PALMAS_REG_PDATA(smps3),
681         PALMAS_REG_PDATA(smps45),
682         PALMAS_REG_PDATA(smps457),
683         NULL,
684         NULL,
685         PALMAS_REG_PDATA(smps8),
686         PALMAS_REG_PDATA(smps9),
687         NULL,
688         PALMAS_REG_PDATA(ldo1),
689         PALMAS_REG_PDATA(ldo2),
690         PALMAS_REG_PDATA(ldo3),
691         PALMAS_REG_PDATA(ldo4),
692         NULL,
693         PALMAS_REG_PDATA(ldo6),
694         PALMAS_REG_PDATA(ldo7),
695         PALMAS_REG_PDATA(ldo8),
696         PALMAS_REG_PDATA(ldo9),
697         NULL,
698         NULL,
699         NULL,
700         NULL,
701         NULL,
702         PALMAS_REG_PDATA(ldoln),
703         PALMAS_REG_PDATA(ldousb),
704         NULL,
705         NULL,
706         NULL,
707         NULL,
708         NULL,
709 };
710
711 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
712 static struct palmas_reg_init *dalmore_e1611_reg_init[PALMAS_NUM_REGS] = {
713         PALMAS_REG_INIT_DATA(smps12),
714         NULL,
715         PALMAS_REG_INIT_DATA(smps3),
716         PALMAS_REG_INIT_DATA(smps45),
717         PALMAS_REG_INIT_DATA(smps457),
718         NULL,
719         NULL,
720         PALMAS_REG_INIT_DATA(smps8),
721         PALMAS_REG_INIT_DATA(smps9),
722         NULL,
723         PALMAS_REG_INIT_DATA(ldo1),
724         PALMAS_REG_INIT_DATA(ldo2),
725         PALMAS_REG_INIT_DATA(ldo3),
726         PALMAS_REG_INIT_DATA(ldo4),
727         NULL,
728         PALMAS_REG_INIT_DATA(ldo6),
729         PALMAS_REG_INIT_DATA(ldo7),
730         PALMAS_REG_INIT_DATA(ldo8),
731         PALMAS_REG_INIT_DATA(ldo9),
732         NULL,
733         NULL,
734         NULL,
735         NULL,
736         NULL,
737         PALMAS_REG_INIT_DATA(ldoln),
738         PALMAS_REG_INIT_DATA(ldousb),
739         NULL,
740         NULL,
741         NULL,
742         NULL,
743         NULL,
744 };
745
746 static struct palmas_pmic_platform_data pmic_platform = {
747         .disable_smps10_boost_suspend = false,
748 };
749
750 static struct palmas_rtc_platform_data rtc_platform = {
751         .enable_charging = 1,
752         .charging_current_ua = 100,
753 };
754
755 static struct palmas_pinctrl_config palmas_pincfg[] = {
756         PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
757         PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
758         PALMAS_PINMUX(GPIO0, GPIO, DEFAULT, DEFAULT),
759         PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
760         PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
761         PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
762         PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
763         PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
764         PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
765         PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
766 };
767
768 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
769         .pincfg = palmas_pincfg,
770         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
771         .dvfs1_enable = true,
772         .dvfs2_enable = false,
773 };
774
775 static struct palmas_platform_data palmas_pdata = {
776         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
777         .irq_base = PALMAS_TEGRA_IRQ_BASE,
778         .pmic_pdata = &pmic_platform,
779         .rtc_pdata = &rtc_platform,
780         .use_power_off = true,
781         .pinctrl_pdata = &palmas_pinctrl_pdata,
782         #ifndef CONFIG_ANDROID
783         .long_press_delay = PALMAS_LONG_PRESS_KEY_TIME_8SECONDS,
784         #else
785         /* Retaining default value, 12 Seconds */
786         .long_press_delay = PALMAS_LONG_PRESS_KEY_TIME_DEFAULT,
787         #endif
788 };
789
790 static struct i2c_board_info palma_device[] = {
791         {
792                 I2C_BOARD_INFO("tps65913", 0x58),
793                 .irq            = INT_EXTERNAL_PMU,
794                 .platform_data  = &palmas_pdata,
795         },
796 };
797
798 /* EN_AVDD_USB_HDMI From PMU GP1 */
799 static struct regulator_consumer_supply fixed_reg_avdd_usb_hdmi_supply[] = {
800         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
801         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
802         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
803         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
804         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
805         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
806 };
807
808 /* EN_CAM_1v8 From PMU GP5 */
809 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
810         REGULATOR_SUPPLY("vi2c", "2-0030"),
811         REGULATOR_SUPPLY("vif", "2-0036"),
812         REGULATOR_SUPPLY("dovdd", "2-0010"),
813         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
814 };
815
816 /* EN_CAM_1v8 on e1611 From PMU GP6 */
817 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_e1611_supply[] = {
818         REGULATOR_SUPPLY("vi2c", "2-0030"),
819         REGULATOR_SUPPLY("vif", "2-0036"),
820         REGULATOR_SUPPLY("dovdd", "2-0010"),
821         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
822 };
823
824 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
825         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
826 };
827
828 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
829         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
830 };
831
832 /* EN_USB1_VBUS From TEGRA GPIO PN4 PR3(T30) */
833 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
834         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
835         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
836 };
837
838 /* EN_3V3_FUSE From TEGRA GPIO PX4 */
839 static struct regulator_consumer_supply fixed_reg_vpp_fuse_supply[] = {
840         REGULATOR_SUPPLY("vpp_fuse", NULL),
841 };
842
843 /* EN_USB3_VBUS From TEGRA GPIO PM5 */
844 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
845         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
846         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci"),
847 };
848
849 /* EN_1V8_TS From TEGRA_GPIO_PH5 */
850 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
851         REGULATOR_SUPPLY("dvdd", "spi3.2"),
852 };
853
854 /* EN_AVDD_HDMI_PLL From TEGRA_GPIO_PO1 */
855 static struct regulator_consumer_supply fixed_reg_avdd_hdmi_pll_supply[] = {
856         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
857 };
858
859 /* Macro for defining fixed regulator sub device data */
860 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
861 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
862         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
863         static struct regulator_init_data ri_data_##_var =              \
864         {                                                               \
865                 .supply_regulator = _in_supply,                         \
866                 .num_consumer_supplies =                                \
867                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
868                 .consumer_supplies = fixed_reg_##_name##_supply,        \
869                 .constraints = {                                        \
870                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
871                                         REGULATOR_MODE_STANDBY),        \
872                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
873                                         REGULATOR_CHANGE_STATUS |       \
874                                         REGULATOR_CHANGE_VOLTAGE),      \
875                         .always_on = _always_on,                        \
876                         .boot_on = _boot_on,                            \
877                 },                                                      \
878         };                                                              \
879         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
880         {                                                               \
881                 .supply_name = FIXED_SUPPLY(_name),                     \
882                 .microvolts = _millivolts * 1000,                       \
883                 .gpio = _gpio_nr,                                       \
884                 .gpio_is_open_drain = _open_drain,                      \
885                 .enable_high = _active_high,                            \
886                 .enabled_at_boot = _boot_state,                         \
887                 .init_data = &ri_data_##_var,                           \
888         };                                                              \
889         static struct platform_device fixed_reg_##_var##_dev = {        \
890                 .name = "reg-fixed-voltage",                            \
891                 .id = _id,                                              \
892                 .dev = {                                                \
893                         .platform_data = &fixed_reg_##_var##_pdata,     \
894                 },                                                      \
895         }
896
897 FIXED_REG(1,    avdd_usb_hdmi,  avdd_usb_hdmi,
898         tps65090_rails(DCDC2),  0,      0,
899         MAX77663_GPIO_BASE + MAX77663_GPIO1,    true,   true,   1,      3300);
900
901 FIXED_REG(2,    en_1v8_cam,     en_1v8_cam,
902         max77663_rails(sd2),    0,      0,
903         MAX77663_GPIO_BASE + MAX77663_GPIO5,    false,  true,   0,      1800);
904
905 FIXED_REG(3,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
906         tps65090_rails(DCDC1),  0,      0,
907         TEGRA_GPIO_PK1, false,  true,   0,      5000);
908
909 FIXED_REG(4,    vpp_fuse,       vpp_fuse,
910         max77663_rails(sd2),    0,      0,
911         TEGRA_GPIO_PX4, false,  true,   0,      3300);
912
913 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
914         tps65090_rails(DCDC1),  0,      0,
915         TEGRA_GPIO_PN4, true,   true,   0,      5000);
916
917 FIXED_REG(6,    usb3_vbus,      usb3_vbus,
918         tps65090_rails(DCDC1),  0,      0,
919         TEGRA_GPIO_PK6, true,   true,   0,      5000);
920
921 FIXED_REG(7,    en_1v8_cam_e1611,       en_1v8_cam_e1611,
922         palmas_rails(smps3),    0,      0,
923         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
924
925 FIXED_REG(8,    dvdd_ts,        dvdd_ts,
926         palmas_rails(smps3),    0,      0,
927         TEGRA_GPIO_PH5, false,  false,  1,      1800);
928
929 FIXED_REG(9,    lcd_bl_en,      lcd_bl_en,
930         NULL,   0,      0,
931         TEGRA_GPIO_PH2, false,  true,   0,      5000);
932
933 FIXED_REG(10,   avdd_hdmi_pll,  avdd_hdmi_pll,
934         palmas_rails(ldo3),     0,      0,
935         TEGRA_GPIO_PO1, false,  true,   1,      1200);
936 /*
937  * Creating the fixed regulator device tables
938  */
939
940 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
941
942 #define DALMORE_COMMON_FIXED_REG                \
943         ADD_FIXED_REG(usb1_vbus),               \
944         ADD_FIXED_REG(usb3_vbus),               \
945         ADD_FIXED_REG(vdd_hdmi_5v0),            \
946         ADD_FIXED_REG(lcd_bl_en),
947
948 #define E1612_FIXED_REG                         \
949         ADD_FIXED_REG(avdd_usb_hdmi),           \
950         ADD_FIXED_REG(en_1v8_cam),              \
951         ADD_FIXED_REG(vpp_fuse),                \
952
953 #define E1611_FIXED_REG                         \
954         ADD_FIXED_REG(en_1v8_cam_e1611), \
955         ADD_FIXED_REG(dvdd_ts),
956
957 #define DALMORE_POWER_CONFIG_2                  \
958         ADD_FIXED_REG(avdd_hdmi_pll),
959
960 /* Gpio switch regulator platform data for Dalmore E1611 */
961 static struct platform_device *fixed_reg_devs_e1611_a00[] = {
962         DALMORE_COMMON_FIXED_REG
963         E1611_FIXED_REG
964 };
965
966 /* Gpio switch regulator platform data for Dalmore E1612 */
967 static struct platform_device *fixed_reg_devs_e1612_a00[] = {
968         DALMORE_COMMON_FIXED_REG
969         E1612_FIXED_REG
970 };
971
972 static struct platform_device *fixed_reg_devs_dalmore_config2[] = {
973         DALMORE_POWER_CONFIG_2
974 };
975
976 static void set_dalmore_power_fab05(void)
977 {
978         dalmore_e1611_reg_data[PALMAS_REG_LDOLN] =
979                                 PALMAS_REG_PDATA(ldoln_fab05);
980         dalmore_e1611_reg_init[PALMAS_REG_LDOLN] =
981                                 PALMAS_REG_INIT_DATA(ldoln_fab05);
982         dalmore_e1611_reg_data[PALMAS_REG_LDOUSB] =
983                                 PALMAS_REG_PDATA(ldousb_fab05);
984         dalmore_e1611_reg_init[PALMAS_REG_LDOUSB] =
985                                 PALMAS_REG_INIT_DATA(ldousb_fab05);
986         return;
987 }
988
989 static void set_dalmore_power_config2(void)
990 {
991         dalmore_e1611_reg_data[PALMAS_REG_SMPS8] =
992                                 PALMAS_REG_PDATA(smps8_config2);
993         dalmore_e1611_reg_init[PALMAS_REG_SMPS8] =
994                                 PALMAS_REG_INIT_DATA(smps8_config2);
995         dalmore_e1611_reg_data[PALMAS_REG_LDO1] =
996                                 PALMAS_REG_PDATA(ldo1_config2);
997         dalmore_e1611_reg_init[PALMAS_REG_LDO1] =
998                                 PALMAS_REG_INIT_DATA(ldo1_config2);
999         dalmore_e1611_reg_data[PALMAS_REG_LDO2] =
1000                                 PALMAS_REG_PDATA(ldo2_config2);
1001         dalmore_e1611_reg_init[PALMAS_REG_LDO2] =
1002                                 PALMAS_REG_INIT_DATA(ldo2_config2);
1003         dalmore_e1611_reg_data[PALMAS_REG_LDO4] =
1004                                 PALMAS_REG_PDATA(ldo4_config2);
1005         dalmore_e1611_reg_init[PALMAS_REG_LDO4] =
1006                                 PALMAS_REG_INIT_DATA(ldo4_config2);
1007         return;
1008 }
1009
1010 int __init dalmore_palmas_regulator_init(void)
1011 {
1012         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
1013         u32 pmc_ctrl;
1014         u8 power_config;
1015         struct board_info board_info;
1016         int i;
1017
1018         tegra_get_board_info(&board_info);
1019
1020         /* TPS65913: Normal state of INT request line is LOW.
1021          * configure the power management controller to trigger PMU
1022          * interrupts when HIGH.
1023          */
1024         pmc_ctrl = readl(pmc + PMC_CTRL);
1025         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
1026
1027         /* Tracking configuration */
1028         reg_init_data_ldo8.config_flags =
1029                         PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE |
1030                         PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE;
1031
1032         power_config = get_power_config();
1033         if (board_info.fab == BOARD_FAB_A05) {
1034                 set_dalmore_power_config2();
1035                 set_dalmore_power_fab05();
1036         } else if (power_config & POWER_CONFIG2) {
1037                 set_dalmore_power_config2();
1038         }
1039
1040         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
1041                 pmic_platform.reg_data[i] = dalmore_e1611_reg_data[i];
1042                 pmic_platform.reg_init[i] = dalmore_e1611_reg_init[i];
1043         }
1044
1045         i2c_register_board_info(4, palma_device,
1046                         ARRAY_SIZE(palma_device));
1047         return 0;
1048 }
1049
1050 static int ac_online(void)
1051 {
1052         return 1;
1053 }
1054
1055 static struct resource dalmore_pda_resources[] = {
1056         [0] = {
1057                 .name   = "ac",
1058         },
1059 };
1060
1061 static struct pda_power_pdata dalmore_pda_data = {
1062         .is_ac_online   = ac_online,
1063 };
1064
1065 static struct platform_device dalmore_pda_power_device = {
1066         .name           = "pda-power",
1067         .id             = -1,
1068         .resource       = dalmore_pda_resources,
1069         .num_resources  = ARRAY_SIZE(dalmore_pda_resources),
1070         .dev    = {
1071                 .platform_data  = &dalmore_pda_data,
1072         },
1073 };
1074
1075 static struct tegra_suspend_platform_data dalmore_suspend_data = {
1076         .cpu_timer      = 500,
1077         .cpu_off_timer  = 300,
1078         .suspend_mode   = TEGRA_SUSPEND_LP0,
1079         .core_timer     = 0x157e,
1080         .core_off_timer = 2000,
1081         .corereq_high   = true,
1082         .sysclkreq_high = true,
1083         .cpu_lp2_min_residency = 1000,
1084         .min_residency_crail = 20000,
1085 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
1086         .lp1_lowvolt_support = false,
1087         .i2c_base_addr = 0,
1088         .pmuslave_addr = 0,
1089         .core_reg_addr = 0,
1090         .lp1_core_volt_low_cold = 0,
1091         .lp1_core_volt_low = 0,
1092         .lp1_core_volt_high = 0,
1093 #endif
1094         .usb_vbus_internal_wake = true,
1095         .usb_id_internal_wake = true,
1096 };
1097 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1098 /* board parameters for cpu dfll */
1099 static struct tegra_cl_dvfs_cfg_param dalmore_cl_dvfs_param = {
1100         .sample_rate = 12500,
1101
1102         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
1103         .cf = 10,
1104         .ci = 0,
1105         .cg = 2,
1106
1107         .droop_cut_value = 0xF,
1108         .droop_restore_ramp = 0x0,
1109         .scale_out_ramp = 0x0,
1110 };
1111 #endif
1112
1113 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
1114 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
1115 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
1116 static inline void fill_reg_map(void)
1117 {
1118         int i;
1119         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
1120                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
1121                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
1122         }
1123 }
1124
1125 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1126 static struct tegra_cl_dvfs_platform_data dalmore_cl_dvfs_data = {
1127         .dfll_clk_name = "dfll_cpu",
1128         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
1129         .u.pmu_i2c = {
1130                 .fs_rate = 400000,
1131                 .slave_addr = 0x86,
1132                 .reg = 0x00,
1133         },
1134         .vdd_map = pmu_cpu_vdd_map,
1135         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
1136
1137         .cfg_param = &dalmore_cl_dvfs_param,
1138 };
1139
1140 static int __init dalmore_cl_dvfs_init(void)
1141 {
1142         fill_reg_map();
1143         if (tegra_revision < TEGRA_REVISION_A02)
1144                 dalmore_cl_dvfs_data.flags = TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET;
1145         tegra_cl_dvfs_device.dev.platform_data = &dalmore_cl_dvfs_data;
1146         platform_device_register(&tegra_cl_dvfs_device);
1147
1148         return 0;
1149 }
1150 #endif
1151
1152 static int __init dalmore_max77663_regulator_init(void)
1153 {
1154         struct board_info board_info;
1155         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
1156         u32 pmc_ctrl;
1157
1158         tegra_get_board_info(&board_info);
1159         if (board_info.fab < BOARD_FAB_A02)
1160                 max77663_regulator_pdata_ldo4.flags = 0;
1161
1162         /* configure the power management controller to trigger PMU
1163          * interrupts when low */
1164         pmc_ctrl = readl(pmc + PMC_CTRL);
1165         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
1166
1167         i2c_register_board_info(4, max77663_regulators,
1168                                 ARRAY_SIZE(max77663_regulators));
1169
1170         return 0;
1171 }
1172
1173 static struct regulator_bulk_data dalmore_gps_regulator_supply[] = {
1174         [0] = {
1175                 .supply = "avdd",
1176         },
1177         [1] = {
1178                 .supply = "dvdd",
1179         },
1180 };
1181
1182 static struct regulator_userspace_consumer_data dalmore_gps_regulator_pdata = {
1183         .num_supplies   = ARRAY_SIZE(dalmore_gps_regulator_supply),
1184         .supplies       = dalmore_gps_regulator_supply,
1185 };
1186
1187 static struct platform_device dalmore_gps_regulator_device = {
1188         .name   = "reg-userspace-consumer",
1189         .id     = 2,
1190         .dev    = {
1191                         .platform_data = &dalmore_gps_regulator_pdata,
1192         },
1193 };
1194
1195 static int __init dalmore_fixed_regulator_init(void)
1196 {
1197         struct board_info board_info;
1198         u8 power_config;
1199
1200         if (!of_machine_is_compatible("nvidia,dalmore"))
1201                 return 0;
1202
1203         power_config = get_power_config();
1204         tegra_get_board_info(&board_info);
1205
1206         /* Fab05 and power-type2 have the same fixed regs */
1207         if (board_info.fab == BOARD_FAB_A05 || power_config & POWER_CONFIG2)
1208                 platform_add_devices(fixed_reg_devs_dalmore_config2,
1209                                 ARRAY_SIZE(fixed_reg_devs_dalmore_config2));
1210
1211         if (board_info.board_id == BOARD_E1611 ||
1212                 board_info.board_id == BOARD_P2454)
1213                 return platform_add_devices(fixed_reg_devs_e1611_a00,
1214                                 ARRAY_SIZE(fixed_reg_devs_e1611_a00));
1215         else
1216                 return platform_add_devices(fixed_reg_devs_e1612_a00,
1217                                 ARRAY_SIZE(fixed_reg_devs_e1612_a00));
1218 }
1219 subsys_initcall_sync(dalmore_fixed_regulator_init);
1220
1221 static void dalmore_tps65090_init(void)
1222 {
1223         int err;
1224
1225         err = gpio_request(TPS65090_CHARGER_INT, "CHARGER_INT");
1226         if (err < 0) {
1227                 pr_err("%s: gpio_request failed %d\n", __func__, err);
1228                 goto fail_init_irq;
1229         }
1230
1231         err = gpio_direction_input(TPS65090_CHARGER_INT);
1232         if (err < 0) {
1233                 pr_err("%s: gpio_direction_input failed %d\n", __func__, err);
1234                 goto fail_init_irq;
1235         }
1236
1237         tps65090_regulators[0].irq = gpio_to_irq(TPS65090_CHARGER_INT);
1238 fail_init_irq:
1239         i2c_register_board_info(4, tps65090_regulators,
1240                         ARRAY_SIZE(tps65090_regulators));
1241         return;
1242 }
1243
1244 int __init dalmore_regulator_init(void)
1245 {
1246         struct board_info board_info;
1247
1248         dalmore_tps65090_init();
1249 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1250         dalmore_cl_dvfs_init();
1251 #endif
1252         tegra_get_board_info(&board_info);
1253         if (board_info.board_id == BOARD_E1611 ||
1254                 board_info.board_id == BOARD_P2454)
1255                 dalmore_palmas_regulator_init();
1256         else
1257                 dalmore_max77663_regulator_init();
1258
1259         platform_device_register(&dalmore_pda_power_device);
1260         platform_device_register(&dalmore_gps_regulator_device);
1261         return 0;
1262 }
1263
1264 int __init dalmore_suspend_init(void)
1265 {
1266         tegra_init_suspend(&dalmore_suspend_data);
1267         /* Enable dalmore USB wake for VBUS/ID without using PMIC */
1268         tegra_set_usb_vbus_internal_wake(
1269                 dalmore_suspend_data.usb_vbus_internal_wake);
1270         tegra_set_usb_id_internal_wake(
1271                 dalmore_suspend_data.usb_id_internal_wake);
1272         return 0;
1273 }
1274
1275 int __init dalmore_edp_init(void)
1276 {
1277         unsigned int regulator_mA;
1278
1279         regulator_mA = get_maximum_cpu_current_supported();
1280         if (!regulator_mA)
1281                 regulator_mA = 15000;
1282
1283         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1284         tegra_init_cpu_edp_limits(regulator_mA);
1285
1286         regulator_mA = get_maximum_core_current_supported();
1287         if (!regulator_mA)
1288                 regulator_mA = 4000;
1289
1290         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
1291         tegra_init_core_edp_limits(regulator_mA);
1292
1293         return 0;
1294 }
1295
1296 static struct pid_thermal_gov_params soctherm_pid_params = {
1297         .max_err_temp = 9000,
1298         .max_err_gain = 1000,
1299
1300         .gain_p = 1000,
1301         .gain_d = 0,
1302
1303         .up_compensation = 20,
1304         .down_compensation = 20,
1305 };
1306
1307 static struct thermal_zone_params soctherm_tzp = {
1308         .governor_name = "pid_thermal_gov",
1309         .governor_params = &soctherm_pid_params,
1310 };
1311
1312 static struct tegra_tsensor_pmu_data tpdata_palmas = {
1313         .reset_tegra = 1,
1314         .pmu_16bit_ops = 0,
1315         .controller_type = 0,
1316         .pmu_i2c_addr = 0x58,
1317         .i2c_controller_id = 4,
1318         .poweroff_reg_addr = 0xa0,
1319         .poweroff_reg_data = 0x0,
1320 };
1321
1322 static struct tegra_tsensor_pmu_data tpdata_max77663 = {
1323         .reset_tegra = 1,
1324         .pmu_16bit_ops = 0,
1325         .controller_type = 0,
1326         .pmu_i2c_addr = 0x3c,
1327         .i2c_controller_id = 4,
1328         .poweroff_reg_addr = 0x41,
1329         .poweroff_reg_data = 0x80,
1330 };
1331
1332 static struct soctherm_platform_data dalmore_soctherm_data = {
1333         .therm = {
1334                 [THERM_CPU] = {
1335                         .zone_enable = true,
1336                         .passive_delay = 1000,
1337                         .hotspot_offset = 6000,
1338                         .num_trips = 3,
1339                         .trips = {
1340                                 {
1341                                         .cdev_type = "tegra-balanced",
1342                                         .trip_temp = 90000,
1343                                         .trip_type = THERMAL_TRIP_PASSIVE,
1344                                         .upper = THERMAL_NO_LIMIT,
1345                                         .lower = THERMAL_NO_LIMIT,
1346                                 },
1347                                 {
1348                                         .cdev_type = "tegra-heavy",
1349                                         .trip_temp = 100000,
1350                                         .trip_type = THERMAL_TRIP_HOT,
1351                                         .upper = THERMAL_NO_LIMIT,
1352                                         .lower = THERMAL_NO_LIMIT,
1353                                 },
1354                                 {
1355                                         .cdev_type = "tegra-shutdown",
1356                                         .trip_temp = 102000,
1357                                         .trip_type = THERMAL_TRIP_CRITICAL,
1358                                         .upper = THERMAL_NO_LIMIT,
1359                                         .lower = THERMAL_NO_LIMIT,
1360                                 },
1361                         },
1362                         .tzp = &soctherm_tzp,
1363                 },
1364                 [THERM_GPU] = {
1365                         .zone_enable = true,
1366                         .passive_delay = 1000,
1367                         .hotspot_offset = 6000,
1368                         .num_trips = 3,
1369                         .trips = {
1370                                 {
1371                                         .cdev_type = "tegra-balanced",
1372                                         .trip_temp = 90000,
1373                                         .trip_type = THERMAL_TRIP_PASSIVE,
1374                                         .upper = THERMAL_NO_LIMIT,
1375                                         .lower = THERMAL_NO_LIMIT,
1376                                 },
1377                                 {
1378                                         .cdev_type = "tegra-heavy",
1379                                         .trip_temp = 100000,
1380                                         .trip_type = THERMAL_TRIP_HOT,
1381                                         .upper = THERMAL_NO_LIMIT,
1382                                         .lower = THERMAL_NO_LIMIT,
1383                                 },
1384                                 {
1385                                         .cdev_type = "tegra-shutdown",
1386                                         .trip_temp = 102000,
1387                                         .trip_type = THERMAL_TRIP_CRITICAL,
1388                                         .upper = THERMAL_NO_LIMIT,
1389                                         .lower = THERMAL_NO_LIMIT,
1390                                 },
1391                         },
1392                         .tzp = &soctherm_tzp,
1393                 },
1394                 [THERM_PLL] = {
1395                         .zone_enable = true,
1396                 },
1397         },
1398         .throttle = {
1399                 [THROTTLE_HEAVY] = {
1400                         .priority = 100,
1401                         .devs = {
1402                                 [THROTTLE_DEV_CPU] = {
1403                                         .enable = true,
1404                                         .depth = 80,
1405                                 },
1406                         },
1407                 },
1408         },
1409         .tshut_pmu_trip_data = &tpdata_palmas,
1410 };
1411
1412 int __init dalmore_soctherm_init(void)
1413 {
1414         struct board_info board_info;
1415
1416         tegra_get_board_info(&board_info);
1417         if (!(board_info.board_id == BOARD_E1611 ||
1418                 board_info.board_id == BOARD_P2454))
1419                 dalmore_soctherm_data.tshut_pmu_trip_data = &tpdata_max77663;
1420
1421         tegra_platform_edp_init(dalmore_soctherm_data.therm[THERM_CPU].trips,
1422                         &dalmore_soctherm_data.therm[THERM_CPU].num_trips,
1423                         6000); /* edp temperature margin */
1424         tegra_add_tj_trips(dalmore_soctherm_data.therm[THERM_CPU].trips,
1425                         &dalmore_soctherm_data.therm[THERM_CPU].num_trips);
1426         tegra_add_vc_trips(dalmore_soctherm_data.therm[THERM_CPU].trips,
1427                         &dalmore_soctherm_data.therm[THERM_CPU].num_trips);
1428
1429         return tegra11_soctherm_init(&dalmore_soctherm_data);
1430 }