ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-dalmore-power.c
1 /*
2  * arch/arm/mach-tegra/board-dalmore-power.c
3  *
4  * Copyright (c) 2012-2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/io.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/fixed.h>
28 #include <linux/mfd/max77663-core.h>
29 #include <linux/mfd/palmas.h>
30 #include <linux/mfd/tps65090.h>
31 #include <linux/regulator/max77663-regulator.h>
32 #include <linux/regulator/tps51632-regulator.h>
33 #include <linux/gpio.h>
34 #include <linux/interrupt.h>
35 #include <linux/regulator/userspace-consumer.h>
36 #include <linux/pid_thermal_gov.h>
37 #include <linux/tegra-soc.h>
38
39 #include <asm/mach-types.h>
40 #include <linux/power/sbs-battery.h>
41
42 #include <mach/irqs.h>
43 #include <mach/edp.h>
44 #include <mach/gpio-tegra.h>
45
46 #include "cpu-tegra.h"
47 #include "pm.h"
48 #include "tegra-board-id.h"
49 #include "board-pmu-defines.h"
50 #include "board.h"
51 #include "gpio-names.h"
52 #include "board-common.h"
53 #include "board-dalmore.h"
54 #include "tegra_cl_dvfs.h"
55 #include "devices.h"
56 #include "tegra11_soctherm.h"
57 #include "iomap.h"
58 #include "tegra3_tsensor.h"
59
60 #define PMC_CTRL                0x0
61 #define PMC_CTRL_INTR_LOW       (1 << 17)
62 #define TPS65090_CHARGER_INT    TEGRA_GPIO_PJ0
63 #define POWER_CONFIG2   0x02
64
65 /*TPS65090 consumer rails */
66 static struct regulator_consumer_supply tps65090_dcdc1_supply[] = {
67         REGULATOR_SUPPLY("vdd_sys_5v0", NULL),
68         REGULATOR_SUPPLY("vdd_spk", NULL),
69         REGULATOR_SUPPLY("vdd_sys_modem_5v0", NULL),
70         REGULATOR_SUPPLY("vdd_sys_cam_5v0", NULL),
71 };
72
73 static struct regulator_consumer_supply tps65090_dcdc2_supply[] = {
74         REGULATOR_SUPPLY("vdd_sys_3v3", NULL),
75         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
76         REGULATOR_SUPPLY("pwrdet_hv", NULL),
77         REGULATOR_SUPPLY("vdd_sys_ds_3v3", NULL),
78         REGULATOR_SUPPLY("avdd", "0-0028"),
79         REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL),
80         REGULATOR_SUPPLY("vdd_sys_sensor_3v3", NULL),
81         REGULATOR_SUPPLY("vdd_sys_audio_3v3", NULL),
82         REGULATOR_SUPPLY("vdd_sys_dtv_3v3", NULL),
83         REGULATOR_SUPPLY("vcc", "0-007c"),
84         REGULATOR_SUPPLY("vcc", "0-0030"),
85         REGULATOR_SUPPLY("vin", "2-0030"),
86 };
87
88 static struct regulator_consumer_supply tps65090_dcdc3_supply[] = {
89         REGULATOR_SUPPLY("vdd_ao", NULL),
90 };
91
92 static struct regulator_consumer_supply tps65090_ldo1_supply[] = {
93         REGULATOR_SUPPLY("vdd_sby_5v0", NULL),
94 };
95
96 static struct regulator_consumer_supply tps65090_ldo2_supply[] = {
97         REGULATOR_SUPPLY("vdd_sby_3v3", NULL),
98 };
99
100 static struct regulator_consumer_supply tps65090_fet1_supply[] = {
101         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
102 };
103
104 static struct regulator_consumer_supply tps65090_fet3_supply[] = {
105         REGULATOR_SUPPLY("vdd_modem_3v3", NULL),
106 };
107
108 static struct regulator_consumer_supply tps65090_fet4_supply[] = {
109         REGULATOR_SUPPLY("avdd_lcd", NULL),
110         REGULATOR_SUPPLY("avdd", "spi3.2"),
111 };
112
113 static struct regulator_consumer_supply tps65090_fet5_supply[] = {
114         REGULATOR_SUPPLY("vdd_lvds", NULL),
115 };
116
117 static struct regulator_consumer_supply tps65090_fet6_supply[] = {
118         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
119 };
120
121 static struct regulator_consumer_supply tps65090_fet7_supply[] = {
122         REGULATOR_SUPPLY("avdd", "bcm4329_wlan.1"),
123         REGULATOR_SUPPLY("avdd", "reg-userspace-consumer.2"),
124         REGULATOR_SUPPLY("avdd", "bluedroid_pm.0"),
125 };
126
127 #define tps65090_rails(id) "tps65090-"#id
128 #define TPS65090_PDATA_INIT(_id, _name, _supply_reg,                    \
129         _always_on, _boot_on, _apply_uV, _en_ext_ctrl, _gpio, _wait_to) \
130 static struct regulator_init_data ri_data_##_name =                     \
131 {                                                                       \
132         .supply_regulator = _supply_reg,                                \
133         .constraints = {                                                \
134                 .name = tps65090_rails(_id),                            \
135                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
136                                      REGULATOR_MODE_STANDBY),           \
137                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
138                                    REGULATOR_CHANGE_STATUS |            \
139                                    REGULATOR_CHANGE_VOLTAGE),           \
140                 .always_on = _always_on,                                \
141                 .boot_on = _boot_on,                                    \
142                 .apply_uV = _apply_uV,                                  \
143         },                                                              \
144         .num_consumer_supplies =                                        \
145                 ARRAY_SIZE(tps65090_##_name##_supply),                  \
146         .consumer_supplies = tps65090_##_name##_supply,                 \
147 };                                                                      \
148 static struct tps65090_regulator_plat_data                              \
149                         tps65090_regulator_pdata_##_name =              \
150 {                                                                       \
151         .enable_ext_control = _en_ext_ctrl,                             \
152         .gpio = _gpio,                                                  \
153         .reg_init_data = &ri_data_##_name ,                             \
154         .wait_timeout_us = _wait_to,                                    \
155 }
156
157 TPS65090_PDATA_INIT(DCDC1, dcdc1, NULL, 1, 1, 0, true, -1, -1);
158 TPS65090_PDATA_INIT(DCDC2, dcdc2, NULL, 1, 1, 0, true, -1, -1);
159 TPS65090_PDATA_INIT(DCDC3, dcdc3, NULL, 1, 1, 0, true, -1, -1);
160 TPS65090_PDATA_INIT(LDO1, ldo1, NULL, 1, 1, 0, false, -1, -1);
161 TPS65090_PDATA_INIT(LDO2, ldo2, NULL, 1, 1, 0, false, -1, -1);
162 TPS65090_PDATA_INIT(FET1, fet1, NULL, 0, 0, 0, false, -1, 800);
163 TPS65090_PDATA_INIT(FET3, fet3, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
164 TPS65090_PDATA_INIT(FET4, fet4, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
165 TPS65090_PDATA_INIT(FET5, fet5, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
166 TPS65090_PDATA_INIT(FET6, fet6, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
167 TPS65090_PDATA_INIT(FET7, fet7, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0);
168
169 static struct tps65090_charger_data bcharger_pdata = {
170         .irq_base = TPS65090_TEGRA_IRQ_BASE,
171 };
172
173 #define ADD_TPS65090_REG(_name) (&tps65090_regulator_pdata_##_name)
174 static struct tps65090_platform_data tps65090_pdata = {
175         .irq_base = TPS65090_TEGRA_IRQ_BASE,
176         .reg_pdata = {
177                         ADD_TPS65090_REG(dcdc1),
178                         ADD_TPS65090_REG(dcdc2),
179                         ADD_TPS65090_REG(dcdc3),
180                         ADD_TPS65090_REG(fet1),
181                         NULL,
182                         ADD_TPS65090_REG(fet3),
183                         ADD_TPS65090_REG(fet4),
184                         ADD_TPS65090_REG(fet5),
185                         ADD_TPS65090_REG(fet6),
186                         ADD_TPS65090_REG(fet7),
187                         ADD_TPS65090_REG(ldo1),
188                         ADD_TPS65090_REG(ldo2),
189                 },
190         .charger_pdata = &bcharger_pdata,
191 };
192
193 /* MAX77663 consumer rails */
194 static struct regulator_consumer_supply max77663_sd0_supply[] = {
195         REGULATOR_SUPPLY("vdd_core", NULL),
196         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"),
197         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.2"),
198         REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"),
199 };
200
201 static struct regulator_consumer_supply max77663_sd1_supply[] = {
202         REGULATOR_SUPPLY("vddio_ddr", NULL),
203         REGULATOR_SUPPLY("vddio_ddr0", NULL),
204         REGULATOR_SUPPLY("vddio_ddr1", NULL),
205 };
206
207 static struct regulator_consumer_supply max77663_sd2_supply[] = {
208         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
209         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
210         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"),
211         REGULATOR_SUPPLY("vddio_cam", "vi"),
212         REGULATOR_SUPPLY("pwrdet_cam", NULL),
213         REGULATOR_SUPPLY("avdd_osc", NULL),
214         REGULATOR_SUPPLY("vddio_sys", NULL),
215         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
216         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
217         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
218         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
219         REGULATOR_SUPPLY("vdd_emmc", NULL),
220         REGULATOR_SUPPLY("vddio_audio", NULL),
221         REGULATOR_SUPPLY("pwrdet_audio", NULL),
222         REGULATOR_SUPPLY("avdd_audio_1v8", NULL),
223         REGULATOR_SUPPLY("vdd_audio_1v8", NULL),
224         REGULATOR_SUPPLY("vddio_modem", NULL),
225         REGULATOR_SUPPLY("vddio_modem_1v8", NULL),
226         REGULATOR_SUPPLY("vddio_bb", NULL),
227         REGULATOR_SUPPLY("pwrdet_bb", NULL),
228         REGULATOR_SUPPLY("vddio_bb_1v8", NULL),
229         REGULATOR_SUPPLY("vddio_uart", NULL),
230         REGULATOR_SUPPLY("pwrdet_uart", NULL),
231         REGULATOR_SUPPLY("vddio_gmi", NULL),
232         REGULATOR_SUPPLY("pwrdet_nand", NULL),
233         REGULATOR_SUPPLY("vdd_sensor_1v8", NULL),
234         REGULATOR_SUPPLY("vdd_mic_1v8", NULL),
235         REGULATOR_SUPPLY("dvdd", "0-0028"),
236         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
237         REGULATOR_SUPPLY("vdd_spi_1v8", NULL),
238         REGULATOR_SUPPLY("dvdd_lcd", NULL),
239         REGULATOR_SUPPLY("vdd_com_1v8", NULL),
240         REGULATOR_SUPPLY("dvdd", "bcm4329_wlan.1"),
241         REGULATOR_SUPPLY("dvdd", "reg-userspace-consumer.2"),
242         REGULATOR_SUPPLY("dvdd", "bluedroid_pm.0"),
243         REGULATOR_SUPPLY("vdd_dtv_1v8", NULL),
244         REGULATOR_SUPPLY("vlogic", "0-0069"),
245         REGULATOR_SUPPLY("vid", "0-000d"),
246         REGULATOR_SUPPLY("vddio", "0-0078"),
247 };
248
249 static struct regulator_consumer_supply max77663_sd3_supply[] = {
250         REGULATOR_SUPPLY("vcore_emmc", NULL),
251 };
252
253 static struct regulator_consumer_supply max77663_ldo0_supply[] = {
254         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
255         REGULATOR_SUPPLY("avdd_pllx", NULL),
256         REGULATOR_SUPPLY("avdd_plle", NULL),
257         REGULATOR_SUPPLY("avdd_pllm", NULL),
258         REGULATOR_SUPPLY("avdd_pllu", NULL),
259         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
260         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
261         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
262 };
263
264 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
265         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
266 };
267
268 static struct regulator_consumer_supply max77663_ldo2_supply[] = {
269         REGULATOR_SUPPLY("vdd_sensor_2v85", NULL),
270         REGULATOR_SUPPLY("vdd_als", NULL),
271         REGULATOR_SUPPLY("vdd", "0-0048"),
272         REGULATOR_SUPPLY("vdd", "0-004c"),
273         REGULATOR_SUPPLY("vdd", "0-0069"),
274         REGULATOR_SUPPLY("vdd", "0-000d"),
275         REGULATOR_SUPPLY("vdd", "0-0078"),
276 };
277
278 static struct regulator_consumer_supply max77663_ldo3_supply[] = {
279         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
280         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
281         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
282 };
283
284 static struct regulator_consumer_supply max77663_ldo4_supply[] = {
285         REGULATOR_SUPPLY("vdd_rtc", NULL),
286 };
287
288 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
289         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
290         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
291         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
292         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
293         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
294         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
295         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
296         REGULATOR_SUPPLY("vddio_bb_hsic", NULL),
297 };
298
299 static struct regulator_consumer_supply max77663_ldo6_supply[] = {
300         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
301         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
302 };
303
304 /* FIXME!! Put the device address of camera */
305 static struct regulator_consumer_supply max77663_ldo7_supply[] = {
306         REGULATOR_SUPPLY("avdd_cam1", NULL),
307         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
308         REGULATOR_SUPPLY("vana", "2-0036"),
309 };
310
311 /* FIXME!! Put the device address of camera */
312 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
313         REGULATOR_SUPPLY("avdd_cam2", NULL),
314         REGULATOR_SUPPLY("avdd", "2-0010"),
315 };
316
317 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
318         {
319                 .src = FPS_SRC_0,
320                 .en_src = FPS_EN_SRC_EN0,
321                 .time_period = FPS_TIME_PERIOD_DEF,
322         },
323         {
324                 .src = FPS_SRC_1,
325                 .en_src = FPS_EN_SRC_EN1,
326                 .time_period = FPS_TIME_PERIOD_DEF,
327         },
328         {
329                 .src = FPS_SRC_2,
330                 .en_src = FPS_EN_SRC_EN0,
331                 .time_period = FPS_TIME_PERIOD_DEF,
332         },
333 };
334
335 #define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg,   \
336                 _always_on, _boot_on, _apply_uV,                        \
337                 _fps_src, _fps_pu_period, _fps_pd_period, _flags)       \
338         static struct regulator_init_data max77663_regulator_idata_##_id = {   \
339                 .supply_regulator = _supply_reg,                        \
340                 .constraints = {                                        \
341                         .name = max77663_rails(_id),                    \
342                         .min_uV = _min_uV,                              \
343                         .max_uV = _max_uV,                              \
344                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
345                                              REGULATOR_MODE_STANDBY),   \
346                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
347                                            REGULATOR_CHANGE_STATUS |    \
348                                            REGULATOR_CHANGE_VOLTAGE),   \
349                         .always_on = _always_on,                        \
350                         .boot_on = _boot_on,                            \
351                         .apply_uV = _apply_uV,                          \
352                 },                                                      \
353                 .num_consumer_supplies =                                \
354                         ARRAY_SIZE(max77663_##_id##_supply),            \
355                 .consumer_supplies = max77663_##_id##_supply,           \
356         };                                                              \
357 static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id =\
358 {                                                                       \
359                 .reg_init_data = &max77663_regulator_idata_##_id,       \
360                 .id = MAX77663_REGULATOR_ID_##_rid,                     \
361                 .fps_src = _fps_src,                                    \
362                 .fps_pu_period = _fps_pu_period,                        \
363                 .fps_pd_period = _fps_pd_period,                        \
364                 .fps_cfgs = max77663_fps_cfgs,                          \
365                 .flags = _flags,                                        \
366         }
367
368 MAX77663_PDATA_INIT(SD0, sd0,  900000, 1400000, tps65090_rails(DCDC3), 1, 1, 0,
369                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
370
371 MAX77663_PDATA_INIT(SD1, sd1,  1200000, 1200000, tps65090_rails(DCDC3), 1, 1, 1,
372                     FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
373
374 MAX77663_PDATA_INIT(SD2, sd2,  1800000, 1800000, tps65090_rails(DCDC3), 1, 1, 1,
375                     FPS_SRC_0, -1, -1, 0);
376
377 MAX77663_PDATA_INIT(SD3, sd3,  2850000, 2850000, tps65090_rails(DCDC3), 1, 1, 1,
378                     FPS_SRC_NONE, -1, -1, 0);
379
380 MAX77663_PDATA_INIT(LDO0, ldo0, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
381                     FPS_SRC_1, -1, -1, 0);
382
383 MAX77663_PDATA_INIT(LDO1, ldo1, 1050000, 1050000, max77663_rails(sd2), 0, 0, 1,
384                     FPS_SRC_NONE, -1, -1, 0);
385
386 MAX77663_PDATA_INIT(LDO2, ldo2, 2850000, 2850000, tps65090_rails(DCDC2), 1, 1,
387                     1, FPS_SRC_1, -1, -1, 0);
388
389 MAX77663_PDATA_INIT(LDO3, ldo3, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1,
390                     FPS_SRC_NONE, -1, -1, 0);
391
392 MAX77663_PDATA_INIT(LDO4, ldo4, 1100000, 1100000, tps65090_rails(DCDC2), 1, 1,
393                     1, FPS_SRC_NONE, -1, -1, LDO4_EN_TRACKING);
394
395 MAX77663_PDATA_INIT(LDO5, ldo5, 1200000, 1200000, max77663_rails(sd2), 0, 1, 1,
396                     FPS_SRC_NONE, -1, -1, 0);
397
398 MAX77663_PDATA_INIT(LDO6, ldo6, 1800000, 3300000, tps65090_rails(DCDC2), 0, 0, 0,
399                     FPS_SRC_NONE, -1, -1, 0);
400
401 MAX77663_PDATA_INIT(LDO7, ldo7, 2800000, 2800000, tps65090_rails(DCDC2), 0, 0, 1,
402                     FPS_SRC_NONE, -1, -1, 0);
403
404 MAX77663_PDATA_INIT(LDO8, ldo8, 2800000, 2800000, tps65090_rails(DCDC2), 0, 1, 1,
405                     FPS_SRC_1, -1, -1, 0);
406
407 #define MAX77663_REG(_id, _data) (&max77663_regulator_pdata_##_data)
408
409 static struct max77663_regulator_platform_data *max77663_reg_pdata[] = {
410         MAX77663_REG(SD0, sd0),
411         MAX77663_REG(SD1, sd1),
412         MAX77663_REG(SD2, sd2),
413         MAX77663_REG(SD3, sd3),
414         MAX77663_REG(LDO0, ldo0),
415         MAX77663_REG(LDO1, ldo1),
416         MAX77663_REG(LDO2, ldo2),
417         MAX77663_REG(LDO3, ldo3),
418         MAX77663_REG(LDO4, ldo4),
419         MAX77663_REG(LDO5, ldo5),
420         MAX77663_REG(LDO6, ldo6),
421         MAX77663_REG(LDO7, ldo7),
422         MAX77663_REG(LDO8, ldo8),
423 };
424
425 static struct max77663_gpio_config max77663_gpio_cfgs[] = {
426         {
427                 .gpio = MAX77663_GPIO0,
428                 .dir = GPIO_DIR_OUT,
429                 .dout = GPIO_DOUT_LOW,
430                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
431                 .alternate = GPIO_ALT_DISABLE,
432         },
433         {
434                 .gpio = MAX77663_GPIO1,
435                 .dir = GPIO_DIR_IN,
436                 .dout = GPIO_DOUT_HIGH,
437                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
438                 .pull_up = GPIO_PU_ENABLE,
439                 .alternate = GPIO_ALT_DISABLE,
440         },
441         {
442                 .gpio = MAX77663_GPIO2,
443                 .dir = GPIO_DIR_OUT,
444                 .dout = GPIO_DOUT_HIGH,
445                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
446                 .pull_up = GPIO_PU_ENABLE,
447                 .alternate = GPIO_ALT_DISABLE,
448         },
449         {
450                 .gpio = MAX77663_GPIO3,
451                 .dir = GPIO_DIR_OUT,
452                 .dout = GPIO_DOUT_HIGH,
453                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
454                 .pull_up = GPIO_PU_ENABLE,
455                 .alternate = GPIO_ALT_DISABLE,
456         },
457         {
458                 .gpio = MAX77663_GPIO4,
459                 .dir = GPIO_DIR_OUT,
460                 .dout = GPIO_DOUT_HIGH,
461                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
462                 .alternate = GPIO_ALT_ENABLE,
463         },
464         {
465                 .gpio = MAX77663_GPIO5,
466                 .dir = GPIO_DIR_OUT,
467                 .dout = GPIO_DOUT_LOW,
468                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
469                 .alternate = GPIO_ALT_DISABLE,
470         },
471         {
472                 .gpio = MAX77663_GPIO6,
473                 .dir = GPIO_DIR_OUT,
474                 .dout = GPIO_DOUT_LOW,
475                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
476                 .alternate = GPIO_ALT_DISABLE,
477         },
478         {
479                 .gpio = MAX77663_GPIO7,
480                 .dir = GPIO_DIR_OUT,
481                 .dout = GPIO_DOUT_LOW,
482                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
483                 .alternate = GPIO_ALT_DISABLE,
484         },
485 };
486
487 static struct max77663_platform_data max77663_pdata = {
488         .irq_base       = MAX77663_IRQ_BASE,
489         .gpio_base      = MAX77663_GPIO_BASE,
490
491         .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
492         .gpio_cfgs      = max77663_gpio_cfgs,
493
494         .regulator_pdata = max77663_reg_pdata,
495         .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata),
496
497         .rtc_i2c_addr   = 0x68,
498
499         .use_power_off  = false,
500 };
501
502 static struct i2c_board_info __initdata max77663_regulators[] = {
503         {
504                 /* The I2C address was determined by OTP factory setting */
505                 I2C_BOARD_INFO("max77663", 0x3c),
506                 .irq            = INT_EXTERNAL_PMU,
507                 .platform_data  = &max77663_pdata,
508         },
509 };
510
511 static struct i2c_board_info __initdata tps65090_regulators[] = {
512         {
513                 I2C_BOARD_INFO("tps65090", 0x48),
514                 .platform_data  = &tps65090_pdata,
515         },
516 };
517
518 /************************ Palmas based regulator ****************/
519 static struct regulator_consumer_supply palmas_smps12_supply[] = {
520         REGULATOR_SUPPLY("vddio_ddr3l", NULL),
521         REGULATOR_SUPPLY("vcore_ddr3l", NULL),
522         REGULATOR_SUPPLY("vref2_ddr3l", NULL),
523 };
524
525 #define palmas_smps3_supply max77663_sd2_supply
526 #define palmas_smps45_supply max77663_sd0_supply
527 #define palmas_smps457_supply max77663_sd0_supply
528
529 static struct regulator_consumer_supply palmas_smps8_supply[] = {
530         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
531         REGULATOR_SUPPLY("avdd_pllm", NULL),
532         REGULATOR_SUPPLY("avdd_pllu", NULL),
533         REGULATOR_SUPPLY("avdd_pllx", NULL),
534         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
535         REGULATOR_SUPPLY("avdd_plle", NULL),
536         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
537         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
538         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
539         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
540         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
541         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
542         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
543         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
544 };
545
546 static struct regulator_consumer_supply palmas_smps8_config2_supply[] = {
547         REGULATOR_SUPPLY("avdd_plla_p_c", NULL),
548         REGULATOR_SUPPLY("avdd_pllm", NULL),
549         REGULATOR_SUPPLY("avdd_pllu", NULL),
550         REGULATOR_SUPPLY("avdd_pllx", NULL),
551         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
552         REGULATOR_SUPPLY("avdd_plle", NULL),
553         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
554         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
555         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"),
556 };
557
558 static struct regulator_consumer_supply palmas_smps9_supply[] = {
559         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
560 };
561
562 #define palmas_ldo1_supply max77663_ldo7_supply
563
564 static struct regulator_consumer_supply palmas_ldo1_config2_supply[] = {
565         REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"),
566         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
567 };
568
569 #define palmas_ldo2_supply max77663_ldo8_supply
570
571 /* FIXME!! Put the device address of camera */
572 static struct regulator_consumer_supply palmas_ldo2_config2_supply[] = {
573         REGULATOR_SUPPLY("avdd_cam1", NULL),
574         REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL),
575         REGULATOR_SUPPLY("avdd_cam2", NULL),
576         REGULATOR_SUPPLY("vana", "2-0036"),
577         REGULATOR_SUPPLY("vana", "2-0010"),
578         REGULATOR_SUPPLY("vana_imx132", "2-0036"),
579         REGULATOR_SUPPLY("avdd", "2-0010"),
580 };
581
582 #define palmas_ldo3_supply max77663_ldo5_supply
583
584 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
585         REGULATOR_SUPPLY("vpp_fuse", NULL),
586 };
587
588 static struct regulator_consumer_supply palmas_ldo4_config2_supply[] = {
589         REGULATOR_SUPPLY("vpp_fuse", NULL),
590         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"),
591         REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"),
592 };
593
594 #define palmas_ldo6_supply max77663_ldo2_supply
595
596 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
597         REGULATOR_SUPPLY("vdd_af_cam1", NULL),
598         REGULATOR_SUPPLY("vdd", "2-000e"),
599 };
600
601 #define palmas_ldo8_supply max77663_ldo4_supply
602 #define palmas_ldo9_supply max77663_ldo6_supply
603
604 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
605         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
606         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
607 };
608
609 static struct regulator_consumer_supply palmas_ldoln_fab05_supply[] = {
610         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
611 };
612
613 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
614         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
615         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
616         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
617         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
618         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
619 };
620
621 static struct regulator_consumer_supply palmas_ldousb_fab05_supply[] = {
622         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
623         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
624         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
625         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
626         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
627         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
628 };
629
630 static struct regulator_consumer_supply palmas_regen1_supply[] = {
631 };
632
633 static struct regulator_consumer_supply palmas_regen2_supply[] = {
634 };
635
636 PALMAS_REGS_PDATA(smps12, 1350,  1350, tps65090_rails(DCDC3), 1, 1, 0, NORMAL,
637         0, 0, 0, 0, 0);
638 PALMAS_REGS_PDATA(smps3, 1800,  1800, tps65090_rails(DCDC3), 0, 0, 0, NORMAL,
639         0, 0, 0, 0, 0);
640 PALMAS_REGS_PDATA(smps45, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0, NORMAL,
641         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
642 PALMAS_REGS_PDATA(smps457, 900,  1400, tps65090_rails(DCDC2), 1, 1, 0, NORMAL,
643         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
644 PALMAS_REGS_PDATA(smps8, 1050,  1050, tps65090_rails(DCDC2), 0, 1, 1, NORMAL,
645         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
646 PALMAS_REGS_PDATA(smps8_config2, 1050,  1050, tps65090_rails(DCDC2), 0, 1, 1,
647         NORMAL, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
648 PALMAS_REGS_PDATA(smps9, 2800,  2800, tps65090_rails(DCDC2), 1, 0, 0, NORMAL,
649         0, 0, 0, 0, 0);
650 PALMAS_REGS_PDATA(ldo1, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1, 0,
651         0, 0, 0, 0, 0);
652 PALMAS_REGS_PDATA(ldo1_config2, 1200,  1200, tps65090_rails(DCDC2), 0, 0, 1, 0,
653         1, 0, 0, 0, 0);
654 PALMAS_REGS_PDATA(ldo2, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1, 0,
655         0, 0, 0, 0, 0);
656 PALMAS_REGS_PDATA(ldo2_config2, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1, 0,
657         0, 0, 0, 0, 0);
658 PALMAS_REGS_PDATA(ldo3, 1200,  1200, palmas_rails(smps3), 0, 0, 1, 0,
659         0, 0, 0, 0, 0);
660 PALMAS_REGS_PDATA(ldo4_config2, 1200,  1200, tps65090_rails(DCDC2), 0, 0, 1, 0,
661         0, 0, 0, 0, 0);
662 PALMAS_REGS_PDATA(ldo4, 1800,  1800, tps65090_rails(DCDC2), 0, 0, 0, 0,
663         0, 0, 0, 0, 0);
664 PALMAS_REGS_PDATA(ldo6, 2850,  2850, tps65090_rails(DCDC2), 0, 0, 1, 0,
665         0, 0, 0, 0, 0);
666 PALMAS_REGS_PDATA(ldo7, 2800,  2800, tps65090_rails(DCDC2), 0, 0, 1, 0,
667         0, 0, 0, 0, 0);
668 PALMAS_REGS_PDATA(ldo8, 900,  900, tps65090_rails(DCDC3), 1, 1, 1, 0,
669         0, 0, 0, 0, 0);
670 PALMAS_REGS_PDATA(ldo9, 1800,  3300, palmas_rails(smps9), 0, 0, 1, 0,
671         1, 0, 0, 0, 0);
672 PALMAS_REGS_PDATA(ldoln, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1, 0,
673         0, 0, 0, 0, 0);
674 PALMAS_REGS_PDATA(ldoln_fab05, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1, 0,
675         0, 0, 0, 0, 0);
676 PALMAS_REGS_PDATA(ldousb, 3300,  3300, tps65090_rails(DCDC1), 0, 0, 1, 0,
677         0, 0, 0, 0, 0);
678 PALMAS_REGS_PDATA(ldousb_fab05, 3300,  3300, tps65090_rails(DCDC1), 0, 0, 1, 0,
679         0, 0, 0, 0, 0);
680 PALMAS_REGS_PDATA(regen1, 3300,  3300, NULL, 1, 1, 0, 0,
681         0, 0, 0, 0, 0);
682 PALMAS_REGS_PDATA(regen2, 5000,  5000, NULL, 1, 1, 0, 0,
683         0, 0, 0, 0, 0);
684
685 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
686
687 static struct regulator_init_data *dalmore_e1611_reg_data[PALMAS_NUM_REGS] = {
688         PALMAS_REG_PDATA(smps12),
689         NULL,
690         PALMAS_REG_PDATA(smps3),
691         PALMAS_REG_PDATA(smps45),
692         PALMAS_REG_PDATA(smps457),
693         NULL,
694         NULL,
695         PALMAS_REG_PDATA(smps8),
696         PALMAS_REG_PDATA(smps9),
697         NULL,
698         NULL,
699         PALMAS_REG_PDATA(ldo1),
700         PALMAS_REG_PDATA(ldo2),
701         PALMAS_REG_PDATA(ldo3),
702         PALMAS_REG_PDATA(ldo4),
703         NULL,
704         PALMAS_REG_PDATA(ldo6),
705         PALMAS_REG_PDATA(ldo7),
706         PALMAS_REG_PDATA(ldo8),
707         PALMAS_REG_PDATA(ldo9),
708         NULL,
709         NULL,
710         NULL,
711         NULL,
712         NULL,
713         PALMAS_REG_PDATA(ldoln),
714         PALMAS_REG_PDATA(ldousb),
715         PALMAS_REG_PDATA(regen1),
716         PALMAS_REG_PDATA(regen2),
717         NULL,
718         NULL,
719         NULL,
720 };
721
722 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
723 static struct palmas_reg_init *dalmore_e1611_reg_init[PALMAS_NUM_REGS] = {
724         PALMAS_REG_INIT_DATA(smps12),
725         NULL,
726         PALMAS_REG_INIT_DATA(smps3),
727         PALMAS_REG_INIT_DATA(smps45),
728         PALMAS_REG_INIT_DATA(smps457),
729         NULL,
730         NULL,
731         PALMAS_REG_INIT_DATA(smps8),
732         PALMAS_REG_INIT_DATA(smps9),
733         NULL,
734         NULL,
735         PALMAS_REG_INIT_DATA(ldo1),
736         PALMAS_REG_INIT_DATA(ldo2),
737         PALMAS_REG_INIT_DATA(ldo3),
738         PALMAS_REG_INIT_DATA(ldo4),
739         NULL,
740         PALMAS_REG_INIT_DATA(ldo6),
741         PALMAS_REG_INIT_DATA(ldo7),
742         PALMAS_REG_INIT_DATA(ldo8),
743         PALMAS_REG_INIT_DATA(ldo9),
744         NULL,
745         NULL,
746         NULL,
747         NULL,
748         NULL,
749         PALMAS_REG_INIT_DATA(ldoln),
750         PALMAS_REG_INIT_DATA(ldousb),
751         PALMAS_REG_INIT_DATA(regen1),
752         PALMAS_REG_INIT_DATA(regen2),
753         NULL,
754         NULL,
755         NULL,
756 };
757
758 static struct palmas_pmic_platform_data pmic_platform = {
759         .disable_smps10_boost_suspend = false,
760 };
761
762 static struct palmas_rtc_platform_data rtc_platform = {
763         .backup_battery_chargeable = true,
764         .backup_battery_charge_high_current = true,
765 };
766
767 static struct palmas_pinctrl_config palmas_pincfg[] = {
768         PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
769         PALMAS_PINMUX("vac", "vac", NULL, NULL),
770         PALMAS_PINMUX("gpio0", "gpio", NULL, NULL),
771         PALMAS_PINMUX("gpio1", "gpio", NULL, NULL),
772         PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
773         PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
774         PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
775         PALMAS_PINMUX("gpio5", "gpio", NULL, NULL),
776         PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
777         PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
778 };
779
780 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
781         .pincfg = palmas_pincfg,
782         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
783         .dvfs1_enable = true,
784         .dvfs2_enable = false,
785 };
786
787 static struct palmas_platform_data palmas_pdata = {
788         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
789         .irq_base = PALMAS_TEGRA_IRQ_BASE,
790         .pmic_pdata = &pmic_platform,
791         .rtc_pdata = &rtc_platform,
792         .pinctrl_pdata = &palmas_pinctrl_pdata,
793         #ifndef CONFIG_ANDROID
794         .long_press_delay = PALMAS_LONG_PRESS_KEY_TIME_8SECONDS,
795         #else
796         /* Retaining default value, 12 Seconds */
797         .long_press_delay = PALMAS_LONG_PRESS_KEY_TIME_DEFAULT,
798         #endif
799 };
800
801 static struct i2c_board_info palma_device[] = {
802         {
803                 I2C_BOARD_INFO("tps65913", 0x58),
804                 .irq            = INT_EXTERNAL_PMU,
805                 .platform_data  = &palmas_pdata,
806         },
807 };
808
809 /* EN_AVDD_USB_HDMI From PMU GP1 */
810 static struct regulator_consumer_supply fixed_reg_avdd_usb_hdmi_supply[] = {
811         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
812         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
813         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
814         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
815         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
816         REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"),
817 };
818
819 /* EN_CAM_1v8 From PMU GP5 */
820 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = {
821         REGULATOR_SUPPLY("vi2c", "2-0030"),
822         REGULATOR_SUPPLY("vif", "2-0036"),
823         REGULATOR_SUPPLY("dovdd", "2-0010"),
824         REGULATOR_SUPPLY("dvdd", "2-0010"),
825         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
826 };
827
828 /* EN_CAM_1v8 on e1611 From PMU GP6 */
829 static struct regulator_consumer_supply fixed_reg_en_1v8_cam_e1611_supply[] = {
830         REGULATOR_SUPPLY("vi2c", "2-0030"),
831         REGULATOR_SUPPLY("vif", "2-0036"),
832         REGULATOR_SUPPLY("dovdd", "2-0010"),
833         REGULATOR_SUPPLY("dvdd", "2-0010"),
834         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
835 };
836
837 static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = {
838         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
839 };
840
841 static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = {
842         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
843 };
844
845 /* EN_USB1_VBUS From TEGRA GPIO PN4 PR3(T30) */
846 static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = {
847         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
848         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
849         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci"),
850 };
851
852 /* EN_3V3_FUSE From TEGRA GPIO PX4 */
853 static struct regulator_consumer_supply fixed_reg_vpp_fuse_supply[] = {
854         REGULATOR_SUPPLY("vpp_fuse", NULL),
855 };
856
857 /* EN_USB3_VBUS From TEGRA GPIO PM5 */
858 static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = {
859         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
860         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
861 };
862
863 /* EN_1V8_TS From TEGRA_GPIO_PH5 */
864 static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = {
865         REGULATOR_SUPPLY("dvdd", "spi3.2"),
866 };
867
868 /* EN_AVDD_HDMI_PLL From TEGRA_GPIO_PO1 */
869 static struct regulator_consumer_supply fixed_reg_avdd_hdmi_pll_supply[] = {
870         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
871 };
872
873 /* Macro for defining fixed regulator sub device data */
874 #define FIXED_SUPPLY(_name) "fixed_reg_"#_name
875 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
876         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts)  \
877         static struct regulator_init_data ri_data_##_var =              \
878         {                                                               \
879                 .supply_regulator = _in_supply,                         \
880                 .num_consumer_supplies =                                \
881                         ARRAY_SIZE(fixed_reg_##_name##_supply),         \
882                 .consumer_supplies = fixed_reg_##_name##_supply,        \
883                 .constraints = {                                        \
884                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
885                                         REGULATOR_MODE_STANDBY),        \
886                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
887                                         REGULATOR_CHANGE_STATUS |       \
888                                         REGULATOR_CHANGE_VOLTAGE),      \
889                         .always_on = _always_on,                        \
890                         .boot_on = _boot_on,                            \
891                 },                                                      \
892         };                                                              \
893         static struct fixed_voltage_config fixed_reg_##_var##_pdata =   \
894         {                                                               \
895                 .supply_name = FIXED_SUPPLY(_name),                     \
896                 .microvolts = _millivolts * 1000,                       \
897                 .gpio = _gpio_nr,                                       \
898                 .gpio_is_open_drain = _open_drain,                      \
899                 .enable_high = _active_high,                            \
900                 .enabled_at_boot = _boot_state,                         \
901                 .init_data = &ri_data_##_var,                           \
902         };                                                              \
903         static struct platform_device fixed_reg_##_var##_dev = {        \
904                 .name = "reg-fixed-voltage",                            \
905                 .id = _id,                                              \
906                 .dev = {                                                \
907                         .platform_data = &fixed_reg_##_var##_pdata,     \
908                 },                                                      \
909         }
910
911 FIXED_REG(1,    avdd_usb_hdmi,  avdd_usb_hdmi,
912         tps65090_rails(DCDC2),  0,      0,
913         MAX77663_GPIO_BASE + MAX77663_GPIO1,    true,   true,   1,      3300);
914
915 FIXED_REG(2,    en_1v8_cam,     en_1v8_cam,
916         max77663_rails(sd2),    0,      0,
917         MAX77663_GPIO_BASE + MAX77663_GPIO5,    false,  true,   0,      1800);
918
919 FIXED_REG(3,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
920         tps65090_rails(DCDC1),  0,      0,
921         TEGRA_GPIO_PK1, false,  true,   0,      5000);
922
923 FIXED_REG(4,    vpp_fuse,       vpp_fuse,
924         max77663_rails(sd2),    0,      0,
925         TEGRA_GPIO_PX4, false,  true,   0,      3300);
926
927 FIXED_REG(5,    usb1_vbus,      usb1_vbus,
928         tps65090_rails(DCDC1),  0,      0,
929         TEGRA_GPIO_PN4, true,   true,   0,      5000);
930
931 FIXED_REG(6,    usb3_vbus,      usb3_vbus,
932         tps65090_rails(DCDC1),  0,      0,
933         TEGRA_GPIO_PK6, true,   true,   0,      5000);
934
935 FIXED_REG(7,    en_1v8_cam_e1611,       en_1v8_cam_e1611,
936         palmas_rails(smps3),    0,      0,
937         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,  false,  true,   0,      1800);
938
939 FIXED_REG(8,    dvdd_ts,        dvdd_ts,
940         palmas_rails(smps3),    0,      0,
941         TEGRA_GPIO_PH5, false,  false,  1,      1800);
942
943 FIXED_REG(9,    lcd_bl_en,      lcd_bl_en,
944         NULL,   0,      0,
945         TEGRA_GPIO_PH2, false,  true,   0,      5000);
946
947 FIXED_REG(10,   avdd_hdmi_pll,  avdd_hdmi_pll,
948         palmas_rails(ldo3),     0,      0,
949         TEGRA_GPIO_PO1, false,  true,   1,      1200);
950 /*
951  * Creating the fixed regulator device tables
952  */
953
954 #define ADD_FIXED_REG(_name)    (&fixed_reg_##_name##_dev)
955
956 #define DALMORE_COMMON_FIXED_REG                \
957         ADD_FIXED_REG(usb1_vbus),               \
958         ADD_FIXED_REG(usb3_vbus),               \
959         ADD_FIXED_REG(vdd_hdmi_5v0),            \
960         ADD_FIXED_REG(lcd_bl_en),
961
962 #define E1612_FIXED_REG                         \
963         ADD_FIXED_REG(avdd_usb_hdmi),           \
964         ADD_FIXED_REG(en_1v8_cam),              \
965         ADD_FIXED_REG(vpp_fuse),                \
966
967 #define E1611_FIXED_REG                         \
968         ADD_FIXED_REG(en_1v8_cam_e1611), \
969         ADD_FIXED_REG(dvdd_ts),
970
971 #define DALMORE_POWER_CONFIG_2                  \
972         ADD_FIXED_REG(avdd_hdmi_pll),
973
974 /* Gpio switch regulator platform data for Dalmore E1611 */
975 static struct platform_device *fixed_reg_devs_e1611_a00[] = {
976         DALMORE_COMMON_FIXED_REG
977         E1611_FIXED_REG
978 };
979
980 /* Gpio switch regulator platform data for Dalmore E1612 */
981 static struct platform_device *fixed_reg_devs_e1612_a00[] = {
982         DALMORE_COMMON_FIXED_REG
983         E1612_FIXED_REG
984 };
985
986 static struct platform_device *fixed_reg_devs_dalmore_config2[] = {
987         DALMORE_POWER_CONFIG_2
988 };
989
990 static void set_dalmore_power_fab05(void)
991 {
992         dalmore_e1611_reg_data[PALMAS_REG_LDOLN] =
993                                 PALMAS_REG_PDATA(ldoln_fab05);
994         dalmore_e1611_reg_init[PALMAS_REG_LDOLN] =
995                                 PALMAS_REG_INIT_DATA(ldoln_fab05);
996         dalmore_e1611_reg_data[PALMAS_REG_LDOUSB] =
997                                 PALMAS_REG_PDATA(ldousb_fab05);
998         dalmore_e1611_reg_init[PALMAS_REG_LDOUSB] =
999                                 PALMAS_REG_INIT_DATA(ldousb_fab05);
1000         return;
1001 }
1002
1003 static void set_dalmore_power_config2(void)
1004 {
1005         dalmore_e1611_reg_data[PALMAS_REG_SMPS8] =
1006                                 PALMAS_REG_PDATA(smps8_config2);
1007         dalmore_e1611_reg_init[PALMAS_REG_SMPS8] =
1008                                 PALMAS_REG_INIT_DATA(smps8_config2);
1009         dalmore_e1611_reg_data[PALMAS_REG_LDO1] =
1010                                 PALMAS_REG_PDATA(ldo1_config2);
1011         dalmore_e1611_reg_init[PALMAS_REG_LDO1] =
1012                                 PALMAS_REG_INIT_DATA(ldo1_config2);
1013         dalmore_e1611_reg_data[PALMAS_REG_LDO2] =
1014                                 PALMAS_REG_PDATA(ldo2_config2);
1015         dalmore_e1611_reg_init[PALMAS_REG_LDO2] =
1016                                 PALMAS_REG_INIT_DATA(ldo2_config2);
1017         dalmore_e1611_reg_data[PALMAS_REG_LDO4] =
1018                                 PALMAS_REG_PDATA(ldo4_config2);
1019         dalmore_e1611_reg_init[PALMAS_REG_LDO4] =
1020                                 PALMAS_REG_INIT_DATA(ldo4_config2);
1021         return;
1022 }
1023
1024 int __init dalmore_palmas_regulator_init(void)
1025 {
1026         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
1027         u32 pmc_ctrl;
1028         u8 power_config;
1029         struct board_info board_info;
1030         int i;
1031
1032         tegra_get_board_info(&board_info);
1033
1034         /* TPS65913: Normal state of INT request line is LOW.
1035          * configure the power management controller to trigger PMU
1036          * interrupts when HIGH.
1037          */
1038         pmc_ctrl = readl(pmc + PMC_CTRL);
1039         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
1040
1041         /* Enable regulator full constraints */
1042         regulator_has_full_constraints();
1043
1044         reg_idata_ldo6.constraints.enable_time = 1000;
1045         ri_data_fet1.constraints.disable_time = 1500;
1046
1047         /* Tracking configuration */
1048         reg_init_data_ldo8.config_flags =
1049                         PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE |
1050                         PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE;
1051
1052         power_config = get_power_config();
1053         if (board_info.fab == BOARD_FAB_A05) {
1054                 set_dalmore_power_config2();
1055                 set_dalmore_power_fab05();
1056         } else if (power_config & POWER_CONFIG2) {
1057                 set_dalmore_power_config2();
1058         }
1059
1060         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
1061                 pmic_platform.reg_data[i] = dalmore_e1611_reg_data[i];
1062                 pmic_platform.reg_init[i] = dalmore_e1611_reg_init[i];
1063         }
1064
1065         i2c_register_board_info(4, palma_device,
1066                         ARRAY_SIZE(palma_device));
1067         return 0;
1068 }
1069
1070 static int ac_online(void)
1071 {
1072         return 1;
1073 }
1074
1075 static struct resource dalmore_pda_resources[] = {
1076         [0] = {
1077                 .name   = "ac",
1078         },
1079 };
1080
1081 static struct pda_power_pdata dalmore_pda_data = {
1082         .is_ac_online   = ac_online,
1083 };
1084
1085 static struct platform_device dalmore_pda_power_device = {
1086         .name           = "pda-power",
1087         .id             = -1,
1088         .resource       = dalmore_pda_resources,
1089         .num_resources  = ARRAY_SIZE(dalmore_pda_resources),
1090         .dev    = {
1091                 .platform_data  = &dalmore_pda_data,
1092         },
1093 };
1094
1095 static struct tegra_suspend_platform_data dalmore_suspend_data = {
1096         .cpu_timer      = 500,
1097         .cpu_off_timer  = 300,
1098         .suspend_mode   = TEGRA_SUSPEND_LP0,
1099         .core_timer     = 0x157e,
1100         .core_off_timer = 2000,
1101         .corereq_high   = true,
1102         .sysclkreq_high = true,
1103         .cpu_lp2_min_residency = 1000,
1104         .min_residency_crail = 20000,
1105 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
1106         .lp1_lowvolt_support = false,
1107         .i2c_base_addr = 0,
1108         .pmuslave_addr = 0,
1109         .core_reg_addr = 0,
1110         .lp1_core_volt_low_cold = 0,
1111         .lp1_core_volt_low = 0,
1112         .lp1_core_volt_high = 0,
1113 #endif
1114         .usb_vbus_internal_wake = true,
1115         .usb_id_internal_wake = true,
1116 };
1117 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1118 /* board parameters for cpu dfll */
1119 static struct tegra_cl_dvfs_cfg_param dalmore_cl_dvfs_param = {
1120         .sample_rate = 12500,
1121
1122         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
1123         .cf = 10,
1124         .ci = 0,
1125         .cg = 2,
1126
1127         .droop_cut_value = 0xF,
1128         .droop_restore_ramp = 0x0,
1129         .scale_out_ramp = 0x0,
1130 };
1131 #endif
1132
1133 /* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */
1134 #define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1)
1135 static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE];
1136 static inline void fill_reg_map(void)
1137 {
1138         int i;
1139         for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) {
1140                 pmu_cpu_vdd_map[i].reg_value = i + 0x23;
1141                 pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i;
1142         }
1143 }
1144
1145 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1146 static struct tegra_cl_dvfs_platform_data dalmore_cl_dvfs_data = {
1147         .dfll_clk_name = "dfll_cpu",
1148         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
1149         .u.pmu_i2c = {
1150                 .fs_rate = 400000,
1151                 .slave_addr = 0x86,
1152                 .reg = 0x00,
1153         },
1154         .vdd_map = pmu_cpu_vdd_map,
1155         .vdd_map_size = PMU_CPU_VDD_MAP_SIZE,
1156
1157         .cfg_param = &dalmore_cl_dvfs_param,
1158 };
1159
1160 static int __init dalmore_cl_dvfs_init(void)
1161 {
1162         fill_reg_map();
1163         if (tegra_revision < TEGRA_REVISION_A02)
1164                 dalmore_cl_dvfs_data.flags = TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET;
1165         tegra_cl_dvfs_device.dev.platform_data = &dalmore_cl_dvfs_data;
1166         platform_device_register(&tegra_cl_dvfs_device);
1167
1168         return 0;
1169 }
1170 #endif
1171
1172 static int __init dalmore_max77663_regulator_init(void)
1173 {
1174         struct board_info board_info;
1175         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
1176         u32 pmc_ctrl;
1177
1178         tegra_get_board_info(&board_info);
1179         if (board_info.fab < BOARD_FAB_A02)
1180                 max77663_regulator_pdata_ldo4.flags = 0;
1181
1182         /* configure the power management controller to trigger PMU
1183          * interrupts when low */
1184         pmc_ctrl = readl(pmc + PMC_CTRL);
1185         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
1186
1187         i2c_register_board_info(4, max77663_regulators,
1188                                 ARRAY_SIZE(max77663_regulators));
1189
1190         return 0;
1191 }
1192
1193 static struct regulator_bulk_data dalmore_gps_regulator_supply[] = {
1194         [0] = {
1195                 .supply = "avdd",
1196         },
1197         [1] = {
1198                 .supply = "dvdd",
1199         },
1200 };
1201
1202 static struct regulator_userspace_consumer_data dalmore_gps_regulator_pdata = {
1203         .num_supplies   = ARRAY_SIZE(dalmore_gps_regulator_supply),
1204         .supplies       = dalmore_gps_regulator_supply,
1205 };
1206
1207 static struct platform_device dalmore_gps_regulator_device = {
1208         .name   = "reg-userspace-consumer",
1209         .id     = 2,
1210         .dev    = {
1211                         .platform_data = &dalmore_gps_regulator_pdata,
1212         },
1213 };
1214
1215 static int __init dalmore_fixed_regulator_init(void)
1216 {
1217         struct board_info board_info;
1218         u8 power_config;
1219
1220         if (!of_machine_is_compatible("nvidia,dalmore"))
1221                 return 0;
1222
1223         power_config = get_power_config();
1224         tegra_get_board_info(&board_info);
1225
1226         /* Fab05 and power-type2 have the same fixed regs */
1227         if (board_info.fab == BOARD_FAB_A05 || power_config & POWER_CONFIG2)
1228                 platform_add_devices(fixed_reg_devs_dalmore_config2,
1229                                 ARRAY_SIZE(fixed_reg_devs_dalmore_config2));
1230
1231         if (board_info.board_id == BOARD_E1611 ||
1232                 board_info.board_id == BOARD_P2454)
1233                 return platform_add_devices(fixed_reg_devs_e1611_a00,
1234                                 ARRAY_SIZE(fixed_reg_devs_e1611_a00));
1235         else
1236                 return platform_add_devices(fixed_reg_devs_e1612_a00,
1237                                 ARRAY_SIZE(fixed_reg_devs_e1612_a00));
1238 }
1239 subsys_initcall_sync(dalmore_fixed_regulator_init);
1240
1241 static void dalmore_tps65090_init(void)
1242 {
1243         int err;
1244
1245         err = gpio_request(TPS65090_CHARGER_INT, "CHARGER_INT");
1246         if (err < 0) {
1247                 pr_err("%s: gpio_request failed %d\n", __func__, err);
1248                 goto fail_init_irq;
1249         }
1250
1251         err = gpio_direction_input(TPS65090_CHARGER_INT);
1252         if (err < 0) {
1253                 pr_err("%s: gpio_direction_input failed %d\n", __func__, err);
1254                 goto fail_init_irq;
1255         }
1256
1257         tps65090_regulators[0].irq = gpio_to_irq(TPS65090_CHARGER_INT);
1258 fail_init_irq:
1259         i2c_register_board_info(4, tps65090_regulators,
1260                         ARRAY_SIZE(tps65090_regulators));
1261         return;
1262 }
1263
1264 int __init dalmore_regulator_init(void)
1265 {
1266         struct board_info board_info;
1267
1268         dalmore_tps65090_init();
1269 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1270         dalmore_cl_dvfs_init();
1271 #endif
1272         tegra_get_board_info(&board_info);
1273         if (board_info.board_id == BOARD_E1611 ||
1274                 board_info.board_id == BOARD_P2454)
1275                 dalmore_palmas_regulator_init();
1276         else
1277                 dalmore_max77663_regulator_init();
1278
1279         platform_device_register(&dalmore_pda_power_device);
1280         platform_device_register(&dalmore_gps_regulator_device);
1281         return 0;
1282 }
1283
1284 int __init dalmore_suspend_init(void)
1285 {
1286         tegra_init_suspend(&dalmore_suspend_data);
1287         /* Enable dalmore USB wake for VBUS/ID without using PMIC */
1288         tegra_set_usb_vbus_internal_wake(
1289                 dalmore_suspend_data.usb_vbus_internal_wake);
1290         tegra_set_usb_id_internal_wake(
1291                 dalmore_suspend_data.usb_id_internal_wake);
1292         return 0;
1293 }
1294
1295 int __init dalmore_edp_init(void)
1296 {
1297         unsigned int regulator_mA;
1298
1299         regulator_mA = get_maximum_cpu_current_supported();
1300         if (!regulator_mA)
1301                 regulator_mA = 15000;
1302
1303         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1304         tegra_init_cpu_edp_limits(regulator_mA);
1305
1306         regulator_mA = get_maximum_core_current_supported();
1307         if (!regulator_mA)
1308                 regulator_mA = 4000;
1309
1310         pr_info("%s: core regulator %d mA\n", __func__, regulator_mA);
1311         tegra_init_core_edp_limits(regulator_mA);
1312
1313         return 0;
1314 }
1315
1316 static struct pid_thermal_gov_params soctherm_pid_params = {
1317         .max_err_temp = 9000,
1318         .max_err_gain = 1000,
1319
1320         .gain_p = 1000,
1321         .gain_d = 0,
1322
1323         .up_compensation = 20,
1324         .down_compensation = 20,
1325 };
1326
1327 static struct thermal_zone_params soctherm_tzp = {
1328         .governor_name = "pid_thermal_gov",
1329         .governor_params = &soctherm_pid_params,
1330 };
1331
1332 static struct tegra_tsensor_pmu_data tpdata_palmas = {
1333         .reset_tegra = 1,
1334         .pmu_16bit_ops = 0,
1335         .controller_type = 0,
1336         .pmu_i2c_addr = 0x58,
1337         .i2c_controller_id = 4,
1338         .poweroff_reg_addr = 0xa0,
1339         .poweroff_reg_data = 0x0,
1340 };
1341
1342 static struct tegra_tsensor_pmu_data tpdata_max77663 = {
1343         .reset_tegra = 1,
1344         .pmu_16bit_ops = 0,
1345         .controller_type = 0,
1346         .pmu_i2c_addr = 0x3c,
1347         .i2c_controller_id = 4,
1348         .poweroff_reg_addr = 0x41,
1349         .poweroff_reg_data = 0x80,
1350 };
1351
1352 static struct soctherm_platform_data dalmore_soctherm_data = {
1353         .therm = {
1354                 [THERM_CPU] = {
1355                         .zone_enable = true,
1356                         .passive_delay = 1000,
1357                         .hotspot_offset = 6000,
1358                         .num_trips = 3,
1359                         .trips = {
1360                                 {
1361                                         .cdev_type = "tegra-balanced",
1362                                         .trip_temp = 90000,
1363                                         .trip_type = THERMAL_TRIP_PASSIVE,
1364                                         .upper = THERMAL_NO_LIMIT,
1365                                         .lower = THERMAL_NO_LIMIT,
1366                                 },
1367                                 {
1368                                         .cdev_type = "tegra-heavy",
1369                                         .trip_temp = 100000,
1370                                         .trip_type = THERMAL_TRIP_HOT,
1371                                         .upper = THERMAL_NO_LIMIT,
1372                                         .lower = THERMAL_NO_LIMIT,
1373                                 },
1374                                 {
1375                                         .cdev_type = "tegra-shutdown",
1376                                         .trip_temp = 102000,
1377                                         .trip_type = THERMAL_TRIP_CRITICAL,
1378                                         .upper = THERMAL_NO_LIMIT,
1379                                         .lower = THERMAL_NO_LIMIT,
1380                                 },
1381                         },
1382                         .tzp = &soctherm_tzp,
1383                 },
1384                 [THERM_GPU] = {
1385                         .zone_enable = true,
1386                         .passive_delay = 1000,
1387                         .hotspot_offset = 6000,
1388                         .num_trips = 3,
1389                         .trips = {
1390                                 {
1391                                         .cdev_type = "tegra-balanced",
1392                                         .trip_temp = 90000,
1393                                         .trip_type = THERMAL_TRIP_PASSIVE,
1394                                         .upper = THERMAL_NO_LIMIT,
1395                                         .lower = THERMAL_NO_LIMIT,
1396                                 },
1397                                 {
1398                                         .cdev_type = "tegra-heavy",
1399                                         .trip_temp = 100000,
1400                                         .trip_type = THERMAL_TRIP_HOT,
1401                                         .upper = THERMAL_NO_LIMIT,
1402                                         .lower = THERMAL_NO_LIMIT,
1403                                 },
1404                                 {
1405                                         .cdev_type = "tegra-shutdown",
1406                                         .trip_temp = 102000,
1407                                         .trip_type = THERMAL_TRIP_CRITICAL,
1408                                         .upper = THERMAL_NO_LIMIT,
1409                                         .lower = THERMAL_NO_LIMIT,
1410                                 },
1411                         },
1412                         .tzp = &soctherm_tzp,
1413                 },
1414                 [THERM_PLL] = {
1415                         .zone_enable = true,
1416                 },
1417         },
1418         .throttle = {
1419                 [THROTTLE_HEAVY] = {
1420                         .priority = 100,
1421                         .devs = {
1422                                 [THROTTLE_DEV_CPU] = {
1423                                         .enable = true,
1424                                         .depth = 80,
1425                                 },
1426                                 [THROTTLE_DEV_GPU] = {
1427                                         .enable = true,
1428                                         .depth = 80,
1429                                 },
1430                         },
1431                 },
1432         },
1433         .tshut_pmu_trip_data = &tpdata_palmas,
1434 };
1435
1436 int __init dalmore_soctherm_init(void)
1437 {
1438         struct board_info board_info;
1439
1440         tegra_get_board_info(&board_info);
1441         if (!(board_info.board_id == BOARD_E1611 ||
1442                 board_info.board_id == BOARD_P2454))
1443                 dalmore_soctherm_data.tshut_pmu_trip_data = &tpdata_max77663;
1444
1445         tegra_platform_edp_init(dalmore_soctherm_data.therm[THERM_CPU].trips,
1446                         &dalmore_soctherm_data.therm[THERM_CPU].num_trips,
1447                         6000); /* edp temperature margin */
1448         tegra_add_cpu_vmax_trips(dalmore_soctherm_data.therm[THERM_CPU].trips,
1449                         &dalmore_soctherm_data.therm[THERM_CPU].num_trips);
1450         tegra_add_core_edp_trips(dalmore_soctherm_data.therm[THERM_CPU].trips,
1451                         &dalmore_soctherm_data.therm[THERM_CPU].num_trips);
1452
1453         return tegra11_soctherm_init(&dalmore_soctherm_data);
1454 }