ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-dalmore-memory.c
1 /*
2  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
16  * 02111-1307, USA
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_data/tegra_emc.h>
22
23 #include "board.h"
24 #include "board-dalmore.h"
25
26 #include "tegra-board-id.h"
27 #include "tegra11_emc.h"
28 #include "devices.h"
29 #include "common.h"
30
31 static struct tegra11_emc_table e1611_h5tc4g63afr_rda_T40S_table[] = {
32         {
33                 0x41,       /* Rev 4.0.3 */
34                 12750,      /* SDRAM frequency */
35                 900,       /* min voltage */
36                 "pll_p",    /* clock source id */
37                 0x4000003e, /* CLK_SOURCE_EMC */
38                 99,         /* number of burst_regs */
39                 30,         /* number of trim_regs (each channel) */
40                 11,         /* number of up_down_regs */
41                 {
42                         0x00000000, /* EMC_RC */
43                         0x00000003, /* EMC_RFC */
44                         0x00000000, /* EMC_RFC_SLR */
45                         0x00000000, /* EMC_RAS */
46                         0x00000000, /* EMC_RP */
47                         0x00000004, /* EMC_R2W */
48                         0x0000000a, /* EMC_W2R */
49                         0x00000003, /* EMC_R2P */
50                         0x0000000b, /* EMC_W2P */
51                         0x00000000, /* EMC_RD_RCD */
52                         0x00000000, /* EMC_WR_RCD */
53                         0x00000003, /* EMC_RRD */
54                         0x00000001, /* EMC_REXT */
55                         0x00000000, /* EMC_WEXT */
56                         0x00000005, /* EMC_WDV */
57                         0x00000005, /* EMC_WDV_MASK */
58                         0x00000006, /* EMC_IBDLY */
59                         0x00010000, /* EMC_PUTERM_EXTRA */
60                         0x00000000, /* EMC_CDB_CNTL_2 */
61                         0x00000004, /* EMC_QRST */
62                         0x0000000d, /* EMC_RDV_MASK */
63                         0x00000060, /* EMC_REFRESH */
64                         0x00000000, /* EMC_BURST_REFRESH_NUM */
65                         0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
66                         0x00000002, /* EMC_PDEX2WR */
67                         0x00000002, /* EMC_PDEX2RD */
68                         0x00000001, /* EMC_PCHG2PDEN */
69                         0x00000000, /* EMC_ACT2PDEN */
70                         0x00000007, /* EMC_AR2PDEN */
71                         0x0000000f, /* EMC_RW2PDEN */
72                         0x00000005, /* EMC_TXSR */
73                         0x00000005, /* EMC_TXSRDLL */
74                         0x00000004, /* EMC_TCKE */
75                         0x00000004, /* EMC_TCKESR */
76                         0x00000004, /* EMC_TPD */
77                         0x00000001, /* EMC_TFAW */
78                         0x00000000, /* EMC_TRPAB */
79                         0x00000004, /* EMC_TCLKSTABLE */
80                         0x00000005, /* EMC_TCLKSTOP */
81                         0x00000064, /* EMC_TREFBW */
82                         0x00000005, /* EMC_QUSE_EXTRA */
83                         0x00000020, /* EMC_ODT_WRITE */
84                         0x00000000, /* EMC_ODT_READ */
85                         0x0000aa88, /* EMC_FBIO_CFG5 */
86                         0x002c00a0, /* EMC_CFG_DIG_DLL */
87                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
88                         0x0006c000, /* EMC_DLL_XFORM_DQS4 */
89                         0x0006c000, /* EMC_DLL_XFORM_DQS5 */
90                         0x0006c000, /* EMC_DLL_XFORM_DQS6 */
91                         0x0006c000, /* EMC_DLL_XFORM_DQS7 */
92                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
93                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
94                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
95                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
96                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
97                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
98                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
99                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
100                         0x001112a0, /* EMC_XM2CMDPADCTRL */
101                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
102                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
103                         0x00000000, /* EMC_XM2DQPADCTRL2 */
104                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
105                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
106                         0x03035504, /* EMC_XM2VTTGENPADCTRL */
107                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
108                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
109                         0x00000000, /* EMC_TXDSRVTTGEN */
110                         0x02000000, /* EMC_FBIO_SPARE */
111                         0x00000802, /* EMC_CTT_TERM_CTRL */
112                         0x00000000, /* EMC_ZCAL_INTERVAL */
113                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
114                         0x000c000c, /* EMC_MRS_WAIT_CNT */
115                         0x000c000c, /* EMC_MRS_WAIT_CNT2 */
116                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
117                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
118                         0x00000000, /* EMC_CTT */
119                         0x00000000, /* EMC_CTT_DURATION */
120                         0x800001c6, /* EMC_DYN_SELF_REF_CONTROL */
121                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
122                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
123                         0x40040001, /* MC_EMEM_ARB_CFG */
124                         0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */
125                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
126                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
127                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
128                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
129                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
130                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
131                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
132                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
133                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
134                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
135                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
136                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
137                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
138                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
139                         0x77e30303, /* MC_EMEM_ARB_MISC0 */
140                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
141                 },
142                 {
143                         0x00000000, /* EMC_CDB_CNTL_1 */
144                         0x00000006, /* EMC_FBIO_CFG6 */
145                         0x00000006, /* EMC_QUSE */
146                         0x00000004, /* EMC_EINPUT */
147                         0x00000004, /* EMC_EINPUT_DURATION */
148                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
149                         0x00000009, /* EMC_QSAFE */
150                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
151                         0x0000000d, /* EMC_RDV */
152                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
153                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
154                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
155                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
156                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
157                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
158                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
159                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
160                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
161                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
162                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
163                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
164                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
165                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
166                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
167                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
168                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
169                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
170                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
171                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
172                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
173                 },
174                 {
175                         0x00000000, /* EMC_CDB_CNTL_1 */
176                         0x00000006, /* EMC_FBIO_CFG6 */
177                         0x00000006, /* EMC_QUSE */
178                         0x00000004, /* EMC_EINPUT */
179                         0x00000004, /* EMC_EINPUT_DURATION */
180                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
181                         0x00000009, /* EMC_QSAFE */
182                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
183                         0x0000000d, /* EMC_RDV */
184                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
185                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
186                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
187                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
188                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
189                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
190                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
191                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
192                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
193                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
194                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
195                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
196                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
197                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
198                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
199                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
200                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
201                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
202                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
203                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
204                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
205                 },
206                 {
207                         0x0000000e, /* MC_PTSA_GRANT_DECREMENT */
208                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
209                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
210                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
211                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
212                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
213                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
214                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
215                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
216                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
217                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
218                 },
219                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
220                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
221                 0x7320000e, /* EMC_CFG */
222                 0x80001221, /* Mode Register 0 */
223                 0x80100003, /* Mode Register 1 */
224                 0x80200008, /* Mode Register 2 */
225                 0x00000000, /* Mode Register 4 */
226                 57820,      /* expected dvfs latency (ns) */
227         },
228         {
229                 0x41,       /* Rev 4.0.3 */
230                 20400,      /* SDRAM frequency */
231                 900,       /* min voltage */
232                 "pll_p",    /* clock source id */
233                 0x40000026, /* CLK_SOURCE_EMC */
234                 99,         /* number of burst_regs */
235                 30,         /* number of trim_regs (each channel) */
236                 11,         /* number of up_down_regs */
237                 {
238                         0x00000000, /* EMC_RC */
239                         0x00000005, /* EMC_RFC */
240                         0x00000000, /* EMC_RFC_SLR */
241                         0x00000000, /* EMC_RAS */
242                         0x00000000, /* EMC_RP */
243                         0x00000004, /* EMC_R2W */
244                         0x0000000a, /* EMC_W2R */
245                         0x00000003, /* EMC_R2P */
246                         0x0000000b, /* EMC_W2P */
247                         0x00000000, /* EMC_RD_RCD */
248                         0x00000000, /* EMC_WR_RCD */
249                         0x00000003, /* EMC_RRD */
250                         0x00000001, /* EMC_REXT */
251                         0x00000000, /* EMC_WEXT */
252                         0x00000005, /* EMC_WDV */
253                         0x00000005, /* EMC_WDV_MASK */
254                         0x00000006, /* EMC_IBDLY */
255                         0x00010000, /* EMC_PUTERM_EXTRA */
256                         0x00000000, /* EMC_CDB_CNTL_2 */
257                         0x00000004, /* EMC_QRST */
258                         0x0000000d, /* EMC_RDV_MASK */
259                         0x0000009a, /* EMC_REFRESH */
260                         0x00000000, /* EMC_BURST_REFRESH_NUM */
261                         0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
262                         0x00000002, /* EMC_PDEX2WR */
263                         0x00000002, /* EMC_PDEX2RD */
264                         0x00000001, /* EMC_PCHG2PDEN */
265                         0x00000000, /* EMC_ACT2PDEN */
266                         0x00000007, /* EMC_AR2PDEN */
267                         0x0000000f, /* EMC_RW2PDEN */
268                         0x00000006, /* EMC_TXSR */
269                         0x00000006, /* EMC_TXSRDLL */
270                         0x00000004, /* EMC_TCKE */
271                         0x00000004, /* EMC_TCKESR */
272                         0x00000004, /* EMC_TPD */
273                         0x00000001, /* EMC_TFAW */
274                         0x00000000, /* EMC_TRPAB */
275                         0x00000004, /* EMC_TCLKSTABLE */
276                         0x00000005, /* EMC_TCLKSTOP */
277                         0x000000a0, /* EMC_TREFBW */
278                         0x00000005, /* EMC_QUSE_EXTRA */
279                         0x00000020, /* EMC_ODT_WRITE */
280                         0x00000000, /* EMC_ODT_READ */
281                         0x0000aa88, /* EMC_FBIO_CFG5 */
282                         0x002c00a0, /* EMC_CFG_DIG_DLL */
283                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
284                         0x0006c000, /* EMC_DLL_XFORM_DQS4 */
285                         0x0006c000, /* EMC_DLL_XFORM_DQS5 */
286                         0x0006c000, /* EMC_DLL_XFORM_DQS6 */
287                         0x0006c000, /* EMC_DLL_XFORM_DQS7 */
288                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
289                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
290                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
291                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
292                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
293                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
294                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
295                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
296                         0x001112a0, /* EMC_XM2CMDPADCTRL */
297                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
298                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
299                         0x00000000, /* EMC_XM2DQPADCTRL2 */
300                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
301                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
302                         0x03035504, /* EMC_XM2VTTGENPADCTRL */
303                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
304                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
305                         0x00000000, /* EMC_TXDSRVTTGEN */
306                         0x02000000, /* EMC_FBIO_SPARE */
307                         0x00000802, /* EMC_CTT_TERM_CTRL */
308                         0x00000000, /* EMC_ZCAL_INTERVAL */
309                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
310                         0x000c000c, /* EMC_MRS_WAIT_CNT */
311                         0x000c000c, /* EMC_MRS_WAIT_CNT2 */
312                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
313                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
314                         0x00000000, /* EMC_CTT */
315                         0x00000000, /* EMC_CTT_DURATION */
316                         0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
317                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
318                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
319                         0x40020001, /* MC_EMEM_ARB_CFG */
320                         0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */
321                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
322                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
323                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
324                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
325                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
326                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
327                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
328                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
329                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
330                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
331                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
332                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
333                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
334                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
335                         0x76230303, /* MC_EMEM_ARB_MISC0 */
336                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
337                 },
338                 {
339                         0x00000000, /* EMC_CDB_CNTL_1 */
340                         0x00000006, /* EMC_FBIO_CFG6 */
341                         0x00000006, /* EMC_QUSE */
342                         0x00000004, /* EMC_EINPUT */
343                         0x00000004, /* EMC_EINPUT_DURATION */
344                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
345                         0x00000009, /* EMC_QSAFE */
346                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
347                         0x0000000d, /* EMC_RDV */
348                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
349                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
350                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
351                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
352                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
353                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
354                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
355                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
356                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
357                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
358                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
359                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
360                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
361                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
362                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
363                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
364                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
365                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
366                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
367                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
368                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
369                 },
370                 {
371                         0x00000000, /* EMC_CDB_CNTL_1 */
372                         0x00000006, /* EMC_FBIO_CFG6 */
373                         0x00000006, /* EMC_QUSE */
374                         0x00000004, /* EMC_EINPUT */
375                         0x00000004, /* EMC_EINPUT_DURATION */
376                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
377                         0x00000009, /* EMC_QSAFE */
378                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
379                         0x0000000d, /* EMC_RDV */
380                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
381                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
382                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
383                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
384                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
385                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
386                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
387                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
388                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
389                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
390                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
391                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
392                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
393                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
394                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
395                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
396                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
397                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
398                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
399                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
400                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
401                 },
402                 {
403                         0x00000014, /* MC_PTSA_GRANT_DECREMENT */
404                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
405                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
406                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
407                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
408                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
409                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
410                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
411                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
412                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
413                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
414                 },
415                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
416                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
417                 0x7320000e, /* EMC_CFG */
418                 0x80001221, /* Mode Register 0 */
419                 0x80100003, /* Mode Register 1 */
420                 0x80200008, /* Mode Register 2 */
421                 0x00000000, /* Mode Register 4 */
422                 35610,      /* expected dvfs latency (ns) */
423         },
424         {
425                 0x41,       /* Rev 4.0.3 */
426                 40800,      /* SDRAM frequency */
427                 900,       /* min voltage */
428                 "pll_p",    /* clock source id */
429                 0x40000012, /* CLK_SOURCE_EMC */
430                 99,         /* number of burst_regs */
431                 30,         /* number of trim_regs (each channel) */
432                 11,         /* number of up_down_regs */
433                 {
434                         0x00000001, /* EMC_RC */
435                         0x0000000a, /* EMC_RFC */
436                         0x00000000, /* EMC_RFC_SLR */
437                         0x00000001, /* EMC_RAS */
438                         0x00000000, /* EMC_RP */
439                         0x00000004, /* EMC_R2W */
440                         0x0000000a, /* EMC_W2R */
441                         0x00000003, /* EMC_R2P */
442                         0x0000000b, /* EMC_W2P */
443                         0x00000000, /* EMC_RD_RCD */
444                         0x00000000, /* EMC_WR_RCD */
445                         0x00000003, /* EMC_RRD */
446                         0x00000001, /* EMC_REXT */
447                         0x00000000, /* EMC_WEXT */
448                         0x00000005, /* EMC_WDV */
449                         0x00000005, /* EMC_WDV_MASK */
450                         0x00000006, /* EMC_IBDLY */
451                         0x00010000, /* EMC_PUTERM_EXTRA */
452                         0x00000000, /* EMC_CDB_CNTL_2 */
453                         0x00000004, /* EMC_QRST */
454                         0x0000000d, /* EMC_RDV_MASK */
455                         0x00000134, /* EMC_REFRESH */
456                         0x00000000, /* EMC_BURST_REFRESH_NUM */
457                         0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */
458                         0x00000002, /* EMC_PDEX2WR */
459                         0x00000002, /* EMC_PDEX2RD */
460                         0x00000001, /* EMC_PCHG2PDEN */
461                         0x00000000, /* EMC_ACT2PDEN */
462                         0x00000008, /* EMC_AR2PDEN */
463                         0x0000000f, /* EMC_RW2PDEN */
464                         0x0000000c, /* EMC_TXSR */
465                         0x0000000c, /* EMC_TXSRDLL */
466                         0x00000004, /* EMC_TCKE */
467                         0x00000004, /* EMC_TCKESR */
468                         0x00000004, /* EMC_TPD */
469                         0x00000002, /* EMC_TFAW */
470                         0x00000000, /* EMC_TRPAB */
471                         0x00000004, /* EMC_TCLKSTABLE */
472                         0x00000005, /* EMC_TCLKSTOP */
473                         0x0000013f, /* EMC_TREFBW */
474                         0x00000005, /* EMC_QUSE_EXTRA */
475                         0x00000020, /* EMC_ODT_WRITE */
476                         0x00000000, /* EMC_ODT_READ */
477                         0x0000aa88, /* EMC_FBIO_CFG5 */
478                         0x002c00a0, /* EMC_CFG_DIG_DLL */
479                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
480                         0x0006c000, /* EMC_DLL_XFORM_DQS4 */
481                         0x0006c000, /* EMC_DLL_XFORM_DQS5 */
482                         0x0006c000, /* EMC_DLL_XFORM_DQS6 */
483                         0x0006c000, /* EMC_DLL_XFORM_DQS7 */
484                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
485                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
486                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
487                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
488                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
489                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
490                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
491                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
492                         0x001112a0, /* EMC_XM2CMDPADCTRL */
493                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
494                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
495                         0x00000000, /* EMC_XM2DQPADCTRL2 */
496                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
497                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
498                         0x03035504, /* EMC_XM2VTTGENPADCTRL */
499                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
500                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
501                         0x00000000, /* EMC_TXDSRVTTGEN */
502                         0x02000000, /* EMC_FBIO_SPARE */
503                         0x00000802, /* EMC_CTT_TERM_CTRL */
504                         0x00000000, /* EMC_ZCAL_INTERVAL */
505                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
506                         0x000c000c, /* EMC_MRS_WAIT_CNT */
507                         0x000c000c, /* EMC_MRS_WAIT_CNT2 */
508                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
509                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
510                         0x00000000, /* EMC_CTT */
511                         0x00000000, /* EMC_CTT_DURATION */
512                         0x80000370, /* EMC_DYN_SELF_REF_CONTROL */
513                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
514                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
515                         0xa0000001, /* MC_EMEM_ARB_CFG */
516                         0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */
517                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
518                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
519                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
520                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
521                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
522                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
523                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
524                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
525                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
526                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
527                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
528                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
529                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
530                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
531                         0x74a30303, /* MC_EMEM_ARB_MISC0 */
532                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
533                 },
534                 {
535                         0x00000000, /* EMC_CDB_CNTL_1 */
536                         0x00000006, /* EMC_FBIO_CFG6 */
537                         0x00000006, /* EMC_QUSE */
538                         0x00000004, /* EMC_EINPUT */
539                         0x00000004, /* EMC_EINPUT_DURATION */
540                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
541                         0x00000009, /* EMC_QSAFE */
542                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
543                         0x0000000d, /* EMC_RDV */
544                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
545                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
546                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
547                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
548                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
549                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
550                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
551                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
552                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
553                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
554                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
555                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
556                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
557                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
558                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
559                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
560                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
561                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
562                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
563                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
564                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
565                 },
566                 {
567                         0x00000000, /* EMC_CDB_CNTL_1 */
568                         0x00000006, /* EMC_FBIO_CFG6 */
569                         0x00000006, /* EMC_QUSE */
570                         0x00000004, /* EMC_EINPUT */
571                         0x00000004, /* EMC_EINPUT_DURATION */
572                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
573                         0x00000009, /* EMC_QSAFE */
574                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
575                         0x0000000d, /* EMC_RDV */
576                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
577                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
578                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
579                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
580                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
581                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
582                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
583                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
584                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
585                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
586                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
587                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
588                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
589                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
590                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
591                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
592                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
593                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
594                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
595                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
596                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
597                 },
598                 {
599                         0x0000002a, /* MC_PTSA_GRANT_DECREMENT */
600                         0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */
601                         0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */
602                         0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */
603                         0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */
604                         0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */
605                         0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */
606                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
607                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
608                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
609                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
610                 },
611                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
612                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
613                 0x7320000e, /* EMC_CFG */
614                 0x80001221, /* Mode Register 0 */
615                 0x80100003, /* Mode Register 1 */
616                 0x80200008, /* Mode Register 2 */
617                 0x00000000, /* Mode Register 4 */
618                 20850,      /* expected dvfs latency (ns) */
619         },
620         {
621                 0x41,       /* Rev 4.0.3 */
622                 68000,      /* SDRAM frequency */
623                 900,       /* min voltage */
624                 "pll_p",    /* clock source id */
625                 0x4000000a, /* CLK_SOURCE_EMC */
626                 99,         /* number of burst_regs */
627                 30,         /* number of trim_regs (each channel) */
628                 11,         /* number of up_down_regs */
629                 {
630                         0x00000003, /* EMC_RC */
631                         0x00000011, /* EMC_RFC */
632                         0x00000000, /* EMC_RFC_SLR */
633                         0x00000002, /* EMC_RAS */
634                         0x00000000, /* EMC_RP */
635                         0x00000004, /* EMC_R2W */
636                         0x0000000a, /* EMC_W2R */
637                         0x00000003, /* EMC_R2P */
638                         0x0000000b, /* EMC_W2P */
639                         0x00000000, /* EMC_RD_RCD */
640                         0x00000000, /* EMC_WR_RCD */
641                         0x00000003, /* EMC_RRD */
642                         0x00000001, /* EMC_REXT */
643                         0x00000000, /* EMC_WEXT */
644                         0x00000005, /* EMC_WDV */
645                         0x00000005, /* EMC_WDV_MASK */
646                         0x00000006, /* EMC_IBDLY */
647                         0x00010000, /* EMC_PUTERM_EXTRA */
648                         0x00000000, /* EMC_CDB_CNTL_2 */
649                         0x00000004, /* EMC_QRST */
650                         0x0000000d, /* EMC_RDV_MASK */
651                         0x00000202, /* EMC_REFRESH */
652                         0x00000000, /* EMC_BURST_REFRESH_NUM */
653                         0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */
654                         0x00000002, /* EMC_PDEX2WR */
655                         0x00000002, /* EMC_PDEX2RD */
656                         0x00000001, /* EMC_PCHG2PDEN */
657                         0x00000000, /* EMC_ACT2PDEN */
658                         0x0000000f, /* EMC_AR2PDEN */
659                         0x0000000f, /* EMC_RW2PDEN */
660                         0x00000013, /* EMC_TXSR */
661                         0x00000013, /* EMC_TXSRDLL */
662                         0x00000004, /* EMC_TCKE */
663                         0x00000004, /* EMC_TCKESR */
664                         0x00000004, /* EMC_TPD */
665                         0x00000003, /* EMC_TFAW */
666                         0x00000000, /* EMC_TRPAB */
667                         0x00000004, /* EMC_TCLKSTABLE */
668                         0x00000005, /* EMC_TCLKSTOP */
669                         0x00000213, /* EMC_TREFBW */
670                         0x00000005, /* EMC_QUSE_EXTRA */
671                         0x00000020, /* EMC_ODT_WRITE */
672                         0x00000000, /* EMC_ODT_READ */
673                         0x0000aa88, /* EMC_FBIO_CFG5 */
674                         0x002c00a0, /* EMC_CFG_DIG_DLL */
675                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
676                         0x0006c000, /* EMC_DLL_XFORM_DQS4 */
677                         0x0006c000, /* EMC_DLL_XFORM_DQS5 */
678                         0x0006c000, /* EMC_DLL_XFORM_DQS6 */
679                         0x0006c000, /* EMC_DLL_XFORM_DQS7 */
680                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
681                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
682                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
683                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
684                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
685                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
686                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
687                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
688                         0x001112a0, /* EMC_XM2CMDPADCTRL */
689                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
690                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
691                         0x00000000, /* EMC_XM2DQPADCTRL2 */
692                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
693                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
694                         0x03035504, /* EMC_XM2VTTGENPADCTRL */
695                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
696                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
697                         0x00000000, /* EMC_TXDSRVTTGEN */
698                         0x02000000, /* EMC_FBIO_SPARE */
699                         0x00000802, /* EMC_CTT_TERM_CTRL */
700                         0x00000000, /* EMC_ZCAL_INTERVAL */
701                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
702                         0x000c000c, /* EMC_MRS_WAIT_CNT */
703                         0x000c000c, /* EMC_MRS_WAIT_CNT2 */
704                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
705                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
706                         0x00000000, /* EMC_CTT */
707                         0x00000000, /* EMC_CTT_DURATION */
708                         0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */
709                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
710                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
711                         0x00000001, /* MC_EMEM_ARB_CFG */
712                         0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */
713                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
714                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
715                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
716                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
717                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
718                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
719                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
720                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
721                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
722                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
723                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
724                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
725                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
726                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
727                         0x74230403, /* MC_EMEM_ARB_MISC0 */
728                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
729                 },
730                 {
731                         0x00000000, /* EMC_CDB_CNTL_1 */
732                         0x00000006, /* EMC_FBIO_CFG6 */
733                         0x00000006, /* EMC_QUSE */
734                         0x00000004, /* EMC_EINPUT */
735                         0x00000004, /* EMC_EINPUT_DURATION */
736                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
737                         0x00000009, /* EMC_QSAFE */
738                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
739                         0x0000000d, /* EMC_RDV */
740                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
741                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
742                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
743                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
744                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
745                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
746                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
747                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
748                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
749                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
750                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
751                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
752                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
753                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
754                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
755                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
756                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
757                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
758                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
759                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
760                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
761                 },
762                 {
763                         0x00000000, /* EMC_CDB_CNTL_1 */
764                         0x00000006, /* EMC_FBIO_CFG6 */
765                         0x00000006, /* EMC_QUSE */
766                         0x00000004, /* EMC_EINPUT */
767                         0x00000004, /* EMC_EINPUT_DURATION */
768                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
769                         0x00000009, /* EMC_QSAFE */
770                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
771                         0x0000000d, /* EMC_RDV */
772                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
773                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
774                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
775                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
776                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
777                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
778                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
779                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
780                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
781                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
782                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
783                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
784                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
785                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
786                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
787                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
788                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
789                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
790                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
791                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
792                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
793                 },
794                 {
795                         0x00000046, /* MC_PTSA_GRANT_DECREMENT */
796                         0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */
797                         0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */
798                         0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */
799                         0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */
800                         0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */
801                         0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */
802                         0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */
803                         0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */
804                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
805                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
806                 },
807                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
808                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
809                 0x7320000e, /* EMC_CFG */
810                 0x80001221, /* Mode Register 0 */
811                 0x80100003, /* Mode Register 1 */
812                 0x80200008, /* Mode Register 2 */
813                 0x00000000, /* Mode Register 4 */
814                 10720,      /* expected dvfs latency (ns) */
815         },
816         {
817                 0x41,       /* Rev 4.0.3 */
818                 102000,     /* SDRAM frequency */
819                 900,       /* min voltage */
820                 "pll_p",    /* clock source id */
821                 0x40000006, /* CLK_SOURCE_EMC */
822                 99,         /* number of burst_regs */
823                 30,         /* number of trim_regs (each channel) */
824                 11,         /* number of up_down_regs */
825                 {
826                         0x00000004, /* EMC_RC */
827                         0x0000001a, /* EMC_RFC */
828                         0x00000000, /* EMC_RFC_SLR */
829                         0x00000003, /* EMC_RAS */
830                         0x00000001, /* EMC_RP */
831                         0x00000004, /* EMC_R2W */
832                         0x0000000a, /* EMC_W2R */
833                         0x00000003, /* EMC_R2P */
834                         0x0000000b, /* EMC_W2P */
835                         0x00000001, /* EMC_RD_RCD */
836                         0x00000001, /* EMC_WR_RCD */
837                         0x00000003, /* EMC_RRD */
838                         0x00000001, /* EMC_REXT */
839                         0x00000000, /* EMC_WEXT */
840                         0x00000005, /* EMC_WDV */
841                         0x00000005, /* EMC_WDV_MASK */
842                         0x00000006, /* EMC_IBDLY */
843                         0x00010000, /* EMC_PUTERM_EXTRA */
844                         0x00000000, /* EMC_CDB_CNTL_2 */
845                         0x00000004, /* EMC_QRST */
846                         0x0000000d, /* EMC_RDV_MASK */
847                         0x00000303, /* EMC_REFRESH */
848                         0x00000000, /* EMC_BURST_REFRESH_NUM */
849                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
850                         0x00000002, /* EMC_PDEX2WR */
851                         0x00000002, /* EMC_PDEX2RD */
852                         0x00000001, /* EMC_PCHG2PDEN */
853                         0x00000000, /* EMC_ACT2PDEN */
854                         0x00000018, /* EMC_AR2PDEN */
855                         0x0000000f, /* EMC_RW2PDEN */
856                         0x0000001c, /* EMC_TXSR */
857                         0x0000001c, /* EMC_TXSRDLL */
858                         0x00000004, /* EMC_TCKE */
859                         0x00000004, /* EMC_TCKESR */
860                         0x00000004, /* EMC_TPD */
861                         0x00000005, /* EMC_TFAW */
862                         0x00000000, /* EMC_TRPAB */
863                         0x00000004, /* EMC_TCLKSTABLE */
864                         0x00000005, /* EMC_TCLKSTOP */
865                         0x0000031c, /* EMC_TREFBW */
866                         0x00000005, /* EMC_QUSE_EXTRA */
867                         0x00000020, /* EMC_ODT_WRITE */
868                         0x00000000, /* EMC_ODT_READ */
869                         0x0000aa88, /* EMC_FBIO_CFG5 */
870                         0x002c00a0, /* EMC_CFG_DIG_DLL */
871                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
872                         0x0006c000, /* EMC_DLL_XFORM_DQS4 */
873                         0x0006c000, /* EMC_DLL_XFORM_DQS5 */
874                         0x0006c000, /* EMC_DLL_XFORM_DQS6 */
875                         0x0006c000, /* EMC_DLL_XFORM_DQS7 */
876                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
877                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
878                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
879                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
880                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
881                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
882                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
883                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
884                         0x001112a0, /* EMC_XM2CMDPADCTRL */
885                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
886                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
887                         0x00000000, /* EMC_XM2DQPADCTRL2 */
888                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
889                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
890                         0x03035504, /* EMC_XM2VTTGENPADCTRL */
891                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
892                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
893                         0x00000000, /* EMC_TXDSRVTTGEN */
894                         0x02000000, /* EMC_FBIO_SPARE */
895                         0x00000802, /* EMC_CTT_TERM_CTRL */
896                         0x00000000, /* EMC_ZCAL_INTERVAL */
897                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
898                         0x000c000c, /* EMC_MRS_WAIT_CNT */
899                         0x000c000c, /* EMC_MRS_WAIT_CNT2 */
900                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
901                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
902                         0x00000000, /* EMC_CTT */
903                         0x00000000, /* EMC_CTT_DURATION */
904                         0x80000714, /* EMC_DYN_SELF_REF_CONTROL */
905                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
906                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
907                         0x08000001, /* MC_EMEM_ARB_CFG */
908                         0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */
909                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
910                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
911                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
912                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
913                         0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
914                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
915                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
916                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
917                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
918                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
919                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
920                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
921                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
922                         0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
923                         0x73c30504, /* MC_EMEM_ARB_MISC0 */
924                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
925                 },
926                 {
927                         0x00000000, /* EMC_CDB_CNTL_1 */
928                         0x00000006, /* EMC_FBIO_CFG6 */
929                         0x00000006, /* EMC_QUSE */
930                         0x00000004, /* EMC_EINPUT */
931                         0x00000004, /* EMC_EINPUT_DURATION */
932                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
933                         0x00000009, /* EMC_QSAFE */
934                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
935                         0x0000000d, /* EMC_RDV */
936                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
937                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
938                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
939                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
940                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
941                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
942                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
943                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
944                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
945                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
946                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
947                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
948                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
949                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
950                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
951                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
952                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
953                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
954                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
955                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
956                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
957                 },
958                 {
959                         0x00000000, /* EMC_CDB_CNTL_1 */
960                         0x00000006, /* EMC_FBIO_CFG6 */
961                         0x00000006, /* EMC_QUSE */
962                         0x00000004, /* EMC_EINPUT */
963                         0x00000004, /* EMC_EINPUT_DURATION */
964                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
965                         0x00000009, /* EMC_QSAFE */
966                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
967                         0x0000000d, /* EMC_RDV */
968                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
969                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
970                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
971                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
972                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
973                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
974                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
975                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
976                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
977                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
978                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
979                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
980                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
981                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
982                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
983                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
984                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
985                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
986                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
987                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
988                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
989                 },
990                 {
991                         0x00000068, /* MC_PTSA_GRANT_DECREMENT */
992                         0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */
993                         0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */
994                         0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */
995                         0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
996                         0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */
997                         0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */
998                         0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */
999                         0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */
1000                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1001                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1002                 },
1003                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
1004                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1005                 0x7320000e, /* EMC_CFG */
1006                 0x80001221, /* Mode Register 0 */
1007                 0x80100003, /* Mode Register 1 */
1008                 0x80200008, /* Mode Register 2 */
1009                 0x00000000, /* Mode Register 4 */
1010                 6890,       /* expected dvfs latency (ns) */
1011         },
1012         {
1013                 0x41,       /* Rev 4.0.3 */
1014                 204000,     /* SDRAM frequency */
1015                 900,       /* min voltage */
1016                 "pll_p",    /* clock source id */
1017                 0x40000002, /* CLK_SOURCE_EMC */
1018                 99,         /* number of burst_regs */
1019                 30,         /* number of trim_regs (each channel) */
1020                 11,         /* number of up_down_regs */
1021                 {
1022                         0x00000009, /* EMC_RC */
1023                         0x00000035, /* EMC_RFC */
1024                         0x00000000, /* EMC_RFC_SLR */
1025                         0x00000007, /* EMC_RAS */
1026                         0x00000002, /* EMC_RP */
1027                         0x00000004, /* EMC_R2W */
1028                         0x0000000a, /* EMC_W2R */
1029                         0x00000003, /* EMC_R2P */
1030                         0x0000000b, /* EMC_W2P */
1031                         0x00000002, /* EMC_RD_RCD */
1032                         0x00000002, /* EMC_WR_RCD */
1033                         0x00000003, /* EMC_RRD */
1034                         0x00000001, /* EMC_REXT */
1035                         0x00000000, /* EMC_WEXT */
1036                         0x00000005, /* EMC_WDV */
1037                         0x00000005, /* EMC_WDV_MASK */
1038                         0x00000006, /* EMC_IBDLY */
1039                         0x00010000, /* EMC_PUTERM_EXTRA */
1040                         0x00000000, /* EMC_CDB_CNTL_2 */
1041                         0x00000004, /* EMC_QRST */
1042                         0x0000000d, /* EMC_RDV_MASK */
1043                         0x00000607, /* EMC_REFRESH */
1044                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1045                         0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
1046                         0x00000002, /* EMC_PDEX2WR */
1047                         0x00000002, /* EMC_PDEX2RD */
1048                         0x00000001, /* EMC_PCHG2PDEN */
1049                         0x00000000, /* EMC_ACT2PDEN */
1050                         0x00000032, /* EMC_AR2PDEN */
1051                         0x0000000f, /* EMC_RW2PDEN */
1052                         0x00000038, /* EMC_TXSR */
1053                         0x00000038, /* EMC_TXSRDLL */
1054                         0x00000004, /* EMC_TCKE */
1055                         0x00000004, /* EMC_TCKESR */
1056                         0x00000004, /* EMC_TPD */
1057                         0x00000009, /* EMC_TFAW */
1058                         0x00000000, /* EMC_TRPAB */
1059                         0x00000004, /* EMC_TCLKSTABLE */
1060                         0x00000005, /* EMC_TCLKSTOP */
1061                         0x00000638, /* EMC_TREFBW */
1062                         0x00000006, /* EMC_QUSE_EXTRA */
1063                         0x00000020, /* EMC_ODT_WRITE */
1064                         0x00000000, /* EMC_ODT_READ */
1065                         0x0000aa88, /* EMC_FBIO_CFG5 */
1066                         0x000000a0, /* EMC_CFG_DIG_DLL */
1067                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1068                         0x0006c000, /* EMC_DLL_XFORM_DQS4 */
1069                         0x0006c000, /* EMC_DLL_XFORM_DQS5 */
1070                         0x0006c000, /* EMC_DLL_XFORM_DQS6 */
1071                         0x0006c000, /* EMC_DLL_XFORM_DQS7 */
1072                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1073                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1074                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1075                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1076                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1077                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1078                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1079                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1080                         0x001112a0, /* EMC_XM2CMDPADCTRL */
1081                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
1082                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
1083                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1084                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
1085                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
1086                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
1087                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
1088                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1089                         0x00000000, /* EMC_TXDSRVTTGEN */
1090                         0x02000000, /* EMC_FBIO_SPARE */
1091                         0x00000802, /* EMC_CTT_TERM_CTRL */
1092                         0x00020000, /* EMC_ZCAL_INTERVAL */
1093                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1094                         0x000c000c, /* EMC_MRS_WAIT_CNT */
1095                         0x000c000c, /* EMC_MRS_WAIT_CNT2 */
1096                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1097                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1098                         0x00000000, /* EMC_CTT */
1099                         0x00000000, /* EMC_CTT_DURATION */
1100                         0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
1101                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1102                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1103                         0x01000003, /* MC_EMEM_ARB_CFG */
1104                         0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1105                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1106                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1107                         0x00000005, /* MC_EMEM_ARB_TIMING_RC */
1108                         0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
1109                         0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
1110                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1111                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1112                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1113                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1114                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
1115                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1116                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1117                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
1118                         0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
1119                         0x73840a06, /* MC_EMEM_ARB_MISC0 */
1120                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1121                 },
1122                 {
1123                         0x00000000, /* EMC_CDB_CNTL_1 */
1124                         0x00000004, /* EMC_FBIO_CFG6 */
1125                         0x00000007, /* EMC_QUSE */
1126                         0x00000004, /* EMC_EINPUT */
1127                         0x00000004, /* EMC_EINPUT_DURATION */
1128                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
1129                         0x00000009, /* EMC_QSAFE */
1130                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1131                         0x0000000d, /* EMC_RDV */
1132                         0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
1133                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
1134                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
1135                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1136                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
1137                         0x00000808, /* EMC_XM2CLKPADCTRL2 */
1138                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1139                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1140                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
1141                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
1142                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
1143                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
1144                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
1145                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
1146                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
1147                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1148                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1149                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1150                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1151                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1152                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1153                 },
1154                 {
1155                         0x00000000, /* EMC_CDB_CNTL_1 */
1156                         0x00000004, /* EMC_FBIO_CFG6 */
1157                         0x00000007, /* EMC_QUSE */
1158                         0x00000004, /* EMC_EINPUT */
1159                         0x00000004, /* EMC_EINPUT_DURATION */
1160                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
1161                         0x00000009, /* EMC_QSAFE */
1162                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1163                         0x0000000d, /* EMC_RDV */
1164                         0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
1165                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
1166                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
1167                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
1168                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
1169                         0x00000808, /* EMC_XM2CLKPADCTRL2 */
1170                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1171                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
1172                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
1173                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
1174                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
1175                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
1176                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
1177                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
1178                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
1179                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1180                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1181                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1182                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1183                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1184                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1185                 },
1186                 {
1187                         0x000000d0, /* MC_PTSA_GRANT_DECREMENT */
1188                         0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
1189                         0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
1190                         0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
1191                         0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1192                         0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */
1193                         0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */
1194                         0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1195                         0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
1196                         0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1197                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1198                 },
1199                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
1200                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1201                 0x7320000e, /* EMC_CFG */
1202                 0x80001221, /* Mode Register 0 */
1203                 0x80100003, /* Mode Register 1 */
1204                 0x80200008, /* Mode Register 2 */
1205                 0x00000000, /* Mode Register 4 */
1206                 3420,       /* expected dvfs latency (ns) */
1207         },
1208         {
1209                 0x41,       /* Rev 4.0.3 */
1210                 312000,     /* SDRAM frequency */
1211                 1000,       /* min voltage */
1212                 "pll_c",    /* clock source id */
1213                 0x24000002, /* CLK_SOURCE_EMC */
1214                 99,         /* number of burst_regs */
1215                 30,         /* number of trim_regs (each channel) */
1216                 11,         /* number of up_down_regs */
1217                 {
1218                         0x0000000e, /* EMC_RC */
1219                         0x00000050, /* EMC_RFC */
1220                         0x00000000, /* EMC_RFC_SLR */
1221                         0x00000009, /* EMC_RAS */
1222                         0x00000003, /* EMC_RP */
1223                         0x00000004, /* EMC_R2W */
1224                         0x00000008, /* EMC_W2R */
1225                         0x00000002, /* EMC_R2P */
1226                         0x00000009, /* EMC_W2P */
1227                         0x00000003, /* EMC_RD_RCD */
1228                         0x00000003, /* EMC_WR_RCD */
1229                         0x00000002, /* EMC_RRD */
1230                         0x00000001, /* EMC_REXT */
1231                         0x00000000, /* EMC_WEXT */
1232                         0x00000004, /* EMC_WDV */
1233                         0x00000004, /* EMC_WDV_MASK */
1234                         0x00000007, /* EMC_IBDLY */
1235                         0x00080006, /* EMC_PUTERM_EXTRA */
1236                         0x00000000, /* EMC_CDB_CNTL_2 */
1237                         0x00000004, /* EMC_QRST */
1238                         0x0000000d, /* EMC_RDV_MASK */
1239                         0x00000945, /* EMC_REFRESH */
1240                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1241                         0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */
1242                         0x00000001, /* EMC_PDEX2WR */
1243                         0x00000008, /* EMC_PDEX2RD */
1244                         0x00000001, /* EMC_PCHG2PDEN */
1245                         0x00000000, /* EMC_ACT2PDEN */
1246                         0x0000004d, /* EMC_AR2PDEN */
1247                         0x0000000e, /* EMC_RW2PDEN */
1248                         0x00000055, /* EMC_TXSR */
1249                         0x00000200, /* EMC_TXSRDLL */
1250                         0x00000004, /* EMC_TCKE */
1251                         0x00000004, /* EMC_TCKESR */
1252                         0x00000004, /* EMC_TPD */
1253                         0x0000000d, /* EMC_TFAW */
1254                         0x00000000, /* EMC_TRPAB */
1255                         0x00000004, /* EMC_TCLKSTABLE */
1256                         0x00000005, /* EMC_TCLKSTOP */
1257                         0x00000986, /* EMC_TREFBW */
1258                         0x00000006, /* EMC_QUSE_EXTRA */
1259                         0x00000020, /* EMC_ODT_WRITE */
1260                         0x00000000, /* EMC_ODT_READ */
1261                         0x0000ba88, /* EMC_FBIO_CFG5 */
1262                         0x002c00a0, /* EMC_CFG_DIG_DLL */
1263                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1264                         0x00030000, /* EMC_DLL_XFORM_DQS4 */
1265                         0x00030000, /* EMC_DLL_XFORM_DQS5 */
1266                         0x00030000, /* EMC_DLL_XFORM_DQS6 */
1267                         0x00030000, /* EMC_DLL_XFORM_DQS7 */
1268                         0x00028000, /* EMC_DLL_XFORM_QUSE4 */
1269                         0x00028000, /* EMC_DLL_XFORM_QUSE5 */
1270                         0x00028000, /* EMC_DLL_XFORM_QUSE6 */
1271                         0x00028000, /* EMC_DLL_XFORM_QUSE7 */
1272                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1273                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1274                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1275                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1276                         0x001112a0, /* EMC_XM2CMDPADCTRL */
1277                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
1278                         0x0001013d, /* EMC_XM2DQSPADCTRL2 */
1279                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1280                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
1281                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
1282                         0x03035504, /* EMC_XM2VTTGENPADCTRL */
1283                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
1284                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1285                         0x00000000, /* EMC_TXDSRVTTGEN */
1286                         0x02000000, /* EMC_FBIO_SPARE */
1287                         0x00000802, /* EMC_CTT_TERM_CTRL */
1288                         0x00020000, /* EMC_ZCAL_INTERVAL */
1289                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1290                         0x0171000c, /* EMC_MRS_WAIT_CNT */
1291                         0x0171000c, /* EMC_MRS_WAIT_CNT2 */
1292                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1293                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1294                         0x00000000, /* EMC_CTT */
1295                         0x00000000, /* EMC_CTT_DURATION */
1296                         0x80001395, /* EMC_DYN_SELF_REF_CONTROL */
1297                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1298                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1299                         0x0b000004, /* MC_EMEM_ARB_CFG */
1300                         0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1301                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1302                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
1303                         0x00000007, /* MC_EMEM_ARB_TIMING_RC */
1304                         0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
1305                         0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
1306                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1307                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1308                         0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1309                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1310                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1311                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
1312                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1313                         0x06040202, /* MC_EMEM_ARB_DA_TURNS */
1314                         0x000b0607, /* MC_EMEM_ARB_DA_COVERS */
1315                         0x76e50f08, /* MC_EMEM_ARB_MISC0 */
1316                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1317                 },
1318                 {
1319                         0x00000000, /* EMC_CDB_CNTL_1 */
1320                         0x00000004, /* EMC_FBIO_CFG6 */
1321                         0x00000007, /* EMC_QUSE */
1322                         0x00000005, /* EMC_EINPUT */
1323                         0x00000004, /* EMC_EINPUT_DURATION */
1324                         0x00030000, /* EMC_DLL_XFORM_DQS0 */
1325                         0x0000000b, /* EMC_QSAFE */
1326                         0x00028000, /* EMC_DLL_XFORM_QUSE0 */
1327                         0x0000000d, /* EMC_RDV */
1328                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
1329                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
1330                         0x00030000, /* EMC_DLL_XFORM_DQ0 */
1331                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1332                         0x00024000, /* EMC_DLL_XFORM_ADDR0 */
1333                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
1334                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1335                         0x00024000, /* EMC_DLL_XFORM_ADDR1 */
1336                         0x00024000, /* EMC_DLL_XFORM_ADDR2 */
1337                         0x00030000, /* EMC_DLL_XFORM_DQS1 */
1338                         0x00030000, /* EMC_DLL_XFORM_DQS2 */
1339                         0x00030000, /* EMC_DLL_XFORM_DQS3 */
1340                         0x00030000, /* EMC_DLL_XFORM_DQ1 */
1341                         0x00030000, /* EMC_DLL_XFORM_DQ2 */
1342                         0x00030000, /* EMC_DLL_XFORM_DQ3 */
1343                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1344                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1345                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1346                         0x00028000, /* EMC_DLL_XFORM_QUSE1 */
1347                         0x00028000, /* EMC_DLL_XFORM_QUSE2 */
1348                         0x00028000, /* EMC_DLL_XFORM_QUSE3 */
1349                 },
1350                 {
1351                         0x00000000, /* EMC_CDB_CNTL_1 */
1352                         0x00000004, /* EMC_FBIO_CFG6 */
1353                         0x00000007, /* EMC_QUSE */
1354                         0x00000005, /* EMC_EINPUT */
1355                         0x00000004, /* EMC_EINPUT_DURATION */
1356                         0x00030000, /* EMC_DLL_XFORM_DQS0 */
1357                         0x0000000b, /* EMC_QSAFE */
1358                         0x00028000, /* EMC_DLL_XFORM_QUSE0 */
1359                         0x0000000d, /* EMC_RDV */
1360                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
1361                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
1362                         0x00030000, /* EMC_DLL_XFORM_DQ0 */
1363                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
1364                         0x00024000, /* EMC_DLL_XFORM_ADDR0 */
1365                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
1366                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1367                         0x00024000, /* EMC_DLL_XFORM_ADDR1 */
1368                         0x00024000, /* EMC_DLL_XFORM_ADDR2 */
1369                         0x00030000, /* EMC_DLL_XFORM_DQS1 */
1370                         0x00030000, /* EMC_DLL_XFORM_DQS2 */
1371                         0x00030000, /* EMC_DLL_XFORM_DQS3 */
1372                         0x00030000, /* EMC_DLL_XFORM_DQ1 */
1373                         0x00030000, /* EMC_DLL_XFORM_DQ2 */
1374                         0x00030000, /* EMC_DLL_XFORM_DQ3 */
1375                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1376                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1377                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1378                         0x00028000, /* EMC_DLL_XFORM_QUSE1 */
1379                         0x00028000, /* EMC_DLL_XFORM_QUSE2 */
1380                         0x00028000, /* EMC_DLL_XFORM_QUSE3 */
1381                 },
1382                 {
1383                         0x00000140, /* MC_PTSA_GRANT_DECREMENT */
1384                         0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */
1385                         0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */
1386                         0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */
1387                         0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1388                         0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */
1389                         0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */
1390                         0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1391                         0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */
1392                         0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1393                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1394                 },
1395                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
1396                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1397                 0x5320000e, /* EMC_CFG */
1398                 0x80000321, /* Mode Register 0 */
1399                 0x80100002, /* Mode Register 1 */
1400                 0x80200000, /* Mode Register 2 */
1401                 0x00000000, /* Mode Register 4 */
1402                 2680,       /* expected dvfs latency (ns) */
1403         },
1404         {
1405                 0x41,       /* Rev 4.0.3 */
1406                 408000,     /* SDRAM frequency */
1407                 1000,       /* min voltage */
1408                 "pll_p",    /* clock source id */
1409                 0x40000000, /* CLK_SOURCE_EMC */
1410                 99,         /* number of burst_regs */
1411                 30,         /* number of trim_regs (each channel) */
1412                 11,         /* number of up_down_regs */
1413                 {
1414                         0x00000012, /* EMC_RC */
1415                         0x00000069, /* EMC_RFC */
1416                         0x00000000, /* EMC_RFC_SLR */
1417                         0x0000000d, /* EMC_RAS */
1418                         0x00000004, /* EMC_RP */
1419                         0x00000005, /* EMC_R2W */
1420                         0x00000009, /* EMC_W2R */
1421                         0x00000002, /* EMC_R2P */
1422                         0x0000000c, /* EMC_W2P */
1423                         0x00000004, /* EMC_RD_RCD */
1424                         0x00000004, /* EMC_WR_RCD */
1425                         0x00000002, /* EMC_RRD */
1426                         0x00000001, /* EMC_REXT */
1427                         0x00000000, /* EMC_WEXT */
1428                         0x00000004, /* EMC_WDV */
1429                         0x00000004, /* EMC_WDV_MASK */
1430                         0x00000007, /* EMC_IBDLY */
1431                         0x00080006, /* EMC_PUTERM_EXTRA */
1432                         0x00000000, /* EMC_CDB_CNTL_2 */
1433                         0x00000004, /* EMC_QRST */
1434                         0x0000000e, /* EMC_RDV_MASK */
1435                         0x00000c2f, /* EMC_REFRESH */
1436                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1437                         0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
1438                         0x00000001, /* EMC_PDEX2WR */
1439                         0x00000008, /* EMC_PDEX2RD */
1440                         0x00000001, /* EMC_PCHG2PDEN */
1441                         0x00000000, /* EMC_ACT2PDEN */
1442                         0x00000066, /* EMC_AR2PDEN */
1443                         0x00000011, /* EMC_RW2PDEN */
1444                         0x0000006f, /* EMC_TXSR */
1445                         0x00000200, /* EMC_TXSRDLL */
1446                         0x00000004, /* EMC_TCKE */
1447                         0x00000004, /* EMC_TCKESR */
1448                         0x00000004, /* EMC_TPD */
1449                         0x00000011, /* EMC_TFAW */
1450                         0x00000000, /* EMC_TRPAB */
1451                         0x00000004, /* EMC_TCLKSTABLE */
1452                         0x00000005, /* EMC_TCLKSTOP */
1453                         0x00000c70, /* EMC_TREFBW */
1454                         0x00000006, /* EMC_QUSE_EXTRA */
1455                         0x00000020, /* EMC_ODT_WRITE */
1456                         0x00000000, /* EMC_ODT_READ */
1457                         0x0000ba88, /* EMC_FBIO_CFG5 */
1458                         0x002c0080, /* EMC_CFG_DIG_DLL */
1459                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1460                         0x00018000, /* EMC_DLL_XFORM_DQS4 */
1461                         0x00018000, /* EMC_DLL_XFORM_DQS5 */
1462                         0x00018000, /* EMC_DLL_XFORM_DQS6 */
1463                         0x00018000, /* EMC_DLL_XFORM_DQS7 */
1464                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1465                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1466                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1467                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1468                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1469                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1470                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1471                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1472                         0x001112a0, /* EMC_XM2CMDPADCTRL */
1473                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
1474                         0x0001013d, /* EMC_XM2DQSPADCTRL2 */
1475                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1476                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
1477                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
1478                         0x03035504, /* EMC_XM2VTTGENPADCTRL */
1479                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
1480                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1481                         0x00000000, /* EMC_TXDSRVTTGEN */
1482                         0x02000000, /* EMC_FBIO_SPARE */
1483                         0x00000802, /* EMC_CTT_TERM_CTRL */
1484                         0x00020000, /* EMC_ZCAL_INTERVAL */
1485                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1486                         0x0158000c, /* EMC_MRS_WAIT_CNT */
1487                         0x0158000c, /* EMC_MRS_WAIT_CNT2 */
1488                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1489                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1490                         0x00000000, /* EMC_CTT */
1491                         0x00000000, /* EMC_CTT_DURATION */
1492                         0x80001944, /* EMC_DYN_SELF_REF_CONTROL */
1493                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1494                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1495                         0x02000006, /* MC_EMEM_ARB_CFG */
1496                         0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1497                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1498                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
1499                         0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
1500                         0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
1501                         0x00000008, /* MC_EMEM_ARB_TIMING_FAW */
1502                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1503                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1504                         0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1505                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1506                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1507                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
1508                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1509                         0x06040202, /* MC_EMEM_ARB_DA_TURNS */
1510                         0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
1511                         0x7547130b, /* MC_EMEM_ARB_MISC0 */
1512                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1513                 },
1514                 {
1515                         0x00000000, /* EMC_CDB_CNTL_1 */
1516                         0x00000004, /* EMC_FBIO_CFG6 */
1517                         0x00000007, /* EMC_QUSE */
1518                         0x00000005, /* EMC_EINPUT */
1519                         0x00000004, /* EMC_EINPUT_DURATION */
1520                         0x00018000, /* EMC_DLL_XFORM_DQS0 */
1521                         0x0000000c, /* EMC_QSAFE */
1522                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1523                         0x0000000e, /* EMC_RDV */
1524                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
1525                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
1526                         0x00020001, /* EMC_DLL_XFORM_DQ0 */
1527                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1528                         0x00000005, /* EMC_DLL_XFORM_ADDR0 */
1529                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
1530                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1531                         0x00000005, /* EMC_DLL_XFORM_ADDR1 */
1532                         0x00000005, /* EMC_DLL_XFORM_ADDR2 */
1533                         0x00018000, /* EMC_DLL_XFORM_DQS1 */
1534                         0x00018000, /* EMC_DLL_XFORM_DQS2 */
1535                         0x00018000, /* EMC_DLL_XFORM_DQS3 */
1536                         0x00020001, /* EMC_DLL_XFORM_DQ1 */
1537                         0x00020001, /* EMC_DLL_XFORM_DQ2 */
1538                         0x00020001, /* EMC_DLL_XFORM_DQ3 */
1539                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1540                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1541                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1542                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1543                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1544                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1545                 },
1546                 {
1547                         0x00000000, /* EMC_CDB_CNTL_1 */
1548                         0x00000004, /* EMC_FBIO_CFG6 */
1549                         0x00000007, /* EMC_QUSE */
1550                         0x00000005, /* EMC_EINPUT */
1551                         0x00000004, /* EMC_EINPUT_DURATION */
1552                         0x00018000, /* EMC_DLL_XFORM_DQS0 */
1553                         0x0000000c, /* EMC_QSAFE */
1554                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1555                         0x0000000e, /* EMC_RDV */
1556                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
1557                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
1558                         0x00020001, /* EMC_DLL_XFORM_DQ0 */
1559                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
1560                         0x00000005, /* EMC_DLL_XFORM_ADDR0 */
1561                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
1562                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1563                         0x00000005, /* EMC_DLL_XFORM_ADDR1 */
1564                         0x00000005, /* EMC_DLL_XFORM_ADDR2 */
1565                         0x00018000, /* EMC_DLL_XFORM_DQS1 */
1566                         0x00018000, /* EMC_DLL_XFORM_DQS2 */
1567                         0x00018000, /* EMC_DLL_XFORM_DQS3 */
1568                         0x00020001, /* EMC_DLL_XFORM_DQ1 */
1569                         0x00020001, /* EMC_DLL_XFORM_DQ2 */
1570                         0x00020001, /* EMC_DLL_XFORM_DQ3 */
1571                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1572                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1573                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1574                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1575                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1576                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1577                 },
1578                 {
1579                         0x000000d1, /* MC_PTSA_GRANT_DECREMENT */
1580                         0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */
1581                         0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */
1582                         0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */
1583                         0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1584                         0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */
1585                         0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */
1586                         0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1587                         0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */
1588                         0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1589                         0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1590                 },
1591                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
1592                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1593                 0x53200006, /* EMC_CFG */
1594                 0x80000731, /* Mode Register 0 */
1595                 0x80100002, /* Mode Register 1 */
1596                 0x80200008, /* Mode Register 2 */
1597                 0x00000000, /* Mode Register 4 */
1598                 1750,       /* expected dvfs latency (ns) */
1599         },
1600         {
1601                 0x41,       /* Rev 4.0.3 */
1602                 528000,     /* SDRAM frequency */
1603                 1100,       /* min voltage */
1604                 "pll_m",    /* clock source id */
1605                 0x80000000, /* CLK_SOURCE_EMC */
1606                 99,         /* number of burst_regs */
1607                 30,         /* number of trim_regs (each channel) */
1608                 11,         /* number of up_down_regs */
1609                 {
1610                         0x00000018, /* EMC_RC */
1611                         0x00000088, /* EMC_RFC */
1612                         0x00000000, /* EMC_RFC_SLR */
1613                         0x00000010, /* EMC_RAS */
1614                         0x00000006, /* EMC_RP */
1615                         0x00000004, /* EMC_R2W */
1616                         0x00000009, /* EMC_W2R */
1617                         0x00000002, /* EMC_R2P */
1618                         0x0000000d, /* EMC_W2P */
1619                         0x00000006, /* EMC_RD_RCD */
1620                         0x00000006, /* EMC_WR_RCD */
1621                         0x00000002, /* EMC_RRD */
1622                         0x00000001, /* EMC_REXT */
1623                         0x00000000, /* EMC_WEXT */
1624                         0x00000005, /* EMC_WDV */
1625                         0x00000005, /* EMC_WDV_MASK */
1626                         0x00000009, /* EMC_IBDLY */
1627                         0x00090007, /* EMC_PUTERM_EXTRA */
1628                         0x00000000, /* EMC_CDB_CNTL_2 */
1629                         0x00000007, /* EMC_QRST */
1630                         0x00000010, /* EMC_RDV_MASK */
1631                         0x00000fd8, /* EMC_REFRESH */
1632                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1633                         0x000003f6, /* EMC_PRE_REFRESH_REQ_CNT */
1634                         0x00000002, /* EMC_PDEX2WR */
1635                         0x0000000b, /* EMC_PDEX2RD */
1636                         0x00000001, /* EMC_PCHG2PDEN */
1637                         0x00000000, /* EMC_ACT2PDEN */
1638                         0x00000085, /* EMC_AR2PDEN */
1639                         0x00000012, /* EMC_RW2PDEN */
1640                         0x0000008f, /* EMC_TXSR */
1641                         0x00000200, /* EMC_TXSRDLL */
1642                         0x00000004, /* EMC_TCKE */
1643                         0x00000004, /* EMC_TCKESR */
1644                         0x00000004, /* EMC_TPD */
1645                         0x00000016, /* EMC_TFAW */
1646                         0x00000000, /* EMC_TRPAB */
1647                         0x00000005, /* EMC_TCLKSTABLE */
1648                         0x00000006, /* EMC_TCLKSTOP */
1649                         0x00001019, /* EMC_TREFBW */
1650                         0x00000008, /* EMC_QUSE_EXTRA */
1651                         0x00000020, /* EMC_ODT_WRITE */
1652                         0x00000000, /* EMC_ODT_READ */
1653                         0x0000ba88, /* EMC_FBIO_CFG5 */
1654                         0xf0120091, /* EMC_CFG_DIG_DLL */
1655                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1656                         0x0000000a, /* EMC_DLL_XFORM_DQS4 */
1657                         0x0000000a, /* EMC_DLL_XFORM_DQS5 */
1658                         0x0000000a, /* EMC_DLL_XFORM_DQS6 */
1659                         0x0000000a, /* EMC_DLL_XFORM_DQS7 */
1660                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1661                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1662                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1663                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1664                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1665                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1666                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1667                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1668                         0x001112a0, /* EMC_XM2CMDPADCTRL */
1669                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
1670                         0x0000013d, /* EMC_XM2DQSPADCTRL2 */
1671                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1672                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
1673                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
1674                         0x07077504, /* EMC_XM2VTTGENPADCTRL */
1675                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
1676                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1677                         0x00000000, /* EMC_TXDSRVTTGEN */
1678                         0x02000000, /* EMC_FBIO_SPARE */
1679                         0x00000802, /* EMC_CTT_TERM_CTRL */
1680                         0x00020000, /* EMC_ZCAL_INTERVAL */
1681                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1682                         0x0139000f, /* EMC_MRS_WAIT_CNT */
1683                         0x0139000f, /* EMC_MRS_WAIT_CNT2 */
1684                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1685                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1686                         0x00000000, /* EMC_CTT */
1687                         0x00000000, /* EMC_CTT_DURATION */
1688                         0x80002066, /* EMC_DYN_SELF_REF_CONTROL */
1689                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1690                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1691                         0x0f000007, /* MC_EMEM_ARB_CFG */
1692                         0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1693                         0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
1694                         0x00000003, /* MC_EMEM_ARB_TIMING_RP */
1695                         0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
1696                         0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
1697                         0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
1698                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1699                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1700                         0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1701                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1702                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1703                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
1704                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1705                         0x06040202, /* MC_EMEM_ARB_DA_TURNS */
1706                         0x0010090c, /* MC_EMEM_ARB_DA_COVERS */
1707                         0x7428180d, /* MC_EMEM_ARB_MISC0 */
1708                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1709                 },
1710                 {
1711                         0x00000000, /* EMC_CDB_CNTL_1 */
1712                         0x00000006, /* EMC_FBIO_CFG6 */
1713                         0x00000009, /* EMC_QUSE */
1714                         0x00000007, /* EMC_EINPUT */
1715                         0x00000004, /* EMC_EINPUT_DURATION */
1716                         0x0000000a, /* EMC_DLL_XFORM_DQS0 */
1717                         0x0000000c, /* EMC_QSAFE */
1718                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1719                         0x00000010, /* EMC_RDV */
1720                         0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
1721                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
1722                         0x0000000a, /* EMC_DLL_XFORM_DQ0 */
1723                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1724                         0x00010000, /* EMC_DLL_XFORM_ADDR0 */
1725                         0x00000909, /* EMC_XM2CLKPADCTRL2 */
1726                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1727                         0x00010000, /* EMC_DLL_XFORM_ADDR1 */
1728                         0x00010000, /* EMC_DLL_XFORM_ADDR2 */
1729                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
1730                         0x0000000a, /* EMC_DLL_XFORM_DQS2 */
1731                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
1732                         0x0000000a, /* EMC_DLL_XFORM_DQ1 */
1733                         0x0000000a, /* EMC_DLL_XFORM_DQ2 */
1734                         0x0000000a, /* EMC_DLL_XFORM_DQ3 */
1735                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1736                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1737                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1738                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1739                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1740                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1741                 },
1742                 {
1743                         0x00000000, /* EMC_CDB_CNTL_1 */
1744                         0x00000006, /* EMC_FBIO_CFG6 */
1745                         0x00000009, /* EMC_QUSE */
1746                         0x00000007, /* EMC_EINPUT */
1747                         0x00000004, /* EMC_EINPUT_DURATION */
1748                         0x0000000a, /* EMC_DLL_XFORM_DQS0 */
1749                         0x0000000c, /* EMC_QSAFE */
1750                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1751                         0x00000010, /* EMC_RDV */
1752                         0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
1753                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
1754                         0x0000000a, /* EMC_DLL_XFORM_DQ0 */
1755                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
1756                         0x00010000, /* EMC_DLL_XFORM_ADDR0 */
1757                         0x00000909, /* EMC_XM2CLKPADCTRL2 */
1758                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1759                         0x00010000, /* EMC_DLL_XFORM_ADDR1 */
1760                         0x00010000, /* EMC_DLL_XFORM_ADDR2 */
1761                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
1762                         0x0000000a, /* EMC_DLL_XFORM_DQS2 */
1763                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
1764                         0x0000000a, /* EMC_DLL_XFORM_DQ1 */
1765                         0x0000000a, /* EMC_DLL_XFORM_DQ2 */
1766                         0x0000000a, /* EMC_DLL_XFORM_DQ3 */
1767                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1768                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1769                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1770                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1771                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1772                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1773                 },
1774                 {
1775                         0x0000010e, /* MC_PTSA_GRANT_DECREMENT */
1776                         0x000d000d, /* MC_LATENCY_ALLOWANCE_G2_0 */
1777                         0x000d000f, /* MC_LATENCY_ALLOWANCE_G2_1 */
1778                         0x00100012, /* MC_LATENCY_ALLOWANCE_NV_0 */
1779                         0x00000012, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1780                         0x00120012, /* MC_LATENCY_ALLOWANCE_NV_2 */
1781                         0x00180012, /* MC_LATENCY_ALLOWANCE_NV_1 */
1782                         0x00000018, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1783                         0x00180018, /* MC_LATENCY_ALLOWANCE_NV3 */
1784                         0x00a3004d, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1785                         0x00a300a3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1786                 },
1787                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
1788                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1789                 0x73100004, /* EMC_CFG */
1790                 0x80000941, /* Mode Register 0 */
1791                 0x80100002, /* Mode Register 1 */
1792                 0x80200008, /* Mode Register 2 */
1793                 0x00000000, /* Mode Register 4 */
1794                 1440,       /* expected dvfs latency (ns) */
1795         },
1796         {
1797                 0x41,       /* Rev 4.0.3 */
1798                 624000,     /* SDRAM frequency */
1799                 1100,       /* min voltage */
1800                 "pll_c",    /* clock source id */
1801                 0x24000000, /* CLK_SOURCE_EMC */
1802                 99,         /* number of burst_regs */
1803                 30,         /* number of trim_regs (each channel) */
1804                 11,         /* number of up_down_regs */
1805                 {
1806                         0x0000001d, /* EMC_RC */
1807                         0x000000a1, /* EMC_RFC */
1808                         0x00000000, /* EMC_RFC_SLR */
1809                         0x00000014, /* EMC_RAS */
1810                         0x00000007, /* EMC_RP */
1811                         0x00000007, /* EMC_R2W */
1812                         0x0000000b, /* EMC_W2R */
1813                         0x00000003, /* EMC_R2P */
1814                         0x00000010, /* EMC_W2P */
1815                         0x00000007, /* EMC_RD_RCD */
1816                         0x00000007, /* EMC_WR_RCD */
1817                         0x00000002, /* EMC_RRD */
1818                         0x00000001, /* EMC_REXT */
1819                         0x00000000, /* EMC_WEXT */
1820                         0x00000005, /* EMC_WDV */
1821                         0x00000005, /* EMC_WDV_MASK */
1822                         0x0000000a, /* EMC_IBDLY */
1823                         0x000c000a, /* EMC_PUTERM_EXTRA */
1824                         0x00000000, /* EMC_CDB_CNTL_2 */
1825                         0x00000007, /* EMC_QRST */
1826                         0x00000012, /* EMC_RDV_MASK */
1827                         0x000012c4, /* EMC_REFRESH */
1828                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1829                         0x000004b1, /* EMC_PRE_REFRESH_REQ_CNT */
1830                         0x00000002, /* EMC_PDEX2WR */
1831                         0x0000000d, /* EMC_PDEX2RD */
1832                         0x00000001, /* EMC_PCHG2PDEN */
1833                         0x00000000, /* EMC_ACT2PDEN */
1834                         0x0000009c, /* EMC_AR2PDEN */
1835                         0x00000015, /* EMC_RW2PDEN */
1836                         0x000000a9, /* EMC_TXSR */
1837                         0x00000200, /* EMC_TXSRDLL */
1838                         0x00000005, /* EMC_TCKE */
1839                         0x00000005, /* EMC_TCKESR */
1840                         0x00000005, /* EMC_TPD */
1841                         0x00000019, /* EMC_TFAW */
1842                         0x00000000, /* EMC_TRPAB */
1843                         0x00000006, /* EMC_TCLKSTABLE */
1844                         0x00000007, /* EMC_TCLKSTOP */
1845                         0x00001305, /* EMC_TREFBW */
1846                         0x00000009, /* EMC_QUSE_EXTRA */
1847                         0x00000020, /* EMC_ODT_WRITE */
1848                         0x00000000, /* EMC_ODT_READ */
1849                         0x0000ba88, /* EMC_FBIO_CFG5 */
1850                         0xf00d0191, /* EMC_CFG_DIG_DLL */
1851                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1852                         0x007fc00b, /* EMC_DLL_XFORM_DQS4 */
1853                         0x007fc00b, /* EMC_DLL_XFORM_DQS5 */
1854                         0x007fc00b, /* EMC_DLL_XFORM_DQS6 */
1855                         0x007fc00b, /* EMC_DLL_XFORM_DQS7 */
1856                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1857                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1858                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1859                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1860                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1861                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1862                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1863                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1864                         0x001112a0, /* EMC_XM2CMDPADCTRL */
1865                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
1866                         0x0000013d, /* EMC_XM2DQSPADCTRL2 */
1867                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1868                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
1869                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
1870                         0x07077504, /* EMC_XM2VTTGENPADCTRL */
1871                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
1872                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
1873                         0x00000000, /* EMC_TXDSRVTTGEN */
1874                         0x02000000, /* EMC_FBIO_SPARE */
1875                         0x00000802, /* EMC_CTT_TERM_CTRL */
1876                         0x00020000, /* EMC_ZCAL_INTERVAL */
1877                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1878                         0x0122000c, /* EMC_MRS_WAIT_CNT */
1879                         0x0122000c, /* EMC_MRS_WAIT_CNT2 */
1880                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
1881                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
1882                         0x00000000, /* EMC_CTT */
1883                         0x00000000, /* EMC_CTT_DURATION */
1884                         0x8000261a, /* EMC_DYN_SELF_REF_CONTROL */
1885                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
1886                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
1887                         0x06000009, /* MC_EMEM_ARB_CFG */
1888                         0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1889                         0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
1890                         0x00000004, /* MC_EMEM_ARB_TIMING_RP */
1891                         0x0000000f, /* MC_EMEM_ARB_TIMING_RC */
1892                         0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
1893                         0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */
1894                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1895                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1896                         0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1897                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1898                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1899                         0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
1900                         0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
1901                         0x07050202, /* MC_EMEM_ARB_DA_TURNS */
1902                         0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */
1903                         0x736a1d10, /* MC_EMEM_ARB_MISC0 */
1904                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1905                 },
1906                 {
1907                         0x00000000, /* EMC_CDB_CNTL_1 */
1908                         0x00000006, /* EMC_FBIO_CFG6 */
1909                         0x0000000a, /* EMC_QUSE */
1910                         0x00000008, /* EMC_EINPUT */
1911                         0x00000004, /* EMC_EINPUT_DURATION */
1912                         0x007fc00b, /* EMC_DLL_XFORM_DQS0 */
1913                         0x0000000c, /* EMC_QSAFE */
1914                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1915                         0x00000012, /* EMC_RDV */
1916                         0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
1917                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
1918                         0x00000009, /* EMC_DLL_XFORM_DQ0 */
1919                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1920                         0x007f400e, /* EMC_DLL_XFORM_ADDR0 */
1921                         0x00000909, /* EMC_XM2CLKPADCTRL2 */
1922                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1923                         0x007f400e, /* EMC_DLL_XFORM_ADDR1 */
1924                         0x007f400e, /* EMC_DLL_XFORM_ADDR2 */
1925                         0x007fc00b, /* EMC_DLL_XFORM_DQS1 */
1926                         0x007fc00b, /* EMC_DLL_XFORM_DQS2 */
1927                         0x007fc00b, /* EMC_DLL_XFORM_DQS3 */
1928                         0x00000009, /* EMC_DLL_XFORM_DQ1 */
1929                         0x00000009, /* EMC_DLL_XFORM_DQ2 */
1930                         0x00000009, /* EMC_DLL_XFORM_DQ3 */
1931                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1932                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1933                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1934                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1935                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1936                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1937                 },
1938                 {
1939                         0x00000000, /* EMC_CDB_CNTL_1 */
1940                         0x00000006, /* EMC_FBIO_CFG6 */
1941                         0x0000000a, /* EMC_QUSE */
1942                         0x00000008, /* EMC_EINPUT */
1943                         0x00000004, /* EMC_EINPUT_DURATION */
1944                         0x007fc00b, /* EMC_DLL_XFORM_DQS0 */
1945                         0x0000000c, /* EMC_QSAFE */
1946                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1947                         0x00000012, /* EMC_RDV */
1948                         0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
1949                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
1950                         0x00000009, /* EMC_DLL_XFORM_DQ0 */
1951                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
1952                         0x007f400e, /* EMC_DLL_XFORM_ADDR0 */
1953                         0x00000909, /* EMC_XM2CLKPADCTRL2 */
1954                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1955                         0x007f400e, /* EMC_DLL_XFORM_ADDR1 */
1956                         0x007f400e, /* EMC_DLL_XFORM_ADDR2 */
1957                         0x007fc00b, /* EMC_DLL_XFORM_DQS1 */
1958                         0x007fc00b, /* EMC_DLL_XFORM_DQS2 */
1959                         0x007fc00b, /* EMC_DLL_XFORM_DQS3 */
1960                         0x00000009, /* EMC_DLL_XFORM_DQ1 */
1961                         0x00000009, /* EMC_DLL_XFORM_DQ2 */
1962                         0x00000009, /* EMC_DLL_XFORM_DQ3 */
1963                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1964                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1965                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1966                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1967                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1968                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1969                 },
1970                 {
1971                         0x0000013f, /* MC_PTSA_GRANT_DECREMENT */
1972                         0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */
1973                         0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */
1974                         0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */
1975                         0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
1976                         0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */
1977                         0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */
1978                         0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */
1979                         0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */
1980                         0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */
1981                         0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */
1982                 },
1983                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
1984                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1985                 0x53200000, /* EMC_CFG */
1986                 0x80000b61, /* Mode Register 0 */
1987                 0x80100002, /* Mode Register 1 */
1988                 0x80200010, /* Mode Register 2 */
1989                 0x00000000, /* Mode Register 4 */
1990                 1440,       /* expected dvfs latency (ns) */
1991         },
1992         {
1993                 0x41,       /* Rev 4.0.3 */
1994                 792000,     /* SDRAM frequency */
1995                 1100,       /* min voltage */
1996                 "pll_m",    /* clock source id */
1997                 0x80000000, /* CLK_SOURCE_EMC */
1998                 99,         /* number of burst_regs */
1999                 30,         /* number of trim_regs (each channel) */
2000                 11,         /* number of up_down_regs */
2001                 {
2002                         0x00000024, /* EMC_RC */
2003                         0x000000cd, /* EMC_RFC */
2004                         0x00000000, /* EMC_RFC_SLR */
2005                         0x00000019, /* EMC_RAS */
2006                         0x0000000a, /* EMC_RP */
2007                         0x00000009, /* EMC_R2W */
2008                         0x0000000d, /* EMC_W2R */
2009                         0x00000004, /* EMC_R2P */
2010                         0x00000013, /* EMC_W2P */
2011                         0x0000000a, /* EMC_RD_RCD */
2012                         0x0000000a, /* EMC_WR_RCD */
2013                         0x00000003, /* EMC_RRD */
2014                         0x00000001, /* EMC_REXT */
2015                         0x00000000, /* EMC_WEXT */
2016                         0x00000006, /* EMC_WDV */
2017                         0x00000006, /* EMC_WDV_MASK */
2018                         0x0000000b, /* EMC_IBDLY */
2019                         0x000d000a, /* EMC_PUTERM_EXTRA */
2020                         0x00000000, /* EMC_CDB_CNTL_2 */
2021                         0x00000008, /* EMC_QRST */
2022                         0x00000014, /* EMC_RDV_MASK */
2023                         0x000017e4, /* EMC_REFRESH */
2024                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2025                         0x000005f9, /* EMC_PRE_REFRESH_REQ_CNT */
2026                         0x00000003, /* EMC_PDEX2WR */
2027                         0x00000012, /* EMC_PDEX2RD */
2028                         0x00000001, /* EMC_PCHG2PDEN */
2029                         0x00000000, /* EMC_ACT2PDEN */
2030                         0x000000c6, /* EMC_AR2PDEN */
2031                         0x00000018, /* EMC_RW2PDEN */
2032                         0x000000d6, /* EMC_TXSR */
2033                         0x00000200, /* EMC_TXSRDLL */
2034                         0x00000005, /* EMC_TCKE */
2035                         0x00000005, /* EMC_TCKESR */
2036                         0x00000005, /* EMC_TPD */
2037                         0x00000020, /* EMC_TFAW */
2038                         0x00000000, /* EMC_TRPAB */
2039                         0x00000007, /* EMC_TCLKSTABLE */
2040                         0x00000008, /* EMC_TCLKSTOP */
2041                         0x00001825, /* EMC_TREFBW */
2042                         0x0000000a, /* EMC_QUSE_EXTRA */
2043                         0x80000020, /* EMC_ODT_WRITE */
2044                         0x00000000, /* EMC_ODT_READ */
2045                         0x0000ba88, /* EMC_FBIO_CFG5 */
2046                         0xf0070191, /* EMC_CFG_DIG_DLL */
2047                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2048                         0x0000000a, /* EMC_DLL_XFORM_DQS4 */
2049                         0x0000000a, /* EMC_DLL_XFORM_DQS5 */
2050                         0x0000000a, /* EMC_DLL_XFORM_DQS6 */
2051                         0x0000000a, /* EMC_DLL_XFORM_DQS7 */
2052                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2053                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2054                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2055                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2056                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2057                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2058                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2059                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2060                         0x001112a0, /* EMC_XM2CMDPADCTRL */
2061                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
2062                         0x0000013d, /* EMC_XM2DQSPADCTRL2 */
2063                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2064                         0x77ffc084, /* EMC_XM2CLKPADCTRL */
2065                         0x81f1f508, /* EMC_XM2COMPPADCTRL */
2066                         0x07077704, /* EMC_XM2VTTGENPADCTRL */
2067                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
2068                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
2069                         0x00000000, /* EMC_TXDSRVTTGEN */
2070                         0x02000000, /* EMC_FBIO_SPARE */
2071                         0x00000802, /* EMC_CTT_TERM_CTRL */
2072                         0x00020000, /* EMC_ZCAL_INTERVAL */
2073                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
2074                         0x00f8000f, /* EMC_MRS_WAIT_CNT */
2075                         0x00f8000f, /* EMC_MRS_WAIT_CNT2 */
2076                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
2077                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
2078                         0x00000000, /* EMC_CTT */
2079                         0x00000000, /* EMC_CTT_DURATION */
2080                         0x80003018, /* EMC_DYN_SELF_REF_CONTROL */
2081                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
2082                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
2083                         0x0e00000b, /* MC_EMEM_ARB_CFG */
2084                         0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2085                         0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
2086                         0x00000005, /* MC_EMEM_ARB_TIMING_RP */
2087                         0x00000013, /* MC_EMEM_ARB_TIMING_RC */
2088                         0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
2089                         0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
2090                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
2091                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2092                         0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2093                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2094                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2095                         0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
2096                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
2097                         0x08060202, /* MC_EMEM_ARB_DA_TURNS */
2098                         0x00170e13, /* MC_EMEM_ARB_DA_COVERS */
2099                         0x734c2414, /* MC_EMEM_ARB_MISC0 */
2100                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2101                 },
2102                 {
2103                         0x00000000, /* EMC_CDB_CNTL_1 */
2104                         0x00000006, /* EMC_FBIO_CFG6 */
2105                         0x0000000b, /* EMC_QUSE */
2106                         0x00000008, /* EMC_EINPUT */
2107                         0x00000006, /* EMC_EINPUT_DURATION */
2108                         0x0000000a, /* EMC_DLL_XFORM_DQS0 */
2109                         0x0000000d, /* EMC_QSAFE */
2110                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2111                         0x00000014, /* EMC_RDV */
2112                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
2113                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
2114                         0x0000000a, /* EMC_DLL_XFORM_DQ0 */
2115                         0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
2116                         0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
2117                         0x00000b0b, /* EMC_XM2CLKPADCTRL2 */
2118                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2119                         0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
2120                         0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
2121                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
2122                         0x0000000a, /* EMC_DLL_XFORM_DQS2 */
2123                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
2124                         0x0000000a, /* EMC_DLL_XFORM_DQ1 */
2125                         0x0000000a, /* EMC_DLL_XFORM_DQ2 */
2126                         0x0000000a, /* EMC_DLL_XFORM_DQ3 */
2127                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2128                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2129                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2130                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2131                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2132                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2133                 },
2134                 {
2135                         0x00000000, /* EMC_CDB_CNTL_1 */
2136                         0x00000006, /* EMC_FBIO_CFG6 */
2137                         0x0000000b, /* EMC_QUSE */
2138                         0x00000008, /* EMC_EINPUT */
2139                         0x00000006, /* EMC_EINPUT_DURATION */
2140                         0x0000000a, /* EMC_DLL_XFORM_DQS0 */
2141                         0x0000000d, /* EMC_QSAFE */
2142                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2143                         0x00000014, /* EMC_RDV */
2144                         0x00249249, /* EMC_XM2DQSPADCTRL4 */
2145                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
2146                         0x0000000a, /* EMC_DLL_XFORM_DQ0 */
2147                         0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
2148                         0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
2149                         0x00000b0b, /* EMC_XM2CLKPADCTRL2 */
2150                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2151                         0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
2152                         0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
2153                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
2154                         0x0000000a, /* EMC_DLL_XFORM_DQS2 */
2155                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
2156                         0x0000000a, /* EMC_DLL_XFORM_DQ1 */
2157                         0x0000000a, /* EMC_DLL_XFORM_DQ2 */
2158                         0x0000000a, /* EMC_DLL_XFORM_DQ3 */
2159                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2160                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2161                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2162                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2163                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2164                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2165                 },
2166                 {
2167                         0x00000196, /* MC_PTSA_GRANT_DECREMENT */
2168                         0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */
2169                         0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */
2170                         0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */
2171                         0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */
2172                         0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */
2173                         0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */
2174                         0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */
2175                         0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */
2176                         0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */
2177                         0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */
2178                 },
2179                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
2180                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2181                 0x73000000, /* EMC_CFG */
2182                 0x80000d71, /* Mode Register 0 */
2183                 0x80100002, /* Mode Register 1 */
2184                 0x80200218, /* Mode Register 2 */
2185                 0x00000000, /* Mode Register 4 */
2186                 1200,       /* expected dvfs latency (ns) */
2187         },
2188 };
2189
2190 static struct tegra11_emc_table e1611_h5tc4g63afr_rda_T40T_table[] = {
2191         {
2192                 0x41,       /* Rev 4.0.3 */
2193                 12750,      /* SDRAM frequency */
2194                 900,       /* min voltage */
2195                 "pll_p",    /* clock source id */
2196                 0x4000003e, /* CLK_SOURCE_EMC */
2197                 99,         /* number of burst_regs */
2198                 30,         /* number of trim_regs (each channel) */
2199                 11,         /* number of up_down_regs */
2200                 {
2201                         0x00000000, /* EMC_RC */
2202                         0x00000003, /* EMC_RFC */
2203                         0x00000000, /* EMC_RFC_SLR */
2204                         0x00000000, /* EMC_RAS */
2205                         0x00000000, /* EMC_RP */
2206                         0x00000004, /* EMC_R2W */
2207                         0x0000000a, /* EMC_W2R */
2208                         0x00000003, /* EMC_R2P */
2209                         0x0000000b, /* EMC_W2P */
2210                         0x00000000, /* EMC_RD_RCD */
2211                         0x00000000, /* EMC_WR_RCD */
2212                         0x00000003, /* EMC_RRD */
2213                         0x00000001, /* EMC_REXT */
2214                         0x00000000, /* EMC_WEXT */
2215                         0x00000005, /* EMC_WDV */
2216                         0x00000005, /* EMC_WDV_MASK */
2217                         0x00000006, /* EMC_IBDLY */
2218                         0x00010000, /* EMC_PUTERM_EXTRA */
2219                         0x00000000, /* EMC_CDB_CNTL_2 */
2220                         0x00000004, /* EMC_QRST */
2221                         0x0000000d, /* EMC_RDV_MASK */
2222                         0x00000060, /* EMC_REFRESH */
2223                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2224                         0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
2225                         0x00000002, /* EMC_PDEX2WR */
2226                         0x00000002, /* EMC_PDEX2RD */
2227                         0x00000001, /* EMC_PCHG2PDEN */
2228                         0x00000000, /* EMC_ACT2PDEN */
2229                         0x00000007, /* EMC_AR2PDEN */
2230                         0x0000000f, /* EMC_RW2PDEN */
2231                         0x00000005, /* EMC_TXSR */
2232                         0x00000005, /* EMC_TXSRDLL */
2233                         0x00000004, /* EMC_TCKE */
2234                         0x00000004, /* EMC_TCKESR */
2235                         0x00000004, /* EMC_TPD */
2236                         0x00000001, /* EMC_TFAW */
2237                         0x00000000, /* EMC_TRPAB */
2238                         0x00000004, /* EMC_TCLKSTABLE */
2239                         0x00000005, /* EMC_TCLKSTOP */
2240                         0x00000064, /* EMC_TREFBW */
2241                         0x00000006, /* EMC_QUSE_EXTRA */
2242                         0x00000020, /* EMC_ODT_WRITE */
2243                         0x00000000, /* EMC_ODT_READ */
2244                         0x0000aa88, /* EMC_FBIO_CFG5 */
2245                         0x002c00a0, /* EMC_CFG_DIG_DLL */
2246                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2247                         0x0006c000, /* EMC_DLL_XFORM_DQS4 */
2248                         0x0006c000, /* EMC_DLL_XFORM_DQS5 */
2249                         0x0006c000, /* EMC_DLL_XFORM_DQS6 */
2250                         0x0006c000, /* EMC_DLL_XFORM_DQS7 */
2251                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2252                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2253                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2254                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2255                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2256                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2257                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2258                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2259                         0x001112a0, /* EMC_XM2CMDPADCTRL */
2260                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
2261                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
2262                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2263                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
2264                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
2265                         0x03035504, /* EMC_XM2VTTGENPADCTRL */
2266                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
2267                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
2268                         0x00000000, /* EMC_TXDSRVTTGEN */
2269                         0x02000000, /* EMC_FBIO_SPARE */
2270                         0x00000802, /* EMC_CTT_TERM_CTRL */
2271                         0x00000000, /* EMC_ZCAL_INTERVAL */
2272                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
2273                         0x000c000c, /* EMC_MRS_WAIT_CNT */
2274                         0x000c000c, /* EMC_MRS_WAIT_CNT2 */
2275                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
2276                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
2277                         0x00000000, /* EMC_CTT */
2278                         0x00000000, /* EMC_CTT_DURATION */
2279                         0x800001c6, /* EMC_DYN_SELF_REF_CONTROL */
2280                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
2281                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
2282                         0x40040001, /* MC_EMEM_ARB_CFG */
2283                         0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2284                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2285                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2286                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2287                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2288                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
2289                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2290                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2291                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2292                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2293                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2294                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
2295                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2296                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
2297                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
2298                         0x77e30303, /* MC_EMEM_ARB_MISC0 */
2299                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2300                 },
2301                 {
2302                         0x00000000, /* EMC_CDB_CNTL_1 */
2303                         0x00000004, /* EMC_FBIO_CFG6 */
2304                         0x00000007, /* EMC_QUSE */
2305                         0x00000004, /* EMC_EINPUT */
2306                         0x00000004, /* EMC_EINPUT_DURATION */
2307                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
2308                         0x00000009, /* EMC_QSAFE */
2309                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2310                         0x0000000d, /* EMC_RDV */
2311                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
2312                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
2313                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
2314                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2315                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2316                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
2317                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2318                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2319                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
2320                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
2321                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
2322                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
2323                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
2324                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
2325                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
2326                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2327                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2328                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2329                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2330                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2331                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2332                 },
2333                 {
2334                         0x00000000, /* EMC_CDB_CNTL_1 */
2335                         0x00000004, /* EMC_FBIO_CFG6 */
2336                         0x00000007, /* EMC_QUSE */
2337                         0x00000004, /* EMC_EINPUT */
2338                         0x00000004, /* EMC_EINPUT_DURATION */
2339                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
2340                         0x00000009, /* EMC_QSAFE */
2341                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2342                         0x0000000d, /* EMC_RDV */
2343                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
2344                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
2345                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
2346                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
2347                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2348                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
2349                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2350                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2351                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
2352                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
2353                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
2354                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
2355                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
2356                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
2357                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
2358                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2359                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2360                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2361                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2362                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2363                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2364                 },
2365                 {
2366                         0x0000000e, /* MC_PTSA_GRANT_DECREMENT */
2367                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
2368                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
2369                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
2370                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
2371                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
2372                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
2373                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
2374                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
2375                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
2376                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
2377                 },
2378                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
2379                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2380                 0x7320000e, /* EMC_CFG */
2381                 0x80001221, /* Mode Register 0 */
2382                 0x80100003, /* Mode Register 1 */
2383                 0x80200008, /* Mode Register 2 */
2384                 0x00000000, /* Mode Register 4 */
2385                 57820,      /* expected dvfs latency (ns) */
2386         },
2387         {
2388                 0x41,       /* Rev 4.0.3 */
2389                 20400,      /* SDRAM frequency */
2390                 900,       /* min voltage */
2391                 "pll_p",    /* clock source id */
2392                 0x40000026, /* CLK_SOURCE_EMC */
2393                 99,         /* number of burst_regs */
2394                 30,         /* number of trim_regs (each channel) */
2395                 11,         /* number of up_down_regs */
2396                 {
2397                         0x00000000, /* EMC_RC */
2398                         0x00000005, /* EMC_RFC */
2399                         0x00000000, /* EMC_RFC_SLR */
2400                         0x00000000, /* EMC_RAS */
2401                         0x00000000, /* EMC_RP */
2402                         0x00000004, /* EMC_R2W */
2403                         0x0000000a, /* EMC_W2R */
2404                         0x00000003, /* EMC_R2P */
2405                         0x0000000b, /* EMC_W2P */
2406                         0x00000000, /* EMC_RD_RCD */
2407                         0x00000000, /* EMC_WR_RCD */
2408                         0x00000003, /* EMC_RRD */
2409                         0x00000001, /* EMC_REXT */
2410                         0x00000000, /* EMC_WEXT */
2411                         0x00000005, /* EMC_WDV */
2412                         0x00000005, /* EMC_WDV_MASK */
2413                         0x00000006, /* EMC_IBDLY */
2414                         0x00010000, /* EMC_PUTERM_EXTRA */
2415                         0x00000000, /* EMC_CDB_CNTL_2 */
2416                         0x00000004, /* EMC_QRST */
2417                         0x0000000d, /* EMC_RDV_MASK */
2418                         0x0000009a, /* EMC_REFRESH */
2419                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2420                         0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
2421                         0x00000002, /* EMC_PDEX2WR */
2422                         0x00000002, /* EMC_PDEX2RD */
2423                         0x00000001, /* EMC_PCHG2PDEN */
2424                         0x00000000, /* EMC_ACT2PDEN */
2425                         0x00000007, /* EMC_AR2PDEN */
2426                         0x0000000f, /* EMC_RW2PDEN */
2427                         0x00000006, /* EMC_TXSR */
2428                         0x00000006, /* EMC_TXSRDLL */
2429                         0x00000004, /* EMC_TCKE */
2430                         0x00000004, /* EMC_TCKESR */
2431                         0x00000004, /* EMC_TPD */
2432                         0x00000001, /* EMC_TFAW */
2433                         0x00000000, /* EMC_TRPAB */
2434                         0x00000004, /* EMC_TCLKSTABLE */
2435                         0x00000005, /* EMC_TCLKSTOP */
2436                         0x000000a0, /* EMC_TREFBW */
2437                         0x00000006, /* EMC_QUSE_EXTRA */
2438                         0x00000020, /* EMC_ODT_WRITE */
2439                         0x00000000, /* EMC_ODT_READ */
2440                         0x0000aa88, /* EMC_FBIO_CFG5 */
2441                         0x002c00a0, /* EMC_CFG_DIG_DLL */
2442                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2443                         0x0006c000, /* EMC_DLL_XFORM_DQS4 */
2444                         0x0006c000, /* EMC_DLL_XFORM_DQS5 */
2445                         0x0006c000, /* EMC_DLL_XFORM_DQS6 */
2446                         0x0006c000, /* EMC_DLL_XFORM_DQS7 */
2447                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2448                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2449                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2450                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2451                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2452                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2453                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2454                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2455                         0x001112a0, /* EMC_XM2CMDPADCTRL */
2456                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
2457                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
2458                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2459                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
2460                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
2461                         0x03035504, /* EMC_XM2VTTGENPADCTRL */
2462                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
2463                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
2464                         0x00000000, /* EMC_TXDSRVTTGEN */
2465                         0x02000000, /* EMC_FBIO_SPARE */
2466                         0x00000802, /* EMC_CTT_TERM_CTRL */
2467                         0x00000000, /* EMC_ZCAL_INTERVAL */
2468                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
2469                         0x000c000c, /* EMC_MRS_WAIT_CNT */
2470                         0x000c000c, /* EMC_MRS_WAIT_CNT2 */
2471                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
2472                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
2473                         0x00000000, /* EMC_CTT */
2474                         0x00000000, /* EMC_CTT_DURATION */
2475                         0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
2476                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
2477                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
2478                         0x40020001, /* MC_EMEM_ARB_CFG */
2479                         0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2480                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2481                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2482                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2483                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2484                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
2485                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2486                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2487                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2488                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2489                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2490                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
2491                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2492                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
2493                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
2494                         0x76230303, /* MC_EMEM_ARB_MISC0 */
2495                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2496                 },
2497                 {
2498                         0x00000000, /* EMC_CDB_CNTL_1 */
2499                         0x00000004, /* EMC_FBIO_CFG6 */
2500                         0x00000007, /* EMC_QUSE */
2501                         0x00000004, /* EMC_EINPUT */
2502                         0x00000004, /* EMC_EINPUT_DURATION */
2503                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
2504                         0x00000009, /* EMC_QSAFE */
2505                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2506                         0x0000000d, /* EMC_RDV */
2507                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
2508                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
2509                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
2510                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2511                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2512                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
2513                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2514                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2515                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
2516                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
2517                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
2518                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
2519                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
2520                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
2521                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
2522                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2523                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2524                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2525                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2526                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2527                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2528                 },
2529                 {
2530                         0x00000000, /* EMC_CDB_CNTL_1 */
2531                         0x00000004, /* EMC_FBIO_CFG6 */
2532                         0x00000007, /* EMC_QUSE */
2533                         0x00000004, /* EMC_EINPUT */
2534                         0x00000004, /* EMC_EINPUT_DURATION */
2535                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
2536                         0x00000009, /* EMC_QSAFE */
2537                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2538                         0x0000000d, /* EMC_RDV */
2539                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
2540                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
2541                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
2542                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
2543                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2544                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
2545                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2546                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2547                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
2548                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
2549                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
2550                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
2551                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
2552                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
2553                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
2554                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2555                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2556                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2557                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2558                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2559                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2560                 },
2561                 {
2562                         0x00000014, /* MC_PTSA_GRANT_DECREMENT */
2563                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
2564                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
2565                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
2566                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
2567                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
2568                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
2569                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
2570                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
2571                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
2572                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
2573                 },
2574                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
2575                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2576                 0x7320000e, /* EMC_CFG */
2577                 0x80001221, /* Mode Register 0 */
2578                 0x80100003, /* Mode Register 1 */
2579                 0x80200008, /* Mode Register 2 */
2580                 0x00000000, /* Mode Register 4 */
2581                 35610,      /* expected dvfs latency (ns) */
2582         },
2583         {
2584                 0x41,       /* Rev 4.0.3 */
2585                 40800,      /* SDRAM frequency */
2586                 900,       /* min voltage */
2587                 "pll_p",    /* clock source id */
2588                 0x40000012, /* CLK_SOURCE_EMC */
2589                 99,         /* number of burst_regs */
2590                 30,         /* number of trim_regs (each channel) */
2591                 11,         /* number of up_down_regs */
2592                 {
2593                         0x00000001, /* EMC_RC */
2594                         0x0000000a, /* EMC_RFC */
2595                         0x00000000, /* EMC_RFC_SLR */
2596                         0x00000001, /* EMC_RAS */
2597                         0x00000000, /* EMC_RP */
2598                         0x00000004, /* EMC_R2W */
2599                         0x0000000a, /* EMC_W2R */
2600                         0x00000003, /* EMC_R2P */
2601                         0x0000000b, /* EMC_W2P */
2602                         0x00000000, /* EMC_RD_RCD */
2603                         0x00000000, /* EMC_WR_RCD */
2604                         0x00000003, /* EMC_RRD */
2605                         0x00000001, /* EMC_REXT */
2606                         0x00000000, /* EMC_WEXT */
2607                         0x00000005, /* EMC_WDV */
2608                         0x00000005, /* EMC_WDV_MASK */
2609                         0x00000006, /* EMC_IBDLY */
2610                         0x00010000, /* EMC_PUTERM_EXTRA */
2611                         0x00000000, /* EMC_CDB_CNTL_2 */
2612                         0x00000004, /* EMC_QRST */
2613                         0x0000000d, /* EMC_RDV_MASK */
2614                         0x00000134, /* EMC_REFRESH */
2615                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2616                         0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */
2617                         0x00000002, /* EMC_PDEX2WR */
2618                         0x00000002, /* EMC_PDEX2RD */
2619                         0x00000001, /* EMC_PCHG2PDEN */
2620                         0x00000000, /* EMC_ACT2PDEN */
2621                         0x00000008, /* EMC_AR2PDEN */
2622                         0x0000000f, /* EMC_RW2PDEN */
2623                         0x0000000c, /* EMC_TXSR */
2624                         0x0000000c, /* EMC_TXSRDLL */
2625                         0x00000004, /* EMC_TCKE */
2626                         0x00000004, /* EMC_TCKESR */
2627                         0x00000004, /* EMC_TPD */
2628                         0x00000002, /* EMC_TFAW */
2629                         0x00000000, /* EMC_TRPAB */
2630                         0x00000004, /* EMC_TCLKSTABLE */
2631                         0x00000005, /* EMC_TCLKSTOP */
2632                         0x0000013f, /* EMC_TREFBW */
2633                         0x00000006, /* EMC_QUSE_EXTRA */
2634                         0x00000020, /* EMC_ODT_WRITE */
2635                         0x00000000, /* EMC_ODT_READ */
2636                         0x0000aa88, /* EMC_FBIO_CFG5 */
2637                         0x002c00a0, /* EMC_CFG_DIG_DLL */
2638                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2639                         0x0006c000, /* EMC_DLL_XFORM_DQS4 */
2640                         0x0006c000, /* EMC_DLL_XFORM_DQS5 */
2641                         0x0006c000, /* EMC_DLL_XFORM_DQS6 */
2642                         0x0006c000, /* EMC_DLL_XFORM_DQS7 */
2643                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2644                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2645                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2646                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2647                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2648                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2649                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2650                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2651                         0x001112a0, /* EMC_XM2CMDPADCTRL */
2652                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
2653                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
2654                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2655                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
2656                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
2657                         0x03035504, /* EMC_XM2VTTGENPADCTRL */
2658                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
2659                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
2660                         0x00000000, /* EMC_TXDSRVTTGEN */
2661                         0x02000000, /* EMC_FBIO_SPARE */
2662                         0x00000802, /* EMC_CTT_TERM_CTRL */
2663                         0x00000000, /* EMC_ZCAL_INTERVAL */
2664                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
2665                         0x000c000c, /* EMC_MRS_WAIT_CNT */
2666                         0x000c000c, /* EMC_MRS_WAIT_CNT2 */
2667                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
2668                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
2669                         0x00000000, /* EMC_CTT */
2670                         0x00000000, /* EMC_CTT_DURATION */
2671                         0x80000370, /* EMC_DYN_SELF_REF_CONTROL */
2672                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
2673                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
2674                         0xa0000001, /* MC_EMEM_ARB_CFG */
2675                         0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2676                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2677                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2678                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2679                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2680                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
2681                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2682                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2683                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2684                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2685                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2686                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
2687                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2688                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
2689                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
2690                         0x74a30303, /* MC_EMEM_ARB_MISC0 */
2691                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2692                 },
2693                 {
2694                         0x00000000, /* EMC_CDB_CNTL_1 */
2695                         0x00000004, /* EMC_FBIO_CFG6 */
2696                         0x00000007, /* EMC_QUSE */
2697                         0x00000004, /* EMC_EINPUT */
2698                         0x00000004, /* EMC_EINPUT_DURATION */
2699                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
2700                         0x00000009, /* EMC_QSAFE */
2701                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2702                         0x0000000d, /* EMC_RDV */
2703                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
2704                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
2705                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
2706                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2707                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2708                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
2709                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2710                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2711                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
2712                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
2713                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
2714                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
2715                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
2716                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
2717                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
2718                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2719                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2720                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2721                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2722                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2723                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2724                 },
2725                 {
2726                         0x00000000, /* EMC_CDB_CNTL_1 */
2727                         0x00000004, /* EMC_FBIO_CFG6 */
2728                         0x00000007, /* EMC_QUSE */
2729                         0x00000004, /* EMC_EINPUT */
2730                         0x00000004, /* EMC_EINPUT_DURATION */
2731                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
2732                         0x00000009, /* EMC_QSAFE */
2733                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2734                         0x0000000d, /* EMC_RDV */
2735                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
2736                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
2737                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
2738                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
2739                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2740                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
2741                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2742                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2743                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
2744                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
2745                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
2746                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
2747                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
2748                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
2749                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
2750                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2751                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2752                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2753                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2754                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2755                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2756                 },
2757                 {
2758                         0x0000002a, /* MC_PTSA_GRANT_DECREMENT */
2759                         0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */
2760                         0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */
2761                         0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */
2762                         0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */
2763                         0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */
2764                         0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */
2765                         0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
2766                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
2767                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
2768                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
2769                 },
2770                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
2771                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2772                 0x7320000e, /* EMC_CFG */
2773                 0x80001221, /* Mode Register 0 */
2774                 0x80100003, /* Mode Register 1 */
2775                 0x80200008, /* Mode Register 2 */
2776                 0x00000000, /* Mode Register 4 */
2777                 20850,      /* expected dvfs latency (ns) */
2778         },
2779         {
2780                 0x41,       /* Rev 4.0.3 */
2781                 68000,      /* SDRAM frequency */
2782                 900,       /* min voltage */
2783                 "pll_p",    /* clock source id */
2784                 0x4000000a, /* CLK_SOURCE_EMC */
2785                 99,         /* number of burst_regs */
2786                 30,         /* number of trim_regs (each channel) */
2787                 11,         /* number of up_down_regs */
2788                 {
2789                         0x00000003, /* EMC_RC */
2790                         0x00000011, /* EMC_RFC */
2791                         0x00000000, /* EMC_RFC_SLR */
2792                         0x00000002, /* EMC_RAS */
2793                         0x00000000, /* EMC_RP */
2794                         0x00000004, /* EMC_R2W */
2795                         0x0000000a, /* EMC_W2R */
2796                         0x00000003, /* EMC_R2P */
2797                         0x0000000b, /* EMC_W2P */
2798                         0x00000000, /* EMC_RD_RCD */
2799                         0x00000000, /* EMC_WR_RCD */
2800                         0x00000003, /* EMC_RRD */
2801                         0x00000001, /* EMC_REXT */
2802                         0x00000000, /* EMC_WEXT */
2803                         0x00000005, /* EMC_WDV */
2804                         0x00000005, /* EMC_WDV_MASK */
2805                         0x00000006, /* EMC_IBDLY */
2806                         0x00010000, /* EMC_PUTERM_EXTRA */
2807                         0x00000000, /* EMC_CDB_CNTL_2 */
2808                         0x00000004, /* EMC_QRST */
2809                         0x0000000d, /* EMC_RDV_MASK */
2810                         0x00000202, /* EMC_REFRESH */
2811                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2812                         0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */
2813                         0x00000002, /* EMC_PDEX2WR */
2814                         0x00000002, /* EMC_PDEX2RD */
2815                         0x00000001, /* EMC_PCHG2PDEN */
2816                         0x00000000, /* EMC_ACT2PDEN */
2817                         0x0000000f, /* EMC_AR2PDEN */
2818                         0x0000000f, /* EMC_RW2PDEN */
2819                         0x00000013, /* EMC_TXSR */
2820                         0x00000013, /* EMC_TXSRDLL */
2821                         0x00000004, /* EMC_TCKE */
2822                         0x00000004, /* EMC_TCKESR */
2823                         0x00000004, /* EMC_TPD */
2824                         0x00000003, /* EMC_TFAW */
2825                         0x00000000, /* EMC_TRPAB */
2826                         0x00000004, /* EMC_TCLKSTABLE */
2827                         0x00000005, /* EMC_TCLKSTOP */
2828                         0x00000213, /* EMC_TREFBW */
2829                         0x00000006, /* EMC_QUSE_EXTRA */
2830                         0x00000020, /* EMC_ODT_WRITE */
2831                         0x00000000, /* EMC_ODT_READ */
2832                         0x0000aa88, /* EMC_FBIO_CFG5 */
2833                         0x002c00a0, /* EMC_CFG_DIG_DLL */
2834                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2835                         0x0006c000, /* EMC_DLL_XFORM_DQS4 */
2836                         0x0006c000, /* EMC_DLL_XFORM_DQS5 */
2837                         0x0006c000, /* EMC_DLL_XFORM_DQS6 */
2838                         0x0006c000, /* EMC_DLL_XFORM_DQS7 */
2839                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2840                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2841                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2842                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2843                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2844                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2845                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2846                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2847                         0x001112a0, /* EMC_XM2CMDPADCTRL */
2848                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
2849                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
2850                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2851                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
2852                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
2853                         0x03035504, /* EMC_XM2VTTGENPADCTRL */
2854                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
2855                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
2856                         0x00000000, /* EMC_TXDSRVTTGEN */
2857                         0x02000000, /* EMC_FBIO_SPARE */
2858                         0x00000802, /* EMC_CTT_TERM_CTRL */
2859                         0x00000000, /* EMC_ZCAL_INTERVAL */
2860                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
2861                         0x000c000c, /* EMC_MRS_WAIT_CNT */
2862                         0x000c000c, /* EMC_MRS_WAIT_CNT2 */
2863                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
2864                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
2865                         0x00000000, /* EMC_CTT */
2866                         0x00000000, /* EMC_CTT_DURATION */
2867                         0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */
2868                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
2869                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
2870                         0x00000001, /* MC_EMEM_ARB_CFG */
2871                         0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2872                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2873                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2874                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2875                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2876                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
2877                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2878                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2879                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2880                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2881                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2882                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
2883                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2884                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
2885                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
2886                         0x74230403, /* MC_EMEM_ARB_MISC0 */
2887                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2888                 },
2889                 {
2890                         0x00000000, /* EMC_CDB_CNTL_1 */
2891                         0x00000004, /* EMC_FBIO_CFG6 */
2892                         0x00000007, /* EMC_QUSE */
2893                         0x00000004, /* EMC_EINPUT */
2894                         0x00000004, /* EMC_EINPUT_DURATION */
2895                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
2896                         0x00000009, /* EMC_QSAFE */
2897                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2898                         0x0000000d, /* EMC_RDV */
2899                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
2900                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
2901                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
2902                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2903                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2904                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
2905                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2906                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2907                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
2908                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
2909                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
2910                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
2911                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
2912                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
2913                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
2914                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2915                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2916                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2917                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2918                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2919                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2920                 },
2921                 {
2922                         0x00000000, /* EMC_CDB_CNTL_1 */
2923                         0x00000004, /* EMC_FBIO_CFG6 */
2924                         0x00000007, /* EMC_QUSE */
2925                         0x00000004, /* EMC_EINPUT */
2926                         0x00000004, /* EMC_EINPUT_DURATION */
2927                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
2928                         0x00000009, /* EMC_QSAFE */
2929                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2930                         0x0000000d, /* EMC_RDV */
2931                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
2932                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
2933                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
2934                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
2935                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
2936                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
2937                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2938                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
2939                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
2940                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
2941                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
2942                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
2943                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
2944                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
2945                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
2946                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2947                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2948                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2949                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2950                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2951                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2952                 },
2953                 {
2954                         0x00000046, /* MC_PTSA_GRANT_DECREMENT */
2955                         0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */
2956                         0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */
2957                         0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */
2958                         0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */
2959                         0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */
2960                         0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */
2961                         0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */
2962                         0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */
2963                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
2964                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
2965                 },
2966                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
2967                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2968                 0x7320000e, /* EMC_CFG */
2969                 0x80001221, /* Mode Register 0 */
2970                 0x80100003, /* Mode Register 1 */
2971                 0x80200008, /* Mode Register 2 */
2972                 0x00000000, /* Mode Register 4 */
2973                 10720,      /* expected dvfs latency (ns) */
2974         },
2975         {
2976                 0x41,       /* Rev 4.0.3 */
2977                 102000,     /* SDRAM frequency */
2978                 900,       /* min voltage */
2979                 "pll_p",    /* clock source id */
2980                 0x40000006, /* CLK_SOURCE_EMC */
2981                 99,         /* number of burst_regs */
2982                 30,         /* number of trim_regs (each channel) */
2983                 11,         /* number of up_down_regs */
2984                 {
2985                         0x00000004, /* EMC_RC */
2986                         0x0000001a, /* EMC_RFC */
2987                         0x00000000, /* EMC_RFC_SLR */
2988                         0x00000003, /* EMC_RAS */
2989                         0x00000001, /* EMC_RP */
2990                         0x00000004, /* EMC_R2W */
2991                         0x0000000a, /* EMC_W2R */
2992                         0x00000003, /* EMC_R2P */
2993                         0x0000000b, /* EMC_W2P */
2994                         0x00000001, /* EMC_RD_RCD */
2995                         0x00000001, /* EMC_WR_RCD */
2996                         0x00000003, /* EMC_RRD */
2997                         0x00000001, /* EMC_REXT */
2998                         0x00000000, /* EMC_WEXT */
2999                         0x00000005, /* EMC_WDV */
3000                         0x00000005, /* EMC_WDV_MASK */
3001                         0x00000006, /* EMC_IBDLY */
3002                         0x00010000, /* EMC_PUTERM_EXTRA */
3003                         0x00000000, /* EMC_CDB_CNTL_2 */
3004                         0x00000004, /* EMC_QRST */
3005                         0x0000000d, /* EMC_RDV_MASK */
3006                         0x00000303, /* EMC_REFRESH */
3007                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3008                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
3009                         0x00000002, /* EMC_PDEX2WR */
3010                         0x00000002, /* EMC_PDEX2RD */
3011                         0x00000001, /* EMC_PCHG2PDEN */
3012                         0x00000000, /* EMC_ACT2PDEN */
3013                         0x00000018, /* EMC_AR2PDEN */
3014                         0x0000000f, /* EMC_RW2PDEN */
3015                         0x0000001c, /* EMC_TXSR */
3016                         0x0000001c, /* EMC_TXSRDLL */
3017                         0x00000004, /* EMC_TCKE */
3018                         0x00000004, /* EMC_TCKESR */
3019                         0x00000004, /* EMC_TPD */
3020                         0x00000005, /* EMC_TFAW */
3021                         0x00000000, /* EMC_TRPAB */
3022                         0x00000004, /* EMC_TCLKSTABLE */
3023                         0x00000005, /* EMC_TCLKSTOP */
3024                         0x0000031c, /* EMC_TREFBW */
3025                         0x00000006, /* EMC_QUSE_EXTRA */
3026                         0x00000020, /* EMC_ODT_WRITE */
3027                         0x00000000, /* EMC_ODT_READ */
3028                         0x0000aa88, /* EMC_FBIO_CFG5 */
3029                         0x002c00a0, /* EMC_CFG_DIG_DLL */
3030                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3031                         0x0006c000, /* EMC_DLL_XFORM_DQS4 */
3032                         0x0006c000, /* EMC_DLL_XFORM_DQS5 */
3033                         0x0006c000, /* EMC_DLL_XFORM_DQS6 */
3034                         0x0006c000, /* EMC_DLL_XFORM_DQS7 */
3035                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3036                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3037                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3038                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3039                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3040                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3041                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3042                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3043                         0x001112a0, /* EMC_XM2CMDPADCTRL */
3044                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
3045                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
3046                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3047                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
3048                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
3049                         0x03035504, /* EMC_XM2VTTGENPADCTRL */
3050                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
3051                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
3052                         0x00000000, /* EMC_TXDSRVTTGEN */
3053                         0x02000000, /* EMC_FBIO_SPARE */
3054                         0x00000802, /* EMC_CTT_TERM_CTRL */
3055                         0x00000000, /* EMC_ZCAL_INTERVAL */
3056                         0x00000042, /* EMC_ZCAL_WAIT_CNT */
3057                         0x000c000c, /* EMC_MRS_WAIT_CNT */
3058                         0x000c000c, /* EMC_MRS_WAIT_CNT2 */
3059                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
3060                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
3061                         0x00000000, /* EMC_CTT */
3062                         0x00000000, /* EMC_CTT_DURATION */
3063                         0x80000714, /* EMC_DYN_SELF_REF_CONTROL */
3064                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
3065                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
3066                         0x08000001, /* MC_EMEM_ARB_CFG */
3067                         0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3068                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3069                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3070                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
3071                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
3072                         0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
3073                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3074                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3075                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3076                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3077                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3078                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
3079                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3080                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
3081                         0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
3082                         0x73c30504, /* MC_EMEM_ARB_MISC0 */
3083                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3084                 },
3085                 {
3086                         0x00000000, /* EMC_CDB_CNTL_1 */
3087                         0x00000004, /* EMC_FBIO_CFG6 */
3088                         0x00000007, /* EMC_QUSE */
3089                         0x00000004, /* EMC_EINPUT */
3090                         0x00000004, /* EMC_EINPUT_DURATION */
3091                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
3092                         0x00000009, /* EMC_QSAFE */
3093                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3094                         0x0000000d, /* EMC_RDV */
3095                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
3096                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
3097                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
3098                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3099                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
3100                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
3101                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3102                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3103                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
3104                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
3105                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
3106                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
3107                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
3108                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
3109                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
3110                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3111                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3112                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3113                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3114                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3115                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3116                 },
3117                 {
3118                         0x00000000, /* EMC_CDB_CNTL_1 */
3119                         0x00000004, /* EMC_FBIO_CFG6 */
3120                         0x00000007, /* EMC_QUSE */
3121                         0x00000004, /* EMC_EINPUT */
3122                         0x00000004, /* EMC_EINPUT_DURATION */
3123                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
3124                         0x00000009, /* EMC_QSAFE */
3125                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3126                         0x0000000d, /* EMC_RDV */
3127                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
3128                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
3129                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
3130                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
3131                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
3132                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
3133                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3134                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3135                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
3136                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
3137                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
3138                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
3139                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
3140                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
3141                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
3142                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3143                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3144                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3145                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3146                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3147                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3148                 },
3149                 {
3150                         0x00000068, /* MC_PTSA_GRANT_DECREMENT */
3151                         0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */
3152                         0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */
3153                         0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */
3154                         0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
3155                         0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */
3156                         0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */
3157                         0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */
3158                         0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */
3159                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
3160                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
3161                 },
3162                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
3163                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3164                 0x7320000e, /* EMC_CFG */
3165                 0x80001221, /* Mode Register 0 */
3166                 0x80100003, /* Mode Register 1 */
3167                 0x80200008, /* Mode Register 2 */
3168                 0x00000000, /* Mode Register 4 */
3169                 6890,       /* expected dvfs latency (ns) */
3170         },
3171         {
3172                 0x41,       /* Rev 4.0.3 */
3173                 204000,     /* SDRAM frequency */
3174                 900,       /* min voltage */
3175                 "pll_p",    /* clock source id */
3176                 0x40000002, /* CLK_SOURCE_EMC */
3177                 99,         /* number of burst_regs */
3178                 30,         /* number of trim_regs (each channel) */
3179                 11,         /* number of up_down_regs */
3180                 {
3181                         0x00000009, /* EMC_RC */
3182                         0x00000035, /* EMC_RFC */
3183                         0x00000000, /* EMC_RFC_SLR */
3184                         0x00000007, /* EMC_RAS */
3185                         0x00000002, /* EMC_RP */
3186                         0x00000004, /* EMC_R2W */
3187                         0x0000000a, /* EMC_W2R */
3188                         0x00000003, /* EMC_R2P */
3189                         0x0000000b, /* EMC_W2P */
3190                         0x00000002, /* EMC_RD_RCD */
3191                         0x00000002, /* EMC_WR_RCD */
3192                         0x00000003, /* EMC_RRD */
3193                         0x00000001, /* EMC_REXT */
3194                         0x00000000, /* EMC_WEXT */
3195                         0x00000005, /* EMC_WDV */
3196                         0x00000005, /* EMC_WDV_MASK */
3197                         0x00000006, /* EMC_IBDLY */
3198                         0x00010000, /* EMC_PUTERM_EXTRA */
3199                         0x00000000, /* EMC_CDB_CNTL_2 */
3200                         0x00000004, /* EMC_QRST */
3201                         0x0000000d, /* EMC_RDV_MASK */
3202                         0x00000607, /* EMC_REFRESH */
3203                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3204                         0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
3205                         0x00000002, /* EMC_PDEX2WR */
3206                         0x00000002, /* EMC_PDEX2RD */
3207                         0x00000001, /* EMC_PCHG2PDEN */
3208                         0x00000000, /* EMC_ACT2PDEN */
3209                         0x00000032, /* EMC_AR2PDEN */
3210                         0x0000000f, /* EMC_RW2PDEN */
3211                         0x00000038, /* EMC_TXSR */
3212                         0x00000038, /* EMC_TXSRDLL */
3213                         0x00000004, /* EMC_TCKE */
3214                         0x00000004, /* EMC_TCKESR */
3215                         0x00000004, /* EMC_TPD */
3216                         0x00000009, /* EMC_TFAW */
3217                         0x00000000, /* EMC_TRPAB */
3218                         0x00000004, /* EMC_TCLKSTABLE */
3219                         0x00000005, /* EMC_TCLKSTOP */
3220                         0x00000638, /* EMC_TREFBW */
3221                         0x00000006, /* EMC_QUSE_EXTRA */
3222                         0x00000020, /* EMC_ODT_WRITE */
3223                         0x00000000, /* EMC_ODT_READ */
3224                         0x0000aa88, /* EMC_FBIO_CFG5 */
3225                         0x000000a0, /* EMC_CFG_DIG_DLL */
3226                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3227                         0x0006c000, /* EMC_DLL_XFORM_DQS4 */
3228                         0x0006c000, /* EMC_DLL_XFORM_DQS5 */
3229                         0x0006c000, /* EMC_DLL_XFORM_DQS6 */
3230                         0x0006c000, /* EMC_DLL_XFORM_DQS7 */
3231                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3232                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3233                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3234                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3235                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3236                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3237                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3238                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3239                         0x001112a0, /* EMC_XM2CMDPADCTRL */
3240                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
3241                         0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
3242                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3243                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
3244                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
3245                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
3246                         0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
3247                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
3248                         0x00000000, /* EMC_TXDSRVTTGEN */
3249                         0x02000000, /* EMC_FBIO_SPARE */
3250                         0x00000802, /* EMC_CTT_TERM_CTRL */
3251                         0x00020000, /* EMC_ZCAL_INTERVAL */
3252                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
3253                         0x000c000c, /* EMC_MRS_WAIT_CNT */
3254                         0x000c000c, /* EMC_MRS_WAIT_CNT2 */
3255                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
3256                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
3257                         0x00000000, /* EMC_CTT */
3258                         0x00000000, /* EMC_CTT_DURATION */
3259                         0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
3260                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
3261                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
3262                         0x01000003, /* MC_EMEM_ARB_CFG */
3263                         0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3264                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3265                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3266                         0x00000005, /* MC_EMEM_ARB_TIMING_RC */
3267                         0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
3268                         0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
3269                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3270                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3271                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3272                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3273                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3274                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
3275                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3276                         0x06030102, /* MC_EMEM_ARB_DA_TURNS */
3277                         0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
3278                         0x73840a06, /* MC_EMEM_ARB_MISC0 */
3279                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3280                 },
3281                 {
3282                         0x00000000, /* EMC_CDB_CNTL_1 */
3283                         0x00000004, /* EMC_FBIO_CFG6 */
3284                         0x00000007, /* EMC_QUSE */
3285                         0x00000004, /* EMC_EINPUT */
3286                         0x00000004, /* EMC_EINPUT_DURATION */
3287                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
3288                         0x00000009, /* EMC_QSAFE */
3289                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3290                         0x0000000d, /* EMC_RDV */
3291                         0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
3292                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
3293                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
3294                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3295                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
3296                         0x00000808, /* EMC_XM2CLKPADCTRL2 */
3297                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3298                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3299                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
3300                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
3301                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
3302                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
3303                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
3304                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
3305                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
3306                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3307                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3308                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3309                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3310                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3311                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3312                 },
3313                 {
3314                         0x00000000, /* EMC_CDB_CNTL_1 */
3315                         0x00000004, /* EMC_FBIO_CFG6 */
3316                         0x00000007, /* EMC_QUSE */
3317                         0x00000004, /* EMC_EINPUT */
3318                         0x00000004, /* EMC_EINPUT_DURATION */
3319                         0x0006c000, /* EMC_DLL_XFORM_DQS0 */
3320                         0x00000009, /* EMC_QSAFE */
3321                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3322                         0x0000000d, /* EMC_RDV */
3323                         0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
3324                         0x20820800, /* EMC_XM2DQSPADCTRL3 */
3325                         0x00048000, /* EMC_DLL_XFORM_DQ0 */
3326                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
3327                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
3328                         0x00000808, /* EMC_XM2CLKPADCTRL2 */
3329                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3330                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3331                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
3332                         0x0006c000, /* EMC_DLL_XFORM_DQS1 */
3333                         0x0006c000, /* EMC_DLL_XFORM_DQS2 */
3334                         0x0006c000, /* EMC_DLL_XFORM_DQS3 */
3335                         0x00048000, /* EMC_DLL_XFORM_DQ1 */
3336                         0x00048000, /* EMC_DLL_XFORM_DQ2 */
3337                         0x00048000, /* EMC_DLL_XFORM_DQ3 */
3338                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3339                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3340                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3341                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3342                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3343                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3344                 },
3345                 {
3346                         0x000000d0, /* MC_PTSA_GRANT_DECREMENT */
3347                         0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
3348                         0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
3349                         0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
3350                         0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
3351                         0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */
3352                         0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */
3353                         0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
3354                         0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
3355                         0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
3356                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
3357                 },
3358                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
3359                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3360                 0x7320000e, /* EMC_CFG */
3361                 0x80001221, /* Mode Register 0 */
3362                 0x80100003, /* Mode Register 1 */
3363                 0x80200008, /* Mode Register 2 */
3364                 0x00000000, /* Mode Register 4 */
3365                 3420,       /* expected dvfs latency (ns) */
3366         },
3367         {
3368                 0x41,       /* Rev 4.0.3 */
3369                 312000,     /* SDRAM frequency */
3370                 1000,       /* min voltage */
3371                 "pll_c",    /* clock source id */
3372                 0x24000002, /* CLK_SOURCE_EMC */
3373                 99,         /* number of burst_regs */
3374                 30,         /* number of trim_regs (each channel) */
3375                 11,         /* number of up_down_regs */
3376                 {
3377                         0x0000000e, /* EMC_RC */
3378                         0x00000050, /* EMC_RFC */
3379                         0x00000000, /* EMC_RFC_SLR */
3380                         0x00000009, /* EMC_RAS */
3381                         0x00000003, /* EMC_RP */
3382                         0x00000004, /* EMC_R2W */
3383                         0x00000008, /* EMC_W2R */
3384                         0x00000002, /* EMC_R2P */
3385                         0x00000009, /* EMC_W2P */
3386                         0x00000003, /* EMC_RD_RCD */
3387                         0x00000003, /* EMC_WR_RCD */
3388                         0x00000002, /* EMC_RRD */
3389                         0x00000001, /* EMC_REXT */
3390                         0x00000000, /* EMC_WEXT */
3391                         0x00000004, /* EMC_WDV */
3392                         0x00000004, /* EMC_WDV_MASK */
3393                         0x00000007, /* EMC_IBDLY */
3394                         0x00080006, /* EMC_PUTERM_EXTRA */
3395                         0x00000000, /* EMC_CDB_CNTL_2 */
3396                         0x00000004, /* EMC_QRST */
3397                         0x0000000d, /* EMC_RDV_MASK */
3398                         0x00000945, /* EMC_REFRESH */
3399                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3400                         0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */
3401                         0x00000001, /* EMC_PDEX2WR */
3402                         0x00000008, /* EMC_PDEX2RD */
3403                         0x00000001, /* EMC_PCHG2PDEN */
3404                         0x00000000, /* EMC_ACT2PDEN */
3405                         0x0000004d, /* EMC_AR2PDEN */
3406                         0x0000000e, /* EMC_RW2PDEN */
3407                         0x00000055, /* EMC_TXSR */
3408                         0x00000200, /* EMC_TXSRDLL */
3409                         0x00000004, /* EMC_TCKE */
3410                         0x00000004, /* EMC_TCKESR */
3411                         0x00000004, /* EMC_TPD */
3412                         0x0000000d, /* EMC_TFAW */
3413                         0x00000000, /* EMC_TRPAB */
3414                         0x00000004, /* EMC_TCLKSTABLE */
3415                         0x00000005, /* EMC_TCLKSTOP */
3416                         0x00000986, /* EMC_TREFBW */
3417                         0x00000006, /* EMC_QUSE_EXTRA */
3418                         0x00000020, /* EMC_ODT_WRITE */
3419                         0x00000000, /* EMC_ODT_READ */
3420                         0x0000ba88, /* EMC_FBIO_CFG5 */
3421                         0x002c00a0, /* EMC_CFG_DIG_DLL */
3422                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3423                         0x00030000, /* EMC_DLL_XFORM_DQS4 */
3424                         0x00030000, /* EMC_DLL_XFORM_DQS5 */
3425                         0x00030000, /* EMC_DLL_XFORM_DQS6 */
3426                         0x00030000, /* EMC_DLL_XFORM_DQS7 */
3427                         0x00028000, /* EMC_DLL_XFORM_QUSE4 */
3428                         0x00028000, /* EMC_DLL_XFORM_QUSE5 */
3429                         0x00028000, /* EMC_DLL_XFORM_QUSE6 */
3430                         0x00028000, /* EMC_DLL_XFORM_QUSE7 */
3431                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3432                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3433                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3434                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3435                         0x001112a0, /* EMC_XM2CMDPADCTRL */
3436                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
3437                         0x0001013d, /* EMC_XM2DQSPADCTRL2 */
3438                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3439                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
3440                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
3441                         0x03035504, /* EMC_XM2VTTGENPADCTRL */
3442                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
3443                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
3444                         0x00000000, /* EMC_TXDSRVTTGEN */
3445                         0x02000000, /* EMC_FBIO_SPARE */
3446                         0x00000802, /* EMC_CTT_TERM_CTRL */
3447                         0x00020000, /* EMC_ZCAL_INTERVAL */
3448                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
3449                         0x0171000c, /* EMC_MRS_WAIT_CNT */
3450                         0x0171000c, /* EMC_MRS_WAIT_CNT2 */
3451                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
3452                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
3453                         0x00000000, /* EMC_CTT */
3454                         0x00000000, /* EMC_CTT_DURATION */
3455                         0x80001395, /* EMC_DYN_SELF_REF_CONTROL */
3456                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
3457                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
3458                         0x0b000004, /* MC_EMEM_ARB_CFG */
3459                         0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3460                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3461                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
3462                         0x00000007, /* MC_EMEM_ARB_TIMING_RC */
3463                         0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
3464                         0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
3465                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3466                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3467                         0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3468                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3469                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3470                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
3471                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3472                         0x06040202, /* MC_EMEM_ARB_DA_TURNS */
3473                         0x000b0607, /* MC_EMEM_ARB_DA_COVERS */
3474                         0x76e50f08, /* MC_EMEM_ARB_MISC0 */
3475                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3476                 },
3477                 {
3478                         0x00000000, /* EMC_CDB_CNTL_1 */
3479                         0x00000006, /* EMC_FBIO_CFG6 */
3480                         0x00000007, /* EMC_QUSE */
3481                         0x00000005, /* EMC_EINPUT */
3482                         0x00000004, /* EMC_EINPUT_DURATION */
3483                         0x00030000, /* EMC_DLL_XFORM_DQS0 */
3484                         0x0000000b, /* EMC_QSAFE */
3485                         0x00028000, /* EMC_DLL_XFORM_QUSE0 */
3486                         0x0000000d, /* EMC_RDV */
3487                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
3488                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
3489                         0x00030000, /* EMC_DLL_XFORM_DQ0 */
3490                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3491                         0x00014000, /* EMC_DLL_XFORM_ADDR0 */
3492                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
3493                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3494                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3495                         0x00014000, /* EMC_DLL_XFORM_ADDR2 */
3496                         0x00030000, /* EMC_DLL_XFORM_DQS1 */
3497                         0x00030000, /* EMC_DLL_XFORM_DQS2 */
3498                         0x00030000, /* EMC_DLL_XFORM_DQS3 */
3499                         0x00030000, /* EMC_DLL_XFORM_DQ1 */
3500                         0x00030000, /* EMC_DLL_XFORM_DQ2 */
3501                         0x00030000, /* EMC_DLL_XFORM_DQ3 */
3502                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3503                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3504                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3505                         0x00028000, /* EMC_DLL_XFORM_QUSE1 */
3506                         0x00028000, /* EMC_DLL_XFORM_QUSE2 */
3507                         0x00028000, /* EMC_DLL_XFORM_QUSE3 */
3508                 },
3509                 {
3510                         0x00000000, /* EMC_CDB_CNTL_1 */
3511                         0x00000006, /* EMC_FBIO_CFG6 */
3512                         0x00000007, /* EMC_QUSE */
3513                         0x00000005, /* EMC_EINPUT */
3514                         0x00000004, /* EMC_EINPUT_DURATION */
3515                         0x00030000, /* EMC_DLL_XFORM_DQS0 */
3516                         0x0000000b, /* EMC_QSAFE */
3517                         0x00028000, /* EMC_DLL_XFORM_QUSE0 */
3518                         0x0000000d, /* EMC_RDV */
3519                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
3520                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
3521                         0x00030000, /* EMC_DLL_XFORM_DQ0 */
3522                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
3523                         0x00014000, /* EMC_DLL_XFORM_ADDR0 */
3524                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
3525                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3526                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3527                         0x00014000, /* EMC_DLL_XFORM_ADDR2 */
3528                         0x00030000, /* EMC_DLL_XFORM_DQS1 */
3529                         0x00030000, /* EMC_DLL_XFORM_DQS2 */
3530                         0x00030000, /* EMC_DLL_XFORM_DQS3 */
3531                         0x00030000, /* EMC_DLL_XFORM_DQ1 */
3532                         0x00030000, /* EMC_DLL_XFORM_DQ2 */
3533                         0x00030000, /* EMC_DLL_XFORM_DQ3 */
3534                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3535                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3536                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3537                         0x00028000, /* EMC_DLL_XFORM_QUSE1 */
3538                         0x00028000, /* EMC_DLL_XFORM_QUSE2 */
3539                         0x00028000, /* EMC_DLL_XFORM_QUSE3 */
3540                 },
3541                 {
3542                         0x00000140, /* MC_PTSA_GRANT_DECREMENT */
3543                         0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */
3544                         0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */
3545                         0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */
3546                         0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
3547                         0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */
3548                         0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */
3549                         0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */
3550                         0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */
3551                         0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */
3552                         0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
3553                 },
3554                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
3555                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3556                 0x5320000e, /* EMC_CFG */
3557                 0x80000321, /* Mode Register 0 */
3558                 0x80100002, /* Mode Register 1 */
3559                 0x80200000, /* Mode Register 2 */
3560                 0x00000000, /* Mode Register 4 */
3561                 2680,       /* expected dvfs latency (ns) */
3562         },
3563         {
3564                 0x41,       /* Rev 4.0.3 */
3565                 408000,     /* SDRAM frequency */
3566                 1000,       /* min voltage */
3567                 "pll_p",    /* clock source id */
3568                 0x40000000, /* CLK_SOURCE_EMC */
3569                 99,         /* number of burst_regs */
3570                 30,         /* number of trim_regs (each channel) */
3571                 11,         /* number of up_down_regs */
3572                 {
3573                         0x00000012, /* EMC_RC */
3574                         0x00000069, /* EMC_RFC */
3575                         0x00000000, /* EMC_RFC_SLR */
3576                         0x0000000d, /* EMC_RAS */
3577                         0x00000004, /* EMC_RP */
3578                         0x00000005, /* EMC_R2W */
3579                         0x00000009, /* EMC_W2R */
3580                         0x00000002, /* EMC_R2P */
3581                         0x0000000c, /* EMC_W2P */
3582                         0x00000004, /* EMC_RD_RCD */
3583                         0x00000004, /* EMC_WR_RCD */
3584                         0x00000002, /* EMC_RRD */
3585                         0x00000001, /* EMC_REXT */
3586                         0x00000000, /* EMC_WEXT */
3587                         0x00000004, /* EMC_WDV */
3588                         0x00000004, /* EMC_WDV_MASK */
3589                         0x00000007, /* EMC_IBDLY */
3590                         0x00080006, /* EMC_PUTERM_EXTRA */
3591                         0x00000000, /* EMC_CDB_CNTL_2 */
3592                         0x00000004, /* EMC_QRST */
3593                         0x0000000e, /* EMC_RDV_MASK */
3594                         0x00000c2f, /* EMC_REFRESH */
3595                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3596                         0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
3597                         0x00000001, /* EMC_PDEX2WR */
3598                         0x00000008, /* EMC_PDEX2RD */
3599                         0x00000001, /* EMC_PCHG2PDEN */
3600                         0x00000000, /* EMC_ACT2PDEN */
3601                         0x00000066, /* EMC_AR2PDEN */
3602                         0x00000011, /* EMC_RW2PDEN */
3603                         0x0000006f, /* EMC_TXSR */
3604                         0x00000200, /* EMC_TXSRDLL */
3605                         0x00000004, /* EMC_TCKE */
3606                         0x00000004, /* EMC_TCKESR */
3607                         0x00000004, /* EMC_TPD */
3608                         0x00000011, /* EMC_TFAW */
3609                         0x00000000, /* EMC_TRPAB */
3610                         0x00000004, /* EMC_TCLKSTABLE */
3611                         0x00000005, /* EMC_TCLKSTOP */
3612                         0x00000c70, /* EMC_TREFBW */
3613                         0x00000006, /* EMC_QUSE_EXTRA */
3614                         0x00000020, /* EMC_ODT_WRITE */
3615                         0x00000000, /* EMC_ODT_READ */
3616                         0x0000ba88, /* EMC_FBIO_CFG5 */
3617                         0x002c0080, /* EMC_CFG_DIG_DLL */
3618                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3619                         0x00028000, /* EMC_DLL_XFORM_DQS4 */
3620                         0x00028000, /* EMC_DLL_XFORM_DQS5 */
3621                         0x00028000, /* EMC_DLL_XFORM_DQS6 */
3622                         0x00028000, /* EMC_DLL_XFORM_DQS7 */
3623                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3624                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3625                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3626                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3627                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3628                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3629                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3630                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3631                         0x001112a0, /* EMC_XM2CMDPADCTRL */
3632                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
3633                         0x0001013d, /* EMC_XM2DQSPADCTRL2 */
3634                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3635                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
3636                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
3637                         0x03035504, /* EMC_XM2VTTGENPADCTRL */
3638                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
3639                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
3640                         0x00000000, /* EMC_TXDSRVTTGEN */
3641                         0x02000000, /* EMC_FBIO_SPARE */
3642                         0x00000802, /* EMC_CTT_TERM_CTRL */
3643                         0x00020000, /* EMC_ZCAL_INTERVAL */
3644                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
3645                         0x0158000c, /* EMC_MRS_WAIT_CNT */
3646                         0x0158000c, /* EMC_MRS_WAIT_CNT2 */
3647                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
3648                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
3649                         0x00000000, /* EMC_CTT */
3650                         0x00000000, /* EMC_CTT_DURATION */
3651                         0x80001944, /* EMC_DYN_SELF_REF_CONTROL */
3652                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
3653                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
3654                         0x02000006, /* MC_EMEM_ARB_CFG */
3655                         0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3656                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3657                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
3658                         0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
3659                         0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
3660                         0x00000008, /* MC_EMEM_ARB_TIMING_FAW */
3661                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3662                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3663                         0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3664                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3665                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3666                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
3667                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3668                         0x06040202, /* MC_EMEM_ARB_DA_TURNS */
3669                         0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
3670                         0x7547130b, /* MC_EMEM_ARB_MISC0 */
3671                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3672                 },
3673                 {
3674                         0x00000000, /* EMC_CDB_CNTL_1 */
3675                         0x00000006, /* EMC_FBIO_CFG6 */
3676                         0x00000007, /* EMC_QUSE */
3677                         0x00000005, /* EMC_EINPUT */
3678                         0x00000004, /* EMC_EINPUT_DURATION */
3679                         0x00028000, /* EMC_DLL_XFORM_DQS0 */
3680                         0x0000000c, /* EMC_QSAFE */
3681                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3682                         0x0000000e, /* EMC_RDV */
3683                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
3684                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
3685                         0x00030000, /* EMC_DLL_XFORM_DQ0 */
3686                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3687                         0x00014000, /* EMC_DLL_XFORM_ADDR0 */
3688                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
3689                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3690                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3691                         0x00014000, /* EMC_DLL_XFORM_ADDR2 */
3692                         0x00028000, /* EMC_DLL_XFORM_DQS1 */
3693                         0x00028000, /* EMC_DLL_XFORM_DQS2 */
3694                         0x00028000, /* EMC_DLL_XFORM_DQS3 */
3695                         0x00030000, /* EMC_DLL_XFORM_DQ1 */
3696                         0x00030000, /* EMC_DLL_XFORM_DQ2 */
3697                         0x00030000, /* EMC_DLL_XFORM_DQ3 */
3698                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3699                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3700                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3701                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3702                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3703                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3704                 },
3705                 {
3706                         0x00000000, /* EMC_CDB_CNTL_1 */
3707                         0x00000006, /* EMC_FBIO_CFG6 */
3708                         0x00000007, /* EMC_QUSE */
3709                         0x00000005, /* EMC_EINPUT */
3710                         0x00000004, /* EMC_EINPUT_DURATION */
3711                         0x00028000, /* EMC_DLL_XFORM_DQS0 */
3712                         0x0000000c, /* EMC_QSAFE */
3713                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3714                         0x0000000e, /* EMC_RDV */
3715                         0x00208208, /* EMC_XM2DQSPADCTRL4 */
3716                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
3717                         0x00030000, /* EMC_DLL_XFORM_DQ0 */
3718                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
3719                         0x00014000, /* EMC_DLL_XFORM_ADDR0 */
3720                         0x00000000, /* EMC_XM2CLKPADCTRL2 */
3721                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3722                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3723                         0x00014000, /* EMC_DLL_XFORM_ADDR2 */
3724                         0x00028000, /* EMC_DLL_XFORM_DQS1 */
3725                         0x00028000, /* EMC_DLL_XFORM_DQS2 */
3726                         0x00028000, /* EMC_DLL_XFORM_DQS3 */
3727                         0x00030000, /* EMC_DLL_XFORM_DQ1 */
3728                         0x00030000, /* EMC_DLL_XFORM_DQ2 */
3729                         0x00030000, /* EMC_DLL_XFORM_DQ3 */
3730                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3731                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3732                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3733                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3734                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3735                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3736                 },
3737                 {
3738                         0x000000d1, /* MC_PTSA_GRANT_DECREMENT */
3739                         0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */
3740                         0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */
3741                         0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */
3742                         0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */
3743                         0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */
3744                         0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */
3745                         0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */
3746                         0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */
3747                         0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */
3748                         0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
3749                 },
3750                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
3751                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3752                 0x53200006, /* EMC_CFG */
3753                 0x80000731, /* Mode Register 0 */
3754                 0x80100002, /* Mode Register 1 */
3755                 0x80200008, /* Mode Register 2 */
3756                 0x00000000, /* Mode Register 4 */
3757                 1750,       /* expected dvfs latency (ns) */
3758         },
3759         {
3760                 0x41,       /* Rev 4.0.3 */
3761                 624000,     /* SDRAM frequency */
3762                 1100,       /* min voltage */
3763                 "pll_c",    /* clock source id */
3764                 0x24000000, /* CLK_SOURCE_EMC */
3765                 99,         /* number of burst_regs */
3766                 30,         /* number of trim_regs (each channel) */
3767                 11,         /* number of up_down_regs */
3768                 {
3769                         0x0000001d, /* EMC_RC */
3770                         0x000000a1, /* EMC_RFC */
3771                         0x00000000, /* EMC_RFC_SLR */
3772                         0x00000014, /* EMC_RAS */
3773                         0x00000007, /* EMC_RP */
3774                         0x00000007, /* EMC_R2W */
3775                         0x0000000b, /* EMC_W2R */
3776                         0x00000003, /* EMC_R2P */
3777                         0x00000010, /* EMC_W2P */
3778                         0x00000007, /* EMC_RD_RCD */
3779                         0x00000007, /* EMC_WR_RCD */
3780                         0x00000002, /* EMC_RRD */
3781                         0x00000001, /* EMC_REXT */
3782                         0x00000000, /* EMC_WEXT */
3783                         0x00000005, /* EMC_WDV */
3784                         0x00000005, /* EMC_WDV_MASK */
3785                         0x0000000b, /* EMC_IBDLY */
3786                         0x000c000a, /* EMC_PUTERM_EXTRA */
3787                         0x00000000, /* EMC_CDB_CNTL_2 */
3788                         0x00000007, /* EMC_QRST */
3789                         0x00000012, /* EMC_RDV_MASK */
3790                         0x000012c4, /* EMC_REFRESH */
3791                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3792                         0x000004b1, /* EMC_PRE_REFRESH_REQ_CNT */
3793                         0x00000002, /* EMC_PDEX2WR */
3794                         0x0000000d, /* EMC_PDEX2RD */
3795                         0x00000001, /* EMC_PCHG2PDEN */
3796                         0x00000000, /* EMC_ACT2PDEN */
3797                         0x0000009c, /* EMC_AR2PDEN */
3798                         0x00000015, /* EMC_RW2PDEN */
3799                         0x000000a9, /* EMC_TXSR */
3800                         0x00000200, /* EMC_TXSRDLL */
3801                         0x00000005, /* EMC_TCKE */
3802                         0x00000005, /* EMC_TCKESR */
3803                         0x00000005, /* EMC_TPD */
3804                         0x00000019, /* EMC_TFAW */
3805                         0x00000000, /* EMC_TRPAB */
3806                         0x00000006, /* EMC_TCLKSTABLE */
3807                         0x00000007, /* EMC_TCLKSTOP */
3808                         0x00001305, /* EMC_TREFBW */
3809                         0x0000000a, /* EMC_QUSE_EXTRA */
3810                         0x00000020, /* EMC_ODT_WRITE */
3811                         0x00000000, /* EMC_ODT_READ */
3812                         0x0000ba88, /* EMC_FBIO_CFG5 */
3813                         0xf00d0191, /* EMC_CFG_DIG_DLL */
3814                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3815                         0x007fc00a, /* EMC_DLL_XFORM_DQS4 */
3816                         0x007fc00a, /* EMC_DLL_XFORM_DQS5 */
3817                         0x007fc00a, /* EMC_DLL_XFORM_DQS6 */
3818                         0x007fc00a, /* EMC_DLL_XFORM_DQS7 */
3819                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3820                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3821                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3822                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3823                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3824                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3825                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3826                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3827                         0x001112a0, /* EMC_XM2CMDPADCTRL */
3828                         0x00000000, /* EMC_XM2CMDPADCTRL4 */
3829                         0x0000013d, /* EMC_XM2DQSPADCTRL2 */
3830                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3831                         0x77ffc085, /* EMC_XM2CLKPADCTRL */
3832                         0x81f1f108, /* EMC_XM2COMPPADCTRL */
3833                         0x07077504, /* EMC_XM2VTTGENPADCTRL */
3834                         0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
3835                         0x0000003f, /* EMC_DSR_VTTGEN_DRV */
3836                         0x00000000, /* EMC_TXDSRVTTGEN */
3837                         0x02000000, /* EMC_FBIO_SPARE */
3838                         0x00000802, /* EMC_CTT_TERM_CTRL */
3839                         0x00020000, /* EMC_ZCAL_INTERVAL */
3840                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
3841                         0x0122000c, /* EMC_MRS_WAIT_CNT */
3842                         0x0122000c, /* EMC_MRS_WAIT_CNT2 */
3843                         0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
3844                         0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
3845                         0x00000000, /* EMC_CTT */
3846                         0x00000000, /* EMC_CTT_DURATION */
3847                         0x8000261a, /* EMC_DYN_SELF_REF_CONTROL */
3848                         0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
3849                         0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
3850                         0x06000009, /* MC_EMEM_ARB_CFG */
3851                         0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3852                         0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
3853                         0x00000004, /* MC_EMEM_ARB_TIMING_RP */
3854                         0x0000000f, /* MC_EMEM_ARB_TIMING_RC */
3855                         0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
3856                         0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */
3857                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3858                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3859                         0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3860                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3861                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3862                         0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
3863                         0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
3864                         0x07050202, /* MC_EMEM_ARB_DA_TURNS */
3865                         0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */
3866                         0x736a1d10, /* MC_EMEM_ARB_MISC0 */
3867                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3868                 },
3869                 {
3870                         0x00000000, /* EMC_CDB_CNTL_1 */
3871                         0x00000004, /* EMC_FBIO_CFG6 */
3872                         0x0000000b, /* EMC_QUSE */
3873                         0x00000008, /* EMC_EINPUT */
3874                         0x00000004, /* EMC_EINPUT_DURATION */
3875                         0x007fc00a, /* EMC_DLL_XFORM_DQS0 */
3876                         0x0000000c, /* EMC_QSAFE */
3877                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3878                         0x00000012, /* EMC_RDV */
3879                         0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
3880                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
3881                         0x00000009, /* EMC_DLL_XFORM_DQ0 */
3882                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3883                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
3884                         0x00000909, /* EMC_XM2CLKPADCTRL2 */
3885                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3886                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3887                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
3888                         0x007fc00a, /* EMC_DLL_XFORM_DQS1 */
3889                         0x007fc00a, /* EMC_DLL_XFORM_DQS2 */
3890                         0x007fc00a, /* EMC_DLL_XFORM_DQS3 */
3891                         0x00000009, /* EMC_DLL_XFORM_DQ1 */
3892                         0x00000009, /* EMC_DLL_XFORM_DQ2 */
3893                         0x00000009, /* EMC_DLL_XFORM_DQ3 */
3894                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3895                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3896                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3897                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3898                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3899                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3900                 },
3901                 {
3902                         0x00000000, /* EMC_CDB_CNTL_1 */
3903                         0x00000004, /* EMC_FBIO_CFG6 */
3904                         0x0000000b, /* EMC_QUSE */
3905                         0x00000008, /* EMC_EINPUT */
3906                         0x00000004, /* EMC_EINPUT_DURATION */
3907                         0x007fc00a, /* EMC_DLL_XFORM_DQS0 */
3908                         0x0000000c, /* EMC_QSAFE */
3909                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3910                         0x00000012, /* EMC_RDV */
3911                         0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
3912                         0x10410400, /* EMC_XM2DQSPADCTRL3 */
3913                         0x00000009, /* EMC_DLL_XFORM_DQ0 */
3914                         0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
3915                         0x00000000, /* EMC_DLL_XFORM_ADDR0 */
3916                         0x00000909, /* EMC_XM2CLKPADCTRL2 */
3917                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3918                         0x00000000, /* EMC_DLL_XFORM_ADDR1 */
3919                         0x00000000, /* EMC_DLL_XFORM_ADDR2 */
3920                         0x007fc00a, /* EMC_DLL_XFORM_DQS1 */
3921                         0x007fc00a, /* EMC_DLL_XFORM_DQS2 */
3922                         0x007fc00a, /* EMC_DLL_XFORM_DQS3 */
3923                         0x00000009, /* EMC_DLL_XFORM_DQ1 */
3924                         0x00000009, /* EMC_DLL_XFORM_DQ2 */
3925                         0x00000009, /* EMC_DLL_XFORM_DQ3 */
3926                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3927                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3928                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3929                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3930                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3931                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3932                 },
3933                 {
3934                         0x0000013f, /* MC_PTSA_GRANT_DECREMENT */
3935                         0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */
3936                         0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */
3937                         0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */
3938                         0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
3939                         0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */
3940                         0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */
3941                         0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */
3942                         0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */
3943                         0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */
3944                         0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */
3945                 },
3946                 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
3947                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3948                 0x53200000, /* EMC_CFG */
3949                 0x80000b61, /* Mode Register 0 */
3950                 0x80100002, /* Mode Register 1 */
3951                 0x80200010, /* Mode Register 2 */
3952                 0x00000000, /* Mode Register 4 */
3953                 1440,       /* expected dvfs latency (ns) */
3954         },
3955         {
3956                 0x41,       /* Rev 4.0.3 */
3957                 792000,     /* SDRAM frequency */
3958                 1100,       /* min voltage */
3959                 "pll_m",    /* clock source id */
3960                 0x80000000, /* CLK_SOURCE_EMC */
3961                 99,         /* number of burst_regs */
3962                 30,         /* number of trim_regs (each channel) */
3963                 11,         /* number of up_down_regs */
3964                 {
3965                         0x00000024, /* EMC_RC */
3966                         0x000000cd, /* EMC_RFC */
3967                         0x00000000, /* EMC_RFC_SLR */
3968                         0x00000019, /* EMC_RAS */
3969                         0x0000000a, /* EMC_RP */
3970                         0x00000009, /* EMC_R2W */
3971                         0x0000000d, /* EMC_W2R */
3972                         0x00000004, /* EMC_R2P */
3973                         0x00000013, /* EMC_W2P */
3974                         0x0000000a, /* EMC_RD_RCD */
3975                         0x0000000a, /* EMC_WR_RCD */
3976                         0x00000003, /* EMC_RRD */
3977                         0x00000001, /* EMC_REXT */
3978                         0x00000000, /* EMC_WEXT */
3979                         0x00000006, /* EMC_WDV */
3980                         0x00000006, /* EMC_WDV_MASK */
3981                         0x0000000b, /* EMC_IBDLY */
3982                         0x000d000a, /* EMC_PUTERM_EXTRA */
3983                         0x00000000, /* EMC_CDB_CNTL_2 */
3984                         0x00000008, /* EMC_QRST */
3985                         0x00000014, /* EMC_RDV_MASK */
3986                         0x000017e4, /* EMC_REFRESH */
3987                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3988                         0x000005f9, /* EMC_PRE_REFRESH_REQ_CNT */
3989                         0x00000003, /* EMC_PDEX2WR */
3990                         0x00000012, /* EMC_PDEX2RD */
3991                         0x00000001, /* EMC_PCHG2PDEN */
3992                         0x00000000, /* EMC_ACT2PDEN */
3993                         0x000000c6, /* EMC_AR2PDEN */
3994                         0x00000018, /* EMC_RW2PDEN */
3995                         0x000000d6, /* EMC_TXSR */
3996                         0x00000200, /* EMC_TXSRDLL */
3997                         0x00000005, /* EMC_TCKE */
3998                         0x00000005, /* EMC_TCKESR */
3999                         0x00000005, /* EMC_TPD */
4000                         0x00000020, /* EMC_TFAW */
4001                         0x00000000, /* EMC_TRPAB */
4002                         0x00000007, /* EMC_TCLKSTABLE */
4003                         0x00000008, /* EMC_TCLKSTOP */
4004                         0x00001825, /* EMC_TREFBW */
4005                         0x0000000a, /* EMC_QUSE_EXTRA */
4006                         0x80000020, /* EMC_ODT_WRITE */
4007                         0x00000000, /* EMC_ODT_READ */