2 * board-common.c: Implement function which is common across
5 * Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 #include <linux/clk.h>
23 #include <linux/serial_8250.h>
24 #include <linux/clk/tegra.h>
29 #include "board-common.h"
33 #include "cpu-tegra.h"
35 extern unsigned long debug_uart_port_base;
36 extern struct clk *debug_uart_clk;
38 struct platform_device *uart_console_debug_device = NULL;
40 struct platform_device vibrator_device = {
41 .name = "tegra-vibrator",
45 int tegra_vibrator_init(void)
47 return platform_device_register(&vibrator_device);
50 int uart_console_debug_init(int default_debug_port)
54 debug_port_id = get_tegra_uart_debug_port_id();
55 if (debug_port_id < 0)
56 debug_port_id = default_debug_port;
58 if (debug_port_id < 0) {
59 pr_warn("No debug console channel\n");
63 switch (debug_port_id) {
65 /* UARTA is the debug port. */
66 pr_info("Selecting UARTA as the debug console\n");
67 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
68 debug_uart_port_base = ((struct plat_serial8250_port *)(
69 debug_uarta_device.dev.platform_data))->mapbase;
70 uart_console_debug_device = &debug_uarta_device;
74 /* UARTB is the debug port. */
75 pr_info("Selecting UARTB as the debug console\n");
76 debug_uart_clk = clk_get_sys("serial8250.1", "uartb");
77 debug_uart_port_base = ((struct plat_serial8250_port *)(
78 debug_uartb_device.dev.platform_data))->mapbase;
79 uart_console_debug_device = &debug_uartb_device;
83 /* UARTC is the debug port. */
84 pr_info("Selecting UARTC as the debug console\n");
85 debug_uart_clk = clk_get_sys("serial8250.2", "uartc");
86 debug_uart_port_base = ((struct plat_serial8250_port *)(
87 debug_uartc_device.dev.platform_data))->mapbase;
88 uart_console_debug_device = &debug_uartc_device;
92 /* UARTD is the debug port. */
93 pr_info("Selecting UARTD as the debug console\n");
94 debug_uart_clk = clk_get_sys("serial8250.3", "uartd");
95 debug_uart_port_base = ((struct plat_serial8250_port *)(
96 debug_uartd_device.dev.platform_data))->mapbase;
97 uart_console_debug_device = &debug_uartd_device;
100 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
102 /* UARTE is the debug port. */
103 pr_info("Selecting UARTE as the debug console\n");
104 debug_uart_clk = clk_get_sys("serial8250.4", "uarte");
105 debug_uart_port_base = ((struct plat_serial8250_port *)(
106 debug_uarte_device.dev.platform_data))->mapbase;
107 uart_console_debug_device = &debug_uarte_device;
112 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
113 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
114 debug_uart_port_base = ((struct plat_serial8250_port *)(
115 debug_uarta_device.dev.platform_data))->mapbase;
116 uart_console_debug_device = &debug_uarta_device;
120 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
122 #ifndef CONFIG_COMMON_CLK
123 pr_info("The debug console clock name is %s\n",
124 debug_uart_clk->name);
126 c = tegra_get_clock_by_name("pll_p");
127 if (IS_ERR_OR_NULL(c))
128 pr_err("Not getting the parent clock pll_p\n");
130 clk_set_parent(debug_uart_clk, c);
132 tegra_clk_prepare_enable(debug_uart_clk);
133 clk_set_rate(debug_uart_clk, clk_get_rate(c));
135 pr_err("Not getting the clock for debug consolei %d\n",
138 return debug_port_id;
141 static void tegra_add_trip_points(struct thermal_trip_info *trips,
143 struct tegra_cooling_device *cdev_data)
146 struct thermal_trip_info *trip_state;
148 if (!trips || !num_trips || !cdev_data)
151 if (*num_trips + cdev_data->trip_temperatures_num > THERMAL_MAX_TRIPS) {
152 WARN(1, "%s: cooling device %s has too many trips\n",
153 __func__, cdev_data->cdev_type);
157 for (i = 0; i < cdev_data->trip_temperatures_num; i++) {
158 trip_state = &trips[*num_trips];
160 trip_state->cdev_type = cdev_data->cdev_type;
161 trip_state->trip_temp = cdev_data->trip_temperatures[i] * 1000;
162 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
163 trip_state->upper = trip_state->lower = i + 1;
164 trip_state->hysteresis = 1000;
170 void tegra_add_cdev_trips(struct thermal_trip_info *trips, int *num_trips)
172 tegra_add_trip_points(trips, num_trips, tegra_dvfs_get_cpu_vmin_cdev());
173 tegra_add_trip_points(trips, num_trips,
174 tegra_dvfs_get_core_vmin_cdev());
175 tegra_add_trip_points(trips, num_trips, tegra_dvfs_get_gpu_vmin_cdev());
178 void tegra_add_cpu_vmin_trips(struct thermal_trip_info *trips, int *num_trips)
180 tegra_add_trip_points(trips, num_trips,
181 tegra_dvfs_get_cpu_vmin_cdev());
184 void tegra_add_gpu_vmin_trips(struct thermal_trip_info *trips, int *num_trips)
186 tegra_add_trip_points(trips, num_trips,
187 tegra_dvfs_get_gpu_vmin_cdev());
190 void tegra_add_core_vmin_trips(struct thermal_trip_info *trips, int *num_trips)
192 tegra_add_trip_points(trips, num_trips,
193 tegra_dvfs_get_core_vmin_cdev());
196 void tegra_add_tj_trips(struct thermal_trip_info *trips, int *num_trips)
198 tegra_add_trip_points(trips, num_trips, tegra_dvfs_get_cpu_vmax_cdev());
199 tegra_add_trip_points(trips, num_trips, tegra_core_edp_get_cdev());
202 void tegra_add_tgpu_trips(struct thermal_trip_info *trips, int *num_trips)
204 tegra_add_trip_points(trips, num_trips, tegra_dvfs_get_gpu_vts_cdev());
207 void tegra_add_vc_trips(struct thermal_trip_info *trips, int *num_trips)
209 tegra_add_trip_points(trips, num_trips, tegra_vc_get_cdev());
211 void tegra_add_tpll_trips(struct thermal_trip_info *trips, int *num_trips)
213 tegra_add_trip_points(trips, num_trips,
214 tegra_dvfs_get_core_vmax_cdev());