arm: tegra: bonaire: register apb dma through board file
[linux-3.10.git] / arch / arm / mach-tegra / board-bonaire.c
1 /*
2  * arch/arm/mach-tegra/board-bonaire.c
3  *
4  * Copyright (c) 2013, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/spi/spi.h>
30 #include <linux/spi-tegra.h>
31 #include <linux/i2c/panjit_ts.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/i2c-tegra.h>
35 #include <linux/gpio.h>
36 #include <linux/gpio_keys.h>
37 #include <linux/input.h>
38 #include <linux/platform_data/tegra_usb.h>
39 #include <linux/tegra_uart.h>
40 #include <mach/clk.h>
41 #include <mach/gpio-tegra.h>
42 #include <mach/iomap.h>
43
44 #include <mach/io_dpd.h>
45
46 #include <mach/irqs.h>
47 #include <mach/pinmux.h>
48 #include <mach/iomap.h>
49 #include <mach/io.h>
50 #include <mach/i2s.h>
51 #include <mach/audio.h>
52 #include <mach/usb_phy.h>
53 #include <mach/nand.h>
54 #include <mach/pci.h>
55 #include <mach/hardware.h>
56
57 #include <asm/hardware/gic.h>
58 #include <asm/mach-types.h>
59 #include <asm/mach/arch.h>
60
61 #include "board.h"
62 #include "board-bonaire.h"
63 #include "clock.h"
64 #include "common.h"
65 #include "devices.h"
66 #include "fuse.h"
67 #include "gpio-names.h"
68
69 #define ENABLE_OTG 0
70 /*#define USB_HOST_ONLY*/
71
72 static struct plat_serial8250_port debug_uart_platform_data[] = {
73         {
74                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
75                 .mapbase        = TEGRA_UARTA_BASE,
76                 .irq            = INT_UARTA,
77                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
78                 .type           = PORT_TEGRA,
79                 .iotype         = UPIO_MEM,
80                 .regshift       = 2,
81                 .uartclk        = 13000000,
82         }, {
83                 .flags          = 0,
84         }
85 };
86
87 static struct platform_device debug_uart = {
88         .name = "serial8250",
89         .id = PLAT8250_DEV_PLATFORM,
90         .dev = {
91                 .platform_data = debug_uart_platform_data,
92         },
93 };
94
95 #ifdef CONFIG_BCM4329_RFKILL
96
97 static struct resource bonaire_bcm4329_rfkill_resources[] = {
98         {
99                 .name   = "bcm4329_nreset_gpio",
100                 .start  = TEGRA_GPIO_PU0,
101                 .end    = TEGRA_GPIO_PU0,
102                 .flags  = IORESOURCE_IO,
103         },
104         {
105                 .name   = "bcm4329_nshutdown_gpio",
106                 .start  = TEGRA_GPIO_PK2,
107                 .end    = TEGRA_GPIO_PK2,
108                 .flags  = IORESOURCE_IO,
109         },
110 };
111
112 static struct platform_device bonaire_bcm4329_rfkill_device = {
113         .name = "bcm4329_rfkill",
114         .id             = -1,
115         .num_resources  = ARRAY_SIZE(bonaire_bcm4329_rfkill_resources),
116         .resource       = bonaire_bcm4329_rfkill_resources,
117 };
118
119 static noinline void __init bonaire_bt_rfkill(void)
120 {
121         /*Add Clock Resource*/
122         clk_add_alias("bcm4329_32k_clk", bonaire_bcm4329_rfkill_device.name, \
123                                 "blink", NULL);
124
125         platform_device_register(&bonaire_bcm4329_rfkill_device);
126
127         return;
128 }
129 #else
130 static inline void bonaire_bt_rfkill(void) { }
131 #endif
132
133 static __initdata struct tegra_clk_init_table bonaire_clk_init_table[] = {
134         /* name         parent          rate            enabled */
135         { "uarta",      "clk_m",        13000000,       true},
136         { "uartb",      "clk_m",        13000000,       true},
137         { "uartc",      "clk_m",        13000000,       true},
138         { "uartd",      "clk_m",        13000000,       true},
139         { "uarte",      "clk_m",        13000000,       true},
140         { "sdmmc1",     "clk_m",        26000000,       false},
141         { "sdmmc3",     "clk_m",        26000000,       false},
142         { "sdmmc4",     "clk_m",        26000000,       false},
143         { "pll_m",      NULL,           0,              true},
144         { "blink",      "clk_32k",      32768,          false},
145         { "pll_p_out4", "pll_p",        24000000,       true },
146         { "pwm",        "clk_32k",      32768,          false},
147         { "blink",      "clk_32k",      32768,          false},
148         { "pll_a",      NULL,           56448000,       true},
149         { "pll_a_out0", NULL,           11289600,       true},
150         { "i2s1",       "pll_a_out0",   11289600,       true},
151         { "i2s2",       "pll_a_out0",   11289600,       true},
152         { "d_audio",    "pll_a_out0",   11289600,       false},
153         { "audio_2x",   "audio",        22579200,       true},
154         { NULL,         NULL,           0,              0},
155 };
156
157 static struct i2c_board_info __initdata bonaire_i2c_bus1_board_info[] = {
158         {
159                 I2C_BOARD_INFO("wm8903", 0x1a),
160         },
161 };
162
163 static struct tegra_i2c_platform_data bonaire_i2c1_platform_data = {
164         .bus_clk_rate   = 100000,
165 };
166
167 #if 0   /* !!!FIXME!!! THESE ARE VENTANA SETTINGS */
168 static const struct tegra_pingroup_config i2c2_ddc = {
169         .pingroup       = TEGRA_PINGROUP_DDC,
170         .func           = TEGRA_MUX_I2C2,
171 };
172
173 static const struct tegra_pingroup_config i2c2_gen2 = {
174         .pingroup       = TEGRA_PINGROUP_PTA,
175         .func           = TEGRA_MUX_I2C2,
176 };
177 #endif
178
179 static struct tegra_i2c_platform_data bonaire_i2c2_platform_data = {
180         .bus_clk_rate   = 100000,
181 #if 0   /* !!!FIXME!!!! TESE ARE VENTANA SETTINGS */
182         .bus_mux        = { &i2c2_ddc, &i2c2_gen2 },
183         .bus_mux_len    = { 1, 1 },
184 #endif
185 };
186
187 static struct tegra_i2c_platform_data bonaire_i2c3_platform_data = {
188         .bus_clk_rate   = 100000,
189 };
190
191 static struct tegra_i2c_platform_data bonaire_i2c4_platform_data = {
192         .bus_clk_rate   = 100000,
193 };
194
195 static struct tegra_i2c_platform_data bonaire_i2c5_platform_data = {
196         .bus_clk_rate   = 100000,
197 };
198
199 static struct tegra_i2c_platform_data bonaire_i2c6_platform_data = {
200         .bus_clk_rate   = 100000,
201 };
202
203 static void bonaire_i2c_init(void)
204 {
205         tegra14_i2c_device1.dev.platform_data = &bonaire_i2c1_platform_data;
206         tegra14_i2c_device2.dev.platform_data = &bonaire_i2c2_platform_data;
207         tegra14_i2c_device3.dev.platform_data = &bonaire_i2c3_platform_data;
208         tegra14_i2c_device4.dev.platform_data = &bonaire_i2c4_platform_data;
209         tegra14_i2c_device5.dev.platform_data = &bonaire_i2c5_platform_data;
210         tegra14_i2c_device6.dev.platform_data = &bonaire_i2c6_platform_data;
211
212         i2c_register_board_info(0, bonaire_i2c_bus1_board_info, 1);
213
214         platform_device_register(&tegra14_i2c_device6);
215         platform_device_register(&tegra14_i2c_device5);
216         platform_device_register(&tegra14_i2c_device4);
217         platform_device_register(&tegra14_i2c_device3);
218         platform_device_register(&tegra14_i2c_device2);
219         platform_device_register(&tegra14_i2c_device1);
220 }
221
222 static void bonaire_apbdma_init(void)
223 {
224         platform_device_register(&tegra_apbdma);
225 }
226
227 static struct platform_device *bonaire_spi_devices[] __initdata = {
228         &tegra11_spi_device4,
229 };
230
231 struct spi_clk_parent spi_parent_clk_bonaire[] = {
232         [0] = {.name = "pll_p"},
233 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
234         [1] = {.name = "pll_m"},
235         [2] = {.name = "clk_m"},
236 #else
237         [1] = {.name = "clk_m"},
238 #endif
239 };
240
241 static struct tegra_spi_platform_data bonaire_spi_pdata = {
242         .is_dma_based           = true,
243         .max_dma_buffer         = 16 * 1024,
244         .is_clkon_always        = false,
245         .max_rate               = 25000000,
246 };
247
248 static void __init bonaire_spi_init(void)
249 {
250         int i;
251         struct clk *c;
252         struct board_info board_info, display_board_info;
253
254         tegra_get_board_info(&board_info);
255         tegra_get_display_board_info(&display_board_info);
256
257         for (i = 0; i < ARRAY_SIZE(spi_parent_clk_bonaire); ++i) {
258                 c = tegra_get_clock_by_name(spi_parent_clk_bonaire[i].name);
259                 if (IS_ERR_OR_NULL(c)) {
260                         pr_err("Not able to get the clock for %s\n",
261                                         spi_parent_clk_bonaire[i].name);
262                 continue;
263                 }
264                 spi_parent_clk_bonaire[i].parent_clk = c;
265                 spi_parent_clk_bonaire[i].fixed_clk_rate = clk_get_rate(c);
266         }
267         bonaire_spi_pdata.parent_clk_list = spi_parent_clk_bonaire;
268         bonaire_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk_bonaire);
269         tegra11_spi_device4.dev.platform_data = &bonaire_spi_pdata;
270         platform_add_devices(bonaire_spi_devices,
271                         ARRAY_SIZE(bonaire_spi_devices));
272 }
273
274 #define GPIO_KEY(_id, _gpio, _iswake)           \
275         {                                       \
276                 .code = _id,                    \
277                 .gpio = TEGRA_GPIO_##_gpio,     \
278                 .active_low = 1,                \
279                 .desc = #_id,                   \
280                 .type = EV_KEY,                 \
281                 .wakeup = _iswake,              \
282                 .debounce_interval = 10,        \
283         }
284
285 /* !!!FIXME!!! THESE ARE VENTANA DEFINITIONS */
286 static struct gpio_keys_button bonaire_keys[] = {
287         [0] = GPIO_KEY(KEY_MENU, PQ0, 0),
288         [1] = GPIO_KEY(KEY_HOME, PQ1, 0),
289         [2] = GPIO_KEY(KEY_BACK, PQ2, 0),
290         [3] = GPIO_KEY(KEY_VOLUMEUP, PQ3, 0),
291         [4] = GPIO_KEY(KEY_VOLUMEDOWN, PQ4, 0),
292         [5] = GPIO_KEY(KEY_POWER, PV2, 1),
293 };
294
295 static struct gpio_keys_platform_data bonaire_keys_platform_data = {
296         .buttons        = bonaire_keys,
297         .nbuttons       = ARRAY_SIZE(bonaire_keys),
298 };
299
300 static struct platform_device bonaire_keys_device = {
301         .name   = "gpio-keys",
302         .id     = 0,
303         .dev    = {
304                 .platform_data  = &bonaire_keys_platform_data,
305         },
306 };
307
308 static struct resource tegra_rtc_resources[] = {
309         [0] = {
310                 .start = TEGRA_RTC_BASE,
311                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
312                 .flags = IORESOURCE_MEM,
313         },
314         [1] = {
315                 .start = INT_RTC,
316                 .end = INT_RTC,
317                 .flags = IORESOURCE_IRQ,
318         },
319 };
320
321 static struct platform_device tegra_rtc_device = {
322         .name = "tegra_rtc",
323         .id   = -1,
324         .resource = tegra_rtc_resources,
325         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
326 };
327
328 #if defined(CONFIG_MTD_NAND_TEGRA)
329 static struct resource nand_resources[] = {
330         [0] = {
331                 .start = INT_NANDFLASH,
332                 .end   = INT_NANDFLASH,
333                 .flags = IORESOURCE_IRQ
334         },
335         [1] = {
336                 .start = TEGRA_NAND_BASE,
337                 .end = TEGRA_NAND_BASE + TEGRA_NAND_SIZE - 1,
338                 .flags = IORESOURCE_MEM
339         }
340 };
341
342 static struct tegra_nand_chip_parms nand_chip_parms[] = {
343         /* Samsung K5E2G1GACM */
344         [0] = {
345                 .vendor_id   = 0xEC,
346                 .device_id   = 0xAA,
347                 .capacity    = 256,
348                 .timing      = {
349                         .trp            = 21,
350                         .trh            = 15,
351                         .twp            = 21,
352                         .twh            = 15,
353                         .tcs            = 31,
354                         .twhr           = 60,
355                         .tcr_tar_trr    = 20,
356                         .twb            = 100,
357                         .trp_resp       = 30,
358                         .tadl           = 100,
359                 },
360         },
361         /* Hynix H5PS1GB3EFR */
362         [1] = {
363                 .vendor_id   = 0xAD,
364                 .device_id   = 0xDC,
365                 .capacity    = 512,
366                 .timing      = {
367                         .trp            = 12,
368                         .trh            = 10,
369                         .twp            = 12,
370                         .twh            = 10,
371                         .tcs            = 20,
372                         .twhr           = 80,
373                         .tcr_tar_trr    = 20,
374                         .twb            = 100,
375                         .trp_resp       = 20,
376                         .tadl           = 70,
377                 },
378         },
379 };
380
381 struct tegra_nand_platform nand_data = {
382         .max_chips      = 8,
383         .chip_parms     = nand_chip_parms,
384         .nr_chip_parms  = ARRAY_SIZE(nand_chip_parms),
385 };
386
387 struct platform_device tegra_nand_device = {
388         .name          = "tegra_nand",
389         .id            = -1,
390         .resource      = nand_resources,
391         .num_resources = ARRAY_SIZE(nand_resources),
392         .dev            = {
393                 .platform_data = &nand_data,
394         },
395 };
396 #endif
397
398 static struct platform_device *bonaire_devices[] __initdata = {
399 #if ENABLE_OTG
400         &tegra_otg_device,
401 #endif
402         &debug_uart,
403         &tegra_pmu_device,
404         &tegra_rtc_device,
405 #if !defined(USB_HOST_ONLY)
406         &tegra_udc_device,
407 #endif
408 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
409         &tegra11_se_device,
410 #endif
411 #if defined(CONFIG_TEGRA_IOVMM_SMMU)
412         &tegra_smmu_device,
413 #endif
414         &bonaire_keys_device,
415 #if defined(CONFIG_SND_HDA_TEGRA)
416         &tegra_hda_device,
417 #endif
418         &tegra_avp_device,
419 #if defined(CONFIG_MTD_NAND_TEGRA)
420         &tegra_nand_device,
421 #endif
422 };
423
424 static int __init bonaire_touch_init(void)
425 {
426         return 0;
427 }
428
429 static struct tegra_usb_platform_data tegra_udc_pdata = {
430         .port_otg = false,
431         .has_hostpc = true,
432         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
433         .op_mode = TEGRA_USB_OPMODE_DEVICE,
434         .u_data.dev = {
435                 .vbus_pmu_irq = 0,
436                 .vbus_gpio = -1,
437                 .charging_supported = false,
438                 .remote_wakeup_supported = false,
439         },
440         .u_cfg.utmi = {
441                 .hssync_start_delay = 0,
442                 .elastic_limit = 16,
443                 .idle_wait_delay = 17,
444                 .term_range_adj = 6,
445                 .xcvr_setup = 8,
446                 .xcvr_lsfslew = 2,
447                 .xcvr_lsrslew = 2,
448                 .xcvr_setup_offset = 0,
449                 .xcvr_use_fuses = 1,
450         },
451 };
452
453 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
454         .port_otg = false,
455         .has_hostpc = true,
456         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
457         .op_mode = TEGRA_USB_OPMODE_HOST,
458         .u_data.host = {
459                 .vbus_gpio = -1,
460                 /*.vbus_reg = "vdd_vbus_micro_usb",*/
461                 .hot_plug = true,
462                 .remote_wakeup_supported = true,
463                 .power_off_on_suspend = true,
464         },
465         .u_cfg.utmi = {
466                 .hssync_start_delay = 0,
467                 .elastic_limit = 16,
468                 .idle_wait_delay = 17,
469                 .term_range_adj = 6,
470                 .xcvr_setup = 15,
471                 .xcvr_lsfslew = 2,
472                 .xcvr_lsrslew = 2,
473                 .xcvr_setup_offset = 0,
474                 .xcvr_use_fuses = 1,
475         },
476 };
477
478 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
479         .port_otg = false,
480         .has_hostpc = true,
481         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
482         .op_mode         = TEGRA_USB_OPMODE_HOST,
483         .u_data.host = {
484                 .vbus_gpio = -1,
485                 .hot_plug = true,
486                 .remote_wakeup_supported = true,
487                 .power_off_on_suspend = true,
488         },
489         .u_cfg.utmi = {
490                 .hssync_start_delay = 0,
491                 .elastic_limit = 16,
492                 .idle_wait_delay = 17,
493                 .term_range_adj = 6,
494                 .xcvr_setup = 15,
495                 .xcvr_lsfslew = 2,
496                 .xcvr_lsrslew = 2,
497                 .xcvr_setup_offset = 0,
498                 .xcvr_use_fuses = 1,
499         },
500 };
501
502 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
503         .port_otg = false,
504         .has_hostpc = true,
505         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
506         .op_mode         = TEGRA_USB_OPMODE_HOST,
507         .u_data.host = {
508                 .vbus_gpio = -1,
509                 /*.vbus_reg = "vdd_vbus_typea_usb",*/
510                 .hot_plug = true,
511                 .remote_wakeup_supported = true,
512                 .power_off_on_suspend = true,
513         },
514         .u_cfg.utmi = {
515                 .hssync_start_delay = 0,
516                 .elastic_limit = 16,
517                 .idle_wait_delay = 17,
518                 .term_range_adj = 6,
519                 .xcvr_setup = 8,
520                 .xcvr_lsfslew = 2,
521                 .xcvr_lsrslew = 2,
522                 .xcvr_setup_offset = 0,
523                 .xcvr_use_fuses = 1,
524         },
525 };
526
527 static void bonaire_usb_init(void)
528 {
529 #if defined(USB_HOST_ONLY)
530         tegra_ehci1_device.dev.platform_data = &tegra_ehci1_utmi_pdata;
531         platform_device_register(&tegra_ehci1_device);
532 #else
533         /* setup the udc platform data */
534         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
535
536 #endif
537 }
538
539 static struct platform_device *bonaire_hs_uart_devices[] __initdata = {
540         &tegra_uartd_device, &tegra_uartb_device, &tegra_uartc_device,
541 };
542
543 static struct uart_clk_parent uart_parent_clk[] = {
544         [0] = {.name = "clk_m"},
545 };
546
547 static struct tegra_uart_platform_data bonaire_uart_pdata;
548 static struct tegra_uart_platform_data bonaire_loopback_uart_pdata;
549
550 static void __init bonaire_hs_uart_init(void)
551 {
552         struct clk *c;
553         int i;
554
555         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
556                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
557                 if (IS_ERR_OR_NULL(c)) {
558                         pr_err("Not able to get the clock for %s\n",
559                                         uart_parent_clk[i].name);
560                         continue;
561                 }
562                 uart_parent_clk[i].parent_clk = c;
563                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
564         }
565         bonaire_uart_pdata.parent_clk_list = uart_parent_clk;
566         bonaire_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
567         bonaire_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
568         bonaire_loopback_uart_pdata.parent_clk_count =
569                 ARRAY_SIZE(uart_parent_clk);
570         bonaire_loopback_uart_pdata.is_loopback = true;
571         tegra_uartb_device.dev.platform_data = &bonaire_uart_pdata;
572         tegra_uartc_device.dev.platform_data = &bonaire_uart_pdata;
573         tegra_uartd_device.dev.platform_data = &bonaire_uart_pdata;
574         platform_add_devices(bonaire_hs_uart_devices,
575                         ARRAY_SIZE(bonaire_hs_uart_devices));
576 }
577
578 static struct tegra_pci_platform_data bonaire_pcie_platform_data = {
579         .port_status[0] = 1,
580         .port_status[1] = 1,
581         .use_dock_detect        = 0,
582         .gpio                   = 0,
583 };
584
585 static void bonaire_pcie_init(void)
586 {
587         tegra_pci_device.dev.platform_data = &bonaire_pcie_platform_data;
588         platform_device_register(&tegra_pci_device);
589 }
590
591 static void __init tegra_bonaire_init(void)
592 {
593         tegra_clk_init_from_table(bonaire_clk_init_table);
594         tegra_enable_pinmux();
595         bonaire_pinmux_init();
596         tegra_soc_device_init("bonaire");
597         bonaire_apbdma_init();
598
599 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
600         if (tegra_platform_is_qt())
601                 debug_uart_platform_data[0].uartclk =
602                                                 tegra_clk_measure_input_freq();
603 #endif
604
605         platform_add_devices(bonaire_devices, ARRAY_SIZE(bonaire_devices));
606
607 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
608         bonaire_power_off_init();
609 #endif
610         tegra_io_dpd_init();
611         bonaire_hs_uart_init();
612         bonaire_sdhci_init();
613         bonaire_i2c_init();
614         bonaire_spi_init();
615         bonaire_regulator_init();
616         bonaire_suspend_init();
617         bonaire_touch_init();
618         bonaire_usb_init();
619         bonaire_panel_init();
620         bonaire_bt_rfkill();
621         bonaire_pcie_init();
622 }
623
624 static void __init tegra_bonaire_reserve(void)
625 {
626 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
627         tegra_reserve(0, SZ_4M, 0);
628 #else
629 #if defined(CONFIG_TEGRA_SIMULATION_SPLIT_MEM)
630         if (tegra_split_mem_active())
631                 tegra_reserve(0, 0, 0);
632         else
633 #endif
634                 tegra_reserve(SZ_128M, SZ_4M, 0);
635 #endif
636 }
637
638 static const char * const bonaire_dt_board_compat[] = {
639         "nvidia,bonaire",
640         NULL
641 };
642
643 MACHINE_START(BONAIRE, BONAIRE_BOARD_NAME)
644         .atag_offset    = 0x80000100,
645         .map_io         = tegra_map_common_io,
646         .reserve        = tegra_bonaire_reserve,
647         .init_early     = tegra12x_init_early,
648         .init_irq       = tegra_dt_init_irq,
649         .handle_irq     = gic_handle_irq,
650         .init_machine   = tegra_bonaire_init,
651         .timer          = &tegra_sys_timer,
652         .dt_compat      = bonaire_dt_board_compat,
653 MACHINE_END