2 * arch/arm/mach-tegra/board-bonaire.c
4 * Copyright (c) 2013, NVIDIA Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/gpio_keys.h>
35 #include <linux/input.h>
36 #include <linux/platform_data/tegra_usb.h>
37 #include <linux/tegra_uart.h>
39 #include <mach/gpio-tegra.h>
40 #include <mach/iomap.h>
42 #include <mach/io_dpd.h>
44 #include <mach/irqs.h>
45 #include <mach/pinmux.h>
46 #include <mach/iomap.h>
49 #include <mach/audio.h>
50 #include <mach/usb_phy.h>
51 #include <mach/nand.h>
52 #include <mach/hardware.h>
54 #include <asm/hardware/gic.h>
55 #include <asm/mach-types.h>
56 #include <asm/mach/arch.h>
59 #include "board-bonaire.h"
64 #include "gpio-names.h"
68 static struct plat_serial8250_port debug_uart_platform_data[] = {
70 .membase = IO_ADDRESS(TEGRA_UARTA_BASE),
71 .mapbase = TEGRA_UARTA_BASE,
73 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
83 static struct platform_device debug_uart = {
85 .id = PLAT8250_DEV_PLATFORM,
87 .platform_data = debug_uart_platform_data,
91 #ifdef CONFIG_BCM4329_RFKILL
93 static struct resource bonaire_bcm4329_rfkill_resources[] = {
95 .name = "bcm4329_nreset_gpio",
96 .start = TEGRA_GPIO_PU0,
97 .end = TEGRA_GPIO_PU0,
98 .flags = IORESOURCE_IO,
101 .name = "bcm4329_nshutdown_gpio",
102 .start = TEGRA_GPIO_PK2,
103 .end = TEGRA_GPIO_PK2,
104 .flags = IORESOURCE_IO,
108 static struct platform_device bonaire_bcm4329_rfkill_device = {
109 .name = "bcm4329_rfkill",
111 .num_resources = ARRAY_SIZE(bonaire_bcm4329_rfkill_resources),
112 .resource = bonaire_bcm4329_rfkill_resources,
115 static noinline void __init bonaire_bt_rfkill(void)
117 /*Add Clock Resource*/
118 clk_add_alias("bcm4329_32k_clk", bonaire_bcm4329_rfkill_device.name, \
121 platform_device_register(&bonaire_bcm4329_rfkill_device);
126 static inline void bonaire_bt_rfkill(void) { }
129 static __initdata struct tegra_clk_init_table bonaire_clk_init_table[] = {
130 /* name parent rate enabled */
131 { "uarta", "clk_m", 13000000, true},
132 { "uartb", "clk_m", 13000000, true},
133 { "uartc", "clk_m", 13000000, true},
134 { "uartd", "clk_m", 13000000, true},
135 { "uarte", "clk_m", 13000000, true},
136 { "pll_m", NULL, 0, true},
137 { "blink", "clk_32k", 32768, false},
138 { "pll_p_out4", "pll_p", 24000000, true },
139 { "pwm", "clk_32k", 32768, false},
140 { "blink", "clk_32k", 32768, false},
141 { "pll_a", NULL, 56448000, true},
142 { "pll_a_out0", NULL, 11289600, true},
143 { "i2s1", "pll_a_out0", 11289600, true},
144 { "i2s2", "pll_a_out0", 11289600, true},
145 { "d_audio", "pll_a_out0", 11289600, false},
146 { "audio_2x", "audio", 22579200, true},
150 static struct i2c_board_info __initdata bonaire_i2c_bus1_board_info[] = {
152 I2C_BOARD_INFO("wm8903", 0x1a),
156 static struct tegra_i2c_platform_data bonaire_i2c1_platform_data = {
159 .bus_clk_rate = { 100000, 0 },
162 #if 0 /* !!!FIXME!!! THESE ARE VENTANA SETTINGS */
163 static const struct tegra_pingroup_config i2c2_ddc = {
164 .pingroup = TEGRA_PINGROUP_DDC,
165 .func = TEGRA_MUX_I2C2,
168 static const struct tegra_pingroup_config i2c2_gen2 = {
169 .pingroup = TEGRA_PINGROUP_PTA,
170 .func = TEGRA_MUX_I2C2,
174 static struct tegra_i2c_platform_data bonaire_i2c2_platform_data = {
177 .bus_clk_rate = { 100000, 100000 },
178 #if 0 /* !!!FIXME!!!! TESE ARE VENTANA SETTINGS */
179 .bus_mux = { &i2c2_ddc, &i2c2_gen2 },
180 .bus_mux_len = { 1, 1 },
184 static struct tegra_i2c_platform_data bonaire_i2c3_platform_data = {
187 .bus_clk_rate = { 100000, 0 },
190 static struct tegra_i2c_platform_data bonaire_i2c4_platform_data = {
193 .bus_clk_rate = { 100000, 0 },
196 static struct tegra_i2c_platform_data bonaire_i2c5_platform_data = {
199 .bus_clk_rate = { 100000, 0 },
202 static void bonaire_i2c_init(void)
204 tegra_i2c_device1.dev.platform_data = &bonaire_i2c1_platform_data;
205 tegra_i2c_device2.dev.platform_data = &bonaire_i2c2_platform_data;
206 tegra_i2c_device3.dev.platform_data = &bonaire_i2c3_platform_data;
207 tegra_i2c_device4.dev.platform_data = &bonaire_i2c4_platform_data;
208 tegra_i2c_device5.dev.platform_data = &bonaire_i2c5_platform_data;
210 i2c_register_board_info(0, bonaire_i2c_bus1_board_info, 1);
212 platform_device_register(&tegra_i2c_device5);
213 platform_device_register(&tegra_i2c_device4);
214 platform_device_register(&tegra_i2c_device3);
215 platform_device_register(&tegra_i2c_device2);
216 platform_device_register(&tegra_i2c_device1);
219 #define GPIO_KEY(_id, _gpio, _iswake) \
222 .gpio = TEGRA_GPIO_##_gpio, \
227 .debounce_interval = 10, \
230 /* !!!FIXME!!! THESE ARE VENTANA DEFINITIONS */
231 static struct gpio_keys_button bonaire_keys[] = {
232 [0] = GPIO_KEY(KEY_MENU, PQ0, 0),
233 [1] = GPIO_KEY(KEY_HOME, PQ1, 0),
234 [2] = GPIO_KEY(KEY_BACK, PQ2, 0),
235 [3] = GPIO_KEY(KEY_VOLUMEUP, PQ3, 0),
236 [4] = GPIO_KEY(KEY_VOLUMEDOWN, PQ4, 0),
237 [5] = GPIO_KEY(KEY_POWER, PV2, 1),
240 static struct gpio_keys_platform_data bonaire_keys_platform_data = {
241 .buttons = bonaire_keys,
242 .nbuttons = ARRAY_SIZE(bonaire_keys),
245 static struct platform_device bonaire_keys_device = {
249 .platform_data = &bonaire_keys_platform_data,
253 static struct resource tegra_rtc_resources[] = {
255 .start = TEGRA_RTC_BASE,
256 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
257 .flags = IORESOURCE_MEM,
262 .flags = IORESOURCE_IRQ,
266 static struct platform_device tegra_rtc_device = {
269 .resource = tegra_rtc_resources,
270 .num_resources = ARRAY_SIZE(tegra_rtc_resources),
273 #if defined(CONFIG_MTD_NAND_TEGRA)
274 static struct resource nand_resources[] = {
276 .start = INT_NANDFLASH,
277 .end = INT_NANDFLASH,
278 .flags = IORESOURCE_IRQ
281 .start = TEGRA_NAND_BASE,
282 .end = TEGRA_NAND_BASE + TEGRA_NAND_SIZE - 1,
283 .flags = IORESOURCE_MEM
287 static struct tegra_nand_chip_parms nand_chip_parms[] = {
288 /* Samsung K5E2G1GACM */
306 /* Hynix H5PS1GB3EFR */
326 struct tegra_nand_platform nand_data = {
328 .chip_parms = nand_chip_parms,
329 .nr_chip_parms = ARRAY_SIZE(nand_chip_parms),
332 struct platform_device tegra_nand_device = {
333 .name = "tegra_nand",
335 .resource = nand_resources,
336 .num_resources = ARRAY_SIZE(nand_resources),
338 .platform_data = &nand_data,
343 #if defined(CONFIG_TEGRA_SIMULATION_PLATFORM) && defined(CONFIG_SMC91X)
344 static struct resource tegra_sim_smc91x_resources[] = {
346 .start = TEGRA_SIM_ETH_BASE,
347 .end = TEGRA_SIM_ETH_BASE + TEGRA_SIM_ETH_SIZE - 1,
348 .flags = IORESOURCE_MEM,
353 .flags = IORESOURCE_IRQ,
357 static struct platform_device tegra_sim_smc91x_device = {
360 .num_resources = ARRAY_SIZE(tegra_sim_smc91x_resources),
361 .resource = tegra_sim_smc91x_resources,
365 static struct platform_device *bonaire_devices[] __initdata = {
373 #if defined(CONFIG_TEGRA_IOVMM_SMMU)
376 &bonaire_keys_device,
377 #if defined(CONFIG_SND_HDA_TEGRA)
381 #if defined(CONFIG_MTD_NAND_TEGRA)
384 #if defined(CONFIG_TEGRA_SIMULATION_PLATFORM) && defined(CONFIG_SMC91X)
385 &tegra_sim_smc91x_device,
389 static int __init bonaire_touch_init(void)
394 #if defined(USB_HOST_ONLY)
395 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
397 .phy_config = &utmi_phy_config[0],
398 .operating_mode = TEGRA_USB_HOST,
399 .power_down_on_bus_suspend = 0,
402 .phy_config = &ulpi_phy_config,
403 .operating_mode = TEGRA_USB_HOST,
404 .power_down_on_bus_suspend = 1,
407 .phy_config = &utmi_phy_config[1],
408 .operating_mode = TEGRA_USB_HOST,
409 .power_down_on_bus_suspend = 0,
414 static struct tegra_usb_platform_data tegra_udc_pdata = {
417 .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
418 .op_mode = TEGRA_USB_OPMODE_DEVICE,
422 .charging_supported = false,
423 .remote_wakeup_supported = false,
426 .hssync_start_delay = 0,
428 .idle_wait_delay = 17,
433 .xcvr_setup_offset = 0,
438 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
441 .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
442 .op_mode = TEGRA_USB_OPMODE_HOST,
445 /*.vbus_reg = "vdd_vbus_micro_usb",*/
447 .remote_wakeup_supported = true,
448 .power_off_on_suspend = true,
451 .hssync_start_delay = 0,
453 .idle_wait_delay = 17,
458 .xcvr_setup_offset = 0,
463 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
466 .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
467 .op_mode = TEGRA_USB_OPMODE_HOST,
471 .remote_wakeup_supported = true,
472 .power_off_on_suspend = true,
475 .hssync_start_delay = 0,
477 .idle_wait_delay = 17,
482 .xcvr_setup_offset = 0,
487 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
490 .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
491 .op_mode = TEGRA_USB_OPMODE_HOST,
494 /*.vbus_reg = "vdd_vbus_typea_usb",*/
496 .remote_wakeup_supported = true,
497 .power_off_on_suspend = true,
500 .hssync_start_delay = 0,
502 .idle_wait_delay = 17,
507 .xcvr_setup_offset = 0,
512 static void bonaire_usb_init(void)
514 #if defined(USB_HOST_ONLY)
515 tegra_ehci1_device.dev.platform_data = &tegra_ehci1_utmi_pdata;
516 platform_device_register(&tegra_ehci1_device);
518 /* setup the udc platform data */
519 tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
523 static struct platform_device *bonaire_hs_uart_devices[] __initdata = {
524 &tegra_uartd_device, &tegra_uartb_device, &tegra_uartc_device,
527 static struct uart_clk_parent uart_parent_clk[] = {
528 [0] = {.name = "clk_m"},
531 static struct tegra_uart_platform_data bonaire_uart_pdata;
532 static struct tegra_uart_platform_data bonaire_loopback_uart_pdata;
534 static void __init bonaire_hs_uart_init(void)
539 for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
540 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
541 if (IS_ERR_OR_NULL(c)) {
542 pr_err("Not able to get the clock for %s\n",
543 uart_parent_clk[i].name);
546 uart_parent_clk[i].parent_clk = c;
547 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
549 bonaire_uart_pdata.parent_clk_list = uart_parent_clk;
550 bonaire_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
551 bonaire_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
552 bonaire_loopback_uart_pdata.parent_clk_count =
553 ARRAY_SIZE(uart_parent_clk);
554 bonaire_loopback_uart_pdata.is_loopback = true;
555 tegra_uartb_device.dev.platform_data = &bonaire_uart_pdata;
556 tegra_uartc_device.dev.platform_data = &bonaire_uart_pdata;
557 tegra_uartd_device.dev.platform_data = &bonaire_uart_pdata;
558 platform_add_devices(bonaire_hs_uart_devices,
559 ARRAY_SIZE(bonaire_hs_uart_devices));
562 static void __init tegra_bonaire_init(void)
564 tegra_clk_init_from_table(bonaire_clk_init_table);
565 tegra_enable_pinmux();
566 bonaire_pinmux_init();
567 tegra_soc_device_init("bonaire");
569 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
570 if (tegra_platform_is_qt())
571 debug_uart_platform_data[0].uartclk =
572 tegra_clk_measure_input_freq();
575 platform_add_devices(bonaire_devices, ARRAY_SIZE(bonaire_devices));
577 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
578 bonaire_power_off_init();
581 bonaire_hs_uart_init();
582 bonaire_sdhci_init();
584 bonaire_regulator_init();
585 bonaire_suspend_init();
586 bonaire_touch_init();
588 bonaire_panel_init();
592 static void __init tegra_bonaire_reserve(void)
594 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
595 tegra_reserve(0, SZ_4M, 0);
597 #if defined(CONFIG_TEGRA_SIMULATION_SPLIT_MEM)
598 if (tegra_split_mem_active())
599 tegra_reserve(0, 0, 0);
602 tegra_reserve(SZ_128M, SZ_4M, 0);
607 MACHINE_START(BONAIRE, BONAIRE_BOARD_NAME)
608 .atag_offset = 0x80000100,
609 .map_io = tegra_map_common_io,
610 .reserve = tegra_bonaire_reserve,
611 .init_early = tegra12x_init_early,
612 .init_irq = tegra_dt_init_irq,
613 .handle_irq = gic_handle_irq,
614 .init_machine = tegra_bonaire_init,
615 .timer = &tegra_sys_timer,