xhci: tegra: support HSIC ports
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c.h>
28 #include <linux/i2c/i2c-hid.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/delay.h>
31 #include <linux/i2c-tegra.h>
32 #include <linux/gpio.h>
33 #include <linux/input.h>
34 #include <linux/platform_data/tegra_usb.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/rm31080a_ts.h>
37 #include <linux/tegra_uart.h>
38 #include <linux/memblock.h>
39 #include <linux/spi/spi-tegra.h>
40 #include <linux/nfc/pn544.h>
41 #include <linux/rfkill-gpio.h>
42 #include <linux/skbuff.h>
43 #include <linux/ti_wilink_st.h>
44 #include <linux/regulator/consumer.h>
45 #include <linux/smb349-charger.h>
46 #include <linux/max17048_battery.h>
47 #include <linux/leds.h>
48 #include <linux/i2c/at24.h>
49 #include <linux/of_platform.h>
50 #include <linux/i2c.h>
51 #include <linux/i2c-tegra.h>
52 #include <linux/tegra_uart.h>
53 #include <linux/serial_tegra.h>
54 #include <linux/edp.h>
55 #include <linux/usb/tegra_usb_phy.h>
56 #include <linux/mfd/palmas.h>
57
58 #include <mach/clk.h>
59 #include <mach/irqs.h>
60 #include <mach/pci.h>
61 #include <mach/tegra_fiq_debugger.h>
62
63 #include <mach/pinmux.h>
64 #include <mach/pinmux-t12.h>
65 #include <mach/io_dpd.h>
66 #include <mach/i2s.h>
67 #include <mach/isomgr.h>
68 #include <mach/tegra_asoc_pdata.h>
69 #include <asm/mach-types.h>
70 #include <asm/mach/arch.h>
71 #include <mach/gpio-tegra.h>
72 #include <mach/tegra_fiq_debugger.h>
73 #include <mach/xusb.h>
74 #include <linux/platform_data/tegra_usb_modem_power.h>
75
76 #include "board.h"
77 #include "board-ardbeg.h"
78 #include "board-common.h"
79 #include "board-touch-raydium.h"
80 #include "clock.h"
81 #include "common.h"
82 #include "devices.h"
83 #include "fuse.h"
84 #include "gpio-names.h"
85 #include "iomap.h"
86 #include "pm.h"
87 #include "pm-irq.h"
88 #include "tegra-board-id.h"
89
90 static struct board_info board_info, display_board_info;
91
92 static struct resource ardbeg_bluedroid_pm_resources[] = {
93         [0] = {
94                 .name   = "shutdown_gpio",
95                 .start  = TEGRA_GPIO_PR1,
96                 .end    = TEGRA_GPIO_PR1,
97                 .flags  = IORESOURCE_IO,
98         },
99         [1] = {
100                 .name = "host_wake",
101                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
102         },
103         [2] = {
104                 .name = "gpio_ext_wake",
105                 .start  = TEGRA_GPIO_PEE1,
106                 .end    = TEGRA_GPIO_PEE1,
107                 .flags  = IORESOURCE_IO,
108         },
109         [3] = {
110                 .name = "gpio_host_wake",
111                 .start  = TEGRA_GPIO_PU6,
112                 .end    = TEGRA_GPIO_PU6,
113                 .flags  = IORESOURCE_IO,
114         },
115         [4] = {
116                 .name = "reset_gpio",
117                 .start  = TEGRA_GPIO_PX1,
118                 .end    = TEGRA_GPIO_PX1,
119                 .flags  = IORESOURCE_IO,
120         },
121 };
122
123 static struct platform_device ardbeg_bluedroid_pm_device = {
124         .name = "bluedroid_pm",
125         .id             = 0,
126         .num_resources  = ARRAY_SIZE(ardbeg_bluedroid_pm_resources),
127         .resource       = ardbeg_bluedroid_pm_resources,
128 };
129
130 static noinline void __init ardbeg_setup_bluedroid_pm(void)
131 {
132         ardbeg_bluedroid_pm_resources[1].start =
133                 ardbeg_bluedroid_pm_resources[1].end =
134                                 gpio_to_irq(TEGRA_GPIO_PU6);
135         platform_device_register(&ardbeg_bluedroid_pm_device);
136 }
137
138 /*use board file for T12x*/
139 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || !defined(CONFIG_USE_OF)
140 static struct i2c_board_info __initdata rt5639_board_info = {
141         I2C_BOARD_INFO("rt5639", 0x1c),
142 };
143 static struct i2c_board_info __initdata rt5645_board_info = {
144         I2C_BOARD_INFO("rt5645", 0x1a),
145 };
146 #endif
147
148 static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
149         /* name         parent          rate            enabled */
150         { "pll_m",      NULL,           0,              false},
151         { "hda",        "pll_p",        108000000,      false},
152         { "hda2codec_2x", "pll_p",      48000000,       false},
153         { "pwm",        "pll_p",        3187500,        false},
154         { "i2s1",       "pll_a_out0",   0,              false},
155         { "i2s3",       "pll_a_out0",   0,              false},
156         { "i2s4",       "pll_a_out0",   0,              false},
157         { "spdif_out",  "pll_a_out0",   0,              false},
158         { "d_audio",    "clk_m",        12000000,       false},
159         { "dam0",       "clk_m",        12000000,       false},
160         { "dam1",       "clk_m",        12000000,       false},
161         { "dam2",       "clk_m",        12000000,       false},
162         { "audio1",     "i2s1_sync",    0,              false},
163         { "audio3",     "i2s3_sync",    0,              false},
164         { "vi_sensor",  "pll_p",        150000000,      false},
165         { "vi_sensor2", "pll_p",        150000000,      false},
166         { "cilab",      "pll_p",        150000000,      false},
167         { "cilcd",      "pll_p",        150000000,      false},
168         { "cile",       "pll_p",        150000000,      false},
169         { "i2c1",       "pll_p",        3200000,        false},
170         { "i2c2",       "pll_p",        3200000,        false},
171         { "i2c3",       "pll_p",        3200000,        false},
172         { "i2c4",       "pll_p",        3200000,        false},
173         { "i2c5",       "pll_p",        3200000,        false},
174         { "sbc1",       "pll_p",        25000000,       false},
175         { "sbc2",       "pll_p",        25000000,       false},
176         { "sbc3",       "pll_p",        25000000,       false},
177         { "sbc4",       "pll_p",        25000000,       false},
178         { "sbc5",       "pll_p",        25000000,       false},
179         { "sbc6",       "pll_p",        25000000,       false},
180         { "uarta",      "pll_p",        408000000,      false},
181         { "uartb",      "pll_p",        408000000,      false},
182         { "uartc",      "pll_p",        408000000,      false},
183         { "uartd",      "pll_p",        408000000,      false},
184         { NULL,         NULL,           0,              0},
185 };
186
187 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || !defined(CONFIG_USE_OF)
188 static struct tegra_i2c_platform_data ardbeg_i2c1_platform_data = {
189         .bus_clk_rate   = 100000,
190         .scl_gpio       = TEGRA_GPIO_I2C1_SCL,
191         .sda_gpio       = TEGRA_GPIO_I2C1_SDA,
192 };
193
194 static struct tegra_i2c_platform_data ardbeg_i2c2_platform_data = {
195         .bus_clk_rate   = 100000,
196         .is_clkon_always = true,
197         .scl_gpio       = TEGRA_GPIO_I2C2_SCL,
198         .sda_gpio       = TEGRA_GPIO_I2C2_SDA,
199 };
200
201 static struct tegra_i2c_platform_data ardbeg_i2c3_platform_data = {
202         .bus_clk_rate   = 400000,
203         .scl_gpio       = TEGRA_GPIO_I2C3_SCL,
204         .sda_gpio       = TEGRA_GPIO_I2C3_SDA,
205 };
206
207 static struct tegra_i2c_platform_data ardbeg_i2c4_platform_data = {
208         .bus_clk_rate   = 10000,
209         .scl_gpio       = TEGRA_GPIO_I2C4_SCL,
210         .sda_gpio       = TEGRA_GPIO_I2C4_SDA,
211 };
212
213 static struct tegra_i2c_platform_data ardbeg_i2c5_platform_data = {
214         .bus_clk_rate   = 400000,
215         .scl_gpio       = TEGRA_GPIO_I2C5_SCL,
216         .sda_gpio       = TEGRA_GPIO_I2C5_SDA,
217         .needs_cl_dvfs_clock = true,
218 };
219 #endif
220
221 static struct i2c_hid_platform_data i2c_keyboard_pdata = {
222         .hid_descriptor_address = 0x0,
223 };
224
225 static struct i2c_board_info __initdata i2c_keyboard_board_info = {
226         I2C_BOARD_INFO("hid", 0x3B),
227         .platform_data  = &i2c_keyboard_pdata,
228 };
229
230 static struct i2c_hid_platform_data i2c_touchpad_pdata = {
231         .hid_descriptor_address = 0x20,
232 };
233
234 static struct i2c_board_info __initdata i2c_touchpad_board_info = {
235         I2C_BOARD_INFO("hid", 0x2C),
236         .platform_data  = &i2c_touchpad_pdata,
237 };
238
239 static void ardbeg_i2c_init(void)
240 {
241         struct board_info board_info;
242         tegra_get_board_info(&board_info);
243 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
244 #ifndef CONFIG_USE_OF
245         tegra11_i2c_device1.dev.platform_data = &ardbeg_i2c1_platform_data;
246         tegra11_i2c_device2.dev.platform_data = &ardbeg_i2c2_platform_data;
247         tegra11_i2c_device3.dev.platform_data = &ardbeg_i2c3_platform_data;
248         tegra11_i2c_device4.dev.platform_data = &ardbeg_i2c4_platform_data;
249         tegra11_i2c_device5.dev.platform_data = &ardbeg_i2c5_platform_data;
250
251         platform_device_register(&tegra11_i2c_device5);
252         platform_device_register(&tegra11_i2c_device4);
253         platform_device_register(&tegra11_i2c_device3);
254         platform_device_register(&tegra11_i2c_device2);
255         platform_device_register(&tegra11_i2c_device1);
256 #endif
257 #else
258         /* T124 does not use device tree as of now */
259         tegra14_i2c_device1.dev.platform_data = &ardbeg_i2c1_platform_data;
260         tegra14_i2c_device2.dev.platform_data = &ardbeg_i2c2_platform_data;
261         tegra14_i2c_device3.dev.platform_data = &ardbeg_i2c3_platform_data;
262         tegra14_i2c_device4.dev.platform_data = &ardbeg_i2c4_platform_data;
263         tegra14_i2c_device5.dev.platform_data = &ardbeg_i2c5_platform_data;
264
265         platform_device_register(&tegra14_i2c_device5);
266         platform_device_register(&tegra14_i2c_device4);
267         platform_device_register(&tegra14_i2c_device3);
268         platform_device_register(&tegra14_i2c_device2);
269         platform_device_register(&tegra14_i2c_device1);
270 #endif
271
272 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || !defined(CONFIG_USE_OF)
273         i2c_register_board_info(0, &rt5639_board_info, 1);
274         i2c_register_board_info(0, &rt5645_board_info, 1);
275 #endif
276
277         if (board_info.board_id == BOARD_PM359 ||
278                         board_info.board_id == BOARD_PM358 ||
279                         board_info.board_id == BOARD_PM363) {
280                 i2c_keyboard_board_info.irq = gpio_to_irq(I2C_KB_IRQ);
281                 i2c_register_board_info(1, &i2c_keyboard_board_info , 1);
282
283                 i2c_touchpad_board_info.irq = gpio_to_irq(I2C_TP_IRQ);
284                 i2c_register_board_info(1, &i2c_touchpad_board_info , 1);
285         }
286 }
287
288 #ifndef CONFIG_USE_OF
289 static struct platform_device *ardbeg_uart_devices[] __initdata = {
290         &tegra_uarta_device,
291         &tegra_uartb_device,
292         &tegra_uartc_device,
293 };
294
295 static struct tegra_serial_platform_data ardbeg_uarta_pdata = {
296         .dma_req_selector = 8,
297         .modem_interrupt = false,
298 };
299
300 static struct tegra_serial_platform_data ardbeg_uartb_pdata = {
301         .dma_req_selector = 9,
302         .modem_interrupt = false,
303 };
304
305 static struct tegra_serial_platform_data ardbeg_uartc_pdata = {
306         .dma_req_selector = 10,
307         .modem_interrupt = false,
308 };
309 #endif
310
311 static struct tegra_serial_platform_data ardbeg_uartd_pdata = {
312         .dma_req_selector = 19,
313         .modem_interrupt = false,
314 };
315
316 /*use board file for T12x*/
317 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || !defined(CONFIG_USE_OF)
318 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
319         .gpio_hp_det = TEGRA_GPIO_HP_DET,
320         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
321         .gpio_spkr_en = -1,
322         .gpio_int_mic_en = -1,
323         .gpio_ext_mic_en = -1,
324         .gpio_hp_mute = -1,
325         .gpio_codec1 = -1,
326         .gpio_codec2 = -1,
327         .gpio_codec3 = -1,
328         .i2s_param[HIFI_CODEC]       = {
329                 .audio_port_id = 1,
330                 .is_i2s_master = 0,
331                 .i2s_mode = TEGRA_DAIFMT_I2S,
332         },
333         .i2s_param[BT_SCO] = {
334                 .audio_port_id = 3,
335                 .is_i2s_master = 1,
336                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
337         },
338 };
339
340 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5645 = {
341         .gpio_hp_det = TEGRA_GPIO_HP_DET,
342         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
343         .gpio_spkr_en = -1,
344         .gpio_int_mic_en = -1,
345         .gpio_ext_mic_en = -1,
346         .gpio_hp_mute = -1,
347         .gpio_codec1 = -1,
348         .gpio_codec2 = -1,
349         .gpio_codec3 = -1,
350         .i2s_param[HIFI_CODEC]       = {
351                 .audio_port_id = 1,
352                 .is_i2s_master = 0,
353                 .i2s_mode = TEGRA_DAIFMT_I2S,
354         },
355         .i2s_param[BT_SCO] = {
356                 .audio_port_id = 3,
357                 .is_i2s_master = 1,
358                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
359         },
360 };
361
362 static void ardbeg_audio_init(void)
363 {
364         struct board_info board_info;
365         tegra_get_board_info(&board_info);
366         if (board_info.board_id == BOARD_PM359 ||
367                         board_info.board_id == BOARD_PM358 ||
368                         board_info.board_id == BOARD_PM363) {
369                 /*Laguna*/
370                 ardbeg_audio_pdata_rt5645.gpio_hp_det =
371                         TEGRA_GPIO_HP_DET;
372                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high = 1;
373                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en = -1;
374         } else {
375                 /*Ardbeg*/
376                 ardbeg_audio_pdata_rt5645.gpio_hp_det =
377                         TEGRA_GPIO_HP_DET;
378                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high = 0;
379                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en =
380                         TEGRA_GPIO_LDO_EN;
381         }
382
383         ardbeg_audio_pdata_rt5639.gpio_hp_det =
384                 ardbeg_audio_pdata_rt5645.gpio_hp_det;
385
386         ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high =
387                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high;
388
389         ardbeg_audio_pdata_rt5639.gpio_ldo1_en =
390                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en;
391
392         ardbeg_audio_pdata_rt5639.codec_name = "rt5639.0-001c";
393         ardbeg_audio_pdata_rt5639.codec_dai_name = "rt5639-aif1";
394         ardbeg_audio_pdata_rt5645.codec_name = "rt5645.0-001a";
395         ardbeg_audio_pdata_rt5645.codec_dai_name = "rt5645-aif1";
396 }
397
398 static struct platform_device ardbeg_audio_device_rt5645 = {
399         .name = "tegra-snd-rt5645",
400         .id = 0,
401         .dev = {
402                 .platform_data = &ardbeg_audio_pdata_rt5645,
403         },
404 };
405
406 static struct platform_device ardbeg_audio_device_rt5639 = {
407         .name = "tegra-snd-rt5639",
408         .id = 0,
409         .dev = {
410                 .platform_data = &ardbeg_audio_pdata_rt5639,
411         },
412 };
413
414 #endif
415
416 static void __init ardbeg_uart_init(void)
417 {
418         int debug_port_id;
419
420 #ifndef CONFIG_USE_OF
421         tegra_uarta_device.dev.platform_data = &ardbeg_uarta_pdata;
422         tegra_uartb_device.dev.platform_data = &ardbeg_uartb_pdata;
423         tegra_uartc_device.dev.platform_data = &ardbeg_uartc_pdata;
424         platform_add_devices(ardbeg_uart_devices,
425                         ARRAY_SIZE(ardbeg_uart_devices));
426 #endif
427         tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
428         if (!is_tegra_debug_uartport_hs()) {
429                 debug_port_id = uart_console_debug_init(3);
430                 if (debug_port_id < 0)
431                         return;
432
433                 platform_device_register(uart_console_debug_device);
434         } else {
435                 tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
436                 platform_device_register(&tegra_uartd_device);
437         }
438
439 }
440
441 static struct resource tegra_rtc_resources[] = {
442         [0] = {
443                 .start = TEGRA_RTC_BASE,
444                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
445                 .flags = IORESOURCE_MEM,
446         },
447         [1] = {
448                 .start = INT_RTC,
449                 .end = INT_RTC,
450                 .flags = IORESOURCE_IRQ,
451         },
452 };
453
454 static struct platform_device tegra_rtc_device = {
455         .name = "tegra_rtc",
456         .id   = -1,
457         .resource = tegra_rtc_resources,
458         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
459 };
460
461 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
462 static struct tegra_pci_platform_data laguna_pcie_platform_data = {
463         .port_status[0] = 1,
464         .port_status[1] = 1,
465         .use_dock_detect        = 1,
466         .gpio   = TEGRA_GPIO_PO1,
467         .gpio_x1_slot   = PMU_TCA6416_GPIO(8),
468 };
469
470 static void laguna_pcie_init(void)
471 {
472         struct board_info board_info;
473
474         tegra_get_board_info(&board_info);
475         /* root port 1(x1 slot) is supported only on of ERS-S board */
476         if (board_info.board_id == BOARD_PM358 ||
477                 board_info.board_id == BOARD_PM363)
478                         laguna_pcie_platform_data.port_status[1] = 0;
479
480         tegra_pci_device.dev.platform_data = &laguna_pcie_platform_data;
481         platform_device_register(&tegra_pci_device);
482 }
483 #endif
484
485 static struct platform_device *ardbeg_devices[] __initdata = {
486         &tegra_pmu_device,
487         &tegra_rtc_device,
488         &tegra_udc_device,
489 #if defined(CONFIG_TEGRA_AVP)
490         &tegra_avp_device,
491 #endif
492 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
493 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
494         &tegra12_se_device,
495 #endif
496 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
497         &tegra11_se_device,
498 #endif
499 #endif
500 /*use board file for T12x*/
501 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || !defined(CONFIG_USE_OF)
502         &tegra_ahub_device,
503         &tegra_dam_device0,
504         &tegra_dam_device1,
505         &tegra_dam_device2,
506         &tegra_i2s_device1,
507         &tegra_i2s_device3,
508         &tegra_i2s_device4,
509         &ardbeg_audio_device_rt5639,
510         &tegra_spdif_device,
511 #endif
512         &spdif_dit_device,
513         &bluetooth_dit_device,
514         &tegra_hda_device,
515 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
516         &tegra_aes_device,
517 #endif
518 };
519
520 static struct tegra_usb_platform_data tegra_udc_pdata = {
521         .port_otg = true,
522         .has_hostpc = true,
523         .unaligned_dma_buf_supported = false,
524         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
525         .op_mode = TEGRA_USB_OPMODE_DEVICE,
526         .u_data.dev = {
527                 .vbus_pmu_irq = 0,
528                 .vbus_gpio = -1,
529                 .charging_supported = false,
530                 .remote_wakeup_supported = false,
531         },
532         .u_cfg.utmi = {
533                 .hssync_start_delay = 0,
534                 .elastic_limit = 16,
535                 .idle_wait_delay = 17,
536                 .term_range_adj = 6,
537                 .xcvr_setup = 8,
538                 .xcvr_lsfslew = 2,
539                 .xcvr_lsrslew = 2,
540                 .xcvr_setup_offset = 0,
541                 .xcvr_use_fuses = 1,
542         },
543 };
544
545 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
546         .port_otg = true,
547         .has_hostpc = true,
548         .unaligned_dma_buf_supported = false,
549         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
550         .op_mode = TEGRA_USB_OPMODE_HOST,
551         .u_data.host = {
552                 .vbus_gpio = -1,
553                 .hot_plug = false,
554                 .remote_wakeup_supported = true,
555                 .power_off_on_suspend = true,
556         },
557         .u_cfg.utmi = {
558                 .hssync_start_delay = 0,
559                 .elastic_limit = 16,
560                 .idle_wait_delay = 17,
561                 .term_range_adj = 6,
562                 .xcvr_setup = 15,
563                 .xcvr_lsfslew = 0,
564                 .xcvr_lsrslew = 3,
565                 .xcvr_setup_offset = 0,
566                 .xcvr_use_fuses = 0,
567                 .vbus_oc_map = 0x4,
568                 .xcvr_hsslew_lsb = 2,
569         },
570 };
571
572 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
573 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
574         .port_otg = false,
575         .has_hostpc = true,
576         .unaligned_dma_buf_supported = false,
577         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
578         .op_mode = TEGRA_USB_OPMODE_HOST,
579         .u_data.host = {
580                 .vbus_gpio = -1,
581                 .hot_plug = false,
582                 .remote_wakeup_supported = true,
583                 .power_off_on_suspend = true,
584         },
585         .u_cfg.utmi = {
586                 .hssync_start_delay = 0,
587                 .elastic_limit = 16,
588                 .idle_wait_delay = 17,
589                 .term_range_adj = 6,
590                 .xcvr_setup = 8,
591                 .xcvr_lsfslew = 2,
592                 .xcvr_lsrslew = 2,
593                 .xcvr_setup_offset = 0,
594                 .xcvr_use_fuses = 1,
595                 .vbus_oc_map = 0x5,
596         },
597 };
598 #endif
599
600 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
601         .port_otg = false,
602         .has_hostpc = true,
603         .unaligned_dma_buf_supported = false,
604         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
605         .op_mode = TEGRA_USB_OPMODE_HOST,
606         .u_data.host = {
607                 .vbus_gpio = -1,
608                 .hot_plug = false,
609                 .remote_wakeup_supported = true,
610                 .power_off_on_suspend = true,
611         },
612         .u_cfg.utmi = {
613         .hssync_start_delay = 0,
614                 .elastic_limit = 16,
615                 .idle_wait_delay = 17,
616                 .term_range_adj = 6,
617                 .xcvr_setup = 8,
618                 .xcvr_lsfslew = 2,
619                 .xcvr_lsrslew = 2,
620                 .xcvr_setup_offset = 0,
621                 .xcvr_use_fuses = 1,
622                 .vbus_oc_map = 0x5,
623         },
624 };
625
626 static struct gpio modem_gpios[] = { /* Bruce modem */
627         {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"},
628         {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"},
629 };
630
631 static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = {
632         .port_otg = false,
633         .has_hostpc = true,
634         .unaligned_dma_buf_supported = false,
635         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
636         .op_mode = TEGRA_USB_OPMODE_HOST,
637         .u_data.host = {
638                 .vbus_gpio = -1,
639                 .hot_plug = false,
640                 .remote_wakeup_supported = true,
641                 .power_off_on_suspend = true,
642         },
643 };
644
645 static struct tegra_usb_platform_data tegra_ehci2_hsic_smsc_hub_pdata = {
646         .port_otg = false,
647         .has_hostpc = true,
648         .unaligned_dma_buf_supported = false,
649         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
650         .op_mode        = TEGRA_USB_OPMODE_HOST,
651         .u_data.host = {
652                 .vbus_gpio = -1,
653                 .hot_plug = false,
654                 .remote_wakeup_supported = true,
655                 .power_off_on_suspend = true,
656         },
657 };
658
659
660 static struct tegra_usb_otg_data tegra_otg_pdata = {
661         .ehci_device = &tegra_ehci1_device,
662         .ehci_pdata = &tegra_ehci1_utmi_pdata,
663 };
664
665 static void ardbeg_usb_init(void)
666 {
667         int usb_port_owner_info = tegra_get_usb_port_owner_info();
668         int modem_id = tegra_get_modem_id();
669         struct board_info bi;
670
671         tegra_get_pmu_board_info(&bi);
672
673         switch (bi.board_id) {
674         case BOARD_E1733:
675                 /* Host cable is detected through USB ID */
676                 tegra_udc_pdata.id_det_type = TEGRA_USB_ID;
677                 tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_ID;
678                 break;
679         case BOARD_E1735:
680                 /* Host cable is detected through PMU Interrupt */
681                 tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
682                 tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
683                 tegra_otg_pdata.id_extcon_dev_name = "palmas-extcon";
684         }
685
686         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
687                 tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
688                 platform_device_register(&tegra_otg_device);
689                 /* Setup the udc platform data */
690                 tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
691         }
692 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
693         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
694                 if (!modem_id) {
695                         tegra_ehci2_device.dev.platform_data =
696                                 &tegra_ehci2_utmi_pdata;
697                         platform_device_register(&tegra_ehci2_device);
698                 }
699         }
700 #endif
701         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
702                 tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
703                 platform_device_register(&tegra_ehci3_device);
704         }
705 }
706
707 static struct tegra_xusb_board_data xusb_bdata = {
708 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
709         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_USB2_P1,
710         .supply = {
711                 .s5p0v = "usb_vbus0",
712                 .s5p0v1 = "usb_vbus1",
713                 .s5p0v2 = "usb_vbus2",
714                 .s3p3v = "hvdd_usb",
715                 .s1p8v = "avdd_usb_pll",
716                 .s1p2v = "vddio_hsic",
717                 .s1p05v = "avddio_usb",
718         },
719 #else
720         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_SS_P1 |
721                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_USB2_P2,
722         .supply = {
723                 .s5p0v = "usb_vbus0",
724                 .s5p0v1 = "usb_vbus1",
725                 .s5p0v2 = "usb_vbus2",
726                 .s3p3v = "hvdd_usb",
727                 .s1p8v = "avdd_pll_utmip",
728                 .vddio_hsic = "vddio_hsic",
729                 .s1p05v = "avddio_usb",
730         },
731
732         .hsic = {
733                 .rx_strobe_trim = 0x1,
734                 .rx_data_trim = 0x1,
735                 .tx_rtune_n = 0x8,
736                 .tx_rtune_p = 0xc,
737                 .tx_slew_n = 0,
738                 .tx_slew_p = 0,
739                 .auto_term_en = true,
740                 .strb_trim_val = 0x22,
741         },
742 #endif
743         .uses_external_pmic = false,
744         .uses_different_vbus_per_port = true,
745 };
746
747 static void ardbeg_xusb_init(void)
748 {
749         int usb_port_owner_info = tegra_get_usb_port_owner_info();
750
751         xusb_bdata.lane_owner = (u8) tegra_get_lane_owner_info();
752
753         if (board_info.board_id == BOARD_PM359 ||
754                         board_info.board_id == BOARD_PM358 ||
755                         board_info.board_id == BOARD_PM363) {
756                 /* Laguna */
757                 pr_info("Laguna ERS. 0x%x\n", board_info.board_id);
758                 xusb_bdata.gpio_controls_muxed_ss_lanes = true;
759                 /* D[0:15] = gpio number and D[16:31] = output value */
760                 xusb_bdata.gpio_ss1_sata = PMU_TCA6416_GPIO(9) | (0 << 16);
761                 xusb_bdata.ss_portmap = (TEGRA_XUSB_SS_PORT_MAP_USB2_P0 << 0) |
762                         (TEGRA_XUSB_SS_PORT_MAP_USB2_P1 << 4);
763
764                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
765                         xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
766                                 TEGRA_XUSB_SS_P0);
767
768                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
769                         xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
770                                 TEGRA_XUSB_SS_P1 | TEGRA_XUSB_USB2_P2);
771
772                 /* FIXME Add for UTMIP2 when have odmdata assigend */
773         } else {
774                 /* Ardbeg */
775                 xusb_bdata.gpio_controls_muxed_ss_lanes = false;
776
777                 if (board_info.board_id == BOARD_E1781) {
778                         pr_info("Shield ERS-S. 0x%x\n", board_info.board_id);
779                         /* Shield ERS-S */
780                         xusb_bdata.ss_portmap =
781                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P1 << 0) |
782                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P2 << 4);
783
784                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
785                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
786
787                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
788                                 xusb_bdata.portmap &= ~(
789                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0 |
790                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
791                 } else {
792                         pr_info("Shield ERS 0x%x\n", board_info.board_id);
793                         /* Shield ERS */
794                         xusb_bdata.ss_portmap =
795                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P0 << 0) |
796                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P2 << 4);
797
798                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
799                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
800                                         TEGRA_XUSB_SS_P0);
801
802                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
803                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
804                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
805                 }
806                 /* FIXME Add for UTMIP2 when have odmdata assigend */
807         }
808
809         if (usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)
810                 xusb_bdata.portmap |= TEGRA_XUSB_HSIC_P0;
811
812         if (usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)
813                 xusb_bdata.portmap |= TEGRA_XUSB_HSIC_P1;
814
815         if (xusb_bdata.portmap)
816                 tegra_xusb_init(&xusb_bdata);
817 }
818
819 static int baseband_init(void)
820 {
821         int ret;
822
823         ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios));
824         if (ret) {
825                 pr_warn("%s:gpio request failed\n", __func__);
826                 return ret;
827         }
828
829         /* enable pull-down for MDM_COLD_BOOT */
830         tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4,
831                                     TEGRA_PUPD_PULL_DOWN);
832
833         /* export GPIO for user space access through sysfs */
834         gpio_export(MDM_RST, false);
835
836         return 0;
837 }
838
839 static const struct tegra_modem_operations baseband_operations = {
840         .init = baseband_init,
841 };
842
843 static struct tegra_usb_modem_power_platform_data baseband_pdata = {
844         .ops = &baseband_operations,
845         .regulator_name = "vdd_wwan_mdm",
846         .wake_gpio = -1,
847         .boot_gpio = MDM_COLDBOOT,
848         .boot_irq_flags = IRQF_TRIGGER_RISING |
849                                     IRQF_TRIGGER_FALLING |
850                                     IRQF_ONESHOT,
851         .autosuspend_delay = 2000,
852         .short_autosuspend_delay = 50,
853         .tegra_ehci_device = &tegra_ehci2_device,
854         .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata,
855 };
856
857 static struct platform_device icera_bruce_device = {
858         .name = "tegra_usb_modem_power",
859         .id = -1,
860         .dev = {
861                 .platform_data = &baseband_pdata,
862         },
863 };
864
865 static void ardbeg_modem_init(void)
866 {
867         int modem_id = tegra_get_modem_id();
868         struct board_info board_info;
869         int usb_port_owner_info = tegra_get_usb_port_owner_info();
870
871         tegra_get_board_info(&board_info);
872         pr_info("%s: modem_id = %d\n", __func__, modem_id);
873
874         switch (modem_id) {
875         case TEGRA_BB_BRUCE:
876                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB))
877                         platform_device_register(&icera_bruce_device);
878                 break;
879         case TEGRA_BB_HSIC_HUB: /* HSIC hub */
880                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
881                         tegra_ehci2_device.dev.platform_data =
882                                 &tegra_ehci2_hsic_smsc_hub_pdata;
883                         platform_device_register(&tegra_ehci2_device);
884                 }
885                 break;
886         default:
887                 return;
888         }
889 }
890
891 #ifndef CONFIG_USE_OF
892 static struct platform_device *ardbeg_spi_devices[] __initdata = {
893         &tegra11_spi_device1,
894         &tegra11_spi_device4,
895 };
896
897 static struct tegra_spi_platform_data ardbeg_spi1_pdata = {
898         .dma_req_sel            = 15,
899         .spi_max_frequency      = 25000000,
900         .clock_always_on        = false,
901 };
902
903 static struct tegra_spi_platform_data ardbeg_spi4_pdata = {
904         .dma_req_sel            = 18,
905         .spi_max_frequency      = 25000000,
906         .clock_always_on        = false,
907 };
908
909 static void __init ardbeg_spi_init(void)
910 {
911         tegra11_spi_device1.dev.platform_data = &ardbeg_spi1_pdata;
912         tegra11_spi_device4.dev.platform_data = &ardbeg_spi4_pdata;
913         platform_add_devices(ardbeg_spi_devices,
914                         ARRAY_SIZE(ardbeg_spi_devices));
915 }
916 #else
917 static void __init ardbeg_spi_init(void)
918 {
919 }
920 #endif
921
922 #ifdef CONFIG_USE_OF
923 struct of_dev_auxdata ardbeg_auxdata_lookup[] __initdata = {
924 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
925         /* sdhci and i2c dt support not planned for bringup */
926         OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000600, "sdhci-tegra.3",
927                                 NULL),
928         OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000400, "sdhci-tegra.2",
929                                 NULL),
930 #if 0
931         OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000000, "sdhci-tegra.0",
932                                 &ardbeg_tegra_sdhci_platform_data0),
933 #endif
934         OF_DEV_AUXDATA("nvidia,tegra114-camera", 0x0, "tegra_camera",
935                                 NULL),
936         OF_DEV_AUXDATA("nvidia,tegra114-i2c", 0x7000c000, "tegra11-i2c.0",
937                                 NULL),
938         OF_DEV_AUXDATA("nvidia,tegra114-i2c", 0x7000c400, "tegra11-i2c.1",
939                                 NULL),
940         OF_DEV_AUXDATA("nvidia,tegra114-i2c", 0x7000c500, "tegra11-i2c.2",
941                                 NULL),
942         OF_DEV_AUXDATA("nvidia,tegra114-i2c", 0x7000c700, "tegra11-i2c.3",
943                                 NULL),
944         OF_DEV_AUXDATA("nvidia,tegra114-i2c", 0x7000d000, "tegra11-i2c.4",
945                                 NULL),
946 #endif
947         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d400, "spi-tegra114.0",
948                                 NULL),
949         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d600, "spi-tegra114.1",
950                                 NULL),
951         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d800, "spi-tegra114.2",
952                                 NULL),
953         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000da00, "spi-tegra114.3",
954                                 NULL),
955         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000dc00, "spi-tegra114.4",
956                                 NULL),
957         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000de00, "spi-tegra114.5",
958                                 NULL),
959 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
960         OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub",
961                                 NULL),
962         OF_DEV_AUXDATA("nvidia,tegra-audio-rt5645", 0x0, "tegra-snd-rt5645",
963                                 NULL),
964         OF_DEV_AUXDATA("nvidia,tegra-audio-rt5639", 0x0, "tegra-snd-rt5639",
965                                 NULL),
966         OF_DEV_AUXDATA("nvidia,tegra114-apbdma", 0x6000a000, "tegra-apbdma",
967                                 NULL),
968         OF_DEV_AUXDATA("nvidia,tegra114-host1x", TEGRA_HOST1X_BASE, "host1x",
969                                 NULL),
970         OF_DEV_AUXDATA("nvidia,tegra114-gr3d", TEGRA_GR3D_BASE, "gr3d",
971                                 NULL),
972         OF_DEV_AUXDATA("nvidia,tegra114-gr2d", TEGRA_GR2D_BASE, "gr2d",
973                                 NULL),
974         OF_DEV_AUXDATA("nvidia,tegra114-msenc", TEGRA_MSENC_BASE, "msenc",
975                                 NULL),
976         OF_DEV_AUXDATA("nvidia,tegra114-vi", TEGRA_VI_BASE, "vi",
977                                 NULL),
978         OF_DEV_AUXDATA("nvidia,tegra114-isp", TEGRA_ISP_BASE, "isp",
979                                 NULL),
980         OF_DEV_AUXDATA("nvidia,tegra114-tsec", TEGRA_TSEC_BASE, "tsec",
981                                 NULL),
982 #else
983         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
984                                 NULL),
985         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
986                 NULL),
987         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", 0x538F0000, "gk20a", NULL),
988         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03", NULL),
989         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
990                 NULL),
991         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi", NULL),
992         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp", NULL),
993         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
994 #endif
995         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0",
996                                 NULL),
997         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1",
998                                 NULL),
999         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2",
1000                                 NULL),
1001         {}
1002 };
1003 #endif
1004
1005 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
1006         /* name         parent          rate            enabled */
1007         { "extern2",    "pll_p",        41000000,       false},
1008         { "clk_out_2",  "extern2",      40800000,       false},
1009         { NULL,         NULL,           0,              0},
1010 };
1011
1012 struct rm_spi_ts_platform_data rm31080ts_ardbeg_data = {
1013         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1014         .config = 0,
1015         .platform_id = RM_PLATFORM_A010,
1016         .name_of_clock = "clk_out_2",
1017         .name_of_clock_con = "extern2",
1018 };
1019
1020 static struct tegra_spi_device_controller_data dev_cdata = {
1021         .rx_clk_tap_delay = 0,
1022         .tx_clk_tap_delay = 16,
1023 };
1024
1025 struct spi_board_info rm31080a_ardbeg_spi_board[1] = {
1026         {
1027                 .modalias = "rm_ts_spidev",
1028                 .bus_num = TOUCH_SPI_ID,
1029                 .chip_select = TOUCH_SPI_CS,
1030                 .max_speed_hz = 12 * 1000 * 1000,
1031                 .mode = SPI_MODE_0,
1032                 .controller_data = &dev_cdata,
1033                 .platform_data = &rm31080ts_ardbeg_data,
1034         },
1035 };
1036
1037 static int __init ardbeg_touch_init(void)
1038 {
1039         tegra_clk_init_from_table(touch_clk_init_table);
1040         rm31080a_ardbeg_spi_board[0].irq =
1041                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1042         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1043                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
1044                                 &rm31080ts_ardbeg_data,
1045                                 &rm31080a_ardbeg_spi_board[0],
1046                                 ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1047         return 0;
1048 }
1049
1050 static void __init tegra_ardbeg_early_init(void)
1051 {
1052         tegra_clk_init_from_table(ardbeg_clk_init_table);
1053         tegra_clk_verify_parents();
1054         if (of_machine_is_compatible("nvidia,laguna"))
1055                 tegra_soc_device_init("laguna");
1056         else if (of_machine_is_compatible("nvidia,tn8"))
1057                 tegra_soc_device_init("tn8");
1058         else
1059                 tegra_soc_device_init("ardbeg");
1060 }
1061
1062 static void __init tegra_ardbeg_late_init(void)
1063 {
1064         struct board_info board_info;
1065         tegra_get_board_info(&board_info);
1066         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1067                 board_info.board_id, board_info.sku,
1068                 board_info.fab, board_info.major_revision,
1069                 board_info.minor_revision);
1070         platform_device_register(&tegra_pinmux_device);
1071         if (board_info.board_id == BOARD_PM359 ||
1072                         board_info.board_id == BOARD_PM358 ||
1073                         board_info.board_id == BOARD_PM363)
1074                 laguna_pinmux_init();
1075         else
1076                 ardbeg_pinmux_init();
1077         ardbeg_usb_init();
1078         ardbeg_modem_init();
1079         ardbeg_xusb_init();
1080         ardbeg_i2c_init();
1081         ardbeg_spi_init();
1082         ardbeg_uart_init();
1083 /*use board file for T12x*/
1084 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || !defined(CONFIG_USE_OF)
1085         ardbeg_audio_init();
1086 #endif
1087         platform_add_devices(ardbeg_devices, ARRAY_SIZE(ardbeg_devices));
1088         //tegra_ram_console_debug_init();
1089         tegra_io_dpd_init();
1090         ardbeg_sdhci_init();
1091         if (board_info.board_id == BOARD_PM359 ||
1092                         board_info.board_id == BOARD_PM358 ||
1093                         board_info.board_id == BOARD_PM363)
1094                 laguna_regulator_init();
1095         else
1096                 ardbeg_regulator_init();
1097         ardbeg_suspend_init();
1098 #if 0
1099         ardbeg_emc_init();
1100 #endif
1101         ardbeg_edp_init();
1102         isomgr_init();
1103         ardbeg_touch_init();
1104         ardbeg_panel_init();
1105         ardbeg_kbc_init();
1106         if (board_info.board_id == BOARD_PM358)
1107                 laguna_pm358_pmon_init();
1108         else
1109                 ardbeg_pmon_init();
1110         tegra_release_bootloader_fb();
1111 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
1112         if (board_info.board_id == BOARD_PM359 ||
1113                         board_info.board_id == BOARD_PM358 ||
1114                         board_info.board_id == BOARD_PM363)
1115                 laguna_pcie_init();
1116 #endif
1117 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1118         tegra_wdt_recovery_init();
1119 #endif
1120         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1121
1122         ardbeg_sensors_init();
1123 #if 0
1124         ardbeg_soctherm_init();
1125 #endif
1126         ardbeg_setup_bluedroid_pm();
1127         tegra_register_fuse();
1128         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1129 }
1130
1131 static void __init ardbeg_ramconsole_reserve(unsigned long size)
1132 {
1133         tegra_ram_console_debug_reserve(SZ_1M);
1134 }
1135
1136 static void __init tegra_ardbeg_init_early(void)
1137 {
1138         ardbeg_rail_alignment_init();
1139         tegra12x_init_early();
1140 }
1141
1142 static void __init tegra_ardbeg_dt_init(void)
1143 {
1144         tegra_get_board_info(&board_info);
1145         tegra_get_display_board_info(&display_board_info);
1146
1147         tegra_ardbeg_early_init();
1148 #ifdef CONFIG_USE_OF
1149         of_platform_populate(NULL,
1150                 of_default_bus_match_table, ardbeg_auxdata_lookup,
1151                 &platform_bus);
1152         platform_device_register(&tegra_gpio_device);
1153 #endif
1154
1155         tegra_ardbeg_late_init();
1156 }
1157
1158 static void __init tegra_ardbeg_reserve(void)
1159 {
1160 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) || \
1161                 defined(CONFIG_TEGRA_NO_CARVEOUT)
1162         /* 1920*1200*4*2 = 18432000 bytes */
1163         tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
1164 #else
1165         tegra_reserve(SZ_1G, SZ_16M + SZ_2M, SZ_4M);
1166 #endif
1167         ardbeg_ramconsole_reserve(SZ_1M);
1168 }
1169
1170 static const char * const ardbeg_dt_board_compat[] = {
1171         "nvidia,ardbeg",
1172         NULL
1173 };
1174
1175 static const char * const laguna_dt_board_compat[] = {
1176         "nvidia,laguna",
1177         NULL
1178 };
1179
1180 static const char * const tn8_dt_board_compat[] = {
1181         "nvidia,tn8",
1182         NULL
1183 };
1184
1185 DT_MACHINE_START(LAGUNA, "laguna")
1186         .atag_offset    = 0x100,
1187         .smp            = smp_ops(tegra_smp_ops),
1188         .map_io         = tegra_map_common_io,
1189         .reserve        = tegra_ardbeg_reserve,
1190         .init_early     = tegra_ardbeg_init_early,
1191         .init_irq       = tegra_dt_init_irq,
1192         .init_time      = tegra_init_timer,
1193         .init_machine   = tegra_ardbeg_dt_init,
1194         .restart        = tegra_assert_system_reset,
1195         .dt_compat      = laguna_dt_board_compat,
1196 MACHINE_END
1197
1198 DT_MACHINE_START(TN8, "tn8")
1199         .atag_offset    = 0x100,
1200         .smp            = smp_ops(tegra_smp_ops),
1201         .map_io         = tegra_map_common_io,
1202         .reserve        = tegra_ardbeg_reserve,
1203         .init_early     = tegra_ardbeg_init_early,
1204         .init_irq       = tegra_dt_init_irq,
1205         .init_time      = tegra_init_timer,
1206         .init_machine   = tegra_ardbeg_dt_init,
1207         .restart        = tegra_assert_system_reset,
1208         .dt_compat      = tn8_dt_board_compat,
1209 MACHINE_END
1210
1211 DT_MACHINE_START(ARDBEG, "ardbeg")
1212         .atag_offset    = 0x100,
1213         .smp            = smp_ops(tegra_smp_ops),
1214         .map_io         = tegra_map_common_io,
1215         .reserve        = tegra_ardbeg_reserve,
1216 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
1217         .init_early     = tegra_ardbeg_init_early,
1218 #else
1219         .init_early     = tegra11x_init_early,
1220 #endif
1221         .init_irq       = tegra_dt_init_irq,
1222         .init_time      = tegra_init_timer,
1223         .init_machine   = tegra_ardbeg_dt_init,
1224         .restart        = tegra_assert_system_reset,
1225         .dt_compat      = ardbeg_dt_board_compat,
1226 MACHINE_END