arm: tegra12: jetson: disable usb charging detection
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg.c
3  *
4  * Copyright (c) 2013-2015, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c.h>
28 #include <linux/i2c/i2c-hid.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/delay.h>
31 #include <linux/i2c-tegra.h>
32 #include <linux/gpio.h>
33 #include <linux/input.h>
34 #include <linux/platform_data/tegra_usb.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/rm31080a_ts.h>
37 #include <linux/maxim_sti.h>
38 #include <linux/memblock.h>
39 #include <linux/spi/spi-tegra.h>
40 #include <linux/nfc/pn544.h>
41 #include <linux/rfkill-gpio.h>
42 #include <linux/skbuff.h>
43 #include <linux/ti_wilink_st.h>
44 #include <linux/regulator/consumer.h>
45 #include <linux/smb349-charger.h>
46 #include <linux/max17048_battery.h>
47 #include <linux/leds.h>
48 #include <linux/i2c/at24.h>
49 #include <linux/of_platform.h>
50 #include <linux/i2c.h>
51 #include <linux/i2c-tegra.h>
52 #include <linux/platform_data/serial-tegra.h>
53 #include <linux/edp.h>
54 #include <linux/usb/tegra_usb_phy.h>
55 #include <linux/mfd/palmas.h>
56 #include <linux/clk/tegra.h>
57 #include <media/tegra_dtv.h>
58 #include <linux/clocksource.h>
59 #include <linux/irqchip.h>
60 #include <linux/irqchip/tegra.h>
61 #include <linux/tegra-soc.h>
62 #include <linux/tegra_fiq_debugger.h>
63 #include <linux/platform_data/tegra_usb_modem_power.h>
64 #include <linux/platform_data/tegra_ahci.h>
65 #include <linux/irqchip/tegra.h>
66 #include <sound/max98090.h>
67
68 #include <mach/irqs.h>
69 #include <mach/pinmux.h>
70 #include <mach/pinmux-t12.h>
71 #include <mach/io_dpd.h>
72 #include <mach/i2s.h>
73 #include <mach/isomgr.h>
74 #include <mach/tegra_asoc_pdata.h>
75 #include <mach/dc.h>
76 #include <mach/tegra_usb_pad_ctrl.h>
77
78 #include <asm/mach-types.h>
79 #include <asm/mach/arch.h>
80 #include <mach/gpio-tegra.h>
81 #include <mach/xusb.h>
82
83 #include "board.h"
84 #include "board-ardbeg.h"
85 #include "board-common.h"
86 #include "board-touch-raydium.h"
87 #include "board-touch-maxim_sti.h"
88 #include "clock.h"
89 #include "common.h"
90 #include "devices.h"
91 #include "gpio-names.h"
92 #include "iomap.h"
93 #include "pm.h"
94 #include "tegra-board-id.h"
95 #include "tegra-of-dev-auxdata.h"
96
97 static struct board_info board_info, display_board_info;
98
99 static struct resource ardbeg_bluedroid_pm_resources[] = {
100         [0] = {
101                 .name   = "shutdown_gpio",
102                 .start  = TEGRA_GPIO_PR1,
103                 .end    = TEGRA_GPIO_PR1,
104                 .flags  = IORESOURCE_IO,
105         },
106         [1] = {
107                 .name = "host_wake",
108                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
109         },
110         [2] = {
111                 .name = "gpio_ext_wake",
112                 .start  = TEGRA_GPIO_PEE1,
113                 .end    = TEGRA_GPIO_PEE1,
114                 .flags  = IORESOURCE_IO,
115         },
116         [3] = {
117                 .name = "gpio_host_wake",
118                 .start  = TEGRA_GPIO_PU6,
119                 .end    = TEGRA_GPIO_PU6,
120                 .flags  = IORESOURCE_IO,
121         },
122         [4] = {
123                 .name = "reset_gpio",
124                 .start  = TEGRA_GPIO_PX1,
125                 .end    = TEGRA_GPIO_PX1,
126                 .flags  = IORESOURCE_IO,
127         },
128 };
129
130 static struct platform_device ardbeg_bluedroid_pm_device = {
131         .name = "bluedroid_pm",
132         .id             = 0,
133         .num_resources  = ARRAY_SIZE(ardbeg_bluedroid_pm_resources),
134         .resource       = ardbeg_bluedroid_pm_resources,
135 };
136
137 static noinline void __init ardbeg_setup_bluedroid_pm(void)
138 {
139         ardbeg_bluedroid_pm_resources[1].start =
140                 ardbeg_bluedroid_pm_resources[1].end =
141                                 gpio_to_irq(TEGRA_GPIO_PU6);
142         platform_device_register(&ardbeg_bluedroid_pm_device);
143 }
144
145 static struct i2c_board_info __initdata rt5639_board_info = {
146         I2C_BOARD_INFO("rt5639", 0x1c),
147 };
148
149 static struct max98090_eq_cfg max98090_eq_cfg[] = {
150 };
151
152 static struct max98090_pdata norrin_max98090_pdata = {
153         /* Equalizer Configuration */
154         .eq_cfg = max98090_eq_cfg,
155         .eq_cfgcnt = ARRAY_SIZE(max98090_eq_cfg),
156
157         /* Microphone Configuration */
158         .digmic_left_mode = 1,
159         .digmic_right_mode = 1,
160 };
161
162 static struct i2c_board_info __initdata max98090_board_info = {
163         I2C_BOARD_INFO("max98090", 0x10),
164         .platform_data  = &norrin_max98090_pdata,
165 };
166
167 static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
168         /* name         parent          rate            enabled */
169         { "pll_m",      NULL,           0,              false},
170         { "hda",        "pll_p",        108000000,      false},
171         { "hda2codec_2x", "pll_p",      48000000,       false},
172         { "pwm",        "pll_p",        48000000,       false},
173         { "pll_a",      "pll_p_out1",   282240000,      false},
174         { "pll_a_out0", "pll_a",        12288000,       false},
175         { "i2s1",       "pll_a_out0",   0,              false},
176         { "i2s3",       "pll_a_out0",   0,              false},
177         { "i2s4",       "pll_a_out0",   0,              false},
178         { "spdif_out",  "pll_a_out0",   0,              false},
179         { "d_audio",    "pll_a_out0",   12288000,       false},
180         { "dam0",       "clk_m",        12000000,       false},
181         { "dam1",       "clk_m",        12000000,       false},
182         { "dam2",       "clk_m",        12000000,       false},
183         { "audio1",     "i2s1_sync",    0,              false},
184         { "audio3",     "i2s3_sync",    0,              false},
185         { "vi_sensor",  "pll_p",        150000000,      false},
186         { "vi_sensor2", "pll_p",        150000000,      false},
187         { "cilab",      "pll_p",        150000000,      false},
188         { "cilcd",      "pll_p",        150000000,      false},
189         { "cile",       "pll_p",        150000000,      false},
190         { "i2c1",       "pll_p",        3200000,        false},
191         { "i2c2",       "pll_p",        3200000,        false},
192         { "i2c3",       "pll_p",        3200000,        false},
193         { "i2c4",       "pll_p",        3200000,        false},
194         { "i2c5",       "pll_p",        3200000,        false},
195         { "sbc1",       "pll_p",        25000000,       false},
196         { "sbc2",       "pll_p",        25000000,       false},
197         { "sbc3",       "pll_p",        25000000,       false},
198         { "sbc4",       "pll_p",        25000000,       false},
199         { "sbc5",       "pll_p",        25000000,       false},
200         { "sbc6",       "pll_p",        25000000,       false},
201         { "uarta",      "pll_p",        408000000,      false},
202         { "uartb",      "pll_p",        408000000,      false},
203         { "uartc",      "pll_p",        408000000,      false},
204         { "uartd",      "pll_p",        408000000,      false},
205         { NULL,         NULL,           0,              0},
206 };
207
208 static struct i2c_hid_platform_data i2c_keyboard_pdata = {
209         .hid_descriptor_address = 0x0,
210 };
211
212 static struct i2c_board_info __initdata i2c_keyboard_board_info = {
213         I2C_BOARD_INFO("hid", 0x3B),
214         .platform_data  = &i2c_keyboard_pdata,
215 };
216
217 static struct i2c_hid_platform_data i2c_touchpad_pdata = {
218         .hid_descriptor_address = 0x20,
219 };
220
221 static struct i2c_board_info __initdata i2c_touchpad_board_info = {
222         I2C_BOARD_INFO("hid", 0x2C),
223         .platform_data  = &i2c_touchpad_pdata,
224 };
225
226 static void ardbeg_i2c_init(void)
227 {
228         struct board_info board_info;
229         tegra_get_board_info(&board_info);
230
231         if (board_info.board_id == BOARD_PM374) {
232                 i2c_register_board_info(0, &max98090_board_info, 1);
233         } else if (board_info.board_id != BOARD_PM359)
234                 i2c_register_board_info(0, &rt5639_board_info, 1);
235
236         if (board_info.board_id == BOARD_PM359 ||
237                 board_info.board_id == BOARD_PM358 ||
238                 board_info.board_id == BOARD_PM363 ||
239                 board_info.board_id == BOARD_PM374) {
240                 i2c_keyboard_board_info.irq = gpio_to_irq(I2C_KB_IRQ);
241                 i2c_register_board_info(1, &i2c_keyboard_board_info , 1);
242
243                 i2c_touchpad_board_info.irq = gpio_to_irq(I2C_TP_IRQ);
244                 i2c_register_board_info(1, &i2c_touchpad_board_info , 1);
245         }
246 }
247
248 #ifndef CONFIG_USE_OF
249 static struct platform_device *ardbeg_uart_devices[] __initdata = {
250         &tegra_uarta_device,
251         &tegra_uartb_device,
252         &tegra_uartc_device,
253 };
254
255 static struct tegra_serial_platform_data ardbeg_uarta_pdata = {
256         .dma_req_selector = 8,
257         .modem_interrupt = false,
258 };
259
260 static struct tegra_serial_platform_data ardbeg_uartb_pdata = {
261         .dma_req_selector = 9,
262         .modem_interrupt = false,
263 };
264
265 static struct tegra_serial_platform_data ardbeg_uartc_pdata = {
266         .dma_req_selector = 10,
267         .modem_interrupt = false,
268 };
269 #endif
270
271 static struct tegra_serial_platform_data ardbeg_uartd_pdata = {
272         .dma_req_selector = 19,
273         .modem_interrupt = false,
274 };
275
276 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
277         .gpio_hp_det = TEGRA_GPIO_HP_DET,
278         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
279         .gpio_spkr_en = -1,
280         .gpio_int_mic_en = -1,
281         .gpio_ext_mic_en = -1,
282         .gpio_hp_mute = -1,
283         .gpio_codec1 = -1,
284         .gpio_codec2 = -1,
285         .gpio_codec3 = -1,
286         .i2s_param[HIFI_CODEC]       = {
287                 .audio_port_id = 1,
288                 .is_i2s_master = 1,
289                 .i2s_mode = TEGRA_DAIFMT_I2S,
290                 .sample_size    = 16,
291                 .channels       = 2,
292                 .bit_clk        = 1536000,
293         },
294         .i2s_param[BT_SCO] = {
295                 .audio_port_id = 3,
296                 .is_i2s_master = 1,
297                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
298         },
299         .i2s_param[BASEBAND]    = {
300                 .audio_port_id  = 0,
301                 .is_i2s_master  = 1,
302                 .i2s_mode       = TEGRA_DAIFMT_I2S,
303                 .sample_size    = 16,
304                 .rate           = 16000,
305                 .channels       = 2,
306                 .bit_clk        = 1024000,
307         },
308 };
309
310 static struct tegra_asoc_platform_data norrin_audio_pdata_max98090 = {
311         .gpio_hp_det            = NORRIN_GPIO_HP_DET,
312         .gpio_ext_mic_en        = TEGRA_GPIO_HP_DET,
313         .gpio_hp_mute           = -1,
314         .edp_support            = true,
315         .edp_states             = {1080, 842, 0},
316         .i2s_param[HIFI_CODEC]  = {
317                 .audio_port_id  = 1,
318                 .is_i2s_master  = 1,
319                 .i2s_mode       = TEGRA_DAIFMT_I2S,
320                 .sample_size    = 16,
321                 .channels       = 2,
322                 .bit_clk        = 1536000,
323         },
324         .i2s_param[BT_SCO]      = {
325                 .audio_port_id  = 3,
326                 .is_i2s_master  = 1,
327                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
328                 .sample_size    = 16,
329                 .channels       = 1,
330                 .bit_clk        = 512000,
331         },
332 };
333
334 static void ardbeg_audio_init(void)
335 {
336         struct board_info board_info;
337         tegra_get_board_info(&board_info);
338         if (board_info.board_id == BOARD_PM359 ||
339                         board_info.board_id == BOARD_PM358 ||
340                         board_info.board_id == BOARD_PM370 ||
341                         board_info.board_id == BOARD_PM374 ||
342                         board_info.board_id == BOARD_PM375 ||
343                         board_info.board_id == BOARD_PM377 ||
344                         board_info.board_id == BOARD_PM363) {
345                 /*Laguna*/
346                 ardbeg_audio_pdata_rt5639.gpio_hp_det = TEGRA_GPIO_HP_DET;
347                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 1;
348                 if (board_info.board_id != BOARD_PM363)
349                         ardbeg_audio_pdata_rt5639.gpio_ldo1_en = -1;
350         } else {
351                 /*Ardbeg*/
352
353                 if (board_info.board_id == BOARD_E1762 ||
354                         board_info.board_id == BOARD_P1761 ||
355                         board_info.board_id == BOARD_E1922) {
356                         ardbeg_audio_pdata_rt5639.gpio_hp_det =
357                                 TEGRA_GPIO_CDC_IRQ;
358                         ardbeg_audio_pdata_rt5639.use_codec_jd_irq = true;
359                 } else {
360                         ardbeg_audio_pdata_rt5639.gpio_hp_det =
361                                 TEGRA_GPIO_HP_DET;
362                         ardbeg_audio_pdata_rt5639.use_codec_jd_irq = false;
363                 }
364                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 0;
365                 ardbeg_audio_pdata_rt5639.gpio_ldo1_en = TEGRA_GPIO_LDO_EN;
366         }
367
368         if (board_info.board_id == BOARD_E1971) {
369                 ardbeg_audio_pdata_rt5639.gpio_hp_det = TEGRA_GPIO_CDC_IRQ;
370                 ardbeg_audio_pdata_rt5639.use_codec_jd_irq = true;
371                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 0;
372                 ardbeg_audio_pdata_rt5639.gpio_ldo1_en = TEGRA_GPIO_LDO_EN;
373         }
374
375         ardbeg_audio_pdata_rt5639.codec_name = "rt5639.0-001c";
376         ardbeg_audio_pdata_rt5639.codec_dai_name = "rt5639-aif1";
377
378         norrin_audio_pdata_max98090.codec_name = "max98090.0-0010";
379         norrin_audio_pdata_max98090.codec_dai_name = "HiFi";
380 }
381
382 static struct platform_device ardbeg_audio_device_rt5639 = {
383         .name = "tegra-snd-rt5639",
384         .id = 0,
385         .dev = {
386                 .platform_data = &ardbeg_audio_pdata_rt5639,
387         },
388 };
389
390 static struct platform_device norrin_audio_device_max98090 = {
391         .name   = "tegra-snd-max98090",
392         .id     = 0,
393         .dev    = {
394                 .platform_data = &norrin_audio_pdata_max98090,
395         },
396 };
397
398 static void __init ardbeg_uart_init(void)
399 {
400
401 #ifndef CONFIG_USE_OF
402         tegra_uarta_device.dev.platform_data = &ardbeg_uarta_pdata;
403         tegra_uartb_device.dev.platform_data = &ardbeg_uartb_pdata;
404         tegra_uartc_device.dev.platform_data = &ardbeg_uartc_pdata;
405         platform_add_devices(ardbeg_uart_devices,
406                         ARRAY_SIZE(ardbeg_uart_devices));
407 #endif
408         tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
409         if (!is_tegra_debug_uartport_hs()) {
410                 int debug_port_id = uart_console_debug_init(3);
411                 if (debug_port_id < 0)
412                         return;
413
414 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
415 #if !defined(CONFIG_TRUSTED_FOUNDATIONS) && \
416         defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER)
417         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_AVP, NULL, -1, -1);
418         platform_device_register(uart_console_debug_device);
419 #else
420         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
421 #endif
422 #else
423                 platform_device_register(uart_console_debug_device);
424 #endif
425         } else {
426                 tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
427                 platform_device_register(&tegra_uartd_device);
428         }
429 }
430
431 static struct resource tegra_rtc_resources[] = {
432         [0] = {
433                 .start = TEGRA_RTC_BASE,
434                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
435                 .flags = IORESOURCE_MEM,
436         },
437         [1] = {
438                 .start = INT_RTC,
439                 .end = INT_RTC,
440                 .flags = IORESOURCE_IRQ,
441         },
442 };
443
444 static struct platform_device tegra_rtc_device = {
445         .name = "tegra_rtc",
446         .id   = -1,
447         .resource = tegra_rtc_resources,
448         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
449 };
450
451 static struct platform_device *ardbeg_devices[] __initdata = {
452         &tegra_pmu_device,
453         &tegra_rtc_device,
454 #if defined(CONFIG_TEGRA_WAKEUP_MONITOR)
455         &tegratab_tegra_wakeup_monitor_device,
456 #endif
457         &tegra_udc_device,
458 #if defined(CONFIG_TEGRA_WATCHDOG)
459         &tegra_wdt0_device,
460 #endif
461 #if defined(CONFIG_TEGRA_AVP)
462         &tegra_avp_device,
463 #endif
464 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) && !defined(CONFIG_USE_OF)
465         &tegra12_se_device,
466 #endif
467         &tegra_ahub_device,
468         &tegra_dam_device0,
469         &tegra_dam_device1,
470         &tegra_dam_device2,
471         &tegra_i2s_device0,
472         &tegra_i2s_device1,
473         &tegra_i2s_device3,
474         &tegra_i2s_device4,
475         &tegra_spdif_device,
476         &spdif_dit_device,
477         &bluetooth_dit_device,
478         &baseband_dit_device,
479         &tegra_hda_device,
480         &tegra_offload_device,
481         &tegra30_avp_audio_device,
482 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
483         &tegra_aes_device,
484 #endif
485         &tegra_hier_ictlr_device,
486 };
487
488 static struct tegra_usb_platform_data tegra_udc_pdata = {
489         .port_otg = true,
490         .has_hostpc = true,
491         .unaligned_dma_buf_supported = false,
492         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
493         .op_mode = TEGRA_USB_OPMODE_DEVICE,
494         .u_data.dev = {
495                 .vbus_pmu_irq = 0,
496                 .vbus_gpio = -1,
497                 .charging_supported = true,
498                 .remote_wakeup_supported = false,
499         },
500         .u_cfg.utmi = {
501                 .hssync_start_delay = 0,
502                 .elastic_limit = 16,
503                 .idle_wait_delay = 17,
504                 .term_range_adj = 6,
505                 .xcvr_setup = 8,
506                 .xcvr_lsfslew = 2,
507                 .xcvr_lsrslew = 2,
508                 .xcvr_setup_offset = 0,
509                 .xcvr_use_fuses = 1,
510         },
511 };
512
513 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
514         .port_otg = true,
515         .has_hostpc = true,
516         .unaligned_dma_buf_supported = false,
517         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
518         .op_mode = TEGRA_USB_OPMODE_HOST,
519         .u_data.host = {
520                 .vbus_gpio = -1,
521                 .hot_plug = false,
522                 .remote_wakeup_supported = true,
523                 .power_off_on_suspend = true,
524         },
525         .u_cfg.utmi = {
526                 .hssync_start_delay = 0,
527                 .elastic_limit = 16,
528                 .idle_wait_delay = 17,
529                 .term_range_adj = 6,
530                 .xcvr_setup = 15,
531                 .xcvr_lsfslew = 0,
532                 .xcvr_lsrslew = 3,
533                 .xcvr_setup_offset = 0,
534                 .xcvr_use_fuses = 1,
535                 .vbus_oc_map = 0x4,
536                 .xcvr_hsslew_lsb = 2,
537         },
538 };
539
540 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
541         .port_otg = false,
542         .has_hostpc = true,
543         .unaligned_dma_buf_supported = false,
544         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
545         .op_mode = TEGRA_USB_OPMODE_HOST,
546         .u_data.host = {
547                 .vbus_gpio = -1,
548                 .hot_plug = false,
549                 .remote_wakeup_supported = true,
550                 .power_off_on_suspend = true,
551         },
552         .u_cfg.utmi = {
553                 .hssync_start_delay = 0,
554                 .elastic_limit = 16,
555                 .idle_wait_delay = 17,
556                 .term_range_adj = 6,
557                 .xcvr_setup = 8,
558                 .xcvr_lsfslew = 2,
559                 .xcvr_lsrslew = 2,
560                 .xcvr_setup_offset = 0,
561                 .xcvr_use_fuses = 1,
562                 .vbus_oc_map = 0x5,
563         },
564 };
565
566 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
567         .port_otg = false,
568         .has_hostpc = true,
569         .unaligned_dma_buf_supported = false,
570         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
571         .op_mode = TEGRA_USB_OPMODE_HOST,
572         .u_data.host = {
573                 .vbus_gpio = -1,
574                 .hot_plug = false,
575                 .remote_wakeup_supported = true,
576                 .power_off_on_suspend = true,
577         },
578         .u_cfg.utmi = {
579         .hssync_start_delay = 0,
580                 .elastic_limit = 16,
581                 .idle_wait_delay = 17,
582                 .term_range_adj = 6,
583                 .xcvr_setup = 8,
584                 .xcvr_lsfslew = 2,
585                 .xcvr_lsrslew = 2,
586                 .xcvr_setup_offset = 0,
587                 .xcvr_use_fuses = 1,
588                 .vbus_oc_map = 0x5,
589         },
590 };
591
592 static struct gpio modem_gpios[] = { /* Bruce modem */
593         {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"},
594         {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"},
595         {MDM_SAR0, GPIOF_OUT_INIT_LOW, "MODEM SAR0"},
596 };
597
598 static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = {
599         .port_otg = false,
600         .has_hostpc = true,
601         .unaligned_dma_buf_supported = false,
602         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
603         .op_mode = TEGRA_USB_OPMODE_HOST,
604         .u_data.host = {
605                 .vbus_gpio = -1,
606                 .hot_plug = false,
607                 .remote_wakeup_supported = true,
608                 .power_off_on_suspend = true,
609         },
610 };
611
612 static struct tegra_usb_platform_data tegra_ehci2_hsic_smsc_hub_pdata = {
613         .port_otg = false,
614         .has_hostpc = true,
615         .unaligned_dma_buf_supported = false,
616         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
617         .op_mode        = TEGRA_USB_OPMODE_HOST,
618         .u_data.host = {
619                 .vbus_gpio = -1,
620                 .hot_plug = false,
621                 .remote_wakeup_supported = true,
622                 .power_off_on_suspend = true,
623         },
624 };
625
626
627 static struct tegra_usb_otg_data tegra_otg_pdata = {
628         .ehci_device = &tegra_ehci1_device,
629         .ehci_pdata = &tegra_ehci1_utmi_pdata,
630 };
631
632 static void ardbeg_usb_init(void)
633 {
634         int usb_port_owner_info = tegra_get_usb_port_owner_info();
635         int modem_id = tegra_get_modem_id();
636         struct board_info bi;
637         tegra_get_pmu_board_info(&bi);
638
639         if (board_info.sku == 1100 || board_info.board_id == BOARD_P1761 ||
640                                         board_info.board_id == BOARD_E1784)
641                 tegra_ehci1_utmi_pdata.u_data.host.turn_off_vbus_on_lp0 = true;
642
643         if (board_info.board_id == BOARD_PM359 ||
644                         board_info.board_id == BOARD_PM358 ||
645                         board_info.board_id == BOARD_PM370 ||
646                         board_info.board_id == BOARD_PM374 ||
647                         board_info.board_id == BOARD_PM375 ||
648                         board_info.board_id == BOARD_PM377 ||
649                         board_info.board_id == BOARD_PM363) {
650                 /* Laguna */
651                 /* Host cable is detected through AMS PMU Interrupt */
652                 if (board_info.major_revision >= 'A' &&
653                         board_info.major_revision <= 'D' &&
654                         board_info.board_id == BOARD_PM375) {
655                         tegra_udc_pdata.id_det_type = TEGRA_USB_VIRTUAL_ID;
656                         tegra_ehci1_utmi_pdata.id_det_type =
657                                                 TEGRA_USB_VIRTUAL_ID;
658                 } else {
659                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
660                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
661                 }
662                 tegra_ehci1_utmi_pdata.id_extcon_dev_name = "as3722-extcon";
663
664                 /* Disable Charging detection on Jetson */
665                 if (board_info.board_id == BOARD_PM375)
666                         tegra_udc_pdata.u_data.dev.charging_supported = false;
667
668         } else {
669                 /* Ardbeg and TN8 */
670
671                 /*
672                  * TN8 supports vbus changing and it can handle
673                  * vbus voltages larger then 5V.  Enable this.
674                  */
675                 if (board_info.board_id == BOARD_P1761 ||
676                         board_info.board_id == BOARD_E1784 ||
677                         board_info.board_id == BOARD_E1780) {
678
679                         /*
680                          * Set the maximum voltage that can be supplied
681                          * over USB vbus that the board supports if we use
682                          * a quick charge 2 wall charger.
683                          */
684                         tegra_udc_pdata.qc2_voltage = TEGRA_USB_QC2_9V;
685                         tegra_udc_pdata.u_data.dev.qc2_current_limit_ma = 1200;
686
687                         /* charger needs to be set to 2A - h/w will do 1.8A */
688                         tegra_udc_pdata.u_data.dev.dcp_current_limit_ma = 2000;
689                 }
690
691                 switch (bi.board_id) {
692                 case BOARD_E1733:
693                         /* Host cable is detected through PMU Interrupt */
694                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
695                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
696                         tegra_ehci1_utmi_pdata.id_extcon_dev_name =
697                                                          "as3722-extcon";
698                         break;
699                 case BOARD_E1736:
700                 case BOARD_E1769:
701                 case BOARD_E1735:
702                 case BOARD_E1936:
703                 case BOARD_P1761:
704                         /* Device cable is detected through PMU Interrupt */
705                         tegra_udc_pdata.support_pmu_vbus = true;
706                         tegra_udc_pdata.vbus_extcon_dev_name = "palmas-extcon";
707                         tegra_ehci1_utmi_pdata.support_pmu_vbus = true;
708                         tegra_ehci1_utmi_pdata.vbus_extcon_dev_name =
709                                                          "palmas-extcon";
710                         /* Host cable is detected through PMU Interrupt */
711                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
712                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
713                         tegra_ehci1_utmi_pdata.id_extcon_dev_name =
714                                                          "palmas-extcon";
715                 }
716
717                 /* Enable Y-Cable support */
718                 if (bi.board_id == BOARD_P1761)
719                         tegra_ehci1_utmi_pdata.u_data.host.support_y_cable =
720                                                         true;
721         }
722
723         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
724                 tegra_otg_pdata.is_xhci = false;
725                 tegra_udc_pdata.u_data.dev.is_xhci = false;
726         } else {
727                 tegra_otg_pdata.is_xhci = true;
728                 tegra_udc_pdata.u_data.dev.is_xhci = true;
729         }
730         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
731         platform_device_register(&tegra_otg_device);
732         /* Setup the udc platform data */
733         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
734
735         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
736                 if (!modem_id) {
737                         if ((bi.board_id != BOARD_P1761) &&
738                             (bi.board_id != BOARD_E1922) &&
739                             (bi.board_id != BOARD_E1784)) {
740                                 tegra_ehci2_device.dev.platform_data =
741                                         &tegra_ehci2_utmi_pdata;
742                                 platform_device_register(&tegra_ehci2_device);
743                         }
744                 }
745         }
746
747         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
748                 if ((bi.board_id != BOARD_P1761) &&
749                     (bi.board_id != BOARD_E1922) &&
750                     (bi.board_id != BOARD_E1784)) {
751                         tegra_ehci3_device.dev.platform_data =
752                                 &tegra_ehci3_utmi_pdata;
753                         platform_device_register(&tegra_ehci3_device);
754                 }
755         }
756
757 }
758
759 static struct tegra_xusb_platform_data xusb_pdata = {
760         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_SS_P1 |
761                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_USB2_P2,
762 };
763
764 #ifdef CONFIG_TEGRA_XUSB_PLATFORM
765 static void ardbeg_xusb_init(void)
766 {
767         int usb_port_owner_info = tegra_get_usb_port_owner_info();
768
769         xusb_pdata.lane_owner = (u8) tegra_get_lane_owner_info();
770
771         if (board_info.board_id == BOARD_PM359 ||
772                         board_info.board_id == BOARD_PM358 ||
773                         board_info.board_id == BOARD_PM374 ||
774                         board_info.board_id == BOARD_PM370 ||
775                         board_info.board_id == BOARD_PM363) {
776                 if (board_info.board_id == BOARD_PM374 ||
777                         board_info.board_id == BOARD_PM370)
778                         pr_info("Norrin. 0x%x\n", board_info.board_id);
779                 else
780                         pr_info("Laguna. 0x%x\n", board_info.board_id);
781
782                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
783                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
784                                 TEGRA_XUSB_SS_P0);
785
786                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
787                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
788                                 TEGRA_XUSB_SS_P1 | TEGRA_XUSB_USB2_P2);
789
790                 /* FIXME Add for UTMIP2 when have odmdata assigend */
791         } else if (board_info.board_id == BOARD_PM375) {
792                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
793                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
794                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
795                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P2 |
796                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0);
797                 xusb_pdata.portmap &= ~(TEGRA_XUSB_SS_P1);
798         } else {
799                 /* Ardbeg */
800                 if (board_info.board_id == BOARD_E1781) {
801                         pr_info("Shield ERS-S. 0x%x\n", board_info.board_id);
802                         /* Shield ERS-S */
803                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
804                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
805
806                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
807                                 xusb_pdata.portmap &= ~(
808                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0 |
809                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
810                 } else {
811                         pr_info("Shield ERS 0x%x\n", board_info.board_id);
812                         /* Shield ERS */
813                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
814                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
815                                         TEGRA_XUSB_SS_P0);
816
817                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
818                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
819                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
820                 }
821                 /* FIXME Add for UTMIP2 when have odmdata assigend */
822         }
823
824         if (usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)
825                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P0;
826
827         if (usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)
828                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P1;
829 }
830 #endif
831
832 static int baseband_init(void)
833 {
834         int ret;
835
836         ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios));
837         if (ret) {
838                 pr_warn("%s:gpio request failed\n", __func__);
839                 return ret;
840         }
841
842         /* enable pull-down for MDM_COLD_BOOT */
843         tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4,
844                                     TEGRA_PUPD_PULL_DOWN);
845
846         /* Release modem reset to start boot */
847         gpio_set_value(MDM_RST, 1);
848
849         /* export GPIO for user space access through sysfs */
850         gpio_export(MDM_RST, false);
851         gpio_export(MDM_SAR0, false);
852
853         return 0;
854 }
855
856 static const struct tegra_modem_operations baseband_operations = {
857         .init = baseband_init,
858 };
859
860 static struct tegra_usb_modem_power_platform_data baseband_pdata = {
861         .ops = &baseband_operations,
862         .regulator_name = "vdd_wwan_mdm",
863         .wake_gpio = -1,
864         .boot_gpio = MDM_COLDBOOT,
865         .boot_irq_flags = IRQF_TRIGGER_RISING |
866                                     IRQF_TRIGGER_FALLING |
867                                     IRQF_ONESHOT,
868         .autosuspend_delay = 2000,
869         .short_autosuspend_delay = 50,
870         .tegra_ehci_device = &tegra_ehci2_device,
871         .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata,
872         .mdm_power_report_gpio = MDM_POWER_REPORT,
873         .mdm_power_irq_flags = IRQF_TRIGGER_RISING |
874                                 IRQF_TRIGGER_FALLING |
875                                 IRQF_ONESHOT,
876 };
877
878 static struct platform_device icera_bruce_device = {
879         .name = "tegra_usb_modem_power",
880         .id = -1,
881         .dev = {
882                 .platform_data = &baseband_pdata,
883         },
884 };
885
886 static void ardbeg_modem_init(void)
887 {
888         int modem_id = tegra_get_modem_id();
889         struct board_info board_info;
890         struct board_info pmu_board_info;
891         int usb_port_owner_info = tegra_get_usb_port_owner_info();
892
893         tegra_get_board_info(&board_info);
894         tegra_get_pmu_board_info(&pmu_board_info);
895         pr_info("%s: modem_id = %d\n", __func__, modem_id);
896
897         switch (modem_id) {
898         case TEGRA_BB_BRUCE:
899                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
900                         /* Set specific USB wake source for Ardbeg */
901                         if (board_info.board_id == BOARD_E1780)
902                                 tegra_set_wake_source(42, INT_USB2);
903                         if (pmu_board_info.board_id == BOARD_E1736 ||
904                                 pmu_board_info.board_id == BOARD_E1769 ||
905                                 pmu_board_info.board_id == BOARD_E1936)
906                                 baseband_pdata.regulator_name = NULL;
907                         platform_device_register(&icera_bruce_device);
908                 }
909                 break;
910         case TEGRA_BB_HSIC_HUB: /* HSIC hub */
911                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
912                         tegra_ehci2_device.dev.platform_data =
913                                 &tegra_ehci2_hsic_smsc_hub_pdata;
914                         /* Set specific USB wake source for Ardbeg */
915                         if (board_info.board_id == BOARD_E1780)
916                                 tegra_set_wake_source(42, INT_USB2);
917                         platform_device_register(&tegra_ehci2_device);
918                 } else
919                         xusb_pdata.pretend_connect_0 = true;
920                 break;
921         default:
922                 return;
923         }
924 }
925
926 #ifdef CONFIG_USE_OF
927 static struct of_dev_auxdata ardbeg_auxdata_lookup[] __initdata = {
928         T124_SPI_OF_DEV_AUXDATA,
929         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
930                                 NULL),
931         OF_DEV_AUXDATA("nvidia,tegra124-se", 0x70012000, "tegra12-se", NULL),
932         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
933                 NULL),
934         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", TEGRA_GK20A_BAR0_BASE,
935                 "gk20a.0", NULL),
936 #ifdef CONFIG_ARCH_TEGRA_VIC
937         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03.0", NULL),
938 #endif
939         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
940                 NULL),
941         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi.0", NULL),
942         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp.0", NULL),
943         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISPB_BASE, "isp.1", NULL),
944         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
945         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0",
946                                 NULL),
947         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1",
948                                 NULL),
949         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2",
950                                 NULL),
951         T124_I2C_OF_DEV_AUXDATA,
952         OF_DEV_AUXDATA("nvidia,tegra124-xhci", 0x70090000, "tegra-xhci",
953                                 &xusb_pdata),
954         OF_DEV_AUXDATA("nvidia,tegra124-dc", TEGRA_DISPLAY_BASE, "tegradc.0",
955                 NULL),
956         OF_DEV_AUXDATA("nvidia,tegra124-dc", TEGRA_DISPLAY2_BASE, "tegradc.1",
957                 NULL),
958         OF_DEV_AUXDATA("nvidia,tegra124-nvavp", 0x60001000, "nvavp",
959                                 NULL),
960         OF_DEV_AUXDATA("nvidia,tegra124-pwm", 0x7000a000, "tegra-pwm", NULL),
961         OF_DEV_AUXDATA("nvidia,tegra124-dfll", 0x70110000, "tegra_cl_dvfs",
962                 NULL),
963         OF_DEV_AUXDATA("nvidia,tegra132-dfll", 0x70040084, "tegra_cl_dvfs",
964                 NULL),
965         OF_DEV_AUXDATA("nvidia,tegra124-efuse", TEGRA_FUSE_BASE, "tegra-fuse",
966                 NULL),
967         OF_DEV_AUXDATA("nvidia,tegra124-camera", 0, "pcl-generic",
968                                 NULL),
969         OF_DEV_AUXDATA("nvidia,tegra114-ahci-sata", 0x70027000, "tegra-sata.0",
970                 NULL),
971         {}
972 };
973 #endif
974
975 struct maxim_sti_pdata maxim_sti_pdata = {
976         .touch_fusion         = "/vendor/bin/touch_fusion",
977         .config_file          = "/vendor/firmware/touch_fusion.cfg",
978         .fw_name              = "maxim_fp35.bin",
979         .nl_family            = TF_FAMILY_NAME,
980         .nl_mc_groups         = 5,
981         .chip_access_method   = 2,
982         .default_reset_state  = 0,
983         .tx_buf_size          = 4100,
984         .rx_buf_size          = 4100,
985         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
986         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
987 };
988
989 struct maxim_sti_pdata maxim_sti_pdata_rd = {
990         .touch_fusion         = "/vendor/bin/touch_fusion_rd",
991         .config_file          = "/vendor/firmware/touch_fusion.cfg",
992         .fw_name              = "maxim_fp35.bin",
993         .nl_family            = TF_FAMILY_NAME,
994         .nl_mc_groups         = 5,
995         .chip_access_method   = 2,
996         .default_reset_state  = 0,
997         .tx_buf_size          = 4100,
998         .rx_buf_size          = 4100,
999         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
1000         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
1001 };
1002
1003 static struct tegra_spi_device_controller_data maxim_dev_cdata = {
1004         .rx_clk_tap_delay = 0,
1005         .is_hw_based_cs = true,
1006         .tx_clk_tap_delay = 0,
1007 };
1008
1009 struct spi_board_info maxim_sti_spi_board = {
1010         .modalias = MAXIM_STI_NAME,
1011         .bus_num = TOUCH_SPI_ID,
1012         .chip_select = TOUCH_SPI_CS,
1013         .max_speed_hz = 12 * 1000 * 1000,
1014         .mode = SPI_MODE_0,
1015         .platform_data = &maxim_sti_pdata,
1016         .controller_data = &maxim_dev_cdata,
1017 };
1018
1019 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
1020         /* name         parent          rate            enabled */
1021         { "extern2",    "pll_p",        41000000,       false},
1022         { "clk_out_2",  "extern2",      40800000,       false},
1023         { NULL,         NULL,           0,              0},
1024 };
1025
1026 static struct rm_spi_ts_platform_data rm31080ts_ardbeg_data = {
1027         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1028         .config = 0,
1029         .platform_id = RM_PLATFORM_A010,
1030         .name_of_clock = "clk_out_2",
1031         .name_of_clock_con = "extern2",
1032 };
1033
1034 static struct rm_spi_ts_platform_data rm31080ts_tn8_data = {
1035         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1036         .config = 0,
1037         .platform_id = RM_PLATFORM_T008,
1038         .name_of_clock = "clk_out_2",
1039         .name_of_clock_con = "extern2",
1040 };
1041
1042 static struct rm_spi_ts_platform_data rm31080ts_tn8_p1765_data = {
1043         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1044         .config = 0,
1045         .platform_id = RM_PLATFORM_T008_2,
1046         .name_of_clock = "clk_out_2",
1047         .name_of_clock_con = "extern2",
1048 };
1049
1050 static struct rm_spi_ts_platform_data rm31080ts_norrin_data = {
1051         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1052         .config = 0,
1053         .platform_id = RM_PLATFORM_P140,
1054         .name_of_clock = "clk_out_2",
1055         .name_of_clock_con = "extern2",
1056 };
1057
1058 struct rm_spi_ts_platform_data rm31080ts_t132loki_data = {
1059         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1060         .config = 0,
1061         .platform_id = RM_PLATFORM_L005,
1062         .name_of_clock = "clk_out_2",
1063         .name_of_clock_con = "extern2",
1064 };
1065
1066 struct rm_spi_ts_platform_data rm31080ts_t132loki_data_jdi_5 = {
1067         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1068         .config = 0,
1069         .platform_id = RM_PLATFORM_L005,
1070         .name_of_clock = "clk_out_2",
1071         .name_of_clock_con = "extern2",
1072         .gpio_sensor_select0 = false,
1073         .gpio_sensor_select1 = true,
1074 };
1075 static struct tegra_spi_device_controller_data dev_cdata = {
1076         .rx_clk_tap_delay = 0,
1077         .tx_clk_tap_delay = 16,
1078 };
1079
1080 static struct spi_board_info rm31080a_ardbeg_spi_board[1] = {
1081         {
1082                 .modalias = "rm_ts_spidev",
1083                 .bus_num = TOUCH_SPI_ID,
1084                 .chip_select = TOUCH_SPI_CS,
1085                 .max_speed_hz = 12 * 1000 * 1000,
1086                 .mode = SPI_MODE_0,
1087                 .controller_data = &dev_cdata,
1088                 .platform_data = &rm31080ts_ardbeg_data,
1089         },
1090 };
1091
1092 static struct spi_board_info rm31080a_tn8_spi_board[1] = {
1093         {
1094                 .modalias = "rm_ts_spidev",
1095                 .bus_num = TOUCH_SPI_ID,
1096                 .chip_select = TOUCH_SPI_CS,
1097                 .max_speed_hz = 18 * 1000 * 1000,
1098                 .mode = SPI_MODE_0,
1099                 .controller_data = &dev_cdata,
1100                 .platform_data = &rm31080ts_tn8_data,
1101         },
1102 };
1103
1104 static struct spi_board_info rm31080a_tn8_p1765_spi_board[1] = {
1105         {
1106                 .modalias = "rm_ts_spidev",
1107                 .bus_num = TOUCH_SPI_ID,
1108                 .chip_select = TOUCH_SPI_CS,
1109                 .max_speed_hz = 18 * 1000 * 1000,
1110                 .mode = SPI_MODE_0,
1111                 .controller_data = &dev_cdata,
1112                 .platform_data = &rm31080ts_tn8_p1765_data,
1113         },
1114 };
1115
1116 static struct spi_board_info rm31080a_norrin_spi_board[1] = {
1117         {
1118                 .modalias = "rm_ts_spidev",
1119                 .bus_num = NORRIN_TOUCH_SPI_ID,
1120                 .chip_select = NORRIN_TOUCH_SPI_CS,
1121                 .max_speed_hz = 12 * 1000 * 1000,
1122                 .mode = SPI_MODE_0,
1123                 .controller_data = &dev_cdata,
1124                 .platform_data = &rm31080ts_norrin_data,
1125         },
1126 };
1127
1128 static int __init ardbeg_touch_init(void)
1129 {
1130         tegra_get_board_info(&board_info);
1131
1132         if (tegra_get_touch_vendor_id() == MAXIM_TOUCH) {
1133                 pr_info("%s init maxim touch\n", __func__);
1134 #if defined(CONFIG_TOUCHSCREEN_MAXIM_STI) || \
1135         defined(CONFIG_TOUCHSCREEN_MAXIM_STI_MODULE)
1136                 if (tegra_get_touch_panel_id() == TOUCHPANEL_TN7)
1137                         maxim_sti_spi_board.platform_data = &maxim_sti_pdata_rd;
1138                 (void)touch_init_maxim_sti(&maxim_sti_spi_board);
1139 #endif
1140         } else if (tegra_get_touch_vendor_id() == RAYDIUM_TOUCH) {
1141                 pr_info("%s init raydium touch\n", __func__);
1142                 tegra_clk_init_from_table(touch_clk_init_table);
1143                 if (board_info.board_id == BOARD_PM374) {
1144                         rm31080a_norrin_spi_board[0].irq =
1145                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1146                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1147                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1148                                         &rm31080ts_norrin_data,
1149                                         &rm31080a_norrin_spi_board[0],
1150                                         ARRAY_SIZE(rm31080a_norrin_spi_board));
1151                 } else if ((board_info.board_id == BOARD_P2530) ||
1152                         (board_info.board_id == BOARD_E2548)) {
1153                         if (board_info.sku == BOARD_SKU_FOSTER)
1154                                 return 0;
1155                         if (tegra_get_touch_panel_id() == TOUCHPANEL_LOKI_JDI5)
1156                                 rm31080a_ardbeg_spi_board[0].platform_data =
1157                                         &rm31080ts_t132loki_data_jdi_5;
1158                         else
1159                                 rm31080a_ardbeg_spi_board[0].platform_data =
1160                                         &rm31080ts_t132loki_data;
1161                         if (board_info.fab >= 0xa3) {
1162                                 rm31080ts_t132loki_data.name_of_clock = NULL;
1163                                 rm31080ts_t132loki_data.name_of_clock_con = NULL;
1164                         } else
1165                                 tegra_clk_init_from_table(touch_clk_init_table);
1166                                 rm31080a_ardbeg_spi_board[0].irq =
1167                                         gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1168                                 touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1169                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1170                                         &rm31080ts_t132loki_data,
1171                                         &rm31080a_ardbeg_spi_board[0],
1172                                         ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1173                 } else if (board_info.board_id == BOARD_P1761) {
1174                         rm31080a_tn8_spi_board[0].irq =
1175                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1176                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1177                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
1178                                 &rm31080ts_tn8_data,
1179                                 &rm31080a_tn8_spi_board[0],
1180                                 ARRAY_SIZE(rm31080a_tn8_spi_board));
1181                 } else if (board_info.board_id == BOARD_P1765) {
1182                         rm31080a_tn8_p1765_spi_board[0].irq =
1183                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1184                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1185                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
1186                                 &rm31080ts_tn8_p1765_data,
1187                                 &rm31080a_tn8_p1765_spi_board[0],
1188                                 ARRAY_SIZE(rm31080a_tn8_p1765_spi_board));
1189                 } else {
1190                         rm31080a_ardbeg_spi_board[0].irq =
1191                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1192                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1193                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1194                                         &rm31080ts_ardbeg_data,
1195                                         &rm31080a_ardbeg_spi_board[0],
1196                                         ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1197                 }
1198         }
1199         return 0;
1200 }
1201
1202 static void __init ardbeg_sysedp_init(void)
1203 {
1204         struct board_info bi;
1205
1206         tegra_get_board_info(&bi);
1207
1208         switch (bi.board_id) {
1209         case BOARD_E1780:
1210                 if (bi.sku == 1100) {
1211                         tn8_new_sysedp_init();
1212                 }
1213                 else
1214                         shield_new_sysedp_init();
1215                 break;
1216         case BOARD_E1971:
1217         case BOARD_E1922:
1218         case BOARD_E1784:
1219         case BOARD_P1761:
1220         case BOARD_P1765:
1221                 tn8_new_sysedp_init();
1222                 break;
1223         case BOARD_PM358:
1224         case BOARD_PM359:
1225         case BOARD_PM375:
1226         case BOARD_PM377:
1227         default:
1228                 break;
1229         }
1230 }
1231
1232 static void __init ardbeg_sysedp_dynamic_capping_init(void)
1233 {
1234         struct board_info bi;
1235
1236         tegra_get_board_info(&bi);
1237
1238         switch (bi.board_id) {
1239         case BOARD_E1780:
1240                 if (bi.sku == 1100)
1241                         tn8_sysedp_dynamic_capping_init();
1242                 else
1243                         shield_sysedp_dynamic_capping_init();
1244                 break;
1245         case BOARD_E1971:
1246         case BOARD_E1922:
1247         case BOARD_E1784:
1248         case BOARD_P1761:
1249         case BOARD_P1765:
1250                 tn8_sysedp_dynamic_capping_init();
1251                 break;
1252         case BOARD_PM358:
1253         case BOARD_PM359:
1254         case BOARD_PM375:
1255         case BOARD_PM377:
1256         default:
1257                 break;
1258         }
1259 }
1260
1261 static void __init ardbeg_sysedp_batmon_init(void)
1262 {
1263         struct board_info bi;
1264
1265         if (!IS_ENABLED(CONFIG_SYSEDP_FRAMEWORK))
1266                 return;
1267
1268         tegra_get_board_info(&bi);
1269
1270         switch (bi.board_id) {
1271         case BOARD_E1780:
1272                 if (bi.sku != 1100)
1273                         shield_sysedp_batmon_init();
1274                 break;
1275         case BOARD_PM358:
1276         case BOARD_PM359:
1277         case BOARD_PM375:
1278         case BOARD_PM377:
1279         default:
1280                 break;
1281         }
1282 }
1283
1284
1285
1286 static void __init edp_init(void)
1287 {
1288         struct board_info bi;
1289
1290         tegra_get_board_info(&bi);
1291
1292         switch (bi.board_id) {
1293         case BOARD_E1780:
1294                 if (bi.sku == 1100)
1295                         tn8_edp_init();
1296                 else
1297                         ardbeg_edp_init();
1298                 break;
1299         case BOARD_P1761:
1300                         tn8_edp_init();
1301                         break;
1302         case BOARD_PM358:
1303         case BOARD_PM359:
1304         case BOARD_PM377:
1305                         laguna_edp_init();
1306                         break;
1307         case BOARD_P2530:
1308         case BOARD_E2548:
1309                         loki_edp_init();
1310                         break;
1311         case BOARD_PM375:
1312         default:
1313                         ardbeg_edp_init();
1314                         break;
1315         }
1316 }
1317
1318 static void __init tegra_ardbeg_early_init(void)
1319 {
1320         ardbeg_sysedp_init();
1321         tegra_clk_init_from_table(ardbeg_clk_init_table);
1322         tegra_clk_verify_parents();
1323         if (of_machine_is_compatible("nvidia,jetson-tk1"))
1324                 tegra_soc_device_init("jetson-tk1");
1325         else if (of_machine_is_compatible("nvidia,laguna"))
1326                 tegra_soc_device_init("laguna");
1327         else if (of_machine_is_compatible("nvidia,tn8"))
1328                 tegra_soc_device_init("tn8");
1329         else if (of_machine_is_compatible("nvidia,ardbeg_sata"))
1330                 tegra_soc_device_init("ardbeg_sata");
1331         else if (of_machine_is_compatible("nvidia,norrin"))
1332                 tegra_soc_device_init("norrin");
1333         else if (of_machine_is_compatible("nvidia,bowmore"))
1334                 tegra_soc_device_init("bowmore");
1335         else if (of_machine_is_compatible("nvidia,t132loki"))
1336                 tegra_soc_device_init("t132loki");
1337         else
1338                 tegra_soc_device_init("ardbeg");
1339 }
1340
1341 static struct tegra_dtv_platform_data ardbeg_dtv_pdata = {
1342         .dma_req_selector = 11,
1343 };
1344
1345 static void __init ardbeg_dtv_init(void)
1346 {
1347         tegra_dtv_device.dev.platform_data = &ardbeg_dtv_pdata;
1348         platform_device_register(&tegra_dtv_device);
1349 }
1350
1351 static struct tegra_io_dpd pexbias_io = {
1352         .name                   = "PEX_BIAS",
1353         .io_dpd_reg_index       = 0,
1354         .io_dpd_bit             = 4,
1355 };
1356 static struct tegra_io_dpd pexclk1_io = {
1357         .name                   = "PEX_CLK1",
1358         .io_dpd_reg_index       = 0,
1359         .io_dpd_bit             = 5,
1360 };
1361 static struct tegra_io_dpd pexclk2_io = {
1362         .name                   = "PEX_CLK2",
1363         .io_dpd_reg_index       = 0,
1364         .io_dpd_bit             = 6,
1365 };
1366
1367 #ifdef CONFIG_NV_SENSORHUB
1368 static int __init tegra_jetson_sensorhub_init(void)
1369 {
1370
1371         if (gpio_request(SENSOR_HUB_RST, "sensor_hub_rst"))
1372                 pr_warn("%s:%d: gpio_request failed", __func__, __LINE__);
1373
1374         if (gpio_request(SENSOR_HUB_BOOT0, "sensor_hub_boot0"))
1375                 pr_warn("%s:%d: gpio_request failed", __func__, __LINE__);
1376
1377         if (gpio_direction_output(SENSOR_HUB_BOOT0, 0))
1378                 pr_warn("%s:%d: gpio_direction_output failed",
1379                         __func__, __LINE__);
1380
1381         if (gpio_direction_output(SENSOR_HUB_RST, 0))
1382                 pr_warn("%s:%d: gpio_direction_output failed",
1383                         __func__, __LINE__);
1384
1385         /* SENSOR_HUB_RESET */
1386         gpio_set_value(SENSOR_HUB_RST, 0);
1387         /* Boot0 is useless in Kalamos HW00 board  - Drive low */
1388         gpio_set_value(SENSOR_HUB_BOOT0, 0);
1389         msleep(1000);
1390         gpio_set_value(SENSOR_HUB_RST, 1);
1391
1392         if (gpio_export(SENSOR_HUB_RST, 1))
1393                 pr_warn("%s:%d: gpio_export failed", __func__, __LINE__);
1394
1395         if (gpio_export(SENSOR_HUB_BOOT0, 1))
1396                 pr_warn("%s:%d: gpio_export failed", __func__, __LINE__);
1397
1398         pr_info("%s: MCU init done\n", __func__);
1399
1400         return 0;
1401
1402 }
1403
1404 late_initcall(tegra_jetson_sensorhub_init);
1405 #endif
1406
1407 static void __init tegra_ardbeg_late_init(void)
1408 {
1409         struct board_info board_info;
1410         tegra_get_board_info(&board_info);
1411         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1412                 board_info.board_id, board_info.sku,
1413                 board_info.fab, board_info.major_revision,
1414                 board_info.minor_revision);
1415
1416         if (board_info.board_id == BOARD_E2548 ||
1417                         board_info.board_id == BOARD_P2530)
1418                 loki_pinmux_init();
1419 #ifndef CONFIG_MACH_EXUMA
1420         ardbeg_display_init();
1421 #endif
1422         ardbeg_uart_init();
1423         ardbeg_usb_init();
1424         ardbeg_modem_init();
1425 #ifdef CONFIG_TEGRA_XUSB_PLATFORM
1426         ardbeg_xusb_init();
1427 #endif
1428         ardbeg_i2c_init();
1429         ardbeg_audio_init();
1430         platform_add_devices(ardbeg_devices, ARRAY_SIZE(ardbeg_devices));
1431         if (board_info.board_id == BOARD_PM374) /* Norrin ERS */
1432                 platform_device_register(&norrin_audio_device_max98090);
1433         else if (board_info.board_id != BOARD_PM359)
1434                 platform_device_register(&ardbeg_audio_device_rt5639);
1435         tegra_io_dpd_init();
1436         if (board_info.board_id == BOARD_E2548 ||
1437                         board_info.board_id == BOARD_P2530)
1438                 loki_sdhci_init();
1439         else
1440                 ardbeg_sdhci_init();
1441
1442         if (board_info.board_id == BOARD_PM359 ||
1443                         board_info.board_id == BOARD_PM358 ||
1444                         board_info.board_id == BOARD_PM370 ||
1445                         board_info.board_id == BOARD_PM375 ||
1446                         board_info.board_id == BOARD_PM377 ||
1447                         board_info.board_id == BOARD_PM363)
1448                 laguna_regulator_init();
1449         else if (board_info.board_id == BOARD_PM374)
1450                 norrin_regulator_init();
1451         else if (board_info.board_id == BOARD_E2548 ||
1452                         board_info.board_id == BOARD_P2530)
1453                 loki_regulator_init();
1454         else
1455                 ardbeg_regulator_init();
1456         ardbeg_dtv_init();
1457         ardbeg_suspend_init();
1458
1459         if ((board_info.board_id == BOARD_PM374) ||
1460                 (board_info.board_id == BOARD_E1971) ||
1461                 (board_info.board_id == BOARD_E1973))
1462                 norrin_emc_init();
1463         else if (board_info.board_id == BOARD_E2548 ||
1464                         board_info.board_id == BOARD_P2530)
1465                 loki_emc_init();
1466         else
1467                 ardbeg_emc_init();
1468
1469         edp_init();
1470         isomgr_init();
1471         ardbeg_touch_init();
1472         if (board_info.board_id == BOARD_E2548 ||
1473                         board_info.board_id == BOARD_P2530)
1474                 loki_panel_init();
1475         else
1476                 ardbeg_panel_init();
1477
1478                 /* put PEX pads into DPD mode to save additional power */
1479                 tegra_io_dpd_enable(&pexbias_io);
1480                 tegra_io_dpd_enable(&pexclk1_io);
1481                 tegra_io_dpd_enable(&pexclk2_io);
1482
1483         if (board_info.board_id == BOARD_E2548 ||
1484                         board_info.board_id == BOARD_P2530)
1485                 loki_kbc_init();
1486
1487 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1488         tegra_wdt_recovery_init();
1489 #endif
1490
1491
1492         if (board_info.board_id == BOARD_PM374 ||
1493                 board_info.board_id == BOARD_PM359 ||
1494                 board_info.board_id == BOARD_PM358 ||
1495                 board_info.board_id == BOARD_PM370 ||
1496                 board_info.board_id == BOARD_PM375 ||
1497                 board_info.board_id == BOARD_PM377 ||
1498                 board_info.board_id == BOARD_PM363) {
1499                 ardbeg_sensors_init();
1500                 norrin_soctherm_init();
1501         }       else if (board_info.board_id == BOARD_E2548 ||
1502                         board_info.board_id == BOARD_P2530) {
1503                 loki_sensors_init();
1504                 loki_fan_init();
1505                 loki_soctherm_init();
1506         }       else {
1507                 ardbeg_sensors_init();
1508                 ardbeg_soctherm_init();
1509         }
1510
1511         ardbeg_setup_bluedroid_pm();
1512         ardbeg_sysedp_dynamic_capping_init();
1513         ardbeg_sysedp_batmon_init();
1514 }
1515
1516 static void __init tegra_ardbeg_init_early(void)
1517 {
1518         tegra_get_board_info(&board_info);
1519         if (board_info.board_id == BOARD_E2548 ||
1520                         board_info.board_id == BOARD_P2530)
1521                 loki_rail_alignment_init();
1522         else
1523                 ardbeg_rail_alignment_init();
1524         tegra12x_init_early();
1525 }
1526
1527 static void __init tegra_ardbeg_dt_init(void)
1528 {
1529         tegra_get_board_info(&board_info);
1530         tegra_get_display_board_info(&display_board_info);
1531
1532         tegra_ardbeg_early_init();
1533 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
1534         carveout_linear_set(&tegra_generic_cma_dev);
1535         carveout_linear_set(&tegra_vpr_cma_dev);
1536 #endif
1537 #ifdef CONFIG_USE_OF
1538         ardbeg_camera_auxdata(ardbeg_auxdata_lookup);
1539         of_platform_populate(NULL,
1540                 of_default_bus_match_table, ardbeg_auxdata_lookup,
1541                 &platform_bus);
1542 #endif
1543         tegra_get_board_info(&board_info);
1544         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1545                 board_info.board_id, board_info.sku,
1546                 board_info.fab, board_info.major_revision,
1547                 board_info.minor_revision);
1548
1549         tegra_ardbeg_late_init();
1550 }
1551
1552 static void __init tegra_ardbeg_reserve(void)
1553 {
1554 #ifdef CONFIG_TEGRA_HDMI_PRIMARY
1555         ulong tmp;
1556 #endif /* CONFIG_TEGRA_HDMI_PRIMARY */
1557
1558 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) || \
1559                 defined(CONFIG_TEGRA_NO_CARVEOUT)
1560         ulong carveout_size = 0;
1561         ulong fb2_size = SZ_16M;
1562 #else
1563         ulong carveout_size = SZ_1G;
1564         ulong fb2_size = SZ_4M;
1565 #endif
1566         ulong fb1_size = SZ_16M + SZ_2M;
1567         ulong vpr_size = 186 * SZ_1M;
1568
1569 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
1570         /* support FBcon on 4K monitors */
1571         fb2_size = SZ_64M + SZ_8M;      /* 4096*2160*4*2 = 70778880 bytes */
1572 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
1573
1574 #ifdef CONFIG_TEGRA_HDMI_PRIMARY
1575         tmp = fb1_size;
1576         fb1_size = fb2_size;
1577         fb2_size = tmp;
1578 #endif /* CONFIG_TEGRA_HDMI_PRIMARY */
1579
1580         tegra_reserve4(carveout_size, fb1_size, fb2_size, vpr_size);
1581 }
1582
1583 static const char * const ardbeg_dt_board_compat[] = {
1584         "nvidia,ardbeg",
1585         NULL
1586 };
1587
1588 static const char * const laguna_dt_board_compat[] = {
1589         "nvidia,laguna",
1590         NULL
1591 };
1592
1593 static const char * const tn8_dt_board_compat[] = {
1594         "nvidia,tn8",
1595         NULL
1596 };
1597
1598 static const char * const ardbeg_sata_dt_board_compat[] = {
1599         "nvidia,ardbeg_sata",
1600         NULL
1601 };
1602
1603 static const char * const norrin_dt_board_compat[] = {
1604         "nvidia,norrin",
1605         NULL
1606 };
1607
1608 static const char * const bowmore_dt_board_compat[] = {
1609         "nvidia,bowmore",
1610         NULL
1611 };
1612
1613 static const char * const loki_dt_board_compat[] = {
1614         "nvidia,t132loki",
1615         NULL
1616 };
1617
1618 static const char * const jetson_dt_board_compat[] = {
1619         "nvidia,jetson-tk1",
1620         NULL
1621 };
1622
1623 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
1624 DT_MACHINE_START(LOKI, "t132loki")
1625         .atag_offset    = 0x100,
1626         .smp            = smp_ops(tegra_smp_ops),
1627         .map_io         = tegra_map_common_io,
1628         .reserve        = tegra_ardbeg_reserve,
1629         .init_early     = tegra_ardbeg_init_early,
1630         .init_irq       = irqchip_init,
1631         .init_time      = clocksource_of_init,
1632         .init_machine   = tegra_ardbeg_dt_init,
1633         .restart        = tegra_assert_system_reset,
1634         .dt_compat      = loki_dt_board_compat,
1635         .init_late      = tegra_init_late
1636 MACHINE_END
1637 #endif
1638
1639 DT_MACHINE_START(LAGUNA, "laguna")
1640         .atag_offset    = 0x100,
1641         .smp            = smp_ops(tegra_smp_ops),
1642         .map_io         = tegra_map_common_io,
1643         .reserve        = tegra_ardbeg_reserve,
1644         .init_early     = tegra_ardbeg_init_early,
1645         .init_irq       = irqchip_init,
1646         .init_time      = clocksource_of_init,
1647         .init_machine   = tegra_ardbeg_dt_init,
1648         .restart        = tegra_assert_system_reset,
1649         .dt_compat      = laguna_dt_board_compat,
1650         .init_late      = tegra_init_late
1651 MACHINE_END
1652
1653 DT_MACHINE_START(TN8, "tn8")
1654         .atag_offset    = 0x100,
1655         .smp            = smp_ops(tegra_smp_ops),
1656         .map_io         = tegra_map_common_io,
1657         .reserve        = tegra_ardbeg_reserve,
1658         .init_early     = tegra_ardbeg_init_early,
1659         .init_irq       = irqchip_init,
1660         .init_time      = clocksource_of_init,
1661         .init_machine   = tegra_ardbeg_dt_init,
1662         .restart        = tegra_assert_system_reset,
1663         .dt_compat      = tn8_dt_board_compat,
1664         .init_late      = tegra_init_late
1665 MACHINE_END
1666
1667 DT_MACHINE_START(NORRIN, "norrin")
1668         .atag_offset    = 0x100,
1669         .smp            = smp_ops(tegra_smp_ops),
1670         .map_io         = tegra_map_common_io,
1671         .reserve        = tegra_ardbeg_reserve,
1672         .init_early     = tegra_ardbeg_init_early,
1673         .init_irq       = irqchip_init,
1674         .init_time      = clocksource_of_init,
1675         .init_machine   = tegra_ardbeg_dt_init,
1676         .restart        = tegra_assert_system_reset,
1677         .dt_compat      = norrin_dt_board_compat,
1678         .init_late      = tegra_init_late
1679 MACHINE_END
1680
1681 DT_MACHINE_START(BOWMORE, "bowmore")
1682         .atag_offset    = 0x100,
1683         .smp            = smp_ops(tegra_smp_ops),
1684         .map_io         = tegra_map_common_io,
1685         .reserve        = tegra_ardbeg_reserve,
1686         .init_early     = tegra_ardbeg_init_early,
1687         .init_irq       = irqchip_init,
1688         .init_time      = clocksource_of_init,
1689         .init_machine   = tegra_ardbeg_dt_init,
1690         .restart        = tegra_assert_system_reset,
1691         .dt_compat      = bowmore_dt_board_compat,
1692         .init_late      = tegra_init_late
1693 MACHINE_END
1694
1695 DT_MACHINE_START(ARDBEG, "ardbeg")
1696         .atag_offset    = 0x100,
1697         .smp            = smp_ops(tegra_smp_ops),
1698         .map_io         = tegra_map_common_io,
1699         .reserve        = tegra_ardbeg_reserve,
1700         .init_early     = tegra_ardbeg_init_early,
1701         .init_irq       = irqchip_init,
1702         .init_time      = clocksource_of_init,
1703         .init_machine   = tegra_ardbeg_dt_init,
1704         .restart        = tegra_assert_system_reset,
1705         .dt_compat      = ardbeg_dt_board_compat,
1706         .init_late      = tegra_init_late
1707 MACHINE_END
1708
1709 DT_MACHINE_START(ARDBEG_SATA, "ardbeg_sata")
1710         .atag_offset    = 0x100,
1711         .smp            = smp_ops(tegra_smp_ops),
1712         .map_io         = tegra_map_common_io,
1713         .reserve        = tegra_ardbeg_reserve,
1714         .init_early     = tegra_ardbeg_init_early,
1715         .init_irq       = irqchip_init,
1716         .init_time      = clocksource_of_init,
1717         .init_machine   = tegra_ardbeg_dt_init,
1718         .restart        = tegra_assert_system_reset,
1719         .dt_compat      = ardbeg_sata_dt_board_compat,
1720         .init_late      = tegra_init_late
1721
1722 MACHINE_END
1723
1724 DT_MACHINE_START(JETSON_TK1, "jetson-tk1")
1725         .atag_offset    = 0x100,
1726         .smp            = smp_ops(tegra_smp_ops),
1727         .map_io         = tegra_map_common_io,
1728         .reserve        = tegra_ardbeg_reserve,
1729         .init_early     = tegra_ardbeg_init_early,
1730         .init_irq       = irqchip_init,
1731         .init_time      = clocksource_of_init,
1732         .init_machine   = tegra_ardbeg_dt_init,
1733         .restart        = tegra_assert_system_reset,
1734         .dt_compat      = jetson_dt_board_compat,
1735         .init_late      = tegra_init_late
1736 MACHINE_END