arm: tegra: init tn8 and ardbeg as separate devices
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c.h>
28 #include <linux/i2c/i2c-hid.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/delay.h>
31 #include <linux/i2c-tegra.h>
32 #include <linux/gpio.h>
33 #include <linux/input.h>
34 #include <linux/platform_data/tegra_usb.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/rm31080a_ts.h>
37 #include <linux/tegra_uart.h>
38 #include <linux/memblock.h>
39 #include <linux/spi/spi-tegra.h>
40 #include <linux/nfc/pn544.h>
41 #include <linux/rfkill-gpio.h>
42 #include <linux/skbuff.h>
43 #include <linux/ti_wilink_st.h>
44 #include <linux/regulator/consumer.h>
45 #include <linux/smb349-charger.h>
46 #include <linux/max17048_battery.h>
47 #include <linux/leds.h>
48 #include <linux/i2c/at24.h>
49 #include <linux/of_platform.h>
50 #include <linux/i2c.h>
51 #include <linux/i2c-tegra.h>
52 #include <linux/tegra_uart.h>
53 #include <linux/serial_tegra.h>
54 #include <linux/edp.h>
55 #include <linux/usb/tegra_usb_phy.h>
56 #include <linux/mfd/palmas.h>
57
58 #include <mach/clk.h>
59 #include <mach/irqs.h>
60 #include <mach/pci.h>
61 #include <mach/tegra_fiq_debugger.h>
62
63 #include <mach/pinmux.h>
64 #include <mach/pinmux-t12.h>
65 #include <mach/io_dpd.h>
66 #include <mach/i2s.h>
67 #include <mach/isomgr.h>
68 #include <mach/tegra_asoc_pdata.h>
69 #include <asm/mach-types.h>
70 #include <asm/mach/arch.h>
71 #include <mach/gpio-tegra.h>
72 #include <mach/tegra_fiq_debugger.h>
73 #include <mach/xusb.h>
74 #include <linux/platform_data/tegra_usb_modem_power.h>
75
76 #include "board.h"
77 #include "board-ardbeg.h"
78 #include "board-common.h"
79 #include "board-touch-raydium.h"
80 #include "clock.h"
81 #include "common.h"
82 #include "devices.h"
83 #include "fuse.h"
84 #include "gpio-names.h"
85 #include "iomap.h"
86 #include "pm.h"
87 #include "pm-irq.h"
88 #include "tegra-board-id.h"
89
90 static struct board_info board_info, display_board_info;
91
92 static struct resource ardbeg_bluedroid_pm_resources[] = {
93         [0] = {
94                 .name   = "shutdown_gpio",
95                 .start  = TEGRA_GPIO_PR1,
96                 .end    = TEGRA_GPIO_PR1,
97                 .flags  = IORESOURCE_IO,
98         },
99         [1] = {
100                 .name = "host_wake",
101                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
102         },
103         [2] = {
104                 .name = "gpio_ext_wake",
105                 .start  = TEGRA_GPIO_PEE1,
106                 .end    = TEGRA_GPIO_PEE1,
107                 .flags  = IORESOURCE_IO,
108         },
109         [3] = {
110                 .name = "gpio_host_wake",
111                 .start  = TEGRA_GPIO_PU6,
112                 .end    = TEGRA_GPIO_PU6,
113                 .flags  = IORESOURCE_IO,
114         },
115         [4] = {
116                 .name = "reset_gpio",
117                 .start  = TEGRA_GPIO_PX1,
118                 .end    = TEGRA_GPIO_PX1,
119                 .flags  = IORESOURCE_IO,
120         },
121 };
122
123 static struct platform_device ardbeg_bluedroid_pm_device = {
124         .name = "bluedroid_pm",
125         .id             = 0,
126         .num_resources  = ARRAY_SIZE(ardbeg_bluedroid_pm_resources),
127         .resource       = ardbeg_bluedroid_pm_resources,
128 };
129
130 static noinline void __init ardbeg_setup_bluedroid_pm(void)
131 {
132         ardbeg_bluedroid_pm_resources[1].start =
133                 ardbeg_bluedroid_pm_resources[1].end =
134                                 gpio_to_irq(TEGRA_GPIO_PU6);
135         platform_device_register(&ardbeg_bluedroid_pm_device);
136 }
137
138 /*use board file for T12x*/
139 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || !defined(CONFIG_USE_OF)
140 static struct i2c_board_info __initdata rt5639_board_info = {
141         I2C_BOARD_INFO("rt5639", 0x1c),
142 };
143 static struct i2c_board_info __initdata rt5645_board_info = {
144         I2C_BOARD_INFO("rt5645", 0x1a),
145 };
146 #endif
147
148 static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
149         /* name         parent          rate            enabled */
150         { "pll_m",      NULL,           0,              false},
151         { "hda",        "pll_p",        108000000,      false},
152         { "hda2codec_2x", "pll_p",      48000000,       false},
153         { "pwm",        "pll_p",        3187500,        false},
154         { "i2s1",       "pll_a_out0",   0,              false},
155         { "i2s3",       "pll_a_out0",   0,              false},
156         { "i2s4",       "pll_a_out0",   0,              false},
157         { "spdif_out",  "pll_a_out0",   0,              false},
158         { "d_audio",    "clk_m",        12000000,       false},
159         { "dam0",       "clk_m",        12000000,       false},
160         { "dam1",       "clk_m",        12000000,       false},
161         { "dam2",       "clk_m",        12000000,       false},
162         { "audio1",     "i2s1_sync",    0,              false},
163         { "audio3",     "i2s3_sync",    0,              false},
164         { "vi_sensor",  "pll_p",        150000000,      false},
165         { "vi_sensor2", "pll_p",        150000000,      false},
166         { "cilab",      "pll_p",        150000000,      false},
167         { "cilcd",      "pll_p",        150000000,      false},
168         { "cile",       "pll_p",        150000000,      false},
169         { "i2c1",       "pll_p",        3200000,        false},
170         { "i2c2",       "pll_p",        3200000,        false},
171         { "i2c3",       "pll_p",        3200000,        false},
172         { "i2c4",       "pll_p",        3200000,        false},
173         { "i2c5",       "pll_p",        3200000,        false},
174         { "sbc1",       "pll_p",        25000000,       false},
175         { "sbc2",       "pll_p",        25000000,       false},
176         { "sbc3",       "pll_p",        25000000,       false},
177         { "sbc4",       "pll_p",        25000000,       false},
178         { "sbc5",       "pll_p",        25000000,       false},
179         { "sbc6",       "pll_p",        25000000,       false},
180         { "uarta",      "pll_p",        408000000,      false},
181         { "uartb",      "pll_p",        408000000,      false},
182         { "uartc",      "pll_p",        408000000,      false},
183         { "uartd",      "pll_p",        408000000,      false},
184         { NULL,         NULL,           0,              0},
185 };
186
187 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || !defined(CONFIG_USE_OF)
188 static struct tegra_i2c_platform_data ardbeg_i2c1_platform_data = {
189         .bus_clk_rate   = 100000,
190         .scl_gpio       = TEGRA_GPIO_I2C1_SCL,
191         .sda_gpio       = TEGRA_GPIO_I2C1_SDA,
192 };
193
194 static struct tegra_i2c_platform_data ardbeg_i2c2_platform_data = {
195         .bus_clk_rate   = 100000,
196         .is_clkon_always = true,
197         .scl_gpio       = TEGRA_GPIO_I2C2_SCL,
198         .sda_gpio       = TEGRA_GPIO_I2C2_SDA,
199 };
200
201 static struct tegra_i2c_platform_data ardbeg_i2c3_platform_data = {
202         .bus_clk_rate   = 400000,
203         .scl_gpio       = TEGRA_GPIO_I2C3_SCL,
204         .sda_gpio       = TEGRA_GPIO_I2C3_SDA,
205 };
206
207 static struct tegra_i2c_platform_data ardbeg_i2c4_platform_data = {
208         .bus_clk_rate   = 10000,
209         .scl_gpio       = TEGRA_GPIO_I2C4_SCL,
210         .sda_gpio       = TEGRA_GPIO_I2C4_SDA,
211 };
212
213 static struct tegra_i2c_platform_data ardbeg_i2c5_platform_data = {
214         .bus_clk_rate   = 400000,
215         .scl_gpio       = TEGRA_GPIO_I2C5_SCL,
216         .sda_gpio       = TEGRA_GPIO_I2C5_SDA,
217         .needs_cl_dvfs_clock = true,
218 };
219 #endif
220
221 static struct i2c_hid_platform_data i2c_keyboard_pdata = {
222         .hid_descriptor_address = 0x0,
223 };
224
225 static struct i2c_board_info __initdata i2c_keyboard_board_info = {
226         I2C_BOARD_INFO("hid", 0x3B),
227         .platform_data  = &i2c_keyboard_pdata,
228 };
229
230 static struct i2c_hid_platform_data i2c_touchpad_pdata = {
231         .hid_descriptor_address = 0x20,
232 };
233
234 static struct i2c_board_info __initdata i2c_touchpad_board_info = {
235         I2C_BOARD_INFO("hid", 0x2C),
236         .platform_data  = &i2c_touchpad_pdata,
237 };
238
239 static void ardbeg_i2c_init(void)
240 {
241         struct board_info board_info;
242         tegra_get_board_info(&board_info);
243 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
244 #ifndef CONFIG_USE_OF
245         tegra11_i2c_device1.dev.platform_data = &ardbeg_i2c1_platform_data;
246         tegra11_i2c_device2.dev.platform_data = &ardbeg_i2c2_platform_data;
247         tegra11_i2c_device3.dev.platform_data = &ardbeg_i2c3_platform_data;
248         tegra11_i2c_device4.dev.platform_data = &ardbeg_i2c4_platform_data;
249         tegra11_i2c_device5.dev.platform_data = &ardbeg_i2c5_platform_data;
250
251         platform_device_register(&tegra11_i2c_device5);
252         platform_device_register(&tegra11_i2c_device4);
253         platform_device_register(&tegra11_i2c_device3);
254         platform_device_register(&tegra11_i2c_device2);
255         platform_device_register(&tegra11_i2c_device1);
256 #endif
257 #else
258         /* T124 does not use device tree as of now */
259         tegra14_i2c_device1.dev.platform_data = &ardbeg_i2c1_platform_data;
260         tegra14_i2c_device2.dev.platform_data = &ardbeg_i2c2_platform_data;
261         tegra14_i2c_device3.dev.platform_data = &ardbeg_i2c3_platform_data;
262         tegra14_i2c_device4.dev.platform_data = &ardbeg_i2c4_platform_data;
263         tegra14_i2c_device5.dev.platform_data = &ardbeg_i2c5_platform_data;
264
265         platform_device_register(&tegra14_i2c_device5);
266         platform_device_register(&tegra14_i2c_device4);
267         platform_device_register(&tegra14_i2c_device3);
268         platform_device_register(&tegra14_i2c_device2);
269         platform_device_register(&tegra14_i2c_device1);
270 #endif
271
272 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || !defined(CONFIG_USE_OF)
273         i2c_register_board_info(0, &rt5639_board_info, 1);
274         i2c_register_board_info(0, &rt5645_board_info, 1);
275 #endif
276
277         if (board_info.board_id == BOARD_PM359 ||
278                         board_info.board_id == BOARD_PM358 ||
279                         board_info.board_id == BOARD_PM363) {
280                 i2c_keyboard_board_info.irq = gpio_to_irq(I2C_KB_IRQ);
281                 i2c_register_board_info(1, &i2c_keyboard_board_info , 1);
282
283                 i2c_touchpad_board_info.irq = gpio_to_irq(I2C_TP_IRQ);
284                 i2c_register_board_info(1, &i2c_touchpad_board_info , 1);
285         }
286 }
287
288 #ifndef CONFIG_USE_OF
289 static struct platform_device *ardbeg_uart_devices[] __initdata = {
290         &tegra_uarta_device,
291         &tegra_uartb_device,
292         &tegra_uartc_device,
293 };
294
295 static struct tegra_serial_platform_data ardbeg_uarta_pdata = {
296         .dma_req_selector = 8,
297         .modem_interrupt = false,
298 };
299
300 static struct tegra_serial_platform_data ardbeg_uartb_pdata = {
301         .dma_req_selector = 9,
302         .modem_interrupt = false,
303 };
304
305 static struct tegra_serial_platform_data ardbeg_uartc_pdata = {
306         .dma_req_selector = 10,
307         .modem_interrupt = false,
308 };
309 #endif
310
311 static struct tegra_serial_platform_data ardbeg_uartd_pdata = {
312         .dma_req_selector = 19,
313         .modem_interrupt = false,
314 };
315
316 /*use board file for T12x*/
317 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || !defined(CONFIG_USE_OF)
318 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
319         .gpio_hp_det = TEGRA_GPIO_HP_DET,
320         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
321         .gpio_spkr_en = -1,
322         .gpio_int_mic_en = -1,
323         .gpio_ext_mic_en = -1,
324         .gpio_hp_mute = -1,
325         .gpio_codec1 = -1,
326         .gpio_codec2 = -1,
327         .gpio_codec3 = -1,
328         .i2s_param[HIFI_CODEC]       = {
329                 .audio_port_id = 1,
330                 .is_i2s_master = 0,
331                 .i2s_mode = TEGRA_DAIFMT_I2S,
332         },
333         .i2s_param[BT_SCO] = {
334                 .audio_port_id = 3,
335                 .is_i2s_master = 1,
336                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
337         },
338 };
339
340 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5645 = {
341         .gpio_hp_det = TEGRA_GPIO_HP_DET,
342         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
343         .gpio_spkr_en = -1,
344         .gpio_int_mic_en = -1,
345         .gpio_ext_mic_en = -1,
346         .gpio_hp_mute = -1,
347         .gpio_codec1 = -1,
348         .gpio_codec2 = -1,
349         .gpio_codec3 = -1,
350         .i2s_param[HIFI_CODEC]       = {
351                 .audio_port_id = 1,
352                 .is_i2s_master = 0,
353                 .i2s_mode = TEGRA_DAIFMT_I2S,
354         },
355         .i2s_param[BT_SCO] = {
356                 .audio_port_id = 3,
357                 .is_i2s_master = 1,
358                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
359         },
360 };
361
362 static void ardbeg_audio_init(void)
363 {
364         struct board_info board_info;
365         tegra_get_board_info(&board_info);
366         if (board_info.board_id == BOARD_PM359 ||
367                         board_info.board_id == BOARD_PM358 ||
368                         board_info.board_id == BOARD_PM363) {
369                 /*Laguna*/
370                 ardbeg_audio_pdata_rt5645.gpio_hp_det =
371                         TEGRA_GPIO_HP_DET;
372                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high = 1;
373                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en = -1;
374         } else {
375                 /*Ardbeg*/
376                 ardbeg_audio_pdata_rt5645.gpio_hp_det =
377                         TEGRA_GPIO_HP_DET;
378                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high = 0;
379                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en =
380                         TEGRA_GPIO_LDO_EN;
381         }
382
383         ardbeg_audio_pdata_rt5639.gpio_hp_det =
384                 ardbeg_audio_pdata_rt5645.gpio_hp_det;
385
386         ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high =
387                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high;
388
389         ardbeg_audio_pdata_rt5639.gpio_ldo1_en =
390                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en;
391
392         ardbeg_audio_pdata_rt5639.codec_name = "rt5639.0-001c";
393         ardbeg_audio_pdata_rt5639.codec_dai_name = "rt5639-aif1";
394         ardbeg_audio_pdata_rt5645.codec_name = "rt5645.0-001a";
395         ardbeg_audio_pdata_rt5645.codec_dai_name = "rt5645-aif1";
396 }
397
398 static struct platform_device ardbeg_audio_device_rt5645 = {
399         .name = "tegra-snd-rt5645",
400         .id = 0,
401         .dev = {
402                 .platform_data = &ardbeg_audio_pdata_rt5645,
403         },
404 };
405
406 static struct platform_device ardbeg_audio_device_rt5639 = {
407         .name = "tegra-snd-rt5639",
408         .id = 0,
409         .dev = {
410                 .platform_data = &ardbeg_audio_pdata_rt5639,
411         },
412 };
413
414 #endif
415
416 static void __init ardbeg_uart_init(void)
417 {
418         int debug_port_id;
419
420 #ifndef CONFIG_USE_OF
421         tegra_uarta_device.dev.platform_data = &ardbeg_uarta_pdata;
422         tegra_uartb_device.dev.platform_data = &ardbeg_uartb_pdata;
423         tegra_uartc_device.dev.platform_data = &ardbeg_uartc_pdata;
424         platform_add_devices(ardbeg_uart_devices,
425                         ARRAY_SIZE(ardbeg_uart_devices));
426 #endif
427         tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
428         if (!is_tegra_debug_uartport_hs()) {
429                 debug_port_id = uart_console_debug_init(3);
430                 if (debug_port_id < 0)
431                         return;
432
433                 platform_device_register(uart_console_debug_device);
434         } else {
435                 tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
436                 platform_device_register(&tegra_uartd_device);
437         }
438
439 }
440
441 static struct resource tegra_rtc_resources[] = {
442         [0] = {
443                 .start = TEGRA_RTC_BASE,
444                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
445                 .flags = IORESOURCE_MEM,
446         },
447         [1] = {
448                 .start = INT_RTC,
449                 .end = INT_RTC,
450                 .flags = IORESOURCE_IRQ,
451         },
452 };
453
454 static struct platform_device tegra_rtc_device = {
455         .name = "tegra_rtc",
456         .id   = -1,
457         .resource = tegra_rtc_resources,
458         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
459 };
460
461 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
462 static struct tegra_pci_platform_data laguna_pcie_platform_data = {
463         .port_status[0] = 1,
464         .port_status[1] = 1,
465         .use_dock_detect        = 1,
466         .gpio   = TEGRA_GPIO_PO1,
467         .gpio_x1_slot   = PMU_TCA6416_GPIO(8),
468 };
469
470 static void laguna_pcie_init(void)
471 {
472         struct board_info board_info;
473
474         tegra_get_board_info(&board_info);
475         /* root port 1(x1 slot) is supported only on of ERS-S board */
476         if (board_info.board_id == BOARD_PM358 ||
477                 board_info.board_id == BOARD_PM363)
478                         laguna_pcie_platform_data.port_status[1] = 0;
479
480         tegra_pci_device.dev.platform_data = &laguna_pcie_platform_data;
481         platform_device_register(&tegra_pci_device);
482 }
483 #endif
484
485 static struct platform_device *ardbeg_devices[] __initdata = {
486         &tegra_pmu_device,
487         &tegra_rtc_device,
488         &tegra_udc_device,
489 #if defined(CONFIG_TEGRA_AVP)
490         &tegra_avp_device,
491 #endif
492 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
493 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
494         &tegra12_se_device,
495 #endif
496 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
497         &tegra11_se_device,
498 #endif
499 #endif
500 /*use board file for T12x*/
501 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || !defined(CONFIG_USE_OF)
502         &tegra_ahub_device,
503         &tegra_dam_device0,
504         &tegra_dam_device1,
505         &tegra_dam_device2,
506         &tegra_i2s_device1,
507         &tegra_i2s_device3,
508         &tegra_i2s_device4,
509         &ardbeg_audio_device_rt5639,
510         &tegra_spdif_device,
511 #endif
512         &spdif_dit_device,
513         &bluetooth_dit_device,
514         &tegra_hda_device,
515 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
516         &tegra_aes_device,
517 #endif
518 };
519
520 static struct tegra_usb_platform_data tegra_udc_pdata = {
521         .port_otg = true,
522         .has_hostpc = true,
523         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
524         .op_mode = TEGRA_USB_OPMODE_DEVICE,
525         .u_data.dev = {
526                 .vbus_pmu_irq = 0,
527                 .vbus_gpio = -1,
528                 .charging_supported = false,
529                 .remote_wakeup_supported = false,
530         },
531         .u_cfg.utmi = {
532                 .hssync_start_delay = 0,
533                 .elastic_limit = 16,
534                 .idle_wait_delay = 17,
535                 .term_range_adj = 6,
536                 .xcvr_setup = 8,
537                 .xcvr_lsfslew = 2,
538                 .xcvr_lsrslew = 2,
539                 .xcvr_setup_offset = 0,
540                 .xcvr_use_fuses = 1,
541         },
542 };
543
544 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
545         .port_otg = true,
546         .has_hostpc = true,
547         .unaligned_dma_buf_supported = true,
548         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
549         .op_mode = TEGRA_USB_OPMODE_HOST,
550         .u_data.host = {
551                 .vbus_gpio = -1,
552                 .hot_plug = false,
553                 .remote_wakeup_supported = true,
554                 .power_off_on_suspend = true,
555         },
556         .u_cfg.utmi = {
557                 .hssync_start_delay = 0,
558                 .elastic_limit = 16,
559                 .idle_wait_delay = 17,
560                 .term_range_adj = 6,
561                 .xcvr_setup = 15,
562                 .xcvr_lsfslew = 0,
563                 .xcvr_lsrslew = 3,
564                 .xcvr_setup_offset = 0,
565                 .xcvr_use_fuses = 0,
566                 .vbus_oc_map = 0x4,
567                 .xcvr_hsslew_lsb = 2,
568         },
569 };
570
571 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
572 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
573         .port_otg = false,
574         .has_hostpc = true,
575         .unaligned_dma_buf_supported = true,
576         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
577         .op_mode = TEGRA_USB_OPMODE_HOST,
578         .u_data.host = {
579                 .vbus_gpio = -1,
580                 .hot_plug = false,
581                 .remote_wakeup_supported = true,
582                 .power_off_on_suspend = true,
583         },
584         .u_cfg.utmi = {
585                 .hssync_start_delay = 0,
586                 .elastic_limit = 16,
587                 .idle_wait_delay = 17,
588                 .term_range_adj = 6,
589                 .xcvr_setup = 8,
590                 .xcvr_lsfslew = 2,
591                 .xcvr_lsrslew = 2,
592                 .xcvr_setup_offset = 0,
593                 .xcvr_use_fuses = 1,
594                 .vbus_oc_map = 0x5,
595         },
596 };
597 #endif
598
599 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
600         .port_otg = false,
601         .has_hostpc = true,
602         .unaligned_dma_buf_supported = true,
603         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
604         .op_mode = TEGRA_USB_OPMODE_HOST,
605         .u_data.host = {
606                 .vbus_gpio = -1,
607                 .hot_plug = false,
608                 .remote_wakeup_supported = true,
609                 .power_off_on_suspend = true,
610         },
611         .u_cfg.utmi = {
612         .hssync_start_delay = 0,
613                 .elastic_limit = 16,
614                 .idle_wait_delay = 17,
615                 .term_range_adj = 6,
616                 .xcvr_setup = 8,
617                 .xcvr_lsfslew = 2,
618                 .xcvr_lsrslew = 2,
619                 .xcvr_setup_offset = 0,
620                 .xcvr_use_fuses = 1,
621                 .vbus_oc_map = 0x5,
622         },
623 };
624
625 static struct gpio modem_gpios[] = { /* Bruce modem */
626         {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"},
627         {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"},
628 };
629
630 static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = {
631         .port_otg = false,
632         .has_hostpc = true,
633         .unaligned_dma_buf_supported = true,
634         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
635         .op_mode = TEGRA_USB_OPMODE_HOST,
636         .u_data.host = {
637                 .vbus_gpio = -1,
638                 .hot_plug = false,
639                 .remote_wakeup_supported = true,
640                 .power_off_on_suspend = true,
641         },
642 };
643
644 static struct tegra_usb_platform_data tegra_ehci2_hsic_smsc_hub_pdata = {
645         .port_otg = false,
646         .has_hostpc = true,
647         .unaligned_dma_buf_supported = true,
648         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
649         .op_mode        = TEGRA_USB_OPMODE_HOST,
650         .u_data.host = {
651                 .vbus_gpio = -1,
652                 .hot_plug = false,
653                 .remote_wakeup_supported = true,
654                 .power_off_on_suspend = true,
655         },
656 };
657
658
659 static struct tegra_usb_otg_data tegra_otg_pdata = {
660         .ehci_device = &tegra_ehci1_device,
661         .ehci_pdata = &tegra_ehci1_utmi_pdata,
662 };
663
664 static void ardbeg_usb_init(void)
665 {
666         int usb_port_owner_info = tegra_get_usb_port_owner_info();
667         int modem_id = tegra_get_modem_id();
668         struct board_info bi;
669
670         tegra_get_pmu_board_info(&bi);
671
672         switch (bi.board_id) {
673         case BOARD_E1733:
674                 /* Host cable is detected through USB ID */
675                 tegra_udc_pdata.id_det_type = TEGRA_USB_ID;
676                 tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_ID;
677                 break;
678         case BOARD_E1735:
679                 /* Host cable is detected through PMU Interrupt */
680                 tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
681                 tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
682                 tegra_otg_pdata.id_extcon_dev_name = "palmas-extcon";
683         }
684
685         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
686                 tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
687                 platform_device_register(&tegra_otg_device);
688                 /* Setup the udc platform data */
689                 tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
690         }
691 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
692         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
693                 if (!modem_id) {
694                         tegra_ehci2_device.dev.platform_data =
695                                 &tegra_ehci2_utmi_pdata;
696                         platform_device_register(&tegra_ehci2_device);
697                 }
698         }
699 #endif
700         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
701                 tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
702                 platform_device_register(&tegra_ehci3_device);
703         }
704 }
705
706 static struct tegra_xusb_board_data xusb_bdata = {
707 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
708         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_USB2_P1,
709         .supply = {
710                 .s5p0v = "usb_vbus0",
711                 .s5p0v1 = "usb_vbus1",
712                 .s5p0v2 = "usb_vbus2",
713                 .s3p3v = "hvdd_usb",
714                 .s1p8v = "avdd_usb_pll",
715                 .s1p2v = "vddio_hsic",
716                 .s1p05v = "avddio_usb",
717         },
718 #else
719         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_SS_P1 |
720                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_USB2_P2,
721         .supply = {
722                 .s5p0v = "usb_vbus0",
723                 .s5p0v1 = "usb_vbus1",
724                 .s5p0v2 = "usb_vbus2",
725                 .s3p3v = "hvdd_usb",
726                 .s1p8v = "avdd_pll_utmip",
727                 .s1p2v = "vddio_hsic",
728                 .s1p05v = "avddio_usb",
729         },
730 #endif
731         .uses_external_pmic = false,
732         .uses_different_vbus_per_port = true,
733 };
734
735 static void ardbeg_xusb_init(void)
736 {
737         int usb_port_owner_info = tegra_get_usb_port_owner_info();
738
739         xusb_bdata.lane_owner = (u8) tegra_get_lane_owner_info();
740
741         if (board_info.board_id == BOARD_PM359 ||
742                         board_info.board_id == BOARD_PM358 ||
743                         board_info.board_id == BOARD_PM363) {
744                 /* Laguna */
745                 pr_info("Laguna ERS. 0x%x\n", board_info.board_id);
746                 xusb_bdata.gpio_controls_muxed_ss_lanes = true;
747                 /* D[0:15] = gpio number and D[16:31] = output value */
748                 xusb_bdata.gpio_ss1_sata = PMU_TCA6416_GPIO(9) | (0 << 16);
749                 xusb_bdata.ss_portmap = (TEGRA_XUSB_SS_PORT_MAP_USB2_P0 << 0) |
750                         (TEGRA_XUSB_SS_PORT_MAP_USB2_P1 << 4);
751
752                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
753                         xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
754                                 TEGRA_XUSB_SS_P0);
755
756                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
757                         xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
758                                 TEGRA_XUSB_SS_P1 | TEGRA_XUSB_USB2_P2);
759
760                 /* FIXME Add for UTMIP2 when have odmdata assigend */
761         } else {
762                 /* Ardbeg */
763                 xusb_bdata.gpio_controls_muxed_ss_lanes = false;
764
765                 if (board_info.board_id == BOARD_E1781) {
766                         pr_info("Shield ERS-S. 0x%x\n", board_info.board_id);
767                         /* Shield ERS-S */
768                         xusb_bdata.ss_portmap =
769                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P1 << 0) |
770                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P2 << 4);
771
772                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
773                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
774
775                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
776                                 xusb_bdata.portmap &= ~(
777                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0 |
778                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
779                 } else {
780                         pr_info("Shield ERS 0x%x\n", board_info.board_id);
781                         /* Shield ERS */
782                         xusb_bdata.ss_portmap =
783                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P0 << 0) |
784                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P2 << 4);
785
786                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
787                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
788                                         TEGRA_XUSB_SS_P0);
789
790                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
791                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
792                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
793                 }
794                 /* FIXME Add for UTMIP2 when have odmdata assigend */
795         }
796         if (xusb_bdata.portmap)
797                 tegra_xusb_init(&xusb_bdata);
798 }
799
800 static int baseband_init(void)
801 {
802         int ret;
803
804         ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios));
805         if (ret) {
806                 pr_warn("%s:gpio request failed\n", __func__);
807                 return ret;
808         }
809
810         /* enable pull-down for MDM_COLD_BOOT */
811         tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4,
812                                     TEGRA_PUPD_PULL_DOWN);
813
814         /* export GPIO for user space access through sysfs */
815         gpio_export(MDM_RST, false);
816
817         return 0;
818 }
819
820 static const struct tegra_modem_operations baseband_operations = {
821         .init = baseband_init,
822 };
823
824 static struct tegra_usb_modem_power_platform_data baseband_pdata = {
825         .ops = &baseband_operations,
826         .regulator_name = "vdd_wwan_mdm",
827         .wake_gpio = -1,
828         .boot_gpio = MDM_COLDBOOT,
829         .boot_irq_flags = IRQF_TRIGGER_RISING |
830                                     IRQF_TRIGGER_FALLING |
831                                     IRQF_ONESHOT,
832         .autosuspend_delay = 2000,
833         .short_autosuspend_delay = 50,
834         .tegra_ehci_device = &tegra_ehci2_device,
835         .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata,
836 };
837
838 static struct platform_device icera_bruce_device = {
839         .name = "tegra_usb_modem_power",
840         .id = -1,
841         .dev = {
842                 .platform_data = &baseband_pdata,
843         },
844 };
845
846 static void ardbeg_modem_init(void)
847 {
848         int modem_id = tegra_get_modem_id();
849         struct board_info board_info;
850         int usb_port_owner_info = tegra_get_usb_port_owner_info();
851
852         tegra_get_board_info(&board_info);
853         pr_info("%s: modem_id = %d\n", __func__, modem_id);
854
855         switch (modem_id) {
856         case TEGRA_BB_BRUCE:
857                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB))
858                         platform_device_register(&icera_bruce_device);
859                 break;
860         case TEGRA_BB_HSIC_HUB: /* HSIC hub */
861                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
862                         tegra_ehci2_device.dev.platform_data =
863                                 &tegra_ehci2_hsic_smsc_hub_pdata;
864                         platform_device_register(&tegra_ehci2_device);
865                 }
866                 break;
867         default:
868                 return;
869         }
870 }
871
872 #ifndef CONFIG_USE_OF
873 static struct platform_device *ardbeg_spi_devices[] __initdata = {
874         &tegra11_spi_device1,
875         &tegra11_spi_device4,
876 };
877
878 static struct tegra_spi_platform_data ardbeg_spi1_pdata = {
879         .dma_req_sel            = 15,
880         .spi_max_frequency      = 25000000,
881         .clock_always_on        = false,
882 };
883
884 static struct tegra_spi_platform_data ardbeg_spi4_pdata = {
885         .dma_req_sel            = 18,
886         .spi_max_frequency      = 25000000,
887         .clock_always_on        = false,
888 };
889
890 static void __init ardbeg_spi_init(void)
891 {
892         tegra11_spi_device1.dev.platform_data = &ardbeg_spi1_pdata;
893         tegra11_spi_device4.dev.platform_data = &ardbeg_spi4_pdata;
894         platform_add_devices(ardbeg_spi_devices,
895                         ARRAY_SIZE(ardbeg_spi_devices));
896 }
897 #else
898 static void __init ardbeg_spi_init(void)
899 {
900 }
901 #endif
902
903 #ifdef CONFIG_USE_OF
904 struct of_dev_auxdata ardbeg_auxdata_lookup[] __initdata = {
905 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
906         /* sdhci and i2c dt support not planned for bringup */
907         OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000600, "sdhci-tegra.3",
908                                 NULL),
909         OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000400, "sdhci-tegra.2",
910                                 NULL),
911 #if 0
912         OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000000, "sdhci-tegra.0",
913                                 &ardbeg_tegra_sdhci_platform_data0),
914 #endif
915         OF_DEV_AUXDATA("nvidia,tegra114-camera", 0x0, "tegra_camera",
916                                 NULL),
917         OF_DEV_AUXDATA("nvidia,tegra114-i2c", 0x7000c000, "tegra11-i2c.0",
918                                 NULL),
919         OF_DEV_AUXDATA("nvidia,tegra114-i2c", 0x7000c400, "tegra11-i2c.1",
920                                 NULL),
921         OF_DEV_AUXDATA("nvidia,tegra114-i2c", 0x7000c500, "tegra11-i2c.2",
922                                 NULL),
923         OF_DEV_AUXDATA("nvidia,tegra114-i2c", 0x7000c700, "tegra11-i2c.3",
924                                 NULL),
925         OF_DEV_AUXDATA("nvidia,tegra114-i2c", 0x7000d000, "tegra11-i2c.4",
926                                 NULL),
927 #endif
928         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d400, "spi-tegra114.0",
929                                 NULL),
930         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d600, "spi-tegra114.1",
931                                 NULL),
932         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d800, "spi-tegra114.2",
933                                 NULL),
934         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000da00, "spi-tegra114.3",
935                                 NULL),
936         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000dc00, "spi-tegra114.4",
937                                 NULL),
938         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000de00, "spi-tegra114.5",
939                                 NULL),
940 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
941         OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub",
942                                 NULL),
943         OF_DEV_AUXDATA("nvidia,tegra-audio-rt5645", 0x0, "tegra-snd-rt5645",
944                                 NULL),
945         OF_DEV_AUXDATA("nvidia,tegra-audio-rt5639", 0x0, "tegra-snd-rt5639",
946                                 NULL),
947         OF_DEV_AUXDATA("nvidia,tegra114-apbdma", 0x6000a000, "tegra-apbdma",
948                                 NULL),
949         OF_DEV_AUXDATA("nvidia,tegra114-host1x", TEGRA_HOST1X_BASE, "host1x",
950                                 NULL),
951         OF_DEV_AUXDATA("nvidia,tegra114-gr3d", TEGRA_GR3D_BASE, "gr3d",
952                                 NULL),
953         OF_DEV_AUXDATA("nvidia,tegra114-gr2d", TEGRA_GR2D_BASE, "gr2d",
954                                 NULL),
955         OF_DEV_AUXDATA("nvidia,tegra114-msenc", TEGRA_MSENC_BASE, "msenc",
956                                 NULL),
957         OF_DEV_AUXDATA("nvidia,tegra114-vi", TEGRA_VI_BASE, "vi",
958                                 NULL),
959         OF_DEV_AUXDATA("nvidia,tegra114-isp", TEGRA_ISP_BASE, "isp",
960                                 NULL),
961         OF_DEV_AUXDATA("nvidia,tegra114-tsec", TEGRA_TSEC_BASE, "tsec",
962                                 NULL),
963 #else
964         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
965                                 NULL),
966         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
967                 NULL),
968         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", 0x538F0000, "gk20a", NULL),
969         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03", NULL),
970         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
971                 NULL),
972         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi", NULL),
973         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp", NULL),
974         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
975 #endif
976         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0",
977                                 NULL),
978         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1",
979                                 NULL),
980         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2",
981                                 NULL),
982         {}
983 };
984 #endif
985
986 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
987         /* name         parent          rate            enabled */
988         { "extern2",    "pll_p",        41000000,       false},
989         { "clk_out_2",  "extern2",      40800000,       false},
990         { NULL,         NULL,           0,              0},
991 };
992
993 struct rm_spi_ts_platform_data rm31080ts_ardbeg_data = {
994         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
995         .config = 0,
996         .platform_id = RM_PLATFORM_D010,
997         .name_of_clock = "clk_out_2",
998         .name_of_clock_con = "extern2",
999 };
1000
1001 static struct tegra_spi_device_controller_data dev_cdata = {
1002         .rx_clk_tap_delay = 0,
1003         .tx_clk_tap_delay = 16,
1004 };
1005
1006 struct spi_board_info rm31080a_ardbeg_spi_board[1] = {
1007         {
1008                 .modalias = "rm_ts_spidev",
1009                 .bus_num = TOUCH_SPI_ID,
1010                 .chip_select = TOUCH_SPI_CS,
1011                 .max_speed_hz = 12 * 1000 * 1000,
1012                 .mode = SPI_MODE_0,
1013                 .controller_data = &dev_cdata,
1014                 .platform_data = &rm31080ts_ardbeg_data,
1015         },
1016 };
1017
1018 static int __init ardbeg_touch_init(void)
1019 {
1020         tegra_clk_init_from_table(touch_clk_init_table);
1021         rm31080a_ardbeg_spi_board[0].irq =
1022                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1023         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1024                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
1025                                 &rm31080ts_ardbeg_data,
1026                                 &rm31080a_ardbeg_spi_board[0],
1027                                 ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1028         return 0;
1029 }
1030
1031 static void __init tegra_ardbeg_early_init(void)
1032 {
1033         tegra_clk_init_from_table(ardbeg_clk_init_table);
1034         tegra_clk_verify_parents();
1035         if (of_machine_is_compatible("nvidia,laguna"))
1036                 tegra_soc_device_init("laguna");
1037         else if (of_machine_is_compatible("nvidia,tn8"))
1038                 tegra_soc_device_init("tn8");
1039         else
1040                 tegra_soc_device_init("ardbeg");
1041 }
1042
1043 static void __init tegra_ardbeg_late_init(void)
1044 {
1045         struct board_info board_info;
1046         tegra_get_board_info(&board_info);
1047         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1048                 board_info.board_id, board_info.sku,
1049                 board_info.fab, board_info.major_revision,
1050                 board_info.minor_revision);
1051         platform_device_register(&tegra_pinmux_device);
1052         if (board_info.board_id == BOARD_PM359 ||
1053                         board_info.board_id == BOARD_PM358 ||
1054                         board_info.board_id == BOARD_PM363)
1055                 laguna_pinmux_init();
1056         else
1057                 ardbeg_pinmux_init();
1058         ardbeg_usb_init();
1059         ardbeg_modem_init();
1060         ardbeg_xusb_init();
1061         ardbeg_i2c_init();
1062         ardbeg_spi_init();
1063         ardbeg_uart_init();
1064 /*use board file for T12x*/
1065 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || !defined(CONFIG_USE_OF)
1066         ardbeg_audio_init();
1067 #endif
1068         platform_add_devices(ardbeg_devices, ARRAY_SIZE(ardbeg_devices));
1069         //tegra_ram_console_debug_init();
1070         tegra_io_dpd_init();
1071         ardbeg_sdhci_init();
1072         if (board_info.board_id == BOARD_PM359 ||
1073                         board_info.board_id == BOARD_PM358 ||
1074                         board_info.board_id == BOARD_PM363)
1075                 laguna_regulator_init();
1076         else
1077                 ardbeg_regulator_init();
1078         ardbeg_suspend_init();
1079 #if 0
1080         ardbeg_emc_init();
1081         ardbeg_edp_init();
1082 #endif
1083         isomgr_init();
1084         ardbeg_touch_init();
1085         ardbeg_panel_init();
1086         ardbeg_kbc_init();
1087         if (board_info.board_id == BOARD_PM358)
1088                 laguna_pm358_pmon_init();
1089         else
1090                 ardbeg_pmon_init();
1091         tegra_release_bootloader_fb();
1092 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
1093         if (board_info.board_id == BOARD_PM359 ||
1094                         board_info.board_id == BOARD_PM358 ||
1095                         board_info.board_id == BOARD_PM363)
1096                 laguna_pcie_init();
1097 #endif
1098 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1099         tegra_wdt_recovery_init();
1100 #endif
1101         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1102
1103         ardbeg_sensors_init();
1104 #if 0
1105         ardbeg_soctherm_init();
1106 #endif
1107         ardbeg_setup_bluedroid_pm();
1108         tegra_register_fuse();
1109         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1110 }
1111
1112 static void __init ardbeg_ramconsole_reserve(unsigned long size)
1113 {
1114         tegra_ram_console_debug_reserve(SZ_1M);
1115 }
1116
1117 static void __init tegra_ardbeg_dt_init(void)
1118 {
1119         tegra_get_board_info(&board_info);
1120         tegra_get_display_board_info(&display_board_info);
1121
1122         tegra_ardbeg_early_init();
1123 #ifdef CONFIG_USE_OF
1124         of_platform_populate(NULL,
1125                 of_default_bus_match_table, ardbeg_auxdata_lookup,
1126                 &platform_bus);
1127         platform_device_register(&tegra_gpio_device);
1128 #endif
1129
1130         tegra_ardbeg_late_init();
1131 }
1132
1133 static void __init tegra_ardbeg_reserve(void)
1134 {
1135 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) || \
1136                 defined(CONFIG_TEGRA_NO_CARVEOUT)
1137         /* 1920*1200*4*2 = 18432000 bytes */
1138         tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
1139 #else
1140         tegra_reserve(SZ_1G, SZ_16M + SZ_2M, SZ_4M);
1141 #endif
1142         ardbeg_ramconsole_reserve(SZ_1M);
1143 }
1144
1145 static const char * const ardbeg_dt_board_compat[] = {
1146         "nvidia,ardbeg",
1147         NULL
1148 };
1149
1150 static const char * const laguna_dt_board_compat[] = {
1151         "nvidia,laguna",
1152         NULL
1153 };
1154
1155 static const char * const tn8_dt_board_compat[] = {
1156         "nvidia,tn8",
1157         NULL
1158 };
1159
1160 DT_MACHINE_START(LAGUNA, "laguna")
1161         .atag_offset    = 0x100,
1162         .smp            = smp_ops(tegra_smp_ops),
1163         .map_io         = tegra_map_common_io,
1164         .reserve        = tegra_ardbeg_reserve,
1165         .init_early     = tegra12x_init_early,
1166         .init_irq       = tegra_dt_init_irq,
1167         .init_time      = tegra_init_timer,
1168         .init_machine   = tegra_ardbeg_dt_init,
1169         .restart        = tegra_assert_system_reset,
1170         .dt_compat      = laguna_dt_board_compat,
1171 MACHINE_END
1172
1173 DT_MACHINE_START(TN8, "tn8")
1174         .atag_offset    = 0x100,
1175         .smp            = smp_ops(tegra_smp_ops),
1176         .map_io         = tegra_map_common_io,
1177         .reserve        = tegra_ardbeg_reserve,
1178         .init_early     = tegra12x_init_early,
1179         .init_irq       = tegra_dt_init_irq,
1180         .init_time      = tegra_init_timer,
1181         .init_machine   = tegra_ardbeg_dt_init,
1182         .restart        = tegra_assert_system_reset,
1183         .dt_compat      = tn8_dt_board_compat,
1184 MACHINE_END
1185
1186 DT_MACHINE_START(ARDBEG, "ardbeg")
1187         .atag_offset    = 0x100,
1188         .smp            = smp_ops(tegra_smp_ops),
1189         .map_io         = tegra_map_common_io,
1190         .reserve        = tegra_ardbeg_reserve,
1191 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
1192         .init_early     = tegra12x_init_early,
1193 #else
1194         .init_early     = tegra11x_init_early,
1195 #endif
1196         .init_irq       = tegra_dt_init_irq,
1197         .init_time      = tegra_init_timer,
1198         .init_machine   = tegra_ardbeg_dt_init,
1199         .restart        = tegra_assert_system_reset,
1200         .dt_compat      = ardbeg_dt_board_compat,
1201 MACHINE_END