a0b89c6ec65d1b2adeb1946c01fc4a40c332bb40
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c.h>
28 #include <linux/i2c/i2c-hid.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/delay.h>
31 #include <linux/i2c-tegra.h>
32 #include <linux/gpio.h>
33 #include <linux/input.h>
34 #include <linux/platform_data/tegra_usb.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/rm31080a_ts.h>
37 #include <linux/memblock.h>
38 #include <linux/spi/spi-tegra.h>
39 #include <linux/nfc/pn544.h>
40 #include <linux/rfkill-gpio.h>
41 #include <linux/skbuff.h>
42 #include <linux/ti_wilink_st.h>
43 #include <linux/regulator/consumer.h>
44 #include <linux/smb349-charger.h>
45 #include <linux/max17048_battery.h>
46 #include <linux/leds.h>
47 #include <linux/i2c/at24.h>
48 #include <linux/of_platform.h>
49 #include <linux/i2c.h>
50 #include <linux/i2c-tegra.h>
51 #include <linux/platform_data/serial-tegra.h>
52 #include <linux/edp.h>
53 #include <linux/usb/tegra_usb_phy.h>
54 #include <linux/mfd/palmas.h>
55 #include <linux/clk/tegra.h>
56 #include <media/tegra_dtv.h>
57
58 #include <mach/irqs.h>
59 #include <mach/pci.h>
60 #include <mach/tegra_fiq_debugger.h>
61
62 #include <mach/pinmux.h>
63 #include <mach/pinmux-t12.h>
64 #include <mach/io_dpd.h>
65 #include <mach/i2s.h>
66 #include <mach/isomgr.h>
67 #include <mach/tegra_asoc_pdata.h>
68 #include <asm/mach-types.h>
69 #include <asm/mach/arch.h>
70 #include <mach/gpio-tegra.h>
71 #include <mach/tegra_fiq_debugger.h>
72 #include <mach/xusb.h>
73 #include <linux/platform_data/tegra_usb_modem_power.h>
74 #include <linux/platform_data/tegra_ahci.h>
75
76 #include "board.h"
77 #include "board-ardbeg.h"
78 #include "board-common.h"
79 #include "board-touch-raydium.h"
80 #include "clock.h"
81 #include "common.h"
82 #include "devices.h"
83 #include "fuse.h"
84 #include "gpio-names.h"
85 #include "iomap.h"
86 #include "pm.h"
87 #include "pm-irq.h"
88 #include "tegra-board-id.h"
89
90 static struct board_info board_info, display_board_info;
91
92 static struct resource ardbeg_bluedroid_pm_resources[] = {
93         [0] = {
94                 .name   = "shutdown_gpio",
95                 .start  = TEGRA_GPIO_PR1,
96                 .end    = TEGRA_GPIO_PR1,
97                 .flags  = IORESOURCE_IO,
98         },
99         [1] = {
100                 .name = "host_wake",
101                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
102         },
103         [2] = {
104                 .name = "gpio_ext_wake",
105                 .start  = TEGRA_GPIO_PEE1,
106                 .end    = TEGRA_GPIO_PEE1,
107                 .flags  = IORESOURCE_IO,
108         },
109         [3] = {
110                 .name = "gpio_host_wake",
111                 .start  = TEGRA_GPIO_PU6,
112                 .end    = TEGRA_GPIO_PU6,
113                 .flags  = IORESOURCE_IO,
114         },
115         [4] = {
116                 .name = "reset_gpio",
117                 .start  = TEGRA_GPIO_PX1,
118                 .end    = TEGRA_GPIO_PX1,
119                 .flags  = IORESOURCE_IO,
120         },
121 };
122
123 static struct platform_device ardbeg_bluedroid_pm_device = {
124         .name = "bluedroid_pm",
125         .id             = 0,
126         .num_resources  = ARRAY_SIZE(ardbeg_bluedroid_pm_resources),
127         .resource       = ardbeg_bluedroid_pm_resources,
128 };
129
130 static noinline void __init ardbeg_setup_bluedroid_pm(void)
131 {
132         ardbeg_bluedroid_pm_resources[1].start =
133                 ardbeg_bluedroid_pm_resources[1].end =
134                                 gpio_to_irq(TEGRA_GPIO_PU6);
135         platform_device_register(&ardbeg_bluedroid_pm_device);
136 }
137
138 static struct i2c_board_info __initdata rt5639_board_info = {
139         I2C_BOARD_INFO("rt5639", 0x1c),
140 };
141 static struct i2c_board_info __initdata rt5645_board_info = {
142         I2C_BOARD_INFO("rt5645", 0x1a),
143 };
144
145 static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
146         /* name         parent          rate            enabled */
147         { "pll_m",      NULL,           0,              false},
148         { "hda",        "pll_p",        108000000,      false},
149         { "hda2codec_2x", "pll_p",      48000000,       false},
150         { "pwm",        "pll_p",        3187500,        false},
151         { "i2s1",       "pll_a_out0",   0,              false},
152         { "i2s3",       "pll_a_out0",   0,              false},
153         { "i2s4",       "pll_a_out0",   0,              false},
154         { "spdif_out",  "pll_a_out0",   0,              false},
155         { "d_audio",    "clk_m",        12000000,       false},
156         { "dam0",       "clk_m",        12000000,       false},
157         { "dam1",       "clk_m",        12000000,       false},
158         { "dam2",       "clk_m",        12000000,       false},
159         { "audio1",     "i2s1_sync",    0,              false},
160         { "audio3",     "i2s3_sync",    0,              false},
161         { "vi_sensor",  "pll_p",        150000000,      false},
162         { "vi_sensor2", "pll_p",        150000000,      false},
163         { "cilab",      "pll_p",        150000000,      false},
164         { "cilcd",      "pll_p",        150000000,      false},
165         { "cile",       "pll_p",        150000000,      false},
166         { "i2c1",       "pll_p",        3200000,        false},
167         { "i2c2",       "pll_p",        3200000,        false},
168         { "i2c3",       "pll_p",        3200000,        false},
169         { "i2c4",       "pll_p",        3200000,        false},
170         { "i2c5",       "pll_p",        3200000,        false},
171         { "sbc1",       "pll_p",        25000000,       false},
172         { "sbc2",       "pll_p",        25000000,       false},
173         { "sbc3",       "pll_p",        25000000,       false},
174         { "sbc4",       "pll_p",        25000000,       false},
175         { "sbc5",       "pll_p",        25000000,       false},
176         { "sbc6",       "pll_p",        25000000,       false},
177         { "uarta",      "pll_p",        408000000,      false},
178         { "uartb",      "pll_p",        408000000,      false},
179         { "uartc",      "pll_p",        408000000,      false},
180         { "uartd",      "pll_p",        408000000,      false},
181         { NULL,         NULL,           0,              0},
182 };
183
184 static struct i2c_hid_platform_data i2c_keyboard_pdata = {
185         .hid_descriptor_address = 0x0,
186 };
187
188 static struct i2c_board_info __initdata i2c_keyboard_board_info = {
189         I2C_BOARD_INFO("hid", 0x3B),
190         .platform_data  = &i2c_keyboard_pdata,
191 };
192
193 static struct i2c_hid_platform_data i2c_touchpad_pdata = {
194         .hid_descriptor_address = 0x20,
195 };
196
197 static struct i2c_board_info __initdata i2c_touchpad_board_info = {
198         I2C_BOARD_INFO("hid", 0x2C),
199         .platform_data  = &i2c_touchpad_pdata,
200 };
201
202 static void ardbeg_i2c_init(void)
203 {
204         struct board_info board_info;
205         tegra_get_board_info(&board_info);
206
207         i2c_register_board_info(0, &rt5639_board_info, 1);
208         i2c_register_board_info(0, &rt5645_board_info, 1);
209
210         if (board_info.board_id == BOARD_PM359 ||
211                         board_info.board_id == BOARD_PM358 ||
212                         board_info.board_id == BOARD_PM363) {
213                 i2c_keyboard_board_info.irq = gpio_to_irq(I2C_KB_IRQ);
214                 i2c_register_board_info(1, &i2c_keyboard_board_info , 1);
215
216                 i2c_touchpad_board_info.irq = gpio_to_irq(I2C_TP_IRQ);
217                 i2c_register_board_info(1, &i2c_touchpad_board_info , 1);
218         }
219 }
220
221 #ifndef CONFIG_USE_OF
222 static struct platform_device *ardbeg_uart_devices[] __initdata = {
223         &tegra_uarta_device,
224         &tegra_uartb_device,
225         &tegra_uartc_device,
226 };
227
228 static struct tegra_serial_platform_data ardbeg_uarta_pdata = {
229         .dma_req_selector = 8,
230         .modem_interrupt = false,
231 };
232
233 static struct tegra_serial_platform_data ardbeg_uartb_pdata = {
234         .dma_req_selector = 9,
235         .modem_interrupt = false,
236 };
237
238 static struct tegra_serial_platform_data ardbeg_uartc_pdata = {
239         .dma_req_selector = 10,
240         .modem_interrupt = false,
241 };
242 #endif
243
244 static struct tegra_serial_platform_data ardbeg_uartd_pdata = {
245         .dma_req_selector = 19,
246         .modem_interrupt = false,
247 };
248
249 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
250         .gpio_hp_det = TEGRA_GPIO_HP_DET,
251         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
252         .gpio_spkr_en = -1,
253         .gpio_int_mic_en = -1,
254         .gpio_ext_mic_en = -1,
255         .gpio_hp_mute = -1,
256         .gpio_codec1 = -1,
257         .gpio_codec2 = -1,
258         .gpio_codec3 = -1,
259         .edp_support = true,
260         .edp_states = {1530, 765, 0},
261         .i2s_param[HIFI_CODEC]       = {
262                 .audio_port_id = 1,
263                 .is_i2s_master = 0,
264                 .i2s_mode = TEGRA_DAIFMT_I2S,
265         },
266         .i2s_param[BT_SCO] = {
267                 .audio_port_id = 3,
268                 .is_i2s_master = 1,
269                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
270         },
271 };
272
273 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5645 = {
274         .gpio_hp_det = TEGRA_GPIO_HP_DET,
275         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
276         .gpio_spkr_en = -1,
277         .gpio_int_mic_en = -1,
278         .gpio_ext_mic_en = -1,
279         .gpio_hp_mute = -1,
280         .gpio_codec1 = -1,
281         .gpio_codec2 = -1,
282         .gpio_codec3 = -1,
283         .i2s_param[HIFI_CODEC]       = {
284                 .audio_port_id = 1,
285                 .is_i2s_master = 0,
286                 .i2s_mode = TEGRA_DAIFMT_I2S,
287         },
288         .i2s_param[BT_SCO] = {
289                 .audio_port_id = 3,
290                 .is_i2s_master = 1,
291                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
292         },
293 };
294
295 static void ardbeg_audio_init(void)
296 {
297         struct board_info board_info;
298         tegra_get_board_info(&board_info);
299         if (board_info.board_id == BOARD_PM359 ||
300                         board_info.board_id == BOARD_PM358 ||
301                         board_info.board_id == BOARD_PM363) {
302                 /*Laguna*/
303                 ardbeg_audio_pdata_rt5645.gpio_hp_det =
304                         TEGRA_GPIO_HP_DET;
305                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high = 1;
306                 if (board_info.board_id != BOARD_PM363)
307                         ardbeg_audio_pdata_rt5645.gpio_ldo1_en = -1;
308         } else {
309                 /*Ardbeg*/
310                 ardbeg_audio_pdata_rt5645.gpio_hp_det =
311                         TEGRA_GPIO_HP_DET;
312                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high = 0;
313                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en =
314                         TEGRA_GPIO_LDO_EN;
315         }
316
317         ardbeg_audio_pdata_rt5639.gpio_hp_det =
318                 ardbeg_audio_pdata_rt5645.gpio_hp_det;
319
320         ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high =
321                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high;
322
323         ardbeg_audio_pdata_rt5639.gpio_ldo1_en =
324                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en;
325
326         ardbeg_audio_pdata_rt5639.codec_name = "rt5639.0-001c";
327         ardbeg_audio_pdata_rt5639.codec_dai_name = "rt5639-aif1";
328         ardbeg_audio_pdata_rt5645.codec_name = "rt5645.0-001a";
329         ardbeg_audio_pdata_rt5645.codec_dai_name = "rt5645-aif1";
330 }
331
332 static struct platform_device ardbeg_audio_device_rt5645 = {
333         .name = "tegra-snd-rt5645",
334         .id = 0,
335         .dev = {
336                 .platform_data = &ardbeg_audio_pdata_rt5645,
337         },
338 };
339
340 static struct platform_device ardbeg_audio_device_rt5639 = {
341         .name = "tegra-snd-rt5639",
342         .id = 0,
343         .dev = {
344                 .platform_data = &ardbeg_audio_pdata_rt5639,
345         },
346 };
347
348 static void __init ardbeg_uart_init(void)
349 {
350         int debug_port_id;
351
352 #ifndef CONFIG_USE_OF
353         tegra_uarta_device.dev.platform_data = &ardbeg_uarta_pdata;
354         tegra_uartb_device.dev.platform_data = &ardbeg_uartb_pdata;
355         tegra_uartc_device.dev.platform_data = &ardbeg_uartc_pdata;
356         platform_add_devices(ardbeg_uart_devices,
357                         ARRAY_SIZE(ardbeg_uart_devices));
358 #endif
359         tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
360         if (!is_tegra_debug_uartport_hs()) {
361                 debug_port_id = uart_console_debug_init(3);
362                 if (debug_port_id < 0)
363                         return;
364
365                 platform_device_register(uart_console_debug_device);
366         } else {
367                 tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
368                 platform_device_register(&tegra_uartd_device);
369         }
370
371 }
372
373 static struct resource tegra_rtc_resources[] = {
374         [0] = {
375                 .start = TEGRA_RTC_BASE,
376                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
377                 .flags = IORESOURCE_MEM,
378         },
379         [1] = {
380                 .start = INT_RTC,
381                 .end = INT_RTC,
382                 .flags = IORESOURCE_IRQ,
383         },
384 };
385
386 static struct platform_device tegra_rtc_device = {
387         .name = "tegra_rtc",
388         .id   = -1,
389         .resource = tegra_rtc_resources,
390         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
391 };
392
393 #ifdef CONFIG_SATA_AHCI_TEGRA
394 static void bonaire_sata_init(void)
395 {
396         struct tegra_ahci_platform_data *pdata;
397
398         pdata = tegra_sata_device.dev.platform_data;
399         pdata->pexp_gpio = PMU_TCA6416_GPIO(9);
400
401         platform_device_register(&tegra_sata_device);
402 }
403 #else
404 static void bonaire_sata_init(void) { }
405 #endif
406
407 static struct tegra_pci_platform_data laguna_pcie_platform_data = {
408         .port_status[0] = 1,
409         .port_status[1] = 1,
410         .use_dock_detect        = 1,
411         .gpio   = TEGRA_GPIO_PO1,
412         .gpio_x1_slot   = PMU_TCA6416_GPIO(8),
413 };
414
415 static void laguna_pcie_init(void)
416 {
417         struct board_info board_info;
418
419         tegra_get_board_info(&board_info);
420         /* root port 1(x1 slot) is supported only on of ERS-S board */
421         if (board_info.board_id == BOARD_PM358 ||
422                 board_info.board_id == BOARD_PM363)
423                         laguna_pcie_platform_data.port_status[1] = 0;
424
425         tegra_pci_device.dev.platform_data = &laguna_pcie_platform_data;
426         platform_device_register(&tegra_pci_device);
427 }
428
429 static struct platform_device *ardbeg_devices[] __initdata = {
430         &tegra_pmu_device,
431         &tegra_rtc_device,
432         &tegra_udc_device,
433 #if defined(CONFIG_TEGRA_AVP)
434         &tegra_avp_device,
435 #endif
436 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
437         &tegra12_se_device,
438 #endif
439         &tegra_ahub_device,
440         &tegra_dam_device0,
441         &tegra_dam_device1,
442         &tegra_dam_device2,
443         &tegra_i2s_device1,
444         &tegra_i2s_device3,
445         &tegra_i2s_device4,
446         &ardbeg_audio_device_rt5639,
447         &tegra_spdif_device,
448         &spdif_dit_device,
449         &bluetooth_dit_device,
450         &tegra_hda_device,
451 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
452         &tegra_aes_device,
453 #endif
454 };
455
456 static struct tegra_usb_platform_data tegra_udc_pdata = {
457         .port_otg = true,
458         .has_hostpc = true,
459         .unaligned_dma_buf_supported = false,
460         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
461         .op_mode = TEGRA_USB_OPMODE_DEVICE,
462         .u_data.dev = {
463                 .vbus_pmu_irq = 0,
464                 .vbus_gpio = -1,
465                 .charging_supported = false,
466                 .remote_wakeup_supported = false,
467         },
468         .u_cfg.utmi = {
469                 .hssync_start_delay = 0,
470                 .elastic_limit = 16,
471                 .idle_wait_delay = 17,
472                 .term_range_adj = 6,
473                 .xcvr_setup = 8,
474                 .xcvr_lsfslew = 2,
475                 .xcvr_lsrslew = 2,
476                 .xcvr_setup_offset = 0,
477                 .xcvr_use_fuses = 1,
478         },
479 };
480
481 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
482         .port_otg = true,
483         .has_hostpc = true,
484         .unaligned_dma_buf_supported = false,
485         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
486         .op_mode = TEGRA_USB_OPMODE_HOST,
487         .u_data.host = {
488                 .vbus_gpio = -1,
489                 .hot_plug = false,
490                 .remote_wakeup_supported = true,
491                 .power_off_on_suspend = true,
492         },
493         .u_cfg.utmi = {
494                 .hssync_start_delay = 0,
495                 .elastic_limit = 16,
496                 .idle_wait_delay = 17,
497                 .term_range_adj = 6,
498                 .xcvr_setup = 15,
499                 .xcvr_lsfslew = 0,
500                 .xcvr_lsrslew = 3,
501                 .xcvr_setup_offset = 0,
502                 .xcvr_use_fuses = 1,
503                 .vbus_oc_map = 0x4,
504                 .xcvr_hsslew_lsb = 2,
505         },
506 };
507
508 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
509         .port_otg = false,
510         .has_hostpc = true,
511         .unaligned_dma_buf_supported = false,
512         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
513         .op_mode = TEGRA_USB_OPMODE_HOST,
514         .u_data.host = {
515                 .vbus_gpio = -1,
516                 .hot_plug = false,
517                 .remote_wakeup_supported = true,
518                 .power_off_on_suspend = true,
519         },
520         .u_cfg.utmi = {
521                 .hssync_start_delay = 0,
522                 .elastic_limit = 16,
523                 .idle_wait_delay = 17,
524                 .term_range_adj = 6,
525                 .xcvr_setup = 8,
526                 .xcvr_lsfslew = 2,
527                 .xcvr_lsrslew = 2,
528                 .xcvr_setup_offset = 0,
529                 .xcvr_use_fuses = 1,
530                 .vbus_oc_map = 0x5,
531         },
532 };
533
534 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
535         .port_otg = false,
536         .has_hostpc = true,
537         .unaligned_dma_buf_supported = false,
538         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
539         .op_mode = TEGRA_USB_OPMODE_HOST,
540         .u_data.host = {
541                 .vbus_gpio = -1,
542                 .hot_plug = false,
543                 .remote_wakeup_supported = true,
544                 .power_off_on_suspend = true,
545         },
546         .u_cfg.utmi = {
547         .hssync_start_delay = 0,
548                 .elastic_limit = 16,
549                 .idle_wait_delay = 17,
550                 .term_range_adj = 6,
551                 .xcvr_setup = 8,
552                 .xcvr_lsfslew = 2,
553                 .xcvr_lsrslew = 2,
554                 .xcvr_setup_offset = 0,
555                 .xcvr_use_fuses = 1,
556                 .vbus_oc_map = 0x5,
557         },
558 };
559
560 static struct gpio modem_gpios[] = { /* Bruce modem */
561         {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"},
562         {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"},
563 };
564
565 static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = {
566         .port_otg = false,
567         .has_hostpc = true,
568         .unaligned_dma_buf_supported = false,
569         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
570         .op_mode = TEGRA_USB_OPMODE_HOST,
571         .u_data.host = {
572                 .vbus_gpio = -1,
573                 .hot_plug = false,
574                 .remote_wakeup_supported = true,
575                 .power_off_on_suspend = true,
576         },
577 };
578
579 static struct tegra_usb_platform_data tegra_ehci2_hsic_smsc_hub_pdata = {
580         .port_otg = false,
581         .has_hostpc = true,
582         .unaligned_dma_buf_supported = false,
583         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
584         .op_mode        = TEGRA_USB_OPMODE_HOST,
585         .u_data.host = {
586                 .vbus_gpio = -1,
587                 .hot_plug = false,
588                 .remote_wakeup_supported = true,
589                 .power_off_on_suspend = true,
590         },
591 };
592
593
594 static struct tegra_usb_otg_data tegra_otg_pdata = {
595         .ehci_device = &tegra_ehci1_device,
596         .ehci_pdata = &tegra_ehci1_utmi_pdata,
597 };
598
599 static void ardbeg_usb_init(void)
600 {
601         int usb_port_owner_info = tegra_get_usb_port_owner_info();
602         int modem_id = tegra_get_modem_id();
603         struct board_info bi;
604
605         if (board_info.board_id == BOARD_PM359 ||
606                         board_info.board_id == BOARD_PM358 ||
607                         board_info.board_id == BOARD_PM363) {
608                 /* Laguna */
609                 /* Host cable is detected through AMS PMU Interrupt */
610                 tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
611                 tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
612                 tegra_otg_pdata.id_extcon_dev_name = "as3722-extcon";
613         } else {
614                 /* Ardbeg */
615                 tegra_get_pmu_board_info(&bi);
616
617                 switch (bi.board_id) {
618                 case BOARD_E1733:
619                         /* Host cable is detected through PMU Interrupt */
620                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
621                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
622                         tegra_otg_pdata.id_extcon_dev_name = "as3722-extcon";
623                         break;
624                 case BOARD_E1736:
625                 case BOARD_E1735:
626                         /* Device cable is detected through PMU Interrupt */
627                         tegra_udc_pdata.support_pmu_vbus = true;
628                         tegra_ehci1_utmi_pdata.support_pmu_vbus = true;
629                         tegra_otg_pdata.vbus_extcon_dev_name = "palmas-extcon";
630                         /* Host cable is detected through PMU Interrupt */
631                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
632                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
633                         tegra_otg_pdata.id_extcon_dev_name = "palmas-extcon";
634                 }
635         }
636
637         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
638                 tegra_otg_pdata.is_xhci = false;
639                 tegra_udc_pdata.u_data.dev.is_xhci = false;
640         } else {
641                 tegra_otg_pdata.is_xhci = true;
642                 tegra_udc_pdata.u_data.dev.is_xhci = true;
643         }
644         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
645         platform_device_register(&tegra_otg_device);
646         /* Setup the udc platform data */
647         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
648
649         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
650                 if (!modem_id) {
651                         tegra_ehci2_device.dev.platform_data =
652                                 &tegra_ehci2_utmi_pdata;
653                         platform_device_register(&tegra_ehci2_device);
654                 }
655         }
656         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
657                 tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
658                 platform_device_register(&tegra_ehci3_device);
659         }
660 }
661
662 static struct tegra_xusb_board_data xusb_bdata = {
663         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_SS_P1 |
664                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_USB2_P2,
665         .supply = {
666                 .utmi_vbuses = {
667                         "usb_vbus0", "usb_vbus1", "usb_vbus2"
668                 },
669                 .s3p3v = "hvdd_usb",
670                 .s1p8v = "avdd_pll_utmip",
671                 .vddio_hsic = "vddio_hsic",
672                 .s1p05v = "avddio_usb",
673         },
674
675         .hsic[0] = {
676                 .rx_strobe_trim = 0x1,
677                 .rx_data_trim = 0x1,
678                 .tx_rtune_n = 0x8,
679                 .tx_rtune_p = 0xa,
680                 .tx_slew_n = 0,
681                 .tx_slew_p = 0,
682                 .auto_term_en = true,
683                 .strb_trim_val = 0x22,
684                 .pretend_connect = false,
685         },
686         .uses_external_pmic = false,
687 };
688
689 static void ardbeg_xusb_init(void)
690 {
691         int usb_port_owner_info = tegra_get_usb_port_owner_info();
692
693         xusb_bdata.lane_owner = (u8) tegra_get_lane_owner_info();
694
695         if (board_info.board_id == BOARD_PM359 ||
696                         board_info.board_id == BOARD_PM358 ||
697                         board_info.board_id == BOARD_PM363) {
698                 /* Laguna */
699                 pr_info("Laguna ERS. 0x%x\n", board_info.board_id);
700                 xusb_bdata.gpio_controls_muxed_ss_lanes = true;
701                 /* D[0:15] = gpio number and D[16:31] = output value */
702                 xusb_bdata.gpio_ss1_sata = PMU_TCA6416_GPIO(9) | (0 << 16);
703                 xusb_bdata.ss_portmap = (TEGRA_XUSB_SS_PORT_MAP_USB2_P0 << 0) |
704                         (TEGRA_XUSB_SS_PORT_MAP_USB2_P1 << 4);
705
706                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
707                         xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
708                                 TEGRA_XUSB_SS_P0);
709
710                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
711                         xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
712                                 TEGRA_XUSB_SS_P1 | TEGRA_XUSB_USB2_P2);
713
714                 /* FIXME Add for UTMIP2 when have odmdata assigend */
715         } else {
716                 /* Ardbeg */
717                 xusb_bdata.gpio_controls_muxed_ss_lanes = false;
718
719                 if (board_info.board_id == BOARD_E1781) {
720                         pr_info("Shield ERS-S. 0x%x\n", board_info.board_id);
721                         /* Shield ERS-S */
722                         xusb_bdata.ss_portmap =
723                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P1 << 0) |
724                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P2 << 4);
725
726                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
727                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
728
729                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
730                                 xusb_bdata.portmap &= ~(
731                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0 |
732                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
733                 } else {
734                         pr_info("Shield ERS 0x%x\n", board_info.board_id);
735                         /* Shield ERS */
736                         xusb_bdata.ss_portmap =
737                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P0 << 0) |
738                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P2 << 4);
739
740                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
741                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
742                                         TEGRA_XUSB_SS_P0);
743
744                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
745                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
746                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
747                 }
748                 /* FIXME Add for UTMIP2 when have odmdata assigend */
749         }
750
751         if (usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)
752                 xusb_bdata.portmap |= TEGRA_XUSB_HSIC_P0;
753
754         if (usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)
755                 xusb_bdata.portmap |= TEGRA_XUSB_HSIC_P1;
756
757         if (xusb_bdata.portmap)
758                 tegra_xusb_init(&xusb_bdata);
759 }
760
761 static int baseband_init(void)
762 {
763         int ret;
764
765         ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios));
766         if (ret) {
767                 pr_warn("%s:gpio request failed\n", __func__);
768                 return ret;
769         }
770
771         /* enable pull-down for MDM_COLD_BOOT */
772         tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4,
773                                     TEGRA_PUPD_PULL_DOWN);
774
775         /* export GPIO for user space access through sysfs */
776         gpio_export(MDM_RST, false);
777
778         return 0;
779 }
780
781 static const struct tegra_modem_operations baseband_operations = {
782         .init = baseband_init,
783 };
784
785 static struct tegra_usb_modem_power_platform_data baseband_pdata = {
786         .ops = &baseband_operations,
787         .regulator_name = "vdd_wwan_mdm",
788         .wake_gpio = -1,
789         .boot_gpio = MDM_COLDBOOT,
790         .boot_irq_flags = IRQF_TRIGGER_RISING |
791                                     IRQF_TRIGGER_FALLING |
792                                     IRQF_ONESHOT,
793         .autosuspend_delay = 2000,
794         .short_autosuspend_delay = 50,
795         .tegra_ehci_device = &tegra_ehci2_device,
796         .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata,
797 };
798
799 static struct platform_device icera_bruce_device = {
800         .name = "tegra_usb_modem_power",
801         .id = -1,
802         .dev = {
803                 .platform_data = &baseband_pdata,
804         },
805 };
806
807 static void ardbeg_modem_init(void)
808 {
809         int modem_id = tegra_get_modem_id();
810         struct board_info board_info;
811         struct board_info pmu_board_info;
812         int usb_port_owner_info = tegra_get_usb_port_owner_info();
813
814         tegra_get_board_info(&board_info);
815         tegra_get_pmu_board_info(&pmu_board_info);
816         pr_info("%s: modem_id = %d\n", __func__, modem_id);
817
818         switch (modem_id) {
819         case TEGRA_BB_BRUCE:
820                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
821                         /* Set specific USB wake source for Ardbeg */
822                         if (board_info.board_id == BOARD_E1780)
823                                 tegra_set_wake_source(42, INT_USB2);
824                         if (pmu_board_info.board_id == BOARD_E1736)
825                                 baseband_pdata.regulator_name = NULL;
826                         platform_device_register(&icera_bruce_device);
827                 }
828                 break;
829         case TEGRA_BB_HSIC_HUB: /* HSIC hub */
830                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
831                         tegra_ehci2_device.dev.platform_data =
832                                 &tegra_ehci2_hsic_smsc_hub_pdata;
833                         /* Set specific USB wake source for Ardbeg */
834                         if (board_info.board_id == BOARD_E1780)
835                                 tegra_set_wake_source(42, INT_USB2);
836                         platform_device_register(&tegra_ehci2_device);
837                 } else
838                         xusb_bdata.hsic[0].pretend_connect = true;
839                 break;
840         default:
841                 return;
842         }
843 }
844
845 #ifndef CONFIG_USE_OF
846 static struct platform_device *ardbeg_spi_devices[] __initdata = {
847         &tegra11_spi_device1,
848         &tegra11_spi_device4,
849 };
850
851 static struct tegra_spi_platform_data ardbeg_spi1_pdata = {
852         .dma_req_sel            = 15,
853         .spi_max_frequency      = 25000000,
854         .clock_always_on        = false,
855 };
856
857 static struct tegra_spi_platform_data ardbeg_spi4_pdata = {
858         .dma_req_sel            = 18,
859         .spi_max_frequency      = 25000000,
860         .clock_always_on        = false,
861 };
862
863 static void __init ardbeg_spi_init(void)
864 {
865         tegra11_spi_device1.dev.platform_data = &ardbeg_spi1_pdata;
866         tegra11_spi_device4.dev.platform_data = &ardbeg_spi4_pdata;
867         platform_add_devices(ardbeg_spi_devices,
868                         ARRAY_SIZE(ardbeg_spi_devices));
869 }
870 #else
871 static void __init ardbeg_spi_init(void)
872 {
873 }
874 #endif
875
876 #ifdef CONFIG_USE_OF
877 struct of_dev_auxdata ardbeg_auxdata_lookup[] __initdata = {
878         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d400, "spi-tegra114.0",
879                                 NULL),
880         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d600, "spi-tegra114.1",
881                                 NULL),
882         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d800, "spi-tegra114.2",
883                                 NULL),
884         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000da00, "spi-tegra114.3",
885                                 NULL),
886         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000dc00, "spi-tegra114.4",
887                                 NULL),
888         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000de00, "spi-tegra114.5",
889                                 NULL),
890         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
891                                 NULL),
892         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
893                 NULL),
894         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", 0x538F0000, "gk20a", NULL),
895 #ifdef CONFIG_ARCH_TEGRA_VIC
896         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03", NULL),
897 #endif
898         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
899                 NULL),
900         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi", NULL),
901         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp", NULL),
902         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
903         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0",
904                                 NULL),
905         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1",
906                                 NULL),
907         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2",
908                                 NULL),
909         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c000, "tegra12-i2c.0",
910                                 NULL),
911         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c400, "tegra12-i2c.1",
912                                 NULL),
913         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c500, "tegra12-i2c.2",
914                                 NULL),
915         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c700, "tegra12-i2c.3",
916                                 NULL),
917         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000d000, "tegra12-i2c.4",
918                                 NULL),
919         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000d100, "tegra12-i2c.5",
920                                 NULL),
921         {}
922 };
923 #endif
924
925 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
926         /* name         parent          rate            enabled */
927         { "extern2",    "pll_p",        41000000,       false},
928         { "clk_out_2",  "extern2",      40800000,       false},
929         { NULL,         NULL,           0,              0},
930 };
931
932 struct rm_spi_ts_platform_data rm31080ts_ardbeg_data = {
933         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
934         .config = 0,
935         .platform_id = RM_PLATFORM_A010,
936         .name_of_clock = "clk_out_2",
937         .name_of_clock_con = "extern2",
938 };
939
940 static struct tegra_spi_device_controller_data dev_cdata = {
941         .rx_clk_tap_delay = 16,
942         .tx_clk_tap_delay = 16,
943 };
944
945 struct spi_board_info rm31080a_ardbeg_spi_board[1] = {
946         {
947                 .modalias = "rm_ts_spidev",
948                 .bus_num = TOUCH_SPI_ID,
949                 .chip_select = TOUCH_SPI_CS,
950                 .max_speed_hz = 12 * 1000 * 1000,
951                 .mode = SPI_MODE_0,
952                 .controller_data = &dev_cdata,
953                 .platform_data = &rm31080ts_ardbeg_data,
954         },
955 };
956
957 static int __init ardbeg_touch_init(void)
958 {
959         tegra_clk_init_from_table(touch_clk_init_table);
960         rm31080a_ardbeg_spi_board[0].irq =
961                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
962         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
963                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
964                                 &rm31080ts_ardbeg_data,
965                                 &rm31080a_ardbeg_spi_board[0],
966                                 ARRAY_SIZE(rm31080a_ardbeg_spi_board));
967         return 0;
968 }
969
970 static void __init tegra_ardbeg_early_init(void)
971 {
972         tegra_clk_init_from_table(ardbeg_clk_init_table);
973         tegra_clk_verify_parents();
974         if (of_machine_is_compatible("nvidia,laguna"))
975                 tegra_soc_device_init("laguna");
976         else if (of_machine_is_compatible("nvidia,tn8"))
977                 tegra_soc_device_init("tn8");
978         else
979                 tegra_soc_device_init("ardbeg");
980 }
981
982 static struct tegra_dtv_platform_data ardbeg_dtv_pdata = {
983         .dma_req_selector = 11,
984 };
985
986 static void __init ardbeg_dtv_init(void)
987 {
988         tegra_dtv_device.dev.platform_data = &ardbeg_dtv_pdata;
989         platform_device_register(&tegra_dtv_device);
990 }
991
992 static void __init tegra_ardbeg_late_init(void)
993 {
994         struct board_info board_info;
995         tegra_get_board_info(&board_info);
996         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
997                 board_info.board_id, board_info.sku,
998                 board_info.fab, board_info.major_revision,
999                 board_info.minor_revision);
1000         platform_device_register(&tegra_pinmux_device);
1001         if (board_info.board_id == BOARD_PM359 ||
1002                         board_info.board_id == BOARD_PM358 ||
1003                         board_info.board_id == BOARD_PM363)
1004                 laguna_pinmux_init();
1005         else
1006                 ardbeg_pinmux_init();
1007         ardbeg_usb_init();
1008         ardbeg_modem_init();
1009         ardbeg_xusb_init();
1010         ardbeg_i2c_init();
1011         ardbeg_spi_init();
1012         ardbeg_uart_init();
1013         ardbeg_audio_init();
1014         platform_add_devices(ardbeg_devices, ARRAY_SIZE(ardbeg_devices));
1015         //tegra_ram_console_debug_init();
1016         tegra_io_dpd_init();
1017         ardbeg_sdhci_init();
1018         if (board_info.board_id == BOARD_PM359 ||
1019                         board_info.board_id == BOARD_PM358 ||
1020                         board_info.board_id == BOARD_PM363)
1021                 laguna_regulator_init();
1022         else
1023                 ardbeg_regulator_init();
1024         ardbeg_dtv_init();
1025         ardbeg_suspend_init();
1026 /* TODO: add support for laguna board when dvfs table is ready */
1027         if (board_info.board_id == BOARD_E1780 &&
1028                         (tegra_get_memory_type() == 0))
1029                 ardbeg_emc_init();
1030
1031         ardbeg_edp_init();
1032         isomgr_init();
1033         ardbeg_touch_init();
1034         ardbeg_panel_init();
1035         ardbeg_kbc_init();
1036         if (board_info.board_id == BOARD_PM358)
1037                 laguna_pm358_pmon_init();
1038         else
1039                 ardbeg_pmon_init();
1040         if (board_info.board_id == BOARD_PM359 ||
1041                         board_info.board_id == BOARD_PM358 ||
1042                         board_info.board_id == BOARD_PM363)
1043                 laguna_pcie_init();
1044 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1045         tegra_wdt_recovery_init();
1046 #endif
1047         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1048
1049         ardbeg_sensors_init();
1050
1051         ardbeg_soctherm_init();
1052
1053         ardbeg_setup_bluedroid_pm();
1054         tegra_register_fuse();
1055         bonaire_sata_init();
1056         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1057 }
1058
1059 static void __init ardbeg_ramconsole_reserve(unsigned long size)
1060 {
1061         tegra_ram_console_debug_reserve(SZ_1M);
1062 }
1063
1064 static void __init tegra_ardbeg_init_early(void)
1065 {
1066         ardbeg_rail_alignment_init();
1067         tegra12x_init_early();
1068 }
1069
1070 static void __init tegra_ardbeg_dt_init(void)
1071 {
1072         tegra_get_board_info(&board_info);
1073         tegra_get_display_board_info(&display_board_info);
1074
1075         tegra_ardbeg_early_init();
1076 #ifdef CONFIG_USE_OF
1077         of_platform_populate(NULL,
1078                 of_default_bus_match_table, ardbeg_auxdata_lookup,
1079                 &platform_bus);
1080 #endif
1081
1082         tegra_ardbeg_late_init();
1083 }
1084
1085 static void __init tegra_ardbeg_reserve(void)
1086 {
1087 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) || \
1088                 defined(CONFIG_TEGRA_NO_CARVEOUT)
1089         /* 1920*1200*4*2 = 18432000 bytes */
1090         tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
1091 #else
1092         tegra_reserve(SZ_1G, SZ_16M + SZ_2M, SZ_4M);
1093 #endif
1094         ardbeg_ramconsole_reserve(SZ_1M);
1095 }
1096
1097 static const char * const ardbeg_dt_board_compat[] = {
1098         "nvidia,ardbeg",
1099         NULL
1100 };
1101
1102 static const char * const laguna_dt_board_compat[] = {
1103         "nvidia,laguna",
1104         NULL
1105 };
1106
1107 static const char * const tn8_dt_board_compat[] = {
1108         "nvidia,tn8",
1109         NULL
1110 };
1111
1112 DT_MACHINE_START(LAGUNA, "laguna")
1113         .atag_offset    = 0x100,
1114         .smp            = smp_ops(tegra_smp_ops),
1115         .map_io         = tegra_map_common_io,
1116         .reserve        = tegra_ardbeg_reserve,
1117         .init_early     = tegra_ardbeg_init_early,
1118         .init_irq       = tegra_dt_init_irq,
1119         .init_time      = tegra_init_timer,
1120         .init_machine   = tegra_ardbeg_dt_init,
1121         .restart        = tegra_assert_system_reset,
1122         .dt_compat      = laguna_dt_board_compat,
1123         .init_late      = tegra_init_late
1124 MACHINE_END
1125
1126 DT_MACHINE_START(TN8, "tn8")
1127         .atag_offset    = 0x100,
1128         .smp            = smp_ops(tegra_smp_ops),
1129         .map_io         = tegra_map_common_io,
1130         .reserve        = tegra_ardbeg_reserve,
1131         .init_early     = tegra_ardbeg_init_early,
1132         .init_irq       = tegra_dt_init_irq,
1133         .init_time      = tegra_init_timer,
1134         .init_machine   = tegra_ardbeg_dt_init,
1135         .restart        = tegra_assert_system_reset,
1136         .dt_compat      = tn8_dt_board_compat,
1137         .init_late      = tegra_init_late
1138 MACHINE_END
1139
1140 DT_MACHINE_START(ARDBEG, "ardbeg")
1141         .atag_offset    = 0x100,
1142         .smp            = smp_ops(tegra_smp_ops),
1143         .map_io         = tegra_map_common_io,
1144         .reserve        = tegra_ardbeg_reserve,
1145         .init_early     = tegra_ardbeg_init_early,
1146         .init_irq       = tegra_dt_init_irq,
1147         .init_time      = tegra_init_timer,
1148         .init_machine   = tegra_ardbeg_dt_init,
1149         .restart        = tegra_assert_system_reset,
1150         .dt_compat      = ardbeg_dt_board_compat,
1151         .init_late      = tegra_init_late
1152 MACHINE_END