9e1d0eb6574dad5c73fcda421e9860cff27aba75
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c.h>
28 #include <linux/i2c/i2c-hid.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/delay.h>
31 #include <linux/i2c-tegra.h>
32 #include <linux/gpio.h>
33 #include <linux/input.h>
34 #include <linux/platform_data/tegra_usb.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/rm31080a_ts.h>
37 #include <linux/maxim_sti.h>
38 #include <linux/memblock.h>
39 #include <linux/spi/spi-tegra.h>
40 #include <linux/nfc/pn544.h>
41 #include <linux/rfkill-gpio.h>
42 #include <linux/skbuff.h>
43 #include <linux/ti_wilink_st.h>
44 #include <linux/regulator/consumer.h>
45 #include <linux/smb349-charger.h>
46 #include <linux/max17048_battery.h>
47 #include <linux/leds.h>
48 #include <linux/i2c/at24.h>
49 #include <linux/of_platform.h>
50 #include <linux/i2c.h>
51 #include <linux/i2c-tegra.h>
52 #include <linux/platform_data/serial-tegra.h>
53 #include <linux/edp.h>
54 #include <linux/usb/tegra_usb_phy.h>
55 #include <linux/mfd/palmas.h>
56 #include <linux/clk/tegra.h>
57 #include <media/tegra_dtv.h>
58 #include <linux/clocksource.h>
59 #include <linux/irqchip.h>
60 #include <linux/irqchip/tegra.h>
61 #include <linux/pci-tegra.h>
62 #include <linux/tegra-soc.h>
63
64 #include <mach/irqs.h>
65 #include <mach/tegra_fiq_debugger.h>
66
67 #include <mach/pinmux.h>
68 #include <mach/pinmux-t12.h>
69 #include <mach/io_dpd.h>
70 #include <mach/i2s.h>
71 #include <mach/isomgr.h>
72 #include <mach/tegra_asoc_pdata.h>
73 #include <asm/mach-types.h>
74 #include <asm/mach/arch.h>
75 #include <mach/gpio-tegra.h>
76 #include <mach/tegra_fiq_debugger.h>
77 #include <mach/xusb.h>
78 #include <linux/platform_data/tegra_usb_modem_power.h>
79 #include <linux/platform_data/tegra_ahci.h>
80 #include <linux/irqchip/tegra.h>
81
82 #include "board.h"
83 #include "board-ardbeg.h"
84 #include "board-common.h"
85 #include "board-touch-raydium.h"
86 #include "board-touch-maxim_sti.h"
87 #include "clock.h"
88 #include "common.h"
89 #include "devices.h"
90 #include "gpio-names.h"
91 #include "iomap.h"
92 #include "pm.h"
93 #include "tegra-board-id.h"
94
95 static struct board_info board_info, display_board_info;
96
97 static struct resource ardbeg_bluedroid_pm_resources[] = {
98         [0] = {
99                 .name   = "shutdown_gpio",
100                 .start  = TEGRA_GPIO_PR1,
101                 .end    = TEGRA_GPIO_PR1,
102                 .flags  = IORESOURCE_IO,
103         },
104         [1] = {
105                 .name = "host_wake",
106                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
107         },
108         [2] = {
109                 .name = "gpio_ext_wake",
110                 .start  = TEGRA_GPIO_PEE1,
111                 .end    = TEGRA_GPIO_PEE1,
112                 .flags  = IORESOURCE_IO,
113         },
114         [3] = {
115                 .name = "gpio_host_wake",
116                 .start  = TEGRA_GPIO_PU6,
117                 .end    = TEGRA_GPIO_PU6,
118                 .flags  = IORESOURCE_IO,
119         },
120         [4] = {
121                 .name = "reset_gpio",
122                 .start  = TEGRA_GPIO_PX1,
123                 .end    = TEGRA_GPIO_PX1,
124                 .flags  = IORESOURCE_IO,
125         },
126 };
127
128 static struct platform_device ardbeg_bluedroid_pm_device = {
129         .name = "bluedroid_pm",
130         .id             = 0,
131         .num_resources  = ARRAY_SIZE(ardbeg_bluedroid_pm_resources),
132         .resource       = ardbeg_bluedroid_pm_resources,
133 };
134
135 static noinline void __init ardbeg_setup_bluedroid_pm(void)
136 {
137         ardbeg_bluedroid_pm_resources[1].start =
138                 ardbeg_bluedroid_pm_resources[1].end =
139                                 gpio_to_irq(TEGRA_GPIO_PU6);
140         platform_device_register(&ardbeg_bluedroid_pm_device);
141 }
142
143 static struct i2c_board_info __initdata rt5639_board_info = {
144         I2C_BOARD_INFO("rt5639", 0x1c),
145 };
146 static struct i2c_board_info __initdata rt5645_board_info = {
147         I2C_BOARD_INFO("rt5645", 0x1a),
148 };
149
150 static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
151         /* name         parent          rate            enabled */
152         { "pll_m",      NULL,           0,              false},
153         { "hda",        "pll_p",        108000000,      false},
154         { "hda2codec_2x", "pll_p",      48000000,       false},
155         { "pwm",        "pll_p",        3187500,        false},
156         { "i2s1",       "pll_a_out0",   0,              false},
157         { "i2s3",       "pll_a_out0",   0,              false},
158         { "i2s4",       "pll_a_out0",   0,              false},
159         { "spdif_out",  "pll_a_out0",   0,              false},
160         { "d_audio",    "clk_m",        12000000,       false},
161         { "dam0",       "clk_m",        12000000,       false},
162         { "dam1",       "clk_m",        12000000,       false},
163         { "dam2",       "clk_m",        12000000,       false},
164         { "audio1",     "i2s1_sync",    0,              false},
165         { "audio3",     "i2s3_sync",    0,              false},
166         { "vi_sensor",  "pll_p",        150000000,      false},
167         { "vi_sensor2", "pll_p",        150000000,      false},
168         { "cilab",      "pll_p",        150000000,      false},
169         { "cilcd",      "pll_p",        150000000,      false},
170         { "cile",       "pll_p",        150000000,      false},
171         { "i2c1",       "pll_p",        3200000,        false},
172         { "i2c2",       "pll_p",        3200000,        false},
173         { "i2c3",       "pll_p",        3200000,        false},
174         { "i2c4",       "pll_p",        3200000,        false},
175         { "i2c5",       "pll_p",        3200000,        false},
176         { "sbc1",       "pll_p",        25000000,       false},
177         { "sbc2",       "pll_p",        25000000,       false},
178         { "sbc3",       "pll_p",        25000000,       false},
179         { "sbc4",       "pll_p",        25000000,       false},
180         { "sbc5",       "pll_p",        25000000,       false},
181         { "sbc6",       "pll_p",        25000000,       false},
182         { "uarta",      "pll_p",        408000000,      false},
183         { "uartb",      "pll_p",        408000000,      false},
184         { "uartc",      "pll_p",        408000000,      false},
185         { "uartd",      "pll_p",        408000000,      false},
186         { NULL,         NULL,           0,              0},
187 };
188
189 static struct i2c_hid_platform_data i2c_keyboard_pdata = {
190         .hid_descriptor_address = 0x0,
191 };
192
193 static struct i2c_board_info __initdata i2c_keyboard_board_info = {
194         I2C_BOARD_INFO("hid", 0x3B),
195         .platform_data  = &i2c_keyboard_pdata,
196 };
197
198 static struct i2c_hid_platform_data i2c_touchpad_pdata = {
199         .hid_descriptor_address = 0x20,
200 };
201
202 static struct i2c_board_info __initdata i2c_touchpad_board_info = {
203         I2C_BOARD_INFO("hid", 0x2C),
204         .platform_data  = &i2c_touchpad_pdata,
205 };
206
207 static void ardbeg_i2c_init(void)
208 {
209         struct board_info board_info;
210         tegra_get_board_info(&board_info);
211
212         i2c_register_board_info(0, &rt5639_board_info, 1);
213         i2c_register_board_info(0, &rt5645_board_info, 1);
214
215         if (board_info.board_id == BOARD_PM359 ||
216                         board_info.board_id == BOARD_PM358 ||
217                         board_info.board_id == BOARD_PM374 ||
218                         board_info.board_id == BOARD_PM370 ||
219                         board_info.board_id == BOARD_PM363) {
220                 i2c_keyboard_board_info.irq = gpio_to_irq(I2C_KB_IRQ);
221                 i2c_register_board_info(1, &i2c_keyboard_board_info , 1);
222
223                 i2c_touchpad_board_info.irq = gpio_to_irq(I2C_TP_IRQ);
224                 i2c_register_board_info(1, &i2c_touchpad_board_info , 1);
225         }
226 }
227
228 #ifndef CONFIG_USE_OF
229 static struct platform_device *ardbeg_uart_devices[] __initdata = {
230         &tegra_uarta_device,
231         &tegra_uartb_device,
232         &tegra_uartc_device,
233 };
234
235 static struct tegra_serial_platform_data ardbeg_uarta_pdata = {
236         .dma_req_selector = 8,
237         .modem_interrupt = false,
238 };
239
240 static struct tegra_serial_platform_data ardbeg_uartb_pdata = {
241         .dma_req_selector = 9,
242         .modem_interrupt = false,
243 };
244
245 static struct tegra_serial_platform_data ardbeg_uartc_pdata = {
246         .dma_req_selector = 10,
247         .modem_interrupt = false,
248 };
249 #endif
250
251 static struct tegra_serial_platform_data ardbeg_uartd_pdata = {
252         .dma_req_selector = 19,
253         .modem_interrupt = false,
254 };
255
256 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
257         .gpio_hp_det = TEGRA_GPIO_HP_DET,
258         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
259         .gpio_spkr_en = -1,
260         .gpio_int_mic_en = -1,
261         .gpio_ext_mic_en = -1,
262         .gpio_hp_mute = -1,
263         .gpio_codec1 = -1,
264         .gpio_codec2 = -1,
265         .gpio_codec3 = -1,
266         .edp_support = true,
267         .edp_states = {1530, 765, 0},
268         .i2s_param[HIFI_CODEC]       = {
269                 .audio_port_id = 1,
270                 .is_i2s_master = 0,
271                 .i2s_mode = TEGRA_DAIFMT_I2S,
272         },
273         .i2s_param[BT_SCO] = {
274                 .audio_port_id = 3,
275                 .is_i2s_master = 1,
276                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
277         },
278 };
279
280 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5645 = {
281         .gpio_hp_det = TEGRA_GPIO_HP_DET,
282         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
283         .gpio_spkr_en = -1,
284         .gpio_int_mic_en = -1,
285         .gpio_ext_mic_en = -1,
286         .gpio_hp_mute = -1,
287         .gpio_codec1 = -1,
288         .gpio_codec2 = -1,
289         .gpio_codec3 = -1,
290         .i2s_param[HIFI_CODEC]       = {
291                 .audio_port_id = 1,
292                 .is_i2s_master = 0,
293                 .i2s_mode = TEGRA_DAIFMT_I2S,
294         },
295         .i2s_param[BT_SCO] = {
296                 .audio_port_id = 3,
297                 .is_i2s_master = 1,
298                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
299         },
300 };
301
302 static void ardbeg_audio_init(void)
303 {
304         struct board_info board_info;
305         tegra_get_board_info(&board_info);
306         if (board_info.board_id == BOARD_PM359 ||
307                         board_info.board_id == BOARD_PM358 ||
308                         board_info.board_id == BOARD_PM370 ||
309                         board_info.board_id == BOARD_PM374 ||
310                         board_info.board_id == BOARD_PM363) {
311                 /*Laguna*/
312                 ardbeg_audio_pdata_rt5645.gpio_hp_det =
313                         TEGRA_GPIO_HP_DET;
314                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high = 1;
315                 if (board_info.board_id != BOARD_PM363)
316                         ardbeg_audio_pdata_rt5645.gpio_ldo1_en = -1;
317         } else {
318                 /*Ardbeg*/
319                 ardbeg_audio_pdata_rt5645.gpio_hp_det =
320                         TEGRA_GPIO_HP_DET;
321                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high = 0;
322                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en =
323                         TEGRA_GPIO_LDO_EN;
324         }
325
326         ardbeg_audio_pdata_rt5639.gpio_hp_det =
327                 ardbeg_audio_pdata_rt5645.gpio_hp_det;
328
329         ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high =
330                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high;
331
332         ardbeg_audio_pdata_rt5639.gpio_ldo1_en =
333                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en;
334
335         ardbeg_audio_pdata_rt5639.codec_name = "rt5639.0-001c";
336         ardbeg_audio_pdata_rt5639.codec_dai_name = "rt5639-aif1";
337         ardbeg_audio_pdata_rt5645.codec_name = "rt5645.0-001a";
338         ardbeg_audio_pdata_rt5645.codec_dai_name = "rt5645-aif1";
339 }
340
341 static struct platform_device ardbeg_audio_device_rt5645 = {
342         .name = "tegra-snd-rt5645",
343         .id = 0,
344         .dev = {
345                 .platform_data = &ardbeg_audio_pdata_rt5645,
346         },
347 };
348
349 static struct platform_device ardbeg_audio_device_rt5639 = {
350         .name = "tegra-snd-rt5639",
351         .id = 0,
352         .dev = {
353                 .platform_data = &ardbeg_audio_pdata_rt5639,
354         },
355 };
356
357 static void __init ardbeg_uart_init(void)
358 {
359
360 #ifndef CONFIG_USE_OF
361         tegra_uarta_device.dev.platform_data = &ardbeg_uarta_pdata;
362         tegra_uartb_device.dev.platform_data = &ardbeg_uartb_pdata;
363         tegra_uartc_device.dev.platform_data = &ardbeg_uartc_pdata;
364         platform_add_devices(ardbeg_uart_devices,
365                         ARRAY_SIZE(ardbeg_uart_devices));
366 #endif
367         tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
368         if (!is_tegra_debug_uartport_hs()) {
369                 int debug_port_id = uart_console_debug_init(3);
370                 if (debug_port_id < 0)
371                         return;
372
373 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
374                 tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
375 #else
376                 platform_device_register(uart_console_debug_device);
377 #endif
378         } else {
379                 tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
380                 platform_device_register(&tegra_uartd_device);
381         }
382 }
383
384 static struct resource tegra_rtc_resources[] = {
385         [0] = {
386                 .start = TEGRA_RTC_BASE,
387                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
388                 .flags = IORESOURCE_MEM,
389         },
390         [1] = {
391                 .start = INT_RTC,
392                 .end = INT_RTC,
393                 .flags = IORESOURCE_IRQ,
394         },
395 };
396
397 static struct platform_device tegra_rtc_device = {
398         .name = "tegra_rtc",
399         .id   = -1,
400         .resource = tegra_rtc_resources,
401         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
402 };
403
404 static struct tegra_pci_platform_data laguna_pcie_platform_data = {
405         .port_status[0] = 1,
406         .port_status[1] = 1,
407         .use_dock_detect        = 1,
408         /* Laguna platforms does not support CLKREQ# feature */
409         .has_clkreq     = 0,
410         .gpio   = TEGRA_GPIO_PO1,
411         .gpio_x1_slot   = PMU_TCA6416_GPIO(8),
412 };
413
414 static void laguna_pcie_init(void)
415 {
416         struct board_info board_info;
417
418         tegra_get_board_info(&board_info);
419         /* root port 1(x1 slot) is supported only on of ERS-S board */
420         if (board_info.board_id == BOARD_PM358 ||
421                 board_info.board_id == BOARD_PM363)
422                         laguna_pcie_platform_data.port_status[1] = 0;
423
424         tegra_pci_device.dev.platform_data = &laguna_pcie_platform_data;
425         platform_device_register(&tegra_pci_device);
426 }
427
428 static struct platform_device *ardbeg_devices[] __initdata = {
429         &tegra_pmu_device,
430         &tegra_rtc_device,
431 #if defined(CONFIG_TEGRA_WAKEUP_MONITOR)
432         &tegratab_tegra_wakeup_monitor_device,
433 #endif
434         &tegra_udc_device,
435 #if defined(CONFIG_TEGRA_WATCHDOG)
436         &tegra_wdt0_device,
437 #endif
438 #if defined(CONFIG_TEGRA_AVP)
439         &tegra_avp_device,
440 #endif
441 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
442         &tegra12_se_device,
443 #endif
444         &tegra_ahub_device,
445         &tegra_dam_device0,
446         &tegra_dam_device1,
447         &tegra_dam_device2,
448         &tegra_i2s_device1,
449         &tegra_i2s_device3,
450         &tegra_i2s_device4,
451         &ardbeg_audio_device_rt5639,
452         &tegra_spdif_device,
453         &spdif_dit_device,
454         &bluetooth_dit_device,
455         &tegra_hda_device,
456 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
457         &tegra_aes_device,
458 #endif
459 };
460
461 static struct tegra_usb_platform_data tegra_udc_pdata = {
462         .port_otg = true,
463         .has_hostpc = true,
464         .unaligned_dma_buf_supported = false,
465         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
466         .op_mode = TEGRA_USB_OPMODE_DEVICE,
467         .u_data.dev = {
468                 .vbus_pmu_irq = 0,
469                 .vbus_gpio = -1,
470                 .charging_supported = false,
471                 .remote_wakeup_supported = false,
472         },
473         .u_cfg.utmi = {
474                 .hssync_start_delay = 0,
475                 .elastic_limit = 16,
476                 .idle_wait_delay = 17,
477                 .term_range_adj = 6,
478                 .xcvr_setup = 8,
479                 .xcvr_lsfslew = 2,
480                 .xcvr_lsrslew = 2,
481                 .xcvr_setup_offset = 0,
482                 .xcvr_use_fuses = 1,
483         },
484 };
485
486 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
487         .port_otg = true,
488         .has_hostpc = true,
489         .unaligned_dma_buf_supported = false,
490         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
491         .op_mode = TEGRA_USB_OPMODE_HOST,
492         .u_data.host = {
493                 .vbus_gpio = -1,
494                 .hot_plug = false,
495                 .remote_wakeup_supported = true,
496                 .power_off_on_suspend = true,
497         },
498         .u_cfg.utmi = {
499                 .hssync_start_delay = 0,
500                 .elastic_limit = 16,
501                 .idle_wait_delay = 17,
502                 .term_range_adj = 6,
503                 .xcvr_setup = 15,
504                 .xcvr_lsfslew = 0,
505                 .xcvr_lsrslew = 3,
506                 .xcvr_setup_offset = 0,
507                 .xcvr_use_fuses = 1,
508                 .vbus_oc_map = 0x4,
509                 .xcvr_hsslew_lsb = 2,
510         },
511 };
512
513 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
514         .port_otg = false,
515         .has_hostpc = true,
516         .unaligned_dma_buf_supported = false,
517         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
518         .op_mode = TEGRA_USB_OPMODE_HOST,
519         .u_data.host = {
520                 .vbus_gpio = -1,
521                 .hot_plug = false,
522                 .remote_wakeup_supported = true,
523                 .power_off_on_suspend = true,
524         },
525         .u_cfg.utmi = {
526                 .hssync_start_delay = 0,
527                 .elastic_limit = 16,
528                 .idle_wait_delay = 17,
529                 .term_range_adj = 6,
530                 .xcvr_setup = 8,
531                 .xcvr_lsfslew = 2,
532                 .xcvr_lsrslew = 2,
533                 .xcvr_setup_offset = 0,
534                 .xcvr_use_fuses = 1,
535                 .vbus_oc_map = 0x5,
536         },
537 };
538
539 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
540         .port_otg = false,
541         .has_hostpc = true,
542         .unaligned_dma_buf_supported = false,
543         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
544         .op_mode = TEGRA_USB_OPMODE_HOST,
545         .u_data.host = {
546                 .vbus_gpio = -1,
547                 .hot_plug = false,
548                 .remote_wakeup_supported = true,
549                 .power_off_on_suspend = true,
550         },
551         .u_cfg.utmi = {
552         .hssync_start_delay = 0,
553                 .elastic_limit = 16,
554                 .idle_wait_delay = 17,
555                 .term_range_adj = 6,
556                 .xcvr_setup = 8,
557                 .xcvr_lsfslew = 2,
558                 .xcvr_lsrslew = 2,
559                 .xcvr_setup_offset = 0,
560                 .xcvr_use_fuses = 1,
561                 .vbus_oc_map = 0x5,
562         },
563 };
564
565 static struct gpio modem_gpios[] = { /* Bruce modem */
566         {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"},
567         {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"},
568         {MDM_SAR0, GPIOF_OUT_INIT_LOW, "MODEM SAR0"},
569 };
570
571 static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = {
572         .port_otg = false,
573         .has_hostpc = true,
574         .unaligned_dma_buf_supported = false,
575         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
576         .op_mode = TEGRA_USB_OPMODE_HOST,
577         .u_data.host = {
578                 .vbus_gpio = -1,
579                 .hot_plug = false,
580                 .remote_wakeup_supported = true,
581                 .power_off_on_suspend = true,
582         },
583 };
584
585 static struct tegra_usb_platform_data tegra_ehci2_hsic_smsc_hub_pdata = {
586         .port_otg = false,
587         .has_hostpc = true,
588         .unaligned_dma_buf_supported = false,
589         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
590         .op_mode        = TEGRA_USB_OPMODE_HOST,
591         .u_data.host = {
592                 .vbus_gpio = -1,
593                 .hot_plug = false,
594                 .remote_wakeup_supported = true,
595                 .power_off_on_suspend = true,
596         },
597 };
598
599
600 static struct tegra_usb_otg_data tegra_otg_pdata = {
601         .ehci_device = &tegra_ehci1_device,
602         .ehci_pdata = &tegra_ehci1_utmi_pdata,
603 };
604
605 static void ardbeg_usb_init(void)
606 {
607         int usb_port_owner_info = tegra_get_usb_port_owner_info();
608         int modem_id = tegra_get_modem_id();
609         struct board_info bi;
610
611         if (board_info.sku == 1100)
612                 tegra_ehci1_utmi_pdata.u_data.host.turn_off_vbus_on_lp0 = true;
613
614         if (board_info.board_id == BOARD_PM359 ||
615                         board_info.board_id == BOARD_PM358 ||
616                         board_info.board_id == BOARD_PM370 ||
617                         board_info.board_id == BOARD_PM374 ||
618                         board_info.board_id == BOARD_PM363) {
619                 /* Laguna */
620                 /* Host cable is detected through AMS PMU Interrupt */
621                 tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
622                 tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
623                 tegra_otg_pdata.id_extcon_dev_name = "as3722-extcon";
624         } else {
625                 /* Ardbeg */
626                 tegra_get_pmu_board_info(&bi);
627
628                 switch (bi.board_id) {
629                 case BOARD_E1733:
630                         /* Host cable is detected through PMU Interrupt */
631                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
632                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
633                         tegra_otg_pdata.id_extcon_dev_name = "as3722-extcon";
634                         break;
635                 case BOARD_E1736:
636                 case BOARD_E1769:
637                 case BOARD_E1735:
638                         /* Device cable is detected through PMU Interrupt */
639                         tegra_udc_pdata.support_pmu_vbus = true;
640                         tegra_ehci1_utmi_pdata.support_pmu_vbus = true;
641                         tegra_otg_pdata.vbus_extcon_dev_name = "palmas-extcon";
642                         /* Host cable is detected through PMU Interrupt */
643                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
644                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
645                         tegra_otg_pdata.id_extcon_dev_name = "palmas-extcon";
646                 }
647         }
648
649         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
650                 tegra_otg_pdata.is_xhci = false;
651                 tegra_udc_pdata.u_data.dev.is_xhci = false;
652         } else {
653                 tegra_otg_pdata.is_xhci = true;
654                 tegra_udc_pdata.u_data.dev.is_xhci = true;
655         }
656         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
657         platform_device_register(&tegra_otg_device);
658         /* Setup the udc platform data */
659         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
660
661         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
662                 if (!modem_id) {
663                         tegra_ehci2_device.dev.platform_data =
664                                 &tegra_ehci2_utmi_pdata;
665                         platform_device_register(&tegra_ehci2_device);
666                 }
667         }
668         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
669                 tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
670                 platform_device_register(&tegra_ehci3_device);
671         }
672 }
673
674 static struct tegra_xusb_platform_data xusb_pdata = {
675         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_SS_P1 |
676                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_USB2_P2,
677 };
678
679 static void ardbeg_xusb_init(void)
680 {
681         int usb_port_owner_info = tegra_get_usb_port_owner_info();
682
683         xusb_pdata.lane_owner = (u8) tegra_get_lane_owner_info();
684
685         if (board_info.board_id == BOARD_PM359 ||
686                         board_info.board_id == BOARD_PM358 ||
687                         board_info.board_id == BOARD_PM374 ||
688                         board_info.board_id == BOARD_PM370 ||
689                         board_info.board_id == BOARD_PM363) {
690                 /* Laguna */
691                 pr_info("Laguna ERS. 0x%x\n", board_info.board_id);
692
693                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
694                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
695                                 TEGRA_XUSB_SS_P0);
696
697                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
698                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
699                                 TEGRA_XUSB_SS_P1 | TEGRA_XUSB_USB2_P2);
700
701                 /* FIXME Add for UTMIP2 when have odmdata assigend */
702         } else {
703                 /* Ardbeg */
704                 if (board_info.board_id == BOARD_E1781) {
705                         pr_info("Shield ERS-S. 0x%x\n", board_info.board_id);
706                         /* Shield ERS-S */
707                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
708                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
709
710                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
711                                 xusb_pdata.portmap &= ~(
712                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0 |
713                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
714                 } else {
715                         pr_info("Shield ERS 0x%x\n", board_info.board_id);
716                         /* Shield ERS */
717                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
718                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
719                                         TEGRA_XUSB_SS_P0);
720
721                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
722                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
723                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
724                 }
725                 /* FIXME Add for UTMIP2 when have odmdata assigend */
726         }
727
728         if (usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)
729                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P0;
730
731         if (usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)
732                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P1;
733 }
734
735 static int baseband_init(void)
736 {
737         int ret;
738
739         ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios));
740         if (ret) {
741                 pr_warn("%s:gpio request failed\n", __func__);
742                 return ret;
743         }
744
745         /* enable pull-down for MDM_COLD_BOOT */
746         tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4,
747                                     TEGRA_PUPD_PULL_DOWN);
748
749         /* export GPIO for user space access through sysfs */
750         gpio_export(MDM_RST, false);
751         gpio_export(MDM_SAR0, false);
752
753         return 0;
754 }
755
756 static const struct tegra_modem_operations baseband_operations = {
757         .init = baseband_init,
758 };
759
760 static struct tegra_usb_modem_power_platform_data baseband_pdata = {
761         .ops = &baseband_operations,
762         .regulator_name = "vdd_wwan_mdm",
763         .wake_gpio = -1,
764         .boot_gpio = MDM_COLDBOOT,
765         .boot_irq_flags = IRQF_TRIGGER_RISING |
766                                     IRQF_TRIGGER_FALLING |
767                                     IRQF_ONESHOT,
768         .autosuspend_delay = 2000,
769         .short_autosuspend_delay = 50,
770         .tegra_ehci_device = &tegra_ehci2_device,
771         .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata,
772         .sysedpc_name = "modem",
773 };
774
775 static struct platform_device icera_bruce_device = {
776         .name = "tegra_usb_modem_power",
777         .id = -1,
778         .dev = {
779                 .platform_data = &baseband_pdata,
780         },
781 };
782
783 static void ardbeg_modem_init(void)
784 {
785         int modem_id = tegra_get_modem_id();
786         struct board_info board_info;
787         struct board_info pmu_board_info;
788         int usb_port_owner_info = tegra_get_usb_port_owner_info();
789
790         tegra_get_board_info(&board_info);
791         tegra_get_pmu_board_info(&pmu_board_info);
792         pr_info("%s: modem_id = %d\n", __func__, modem_id);
793
794         switch (modem_id) {
795         case TEGRA_BB_BRUCE:
796                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
797                         /* Set specific USB wake source for Ardbeg */
798                         if (board_info.board_id == BOARD_E1780)
799                                 tegra_set_wake_source(42, INT_USB2);
800                         if (pmu_board_info.board_id == BOARD_E1736 ||
801                                 pmu_board_info.board_id == BOARD_E1769)
802                                 baseband_pdata.regulator_name = NULL;
803                         platform_device_register(&icera_bruce_device);
804                 }
805                 break;
806         case TEGRA_BB_HSIC_HUB: /* HSIC hub */
807                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
808                         tegra_ehci2_device.dev.platform_data =
809                                 &tegra_ehci2_hsic_smsc_hub_pdata;
810                         /* Set specific USB wake source for Ardbeg */
811                         if (board_info.board_id == BOARD_E1780)
812                                 tegra_set_wake_source(42, INT_USB2);
813                         platform_device_register(&tegra_ehci2_device);
814                 } else
815                         xusb_pdata.pretend_connect_0 = true;
816                 break;
817         default:
818                 return;
819         }
820 }
821
822 #ifndef CONFIG_USE_OF
823 static struct platform_device *ardbeg_spi_devices[] __initdata = {
824         &tegra11_spi_device1,
825         &tegra11_spi_device4,
826 };
827
828 static struct tegra_spi_platform_data ardbeg_spi1_pdata = {
829         .dma_req_sel            = 15,
830         .spi_max_frequency      = 25000000,
831         .clock_always_on        = false,
832 };
833
834 static struct tegra_spi_platform_data ardbeg_spi4_pdata = {
835         .dma_req_sel            = 18,
836         .spi_max_frequency      = 25000000,
837         .clock_always_on        = false,
838 };
839
840 static void __init ardbeg_spi_init(void)
841 {
842         tegra11_spi_device1.dev.platform_data = &ardbeg_spi1_pdata;
843         tegra11_spi_device4.dev.platform_data = &ardbeg_spi4_pdata;
844         platform_add_devices(ardbeg_spi_devices,
845                         ARRAY_SIZE(ardbeg_spi_devices));
846 }
847 #else
848 static void __init ardbeg_spi_init(void)
849 {
850 }
851 #endif
852
853 #ifdef CONFIG_USE_OF
854 static struct of_dev_auxdata ardbeg_auxdata_lookup[] __initdata = {
855         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d400, "spi-tegra114.0",
856                                 NULL),
857         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d600, "spi-tegra114.1",
858                                 NULL),
859         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d800, "spi-tegra114.2",
860                                 NULL),
861         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000da00, "spi-tegra114.3",
862                                 NULL),
863         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000dc00, "spi-tegra114.4",
864                                 NULL),
865         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000de00, "spi-tegra114.5",
866                                 NULL),
867         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
868                                 NULL),
869         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
870                 NULL),
871         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", TEGRA_GK20A_BAR0_BASE,
872                 "gk20a.0", NULL),
873 #ifdef CONFIG_ARCH_TEGRA_VIC
874         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03.0", NULL),
875 #endif
876         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
877                 NULL),
878         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi.0", NULL),
879         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp.0", NULL),
880         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISPB_BASE, "isp.1", NULL),
881         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
882         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0",
883                                 NULL),
884         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1",
885                                 NULL),
886         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2",
887                                 NULL),
888         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c000, "tegra12-i2c.0",
889                                 NULL),
890         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c400, "tegra12-i2c.1",
891                                 NULL),
892         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c500, "tegra12-i2c.2",
893                                 NULL),
894         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c700, "tegra12-i2c.3",
895                                 NULL),
896         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000d000, "tegra12-i2c.4",
897                                 NULL),
898         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000d100, "tegra12-i2c.5",
899                                 NULL),
900         OF_DEV_AUXDATA("nvidia,tegra124-xhci", 0x70090000, "tegra-xhci",
901                                 &xusb_pdata),
902         {}
903 };
904 #endif
905
906 struct maxim_sti_pdata maxim_sti_pdata = {
907         .touch_fusion         = "/vendor/bin/touch_fusion",
908         .config_file          = "/vendor/firmware/touch_fusion.cfg",
909         .fw_name              = "maxim_fp35.bin",
910         .nl_family            = TF_FAMILY_NAME,
911         .nl_mc_groups         = 5,
912         .chip_access_method   = 2,
913         .default_reset_state  = 0,
914         .tx_buf_size          = 4100,
915         .rx_buf_size          = 4100,
916         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
917         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
918 };
919
920 static struct tegra_spi_device_controller_data maxim_dev_cdata = {
921         .rx_clk_tap_delay = 0,
922         .is_hw_based_cs = true,
923         .tx_clk_tap_delay = 0,
924 };
925
926 struct spi_board_info maxim_sti_spi_board = {
927         .modalias = MAXIM_STI_NAME,
928         .bus_num = TOUCH_SPI_ID,
929         .chip_select = TOUCH_SPI_CS,
930         .max_speed_hz = 12 * 1000 * 1000,
931         .mode = SPI_MODE_0,
932         .platform_data = &maxim_sti_pdata,
933         .controller_data = &maxim_dev_cdata,
934 };
935
936 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
937         /* name         parent          rate            enabled */
938         { "extern2",    "pll_p",        41000000,       false},
939         { "clk_out_2",  "extern2",      40800000,       false},
940         { NULL,         NULL,           0,              0},
941 };
942
943 static struct rm_spi_ts_platform_data rm31080ts_ardbeg_data = {
944         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
945         .config = 0,
946         .platform_id = RM_PLATFORM_A010,
947         .name_of_clock = "clk_out_2",
948         .name_of_clock_con = "extern2",
949 };
950
951 static struct tegra_spi_device_controller_data dev_cdata = {
952         .rx_clk_tap_delay = 0,
953         .tx_clk_tap_delay = 16,
954 };
955
956 static struct spi_board_info rm31080a_ardbeg_spi_board[1] = {
957         {
958                 .modalias = "rm_ts_spidev",
959                 .bus_num = TOUCH_SPI_ID,
960                 .chip_select = TOUCH_SPI_CS,
961                 .max_speed_hz = 12 * 1000 * 1000,
962                 .mode = SPI_MODE_0,
963                 .controller_data = &dev_cdata,
964                 .platform_data = &rm31080ts_ardbeg_data,
965         },
966 };
967
968 static int __init ardbeg_touch_init(void)
969 {
970         if (tegra_get_touch_vendor_id() == MAXIM_TOUCH) {
971                 pr_info("%s init maxim touch\n", __func__);
972 #if defined(CONFIG_TOUCHSCREEN_MAXIM_STI) || \
973         defined(CONFIG_TOUCHSCREEN_MAXIM_STI_MODULE)
974                 (void)touch_init_maxim_sti(&maxim_sti_spi_board);
975 #endif
976         } else if (tegra_get_touch_vendor_id() == RAYDIUM_TOUCH) {
977                 pr_info("%s init raydium touch\n", __func__);
978                 tegra_clk_init_from_table(touch_clk_init_table);
979                 rm31080a_ardbeg_spi_board[0].irq =
980                         gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
981                 touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
982                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
983                                 &rm31080ts_ardbeg_data,
984                                 &rm31080a_ardbeg_spi_board[0],
985                                 ARRAY_SIZE(rm31080a_ardbeg_spi_board));
986         }
987         return 0;
988 }
989
990 static void __init ardbeg_sysedp_init(void)
991 {
992         struct board_info bi;
993
994         tegra_get_board_info(&bi);
995
996         switch (bi.board_id) {
997         case BOARD_E1780:
998                 if (bi.sku == 1100) {
999                         tn8_new_sysedp_init();
1000                 }
1001                 else
1002                         shield_new_sysedp_init();
1003                 break;
1004         case BOARD_PM358:
1005         case BOARD_PM359:
1006         default:
1007                 break;
1008         }
1009 }
1010
1011 static void __init ardbeg_sysedp_dynamic_capping_init(void)
1012 {
1013         struct board_info bi;
1014
1015         tegra_get_board_info(&bi);
1016
1017         switch (bi.board_id) {
1018         case BOARD_E1780:
1019                 if (bi.sku == 1100)
1020                         tn8_sysedp_dynamic_capping_init();
1021                 else
1022                         shield_sysedp_dynamic_capping_init();
1023                 break;
1024         case BOARD_PM358:
1025         case BOARD_PM359:
1026         default:
1027                 break;
1028         }
1029 }
1030
1031 static void __init ardbeg_sysedp_batmon_init(void)
1032 {
1033         struct board_info bi;
1034
1035         if (!IS_ENABLED(CONFIG_SYSEDP_FRAMEWORK))
1036                 return;
1037
1038         tegra_get_board_info(&bi);
1039
1040         switch (bi.board_id) {
1041         case BOARD_E1780:
1042                 if (bi.sku == 1100)
1043                         tn8_sysedp_batmon_init();
1044                 else
1045                         shield_sysedp_batmon_init();
1046                 break;
1047         case BOARD_PM358:
1048         case BOARD_PM359:
1049         default:
1050                 break;
1051         }
1052 }
1053
1054
1055
1056 static void __init edp_init(void)
1057 {
1058         struct board_info bi;
1059
1060         tegra_get_board_info(&bi);
1061
1062         switch (bi.board_id) {
1063         case BOARD_E1780:
1064                 if (bi.sku == 1100)
1065                         tn8_edp_init();
1066                 else
1067                         ardbeg_edp_init();
1068                 break;
1069         case BOARD_PM358:
1070         case BOARD_PM359:
1071                         laguna_edp_init();
1072                         break;
1073         default:
1074                         ardbeg_edp_init();
1075                         break;
1076         }
1077 }
1078
1079 static void __init tegra_ardbeg_early_init(void)
1080 {
1081         ardbeg_sysedp_init();
1082         tegra_clk_init_from_table(ardbeg_clk_init_table);
1083         tegra_clk_verify_parents();
1084         if (of_machine_is_compatible("nvidia,laguna"))
1085                 tegra_soc_device_init("laguna");
1086         else if (of_machine_is_compatible("nvidia,tn8"))
1087                 tegra_soc_device_init("tn8");
1088         else if (of_machine_is_compatible("nvidia,ardbeg_sata"))
1089                 tegra_soc_device_init("ardbeg_sata");
1090         else
1091                 tegra_soc_device_init("ardbeg");
1092 }
1093
1094 static struct tegra_dtv_platform_data ardbeg_dtv_pdata = {
1095         .dma_req_selector = 11,
1096 };
1097
1098 static void __init ardbeg_dtv_init(void)
1099 {
1100         tegra_dtv_device.dev.platform_data = &ardbeg_dtv_pdata;
1101         platform_device_register(&tegra_dtv_device);
1102 }
1103
1104 static struct tegra_io_dpd pexbias_io = {
1105         .name                   = "PEX_BIAS",
1106         .io_dpd_reg_index       = 0,
1107         .io_dpd_bit             = 4,
1108 };
1109 static struct tegra_io_dpd pexclk1_io = {
1110         .name                   = "PEX_CLK1",
1111         .io_dpd_reg_index       = 0,
1112         .io_dpd_bit             = 5,
1113 };
1114 static struct tegra_io_dpd pexclk2_io = {
1115         .name                   = "PEX_CLK2",
1116         .io_dpd_reg_index       = 0,
1117         .io_dpd_bit             = 6,
1118 };
1119
1120 static void __init tegra_ardbeg_late_init(void)
1121 {
1122         struct board_info board_info;
1123         tegra_get_board_info(&board_info);
1124         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1125                 board_info.board_id, board_info.sku,
1126                 board_info.fab, board_info.major_revision,
1127                 board_info.minor_revision);
1128
1129         if (!of_machine_is_compatible("nvidia,tn8"))
1130                 platform_device_register(&tegra124_pinctrl_device);
1131
1132         if (board_info.board_id == BOARD_PM359 ||
1133                         board_info.board_id == BOARD_PM358 ||
1134                         board_info.board_id == BOARD_PM370 ||
1135                         board_info.board_id == BOARD_PM374 ||
1136                         board_info.board_id == BOARD_PM363)
1137                 laguna_pinmux_init();
1138         else
1139                 ardbeg_pinmux_init();
1140
1141         ardbeg_display_init();
1142         ardbeg_uart_init();
1143         ardbeg_usb_init();
1144         ardbeg_modem_init();
1145         ardbeg_xusb_init();
1146         ardbeg_i2c_init();
1147         ardbeg_spi_init();
1148         ardbeg_audio_init();
1149         platform_add_devices(ardbeg_devices, ARRAY_SIZE(ardbeg_devices));
1150         //tegra_ram_console_debug_init();
1151         tegra_io_dpd_init();
1152         ardbeg_sdhci_init();
1153         ardbeg_sata_init();
1154         if (board_info.board_id == BOARD_PM359 ||
1155                         board_info.board_id == BOARD_PM358 ||
1156                         board_info.board_id == BOARD_PM374 ||
1157                         board_info.board_id == BOARD_PM370 ||
1158                         board_info.board_id == BOARD_PM363)
1159                 laguna_regulator_init();
1160         else
1161                 ardbeg_regulator_init();
1162         ardbeg_dtv_init();
1163         ardbeg_suspend_init();
1164 /* TODO: add support for laguna board when dvfs table is ready */
1165         if ((board_info.board_id == BOARD_E1780) ||
1166                 (board_info.board_id == BOARD_E1792))
1167                 ardbeg_emc_init();
1168
1169         edp_init();
1170         isomgr_init();
1171         ardbeg_touch_init();
1172         ardbeg_panel_init();
1173         if (board_info.board_id == BOARD_PM358)
1174                 laguna_pm358_pmon_init();
1175         else
1176                 ardbeg_pmon_init();
1177         if (board_info.board_id == BOARD_PM359 ||
1178                         board_info.board_id == BOARD_PM358 ||
1179                         board_info.board_id == BOARD_PM374 ||
1180                         board_info.board_id == BOARD_PM370 ||
1181                         board_info.board_id == BOARD_PM363)
1182                 laguna_pcie_init();
1183         else {
1184                 /* put PEX pads into DPD mode to save additional power */
1185                 tegra_io_dpd_enable(&pexbias_io);
1186                 tegra_io_dpd_enable(&pexclk1_io);
1187                 tegra_io_dpd_enable(&pexclk2_io);
1188         }
1189
1190 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1191         tegra_wdt_recovery_init();
1192 #endif
1193
1194         ardbeg_sensors_init();
1195
1196         ardbeg_soctherm_init();
1197
1198         ardbeg_setup_bluedroid_pm();
1199         tegra_register_fuse();
1200
1201         ardbeg_sysedp_dynamic_capping_init();
1202         ardbeg_sysedp_batmon_init();
1203 }
1204
1205 static void __init ardbeg_ramconsole_reserve(unsigned long size)
1206 {
1207         tegra_ram_console_debug_reserve(SZ_1M);
1208 }
1209
1210 static void __init tegra_ardbeg_init_early(void)
1211 {
1212         ardbeg_rail_alignment_init();
1213         tegra12x_init_early();
1214 }
1215
1216 static void __init tegra_ardbeg_dt_init(void)
1217 {
1218         tegra_get_board_info(&board_info);
1219         tegra_get_display_board_info(&display_board_info);
1220
1221         tegra_ardbeg_early_init();
1222 #ifdef CONFIG_USE_OF
1223         of_platform_populate(NULL,
1224                 of_default_bus_match_table, ardbeg_auxdata_lookup,
1225                 &platform_bus);
1226 #endif
1227
1228         tegra_ardbeg_late_init();
1229 }
1230
1231 static void __init tegra_ardbeg_reserve(void)
1232 {
1233 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) || \
1234                 defined(CONFIG_TEGRA_NO_CARVEOUT)
1235         /* 1920*1200*4*2 = 18432000 bytes */
1236         tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
1237 #else
1238         tegra_reserve(SZ_1G, SZ_16M + SZ_2M, SZ_4M);
1239 #endif
1240         ardbeg_ramconsole_reserve(SZ_1M);
1241 }
1242
1243 static const char * const ardbeg_dt_board_compat[] = {
1244         "nvidia,ardbeg",
1245         NULL
1246 };
1247
1248 static const char * const laguna_dt_board_compat[] = {
1249         "nvidia,laguna",
1250         NULL
1251 };
1252
1253 static const char * const tn8_dt_board_compat[] = {
1254         "nvidia,tn8",
1255         NULL
1256 };
1257
1258 static const char * const ardbeg_sata_dt_board_compat[] = {
1259         "nvidia,ardbeg_sata",
1260         NULL
1261 };
1262
1263 DT_MACHINE_START(LAGUNA, "laguna")
1264         .atag_offset    = 0x100,
1265         .smp            = smp_ops(tegra_smp_ops),
1266         .map_io         = tegra_map_common_io,
1267         .reserve        = tegra_ardbeg_reserve,
1268         .init_early     = tegra_ardbeg_init_early,
1269         .init_irq       = irqchip_init,
1270         .init_time      = clocksource_of_init,
1271         .init_machine   = tegra_ardbeg_dt_init,
1272         .restart        = tegra_assert_system_reset,
1273         .dt_compat      = laguna_dt_board_compat,
1274         .init_late      = tegra_init_late
1275 MACHINE_END
1276
1277 DT_MACHINE_START(TN8, "tn8")
1278         .atag_offset    = 0x100,
1279         .smp            = smp_ops(tegra_smp_ops),
1280         .map_io         = tegra_map_common_io,
1281         .reserve        = tegra_ardbeg_reserve,
1282         .init_early     = tegra_ardbeg_init_early,
1283         .init_irq       = irqchip_init,
1284         .init_time      = clocksource_of_init,
1285         .init_machine   = tegra_ardbeg_dt_init,
1286         .restart        = tegra_assert_system_reset,
1287         .dt_compat      = tn8_dt_board_compat,
1288         .init_late      = tegra_init_late
1289 MACHINE_END
1290
1291 DT_MACHINE_START(ARDBEG, "ardbeg")
1292         .atag_offset    = 0x100,
1293         .smp            = smp_ops(tegra_smp_ops),
1294         .map_io         = tegra_map_common_io,
1295         .reserve        = tegra_ardbeg_reserve,
1296         .init_early     = tegra_ardbeg_init_early,
1297         .init_irq       = irqchip_init,
1298         .init_time      = clocksource_of_init,
1299         .init_machine   = tegra_ardbeg_dt_init,
1300         .restart        = tegra_assert_system_reset,
1301         .dt_compat      = ardbeg_dt_board_compat,
1302         .init_late      = tegra_init_late
1303 MACHINE_END
1304
1305 DT_MACHINE_START(ARDBEG_SATA, "ardbeg_sata")
1306         .atag_offset    = 0x100,
1307         .smp            = smp_ops(tegra_smp_ops),
1308         .map_io         = tegra_map_common_io,
1309         .reserve        = tegra_ardbeg_reserve,
1310         .init_early     = tegra_ardbeg_init_early,
1311         .init_irq       = irqchip_init,
1312         .init_time      = clocksource_of_init,
1313         .init_machine   = tegra_ardbeg_dt_init,
1314         .restart        = tegra_assert_system_reset,
1315         .dt_compat      = ardbeg_sata_dt_board_compat,
1316         .init_late      = tegra_init_late
1317
1318 MACHINE_END