arm: tegra: ardbeg: E1782: Add ardbeg_sata m/c
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c.h>
28 #include <linux/i2c/i2c-hid.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/delay.h>
31 #include <linux/i2c-tegra.h>
32 #include <linux/gpio.h>
33 #include <linux/input.h>
34 #include <linux/platform_data/tegra_usb.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/rm31080a_ts.h>
37 #include <linux/maxim_sti.h>
38 #include <linux/memblock.h>
39 #include <linux/spi/spi-tegra.h>
40 #include <linux/nfc/pn544.h>
41 #include <linux/rfkill-gpio.h>
42 #include <linux/skbuff.h>
43 #include <linux/ti_wilink_st.h>
44 #include <linux/regulator/consumer.h>
45 #include <linux/smb349-charger.h>
46 #include <linux/max17048_battery.h>
47 #include <linux/leds.h>
48 #include <linux/i2c/at24.h>
49 #include <linux/of_platform.h>
50 #include <linux/i2c.h>
51 #include <linux/i2c-tegra.h>
52 #include <linux/platform_data/serial-tegra.h>
53 #include <linux/edp.h>
54 #include <linux/usb/tegra_usb_phy.h>
55 #include <linux/mfd/palmas.h>
56 #include <linux/clk/tegra.h>
57 #include <media/tegra_dtv.h>
58 #include <linux/clocksource.h>
59 #include <linux/irqchip.h>
60 #include <linux/irqchip/tegra.h>
61 #include <linux/pci-tegra.h>
62 #include <linux/tegra-soc.h>
63
64 #include <mach/irqs.h>
65 #include <mach/tegra_fiq_debugger.h>
66
67 #include <mach/pinmux.h>
68 #include <mach/pinmux-t12.h>
69 #include <mach/io_dpd.h>
70 #include <mach/i2s.h>
71 #include <mach/isomgr.h>
72 #include <mach/tegra_asoc_pdata.h>
73 #include <asm/mach-types.h>
74 #include <asm/mach/arch.h>
75 #include <mach/gpio-tegra.h>
76 #include <mach/tegra_fiq_debugger.h>
77 #include <mach/xusb.h>
78 #include <linux/platform_data/tegra_usb_modem_power.h>
79 #include <linux/platform_data/tegra_ahci.h>
80 #include <linux/irqchip/tegra.h>
81
82 #include "board.h"
83 #include "board-ardbeg.h"
84 #include "board-common.h"
85 #include "board-touch-raydium.h"
86 #include "board-touch-maxim_sti.h"
87 #include "clock.h"
88 #include "common.h"
89 #include "devices.h"
90 #include "gpio-names.h"
91 #include "iomap.h"
92 #include "pm.h"
93 #include "tegra-board-id.h"
94
95 static struct board_info board_info, display_board_info;
96
97 static struct resource ardbeg_bluedroid_pm_resources[] = {
98         [0] = {
99                 .name   = "shutdown_gpio",
100                 .start  = TEGRA_GPIO_PR1,
101                 .end    = TEGRA_GPIO_PR1,
102                 .flags  = IORESOURCE_IO,
103         },
104         [1] = {
105                 .name = "host_wake",
106                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
107         },
108         [2] = {
109                 .name = "gpio_ext_wake",
110                 .start  = TEGRA_GPIO_PEE1,
111                 .end    = TEGRA_GPIO_PEE1,
112                 .flags  = IORESOURCE_IO,
113         },
114         [3] = {
115                 .name = "gpio_host_wake",
116                 .start  = TEGRA_GPIO_PU6,
117                 .end    = TEGRA_GPIO_PU6,
118                 .flags  = IORESOURCE_IO,
119         },
120         [4] = {
121                 .name = "reset_gpio",
122                 .start  = TEGRA_GPIO_PX1,
123                 .end    = TEGRA_GPIO_PX1,
124                 .flags  = IORESOURCE_IO,
125         },
126 };
127
128 static struct platform_device ardbeg_bluedroid_pm_device = {
129         .name = "bluedroid_pm",
130         .id             = 0,
131         .num_resources  = ARRAY_SIZE(ardbeg_bluedroid_pm_resources),
132         .resource       = ardbeg_bluedroid_pm_resources,
133 };
134
135 static noinline void __init ardbeg_setup_bluedroid_pm(void)
136 {
137         ardbeg_bluedroid_pm_resources[1].start =
138                 ardbeg_bluedroid_pm_resources[1].end =
139                                 gpio_to_irq(TEGRA_GPIO_PU6);
140         platform_device_register(&ardbeg_bluedroid_pm_device);
141 }
142
143 static struct i2c_board_info __initdata rt5639_board_info = {
144         I2C_BOARD_INFO("rt5639", 0x1c),
145 };
146 static struct i2c_board_info __initdata rt5645_board_info = {
147         I2C_BOARD_INFO("rt5645", 0x1a),
148 };
149
150 static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
151         /* name         parent          rate            enabled */
152         { "pll_m",      NULL,           0,              false},
153         { "hda",        "pll_p",        108000000,      false},
154         { "hda2codec_2x", "pll_p",      48000000,       false},
155         { "pwm",        "pll_p",        3187500,        false},
156         { "i2s1",       "pll_a_out0",   0,              false},
157         { "i2s3",       "pll_a_out0",   0,              false},
158         { "i2s4",       "pll_a_out0",   0,              false},
159         { "spdif_out",  "pll_a_out0",   0,              false},
160         { "d_audio",    "clk_m",        12000000,       false},
161         { "dam0",       "clk_m",        12000000,       false},
162         { "dam1",       "clk_m",        12000000,       false},
163         { "dam2",       "clk_m",        12000000,       false},
164         { "audio1",     "i2s1_sync",    0,              false},
165         { "audio3",     "i2s3_sync",    0,              false},
166         { "vi_sensor",  "pll_p",        150000000,      false},
167         { "vi_sensor2", "pll_p",        150000000,      false},
168         { "cilab",      "pll_p",        150000000,      false},
169         { "cilcd",      "pll_p",        150000000,      false},
170         { "cile",       "pll_p",        150000000,      false},
171         { "i2c1",       "pll_p",        3200000,        false},
172         { "i2c2",       "pll_p",        3200000,        false},
173         { "i2c3",       "pll_p",        3200000,        false},
174         { "i2c4",       "pll_p",        3200000,        false},
175         { "i2c5",       "pll_p",        3200000,        false},
176         { "sbc1",       "pll_p",        25000000,       false},
177         { "sbc2",       "pll_p",        25000000,       false},
178         { "sbc3",       "pll_p",        25000000,       false},
179         { "sbc4",       "pll_p",        25000000,       false},
180         { "sbc5",       "pll_p",        25000000,       false},
181         { "sbc6",       "pll_p",        25000000,       false},
182         { "uarta",      "pll_p",        408000000,      false},
183         { "uartb",      "pll_p",        408000000,      false},
184         { "uartc",      "pll_p",        408000000,      false},
185         { "uartd",      "pll_p",        408000000,      false},
186         { NULL,         NULL,           0,              0},
187 };
188
189 static struct i2c_hid_platform_data i2c_keyboard_pdata = {
190         .hid_descriptor_address = 0x0,
191 };
192
193 static struct i2c_board_info __initdata i2c_keyboard_board_info = {
194         I2C_BOARD_INFO("hid", 0x3B),
195         .platform_data  = &i2c_keyboard_pdata,
196 };
197
198 static struct i2c_hid_platform_data i2c_touchpad_pdata = {
199         .hid_descriptor_address = 0x20,
200 };
201
202 static struct i2c_board_info __initdata i2c_touchpad_board_info = {
203         I2C_BOARD_INFO("hid", 0x2C),
204         .platform_data  = &i2c_touchpad_pdata,
205 };
206
207 static void ardbeg_i2c_init(void)
208 {
209         struct board_info board_info;
210         tegra_get_board_info(&board_info);
211
212         i2c_register_board_info(0, &rt5639_board_info, 1);
213         i2c_register_board_info(0, &rt5645_board_info, 1);
214
215         if (board_info.board_id == BOARD_PM359 ||
216                         board_info.board_id == BOARD_PM358 ||
217                         board_info.board_id == BOARD_PM363) {
218                 i2c_keyboard_board_info.irq = gpio_to_irq(I2C_KB_IRQ);
219                 i2c_register_board_info(1, &i2c_keyboard_board_info , 1);
220
221                 i2c_touchpad_board_info.irq = gpio_to_irq(I2C_TP_IRQ);
222                 i2c_register_board_info(1, &i2c_touchpad_board_info , 1);
223         }
224 }
225
226 #ifndef CONFIG_USE_OF
227 static struct platform_device *ardbeg_uart_devices[] __initdata = {
228         &tegra_uarta_device,
229         &tegra_uartb_device,
230         &tegra_uartc_device,
231 };
232
233 static struct tegra_serial_platform_data ardbeg_uarta_pdata = {
234         .dma_req_selector = 8,
235         .modem_interrupt = false,
236 };
237
238 static struct tegra_serial_platform_data ardbeg_uartb_pdata = {
239         .dma_req_selector = 9,
240         .modem_interrupt = false,
241 };
242
243 static struct tegra_serial_platform_data ardbeg_uartc_pdata = {
244         .dma_req_selector = 10,
245         .modem_interrupt = false,
246 };
247 #endif
248
249 static struct tegra_serial_platform_data ardbeg_uartd_pdata = {
250         .dma_req_selector = 19,
251         .modem_interrupt = false,
252 };
253
254 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
255         .gpio_hp_det = TEGRA_GPIO_HP_DET,
256         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
257         .gpio_spkr_en = -1,
258         .gpio_int_mic_en = -1,
259         .gpio_ext_mic_en = -1,
260         .gpio_hp_mute = -1,
261         .gpio_codec1 = -1,
262         .gpio_codec2 = -1,
263         .gpio_codec3 = -1,
264         .edp_support = true,
265         .edp_states = {1530, 765, 0},
266         .i2s_param[HIFI_CODEC]       = {
267                 .audio_port_id = 1,
268                 .is_i2s_master = 0,
269                 .i2s_mode = TEGRA_DAIFMT_I2S,
270         },
271         .i2s_param[BT_SCO] = {
272                 .audio_port_id = 3,
273                 .is_i2s_master = 1,
274                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
275         },
276 };
277
278 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5645 = {
279         .gpio_hp_det = TEGRA_GPIO_HP_DET,
280         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
281         .gpio_spkr_en = -1,
282         .gpio_int_mic_en = -1,
283         .gpio_ext_mic_en = -1,
284         .gpio_hp_mute = -1,
285         .gpio_codec1 = -1,
286         .gpio_codec2 = -1,
287         .gpio_codec3 = -1,
288         .i2s_param[HIFI_CODEC]       = {
289                 .audio_port_id = 1,
290                 .is_i2s_master = 0,
291                 .i2s_mode = TEGRA_DAIFMT_I2S,
292         },
293         .i2s_param[BT_SCO] = {
294                 .audio_port_id = 3,
295                 .is_i2s_master = 1,
296                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
297         },
298 };
299
300 static void ardbeg_audio_init(void)
301 {
302         struct board_info board_info;
303         tegra_get_board_info(&board_info);
304         if (board_info.board_id == BOARD_PM359 ||
305                         board_info.board_id == BOARD_PM358 ||
306                         board_info.board_id == BOARD_PM363) {
307                 /*Laguna*/
308                 ardbeg_audio_pdata_rt5645.gpio_hp_det =
309                         TEGRA_GPIO_HP_DET;
310                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high = 1;
311                 if (board_info.board_id != BOARD_PM363)
312                         ardbeg_audio_pdata_rt5645.gpio_ldo1_en = -1;
313         } else {
314                 /*Ardbeg*/
315                 ardbeg_audio_pdata_rt5645.gpio_hp_det =
316                         TEGRA_GPIO_HP_DET;
317                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high = 0;
318                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en =
319                         TEGRA_GPIO_LDO_EN;
320         }
321
322         ardbeg_audio_pdata_rt5639.gpio_hp_det =
323                 ardbeg_audio_pdata_rt5645.gpio_hp_det;
324
325         ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high =
326                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high;
327
328         ardbeg_audio_pdata_rt5639.gpio_ldo1_en =
329                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en;
330
331         ardbeg_audio_pdata_rt5639.codec_name = "rt5639.0-001c";
332         ardbeg_audio_pdata_rt5639.codec_dai_name = "rt5639-aif1";
333         ardbeg_audio_pdata_rt5645.codec_name = "rt5645.0-001a";
334         ardbeg_audio_pdata_rt5645.codec_dai_name = "rt5645-aif1";
335 }
336
337 static struct platform_device ardbeg_audio_device_rt5645 = {
338         .name = "tegra-snd-rt5645",
339         .id = 0,
340         .dev = {
341                 .platform_data = &ardbeg_audio_pdata_rt5645,
342         },
343 };
344
345 static struct platform_device ardbeg_audio_device_rt5639 = {
346         .name = "tegra-snd-rt5639",
347         .id = 0,
348         .dev = {
349                 .platform_data = &ardbeg_audio_pdata_rt5639,
350         },
351 };
352
353 static void __init ardbeg_uart_init(void)
354 {
355
356 #ifndef CONFIG_USE_OF
357         tegra_uarta_device.dev.platform_data = &ardbeg_uarta_pdata;
358         tegra_uartb_device.dev.platform_data = &ardbeg_uartb_pdata;
359         tegra_uartc_device.dev.platform_data = &ardbeg_uartc_pdata;
360         platform_add_devices(ardbeg_uart_devices,
361                         ARRAY_SIZE(ardbeg_uart_devices));
362 #endif
363         tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
364         if (!is_tegra_debug_uartport_hs()) {
365                 int debug_port_id = uart_console_debug_init(3);
366                 if (debug_port_id < 0)
367                         return;
368
369 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
370                 tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
371 #else
372                 platform_device_register(uart_console_debug_device);
373 #endif
374         } else {
375                 tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
376                 platform_device_register(&tegra_uartd_device);
377         }
378 }
379
380 static struct resource tegra_rtc_resources[] = {
381         [0] = {
382                 .start = TEGRA_RTC_BASE,
383                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
384                 .flags = IORESOURCE_MEM,
385         },
386         [1] = {
387                 .start = INT_RTC,
388                 .end = INT_RTC,
389                 .flags = IORESOURCE_IRQ,
390         },
391 };
392
393 static struct platform_device tegra_rtc_device = {
394         .name = "tegra_rtc",
395         .id   = -1,
396         .resource = tegra_rtc_resources,
397         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
398 };
399
400 static struct tegra_pci_platform_data laguna_pcie_platform_data = {
401         .port_status[0] = 1,
402         .port_status[1] = 1,
403         .use_dock_detect        = 1,
404         /* Laguna platforms does not support CLKREQ# feature */
405         .has_clkreq     = 0,
406         .gpio   = TEGRA_GPIO_PO1,
407         .gpio_x1_slot   = PMU_TCA6416_GPIO(8),
408 };
409
410 static void laguna_pcie_init(void)
411 {
412         struct board_info board_info;
413
414         tegra_get_board_info(&board_info);
415         /* root port 1(x1 slot) is supported only on of ERS-S board */
416         if (board_info.board_id == BOARD_PM358 ||
417                 board_info.board_id == BOARD_PM363)
418                         laguna_pcie_platform_data.port_status[1] = 0;
419
420         tegra_pci_device.dev.platform_data = &laguna_pcie_platform_data;
421         platform_device_register(&tegra_pci_device);
422 }
423
424 static struct platform_device *ardbeg_devices[] __initdata = {
425         &tegra_pmu_device,
426         &tegra_rtc_device,
427 #if defined(CONFIG_TEGRA_WAKEUP_MONITOR)
428         &tegratab_tegra_wakeup_monitor_device,
429 #endif
430         &tegra_udc_device,
431 #if defined(CONFIG_TEGRA_WATCHDOG)
432         &tegra_wdt0_device,
433 #endif
434 #if defined(CONFIG_TEGRA_AVP)
435         &tegra_avp_device,
436 #endif
437 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
438         &tegra12_se_device,
439 #endif
440         &tegra_ahub_device,
441         &tegra_dam_device0,
442         &tegra_dam_device1,
443         &tegra_dam_device2,
444         &tegra_i2s_device1,
445         &tegra_i2s_device3,
446         &tegra_i2s_device4,
447         &ardbeg_audio_device_rt5639,
448         &tegra_spdif_device,
449         &spdif_dit_device,
450         &bluetooth_dit_device,
451         &tegra_hda_device,
452 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
453         &tegra_aes_device,
454 #endif
455 };
456
457 static struct tegra_usb_platform_data tegra_udc_pdata = {
458         .port_otg = true,
459         .has_hostpc = true,
460         .unaligned_dma_buf_supported = false,
461         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
462         .op_mode = TEGRA_USB_OPMODE_DEVICE,
463         .u_data.dev = {
464                 .vbus_pmu_irq = 0,
465                 .vbus_gpio = -1,
466                 .charging_supported = false,
467                 .remote_wakeup_supported = false,
468         },
469         .u_cfg.utmi = {
470                 .hssync_start_delay = 0,
471                 .elastic_limit = 16,
472                 .idle_wait_delay = 17,
473                 .term_range_adj = 6,
474                 .xcvr_setup = 8,
475                 .xcvr_lsfslew = 2,
476                 .xcvr_lsrslew = 2,
477                 .xcvr_setup_offset = 0,
478                 .xcvr_use_fuses = 1,
479         },
480 };
481
482 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
483         .port_otg = true,
484         .has_hostpc = true,
485         .unaligned_dma_buf_supported = false,
486         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
487         .op_mode = TEGRA_USB_OPMODE_HOST,
488         .u_data.host = {
489                 .vbus_gpio = -1,
490                 .hot_plug = false,
491                 .remote_wakeup_supported = true,
492                 .power_off_on_suspend = true,
493         },
494         .u_cfg.utmi = {
495                 .hssync_start_delay = 0,
496                 .elastic_limit = 16,
497                 .idle_wait_delay = 17,
498                 .term_range_adj = 6,
499                 .xcvr_setup = 15,
500                 .xcvr_lsfslew = 0,
501                 .xcvr_lsrslew = 3,
502                 .xcvr_setup_offset = 0,
503                 .xcvr_use_fuses = 1,
504                 .vbus_oc_map = 0x4,
505                 .xcvr_hsslew_lsb = 2,
506         },
507 };
508
509 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
510         .port_otg = false,
511         .has_hostpc = true,
512         .unaligned_dma_buf_supported = false,
513         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
514         .op_mode = TEGRA_USB_OPMODE_HOST,
515         .u_data.host = {
516                 .vbus_gpio = -1,
517                 .hot_plug = false,
518                 .remote_wakeup_supported = true,
519                 .power_off_on_suspend = true,
520         },
521         .u_cfg.utmi = {
522                 .hssync_start_delay = 0,
523                 .elastic_limit = 16,
524                 .idle_wait_delay = 17,
525                 .term_range_adj = 6,
526                 .xcvr_setup = 8,
527                 .xcvr_lsfslew = 2,
528                 .xcvr_lsrslew = 2,
529                 .xcvr_setup_offset = 0,
530                 .xcvr_use_fuses = 1,
531                 .vbus_oc_map = 0x5,
532         },
533 };
534
535 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
536         .port_otg = false,
537         .has_hostpc = true,
538         .unaligned_dma_buf_supported = false,
539         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
540         .op_mode = TEGRA_USB_OPMODE_HOST,
541         .u_data.host = {
542                 .vbus_gpio = -1,
543                 .hot_plug = false,
544                 .remote_wakeup_supported = true,
545                 .power_off_on_suspend = true,
546         },
547         .u_cfg.utmi = {
548         .hssync_start_delay = 0,
549                 .elastic_limit = 16,
550                 .idle_wait_delay = 17,
551                 .term_range_adj = 6,
552                 .xcvr_setup = 8,
553                 .xcvr_lsfslew = 2,
554                 .xcvr_lsrslew = 2,
555                 .xcvr_setup_offset = 0,
556                 .xcvr_use_fuses = 1,
557                 .vbus_oc_map = 0x5,
558         },
559 };
560
561 static struct gpio modem_gpios[] = { /* Bruce modem */
562         {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"},
563         {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"},
564         {MDM_SAR0, GPIOF_OUT_INIT_LOW, "MODEM SAR0"},
565 };
566
567 static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = {
568         .port_otg = false,
569         .has_hostpc = true,
570         .unaligned_dma_buf_supported = false,
571         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
572         .op_mode = TEGRA_USB_OPMODE_HOST,
573         .u_data.host = {
574                 .vbus_gpio = -1,
575                 .hot_plug = false,
576                 .remote_wakeup_supported = true,
577                 .power_off_on_suspend = true,
578         },
579 };
580
581 static struct tegra_usb_platform_data tegra_ehci2_hsic_smsc_hub_pdata = {
582         .port_otg = false,
583         .has_hostpc = true,
584         .unaligned_dma_buf_supported = false,
585         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
586         .op_mode        = TEGRA_USB_OPMODE_HOST,
587         .u_data.host = {
588                 .vbus_gpio = -1,
589                 .hot_plug = false,
590                 .remote_wakeup_supported = true,
591                 .power_off_on_suspend = true,
592         },
593 };
594
595
596 static struct tegra_usb_otg_data tegra_otg_pdata = {
597         .ehci_device = &tegra_ehci1_device,
598         .ehci_pdata = &tegra_ehci1_utmi_pdata,
599 };
600
601 static void ardbeg_usb_init(void)
602 {
603         int usb_port_owner_info = tegra_get_usb_port_owner_info();
604         int modem_id = tegra_get_modem_id();
605         struct board_info bi;
606
607         if (board_info.sku == 1100)
608                 tegra_ehci1_utmi_pdata.u_data.host.turn_off_vbus_on_lp0 = true;
609
610         if (board_info.board_id == BOARD_PM359 ||
611                         board_info.board_id == BOARD_PM358 ||
612                         board_info.board_id == BOARD_PM363) {
613                 /* Laguna */
614                 /* Host cable is detected through AMS PMU Interrupt */
615                 tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
616                 tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
617                 tegra_otg_pdata.id_extcon_dev_name = "as3722-extcon";
618         } else {
619                 /* Ardbeg */
620                 tegra_get_pmu_board_info(&bi);
621
622                 switch (bi.board_id) {
623                 case BOARD_E1733:
624                         /* Host cable is detected through PMU Interrupt */
625                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
626                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
627                         tegra_otg_pdata.id_extcon_dev_name = "as3722-extcon";
628                         break;
629                 case BOARD_E1736:
630                 case BOARD_E1769:
631                 case BOARD_E1735:
632                         /* Device cable is detected through PMU Interrupt */
633                         tegra_udc_pdata.support_pmu_vbus = true;
634                         tegra_ehci1_utmi_pdata.support_pmu_vbus = true;
635                         tegra_otg_pdata.vbus_extcon_dev_name = "palmas-extcon";
636                         /* Host cable is detected through PMU Interrupt */
637                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
638                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
639                         tegra_otg_pdata.id_extcon_dev_name = "palmas-extcon";
640                 }
641         }
642
643         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
644                 tegra_otg_pdata.is_xhci = false;
645                 tegra_udc_pdata.u_data.dev.is_xhci = false;
646         } else {
647                 tegra_otg_pdata.is_xhci = true;
648                 tegra_udc_pdata.u_data.dev.is_xhci = true;
649         }
650         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
651         platform_device_register(&tegra_otg_device);
652         /* Setup the udc platform data */
653         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
654
655         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
656                 if (!modem_id) {
657                         tegra_ehci2_device.dev.platform_data =
658                                 &tegra_ehci2_utmi_pdata;
659                         platform_device_register(&tegra_ehci2_device);
660                 }
661         }
662         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
663                 tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
664                 platform_device_register(&tegra_ehci3_device);
665         }
666 }
667
668 static struct tegra_xusb_platform_data xusb_pdata = {
669         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_SS_P1 |
670                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_USB2_P2,
671 };
672
673 static void ardbeg_xusb_init(void)
674 {
675         int usb_port_owner_info = tegra_get_usb_port_owner_info();
676
677         xusb_pdata.lane_owner = (u8) tegra_get_lane_owner_info();
678
679         if (board_info.board_id == BOARD_PM359 ||
680                         board_info.board_id == BOARD_PM358 ||
681                         board_info.board_id == BOARD_PM363) {
682                 /* Laguna */
683                 pr_info("Laguna ERS. 0x%x\n", board_info.board_id);
684
685                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
686                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
687                                 TEGRA_XUSB_SS_P0);
688
689                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
690                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
691                                 TEGRA_XUSB_SS_P1 | TEGRA_XUSB_USB2_P2);
692
693                 /* FIXME Add for UTMIP2 when have odmdata assigend */
694         } else {
695                 /* Ardbeg */
696                 if (board_info.board_id == BOARD_E1781) {
697                         pr_info("Shield ERS-S. 0x%x\n", board_info.board_id);
698                         /* Shield ERS-S */
699                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
700                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
701
702                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
703                                 xusb_pdata.portmap &= ~(
704                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0 |
705                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
706                 } else {
707                         pr_info("Shield ERS 0x%x\n", board_info.board_id);
708                         /* Shield ERS */
709                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
710                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
711                                         TEGRA_XUSB_SS_P0);
712
713                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
714                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
715                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
716                 }
717                 /* FIXME Add for UTMIP2 when have odmdata assigend */
718         }
719
720         if (usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)
721                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P0;
722
723         if (usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)
724                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P1;
725 }
726
727 static int baseband_init(void)
728 {
729         int ret;
730
731         ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios));
732         if (ret) {
733                 pr_warn("%s:gpio request failed\n", __func__);
734                 return ret;
735         }
736
737         /* enable pull-down for MDM_COLD_BOOT */
738         tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4,
739                                     TEGRA_PUPD_PULL_DOWN);
740
741         /* export GPIO for user space access through sysfs */
742         gpio_export(MDM_RST, false);
743         gpio_export(MDM_SAR0, false);
744
745         return 0;
746 }
747
748 static const struct tegra_modem_operations baseband_operations = {
749         .init = baseband_init,
750 };
751
752 static struct tegra_usb_modem_power_platform_data baseband_pdata = {
753         .ops = &baseband_operations,
754         .regulator_name = "vdd_wwan_mdm",
755         .wake_gpio = -1,
756         .boot_gpio = MDM_COLDBOOT,
757         .boot_irq_flags = IRQF_TRIGGER_RISING |
758                                     IRQF_TRIGGER_FALLING |
759                                     IRQF_ONESHOT,
760         .autosuspend_delay = 2000,
761         .short_autosuspend_delay = 50,
762         .tegra_ehci_device = &tegra_ehci2_device,
763         .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata,
764         .sysedpc_name = "modem",
765 };
766
767 static struct platform_device icera_bruce_device = {
768         .name = "tegra_usb_modem_power",
769         .id = -1,
770         .dev = {
771                 .platform_data = &baseband_pdata,
772         },
773 };
774
775 static void ardbeg_modem_init(void)
776 {
777         int modem_id = tegra_get_modem_id();
778         struct board_info board_info;
779         struct board_info pmu_board_info;
780         int usb_port_owner_info = tegra_get_usb_port_owner_info();
781
782         tegra_get_board_info(&board_info);
783         tegra_get_pmu_board_info(&pmu_board_info);
784         pr_info("%s: modem_id = %d\n", __func__, modem_id);
785
786         switch (modem_id) {
787         case TEGRA_BB_BRUCE:
788                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
789                         /* Set specific USB wake source for Ardbeg */
790                         if (board_info.board_id == BOARD_E1780)
791                                 tegra_set_wake_source(42, INT_USB2);
792                         if (pmu_board_info.board_id == BOARD_E1736 ||
793                                 pmu_board_info.board_id == BOARD_E1769)
794                                 baseband_pdata.regulator_name = NULL;
795                         platform_device_register(&icera_bruce_device);
796                 }
797                 break;
798         case TEGRA_BB_HSIC_HUB: /* HSIC hub */
799                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
800                         tegra_ehci2_device.dev.platform_data =
801                                 &tegra_ehci2_hsic_smsc_hub_pdata;
802                         /* Set specific USB wake source for Ardbeg */
803                         if (board_info.board_id == BOARD_E1780)
804                                 tegra_set_wake_source(42, INT_USB2);
805                         platform_device_register(&tegra_ehci2_device);
806                 } else
807                         xusb_pdata.pretend_connect_0 = true;
808                 break;
809         default:
810                 return;
811         }
812 }
813
814 #ifndef CONFIG_USE_OF
815 static struct platform_device *ardbeg_spi_devices[] __initdata = {
816         &tegra11_spi_device1,
817         &tegra11_spi_device4,
818 };
819
820 static struct tegra_spi_platform_data ardbeg_spi1_pdata = {
821         .dma_req_sel            = 15,
822         .spi_max_frequency      = 25000000,
823         .clock_always_on        = false,
824 };
825
826 static struct tegra_spi_platform_data ardbeg_spi4_pdata = {
827         .dma_req_sel            = 18,
828         .spi_max_frequency      = 25000000,
829         .clock_always_on        = false,
830 };
831
832 static void __init ardbeg_spi_init(void)
833 {
834         tegra11_spi_device1.dev.platform_data = &ardbeg_spi1_pdata;
835         tegra11_spi_device4.dev.platform_data = &ardbeg_spi4_pdata;
836         platform_add_devices(ardbeg_spi_devices,
837                         ARRAY_SIZE(ardbeg_spi_devices));
838 }
839 #else
840 static void __init ardbeg_spi_init(void)
841 {
842 }
843 #endif
844
845 #ifdef CONFIG_USE_OF
846 static struct of_dev_auxdata ardbeg_auxdata_lookup[] __initdata = {
847         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d400, "spi-tegra114.0",
848                                 NULL),
849         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d600, "spi-tegra114.1",
850                                 NULL),
851         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d800, "spi-tegra114.2",
852                                 NULL),
853         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000da00, "spi-tegra114.3",
854                                 NULL),
855         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000dc00, "spi-tegra114.4",
856                                 NULL),
857         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000de00, "spi-tegra114.5",
858                                 NULL),
859         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
860                                 NULL),
861         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
862                 NULL),
863         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", TEGRA_GK20A_BAR0_BASE,
864                 "gk20a.0", NULL),
865 #ifdef CONFIG_ARCH_TEGRA_VIC
866         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03.0", NULL),
867 #endif
868         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
869                 NULL),
870         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi.0", NULL),
871         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp.0", NULL),
872         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISPB_BASE, "isp.1", NULL),
873         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
874         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0",
875                                 NULL),
876         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1",
877                                 NULL),
878         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2",
879                                 NULL),
880         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c000, "tegra12-i2c.0",
881                                 NULL),
882         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c400, "tegra12-i2c.1",
883                                 NULL),
884         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c500, "tegra12-i2c.2",
885                                 NULL),
886         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c700, "tegra12-i2c.3",
887                                 NULL),
888         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000d000, "tegra12-i2c.4",
889                                 NULL),
890         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000d100, "tegra12-i2c.5",
891                                 NULL),
892         OF_DEV_AUXDATA("nvidia,tegra124-xhci", 0x70090000, "tegra-xhci",
893                                 &xusb_pdata),
894         {}
895 };
896 #endif
897
898 struct maxim_sti_pdata maxim_sti_pdata = {
899         .touch_fusion         = "/vendor/bin/touch_fusion",
900         .config_file          = "/vendor/firmware/touch_fusion.cfg",
901         .fw_name              = "maxim_fp35.bin",
902         .nl_family            = TF_FAMILY_NAME,
903         .nl_mc_groups         = 5,
904         .chip_access_method   = 2,
905         .default_reset_state  = 0,
906         .tx_buf_size          = 4100,
907         .rx_buf_size          = 4100,
908         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
909         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
910 };
911
912 static struct tegra_spi_device_controller_data maxim_dev_cdata = {
913         .rx_clk_tap_delay = 0,
914         .is_hw_based_cs = true,
915         .tx_clk_tap_delay = 0,
916 };
917
918 struct spi_board_info maxim_sti_spi_board = {
919         .modalias = MAXIM_STI_NAME,
920         .bus_num = TOUCH_SPI_ID,
921         .chip_select = TOUCH_SPI_CS,
922         .max_speed_hz = 12 * 1000 * 1000,
923         .mode = SPI_MODE_0,
924         .platform_data = &maxim_sti_pdata,
925         .controller_data = &maxim_dev_cdata,
926 };
927
928 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
929         /* name         parent          rate            enabled */
930         { "extern2",    "pll_p",        41000000,       false},
931         { "clk_out_2",  "extern2",      40800000,       false},
932         { NULL,         NULL,           0,              0},
933 };
934
935 static struct rm_spi_ts_platform_data rm31080ts_ardbeg_data = {
936         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
937         .config = 0,
938         .platform_id = RM_PLATFORM_A010,
939         .name_of_clock = "clk_out_2",
940         .name_of_clock_con = "extern2",
941 };
942
943 static struct tegra_spi_device_controller_data dev_cdata = {
944         .rx_clk_tap_delay = 0,
945         .tx_clk_tap_delay = 16,
946 };
947
948 static struct spi_board_info rm31080a_ardbeg_spi_board[1] = {
949         {
950                 .modalias = "rm_ts_spidev",
951                 .bus_num = TOUCH_SPI_ID,
952                 .chip_select = TOUCH_SPI_CS,
953                 .max_speed_hz = 12 * 1000 * 1000,
954                 .mode = SPI_MODE_0,
955                 .controller_data = &dev_cdata,
956                 .platform_data = &rm31080ts_ardbeg_data,
957         },
958 };
959
960 static int __init ardbeg_touch_init(void)
961 {
962         if (tegra_get_touch_vendor_id() == MAXIM_TOUCH) {
963                 pr_info("%s init maxim touch\n", __func__);
964 #if defined(CONFIG_TOUCHSCREEN_MAXIM_STI) || \
965         defined(CONFIG_TOUCHSCREEN_MAXIM_STI_MODULE)
966                 (void)touch_init_maxim_sti(&maxim_sti_spi_board);
967 #endif
968         } else if (tegra_get_touch_vendor_id() == RAYDIUM_TOUCH) {
969                 pr_info("%s init raydium touch\n", __func__);
970                 tegra_clk_init_from_table(touch_clk_init_table);
971                 rm31080a_ardbeg_spi_board[0].irq =
972                         gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
973                 touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
974                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
975                                 &rm31080ts_ardbeg_data,
976                                 &rm31080a_ardbeg_spi_board[0],
977                                 ARRAY_SIZE(rm31080a_ardbeg_spi_board));
978         }
979         return 0;
980 }
981
982 static void __init ardbeg_sysedp_init(void)
983 {
984         struct board_info bi;
985
986         tegra_get_board_info(&bi);
987
988         switch (bi.board_id) {
989         case BOARD_E1780:
990                 if (bi.sku == 1100) {
991                         tn8_new_sysedp_init();
992                 }
993                 break;
994         case BOARD_PM358:
995         case BOARD_PM359:
996         default:
997                 break;
998         }
999 }
1000
1001 static void __init ardbeg_sysedp_dynamic_capping_init(void)
1002 {
1003         struct board_info bi;
1004
1005         tegra_get_board_info(&bi);
1006
1007         switch (bi.board_id) {
1008         case BOARD_E1780:
1009                 if (bi.sku == 1100)
1010                         tn8_sysedp_dynamic_capping_init();
1011                 break;
1012         case BOARD_PM358:
1013         case BOARD_PM359:
1014         default:
1015                 break;
1016         }
1017 }
1018
1019 static void __init ardbeg_sysedp_batmon_init(void)
1020 {
1021         struct board_info bi;
1022
1023         if (!IS_ENABLED(CONFIG_SYSEDP_FRAMEWORK))
1024                 return;
1025
1026         tegra_get_board_info(&bi);
1027
1028         switch (bi.board_id) {
1029         case BOARD_E1780:
1030                 if (bi.sku == 1100)
1031                         tn8_sysedp_batmon_init();
1032                 break;
1033         case BOARD_PM358:
1034         case BOARD_PM359:
1035         default:
1036                 break;
1037         }
1038 }
1039
1040
1041
1042 static void __init edp_init(void)
1043 {
1044         struct board_info bi;
1045
1046         tegra_get_board_info(&bi);
1047
1048         switch (bi.board_id) {
1049         case BOARD_E1780:
1050                 if (bi.sku == 1100)
1051                         tn8_edp_init();
1052                 else
1053                         ardbeg_edp_init();
1054                 break;
1055         case BOARD_PM358:
1056         case BOARD_PM359:
1057                         laguna_edp_init();
1058                         break;
1059         default:
1060                         ardbeg_edp_init();
1061                         break;
1062         }
1063 }
1064
1065 static void __init tegra_ardbeg_early_init(void)
1066 {
1067         ardbeg_sysedp_init();
1068         tegra_clk_init_from_table(ardbeg_clk_init_table);
1069         tegra_clk_verify_parents();
1070         if (of_machine_is_compatible("nvidia,laguna"))
1071                 tegra_soc_device_init("laguna");
1072         else if (of_machine_is_compatible("nvidia,tn8"))
1073                 tegra_soc_device_init("tn8");
1074         else if (of_machine_is_compatible("nvidia,ardbeg_sata"))
1075                 tegra_soc_device_init("ardbeg_sata");
1076         else
1077                 tegra_soc_device_init("ardbeg");
1078 }
1079
1080 static struct tegra_dtv_platform_data ardbeg_dtv_pdata = {
1081         .dma_req_selector = 11,
1082 };
1083
1084 static void __init ardbeg_dtv_init(void)
1085 {
1086         tegra_dtv_device.dev.platform_data = &ardbeg_dtv_pdata;
1087         platform_device_register(&tegra_dtv_device);
1088 }
1089
1090 static struct tegra_io_dpd pexbias_io = {
1091         .name                   = "PEX_BIAS",
1092         .io_dpd_reg_index       = 0,
1093         .io_dpd_bit             = 4,
1094 };
1095 static struct tegra_io_dpd pexclk1_io = {
1096         .name                   = "PEX_CLK1",
1097         .io_dpd_reg_index       = 0,
1098         .io_dpd_bit             = 5,
1099 };
1100 static struct tegra_io_dpd pexclk2_io = {
1101         .name                   = "PEX_CLK2",
1102         .io_dpd_reg_index       = 0,
1103         .io_dpd_bit             = 6,
1104 };
1105
1106 static void __init tegra_ardbeg_late_init(void)
1107 {
1108         struct board_info board_info;
1109         tegra_get_board_info(&board_info);
1110         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1111                 board_info.board_id, board_info.sku,
1112                 board_info.fab, board_info.major_revision,
1113                 board_info.minor_revision);
1114         platform_device_register(&tegra124_pinctrl_device);
1115         if (board_info.board_id == BOARD_PM359 ||
1116                         board_info.board_id == BOARD_PM358 ||
1117                         board_info.board_id == BOARD_PM363)
1118                 laguna_pinmux_init();
1119         else
1120                 ardbeg_pinmux_init();
1121
1122         ardbeg_display_init();
1123         ardbeg_uart_init();
1124         ardbeg_usb_init();
1125         ardbeg_modem_init();
1126         ardbeg_xusb_init();
1127         ardbeg_i2c_init();
1128         ardbeg_spi_init();
1129         ardbeg_audio_init();
1130         platform_add_devices(ardbeg_devices, ARRAY_SIZE(ardbeg_devices));
1131         //tegra_ram_console_debug_init();
1132         tegra_io_dpd_init();
1133         ardbeg_sdhci_init();
1134         ardbeg_sata_init();
1135         if (board_info.board_id == BOARD_PM359 ||
1136                         board_info.board_id == BOARD_PM358 ||
1137                         board_info.board_id == BOARD_PM363)
1138                 laguna_regulator_init();
1139         else
1140                 ardbeg_regulator_init();
1141         ardbeg_dtv_init();
1142         ardbeg_suspend_init();
1143 /* TODO: add support for laguna board when dvfs table is ready */
1144         if ((board_info.board_id == BOARD_E1780 &&
1145                 (tegra_get_memory_type() == 0)) ||
1146                 (board_info.board_id == BOARD_E1792))
1147                 ardbeg_emc_init();
1148
1149         edp_init();
1150         isomgr_init();
1151         ardbeg_touch_init();
1152         ardbeg_panel_init();
1153         if (board_info.board_id == BOARD_PM358)
1154                 laguna_pm358_pmon_init();
1155         else
1156                 ardbeg_pmon_init();
1157         if (board_info.board_id == BOARD_PM359 ||
1158                         board_info.board_id == BOARD_PM358 ||
1159                         board_info.board_id == BOARD_PM363)
1160                 laguna_pcie_init();
1161         else {
1162                 /* put PEX pads into DPD mode to save additional power */
1163                 tegra_io_dpd_enable(&pexbias_io);
1164                 tegra_io_dpd_enable(&pexclk1_io);
1165                 tegra_io_dpd_enable(&pexclk2_io);
1166         }
1167
1168 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1169         tegra_wdt_recovery_init();
1170 #endif
1171
1172         ardbeg_sensors_init();
1173
1174         ardbeg_soctherm_init();
1175
1176         ardbeg_setup_bluedroid_pm();
1177         tegra_register_fuse();
1178
1179         ardbeg_sysedp_dynamic_capping_init();
1180         ardbeg_sysedp_batmon_init();
1181 }
1182
1183 static void __init ardbeg_ramconsole_reserve(unsigned long size)
1184 {
1185         tegra_ram_console_debug_reserve(SZ_1M);
1186 }
1187
1188 static void __init tegra_ardbeg_init_early(void)
1189 {
1190         ardbeg_rail_alignment_init();
1191         tegra12x_init_early();
1192 }
1193
1194 static void __init tegra_ardbeg_dt_init(void)
1195 {
1196         tegra_get_board_info(&board_info);
1197         tegra_get_display_board_info(&display_board_info);
1198
1199         tegra_ardbeg_early_init();
1200 #ifdef CONFIG_USE_OF
1201         of_platform_populate(NULL,
1202                 of_default_bus_match_table, ardbeg_auxdata_lookup,
1203                 &platform_bus);
1204 #endif
1205
1206         tegra_ardbeg_late_init();
1207 }
1208
1209 static void __init tegra_ardbeg_reserve(void)
1210 {
1211 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) || \
1212                 defined(CONFIG_TEGRA_NO_CARVEOUT)
1213         /* 1920*1200*4*2 = 18432000 bytes */
1214         tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
1215 #else
1216         tegra_reserve(SZ_1G, SZ_16M + SZ_2M, SZ_4M);
1217 #endif
1218         ardbeg_ramconsole_reserve(SZ_1M);
1219 }
1220
1221 static const char * const ardbeg_dt_board_compat[] = {
1222         "nvidia,ardbeg",
1223         NULL
1224 };
1225
1226 static const char * const laguna_dt_board_compat[] = {
1227         "nvidia,laguna",
1228         NULL
1229 };
1230
1231 static const char * const tn8_dt_board_compat[] = {
1232         "nvidia,tn8",
1233         NULL
1234 };
1235
1236 static const char * const ardbeg_sata_dt_board_compat[] = {
1237         "nvidia,ardbeg_sata",
1238         NULL
1239 };
1240
1241 DT_MACHINE_START(LAGUNA, "laguna")
1242         .atag_offset    = 0x100,
1243         .smp            = smp_ops(tegra_smp_ops),
1244         .map_io         = tegra_map_common_io,
1245         .reserve        = tegra_ardbeg_reserve,
1246         .init_early     = tegra_ardbeg_init_early,
1247         .init_irq       = irqchip_init,
1248         .init_time      = clocksource_of_init,
1249         .init_machine   = tegra_ardbeg_dt_init,
1250         .restart        = tegra_assert_system_reset,
1251         .dt_compat      = laguna_dt_board_compat,
1252         .init_late      = tegra_init_late
1253 MACHINE_END
1254
1255 DT_MACHINE_START(TN8, "tn8")
1256         .atag_offset    = 0x100,
1257         .smp            = smp_ops(tegra_smp_ops),
1258         .map_io         = tegra_map_common_io,
1259         .reserve        = tegra_ardbeg_reserve,
1260         .init_early     = tegra_ardbeg_init_early,
1261         .init_irq       = irqchip_init,
1262         .init_time      = clocksource_of_init,
1263         .init_machine   = tegra_ardbeg_dt_init,
1264         .restart        = tegra_assert_system_reset,
1265         .dt_compat      = tn8_dt_board_compat,
1266         .init_late      = tegra_init_late
1267 MACHINE_END
1268
1269 DT_MACHINE_START(ARDBEG, "ardbeg")
1270         .atag_offset    = 0x100,
1271         .smp            = smp_ops(tegra_smp_ops),
1272         .map_io         = tegra_map_common_io,
1273         .reserve        = tegra_ardbeg_reserve,
1274         .init_early     = tegra_ardbeg_init_early,
1275         .init_irq       = irqchip_init,
1276         .init_time      = clocksource_of_init,
1277         .init_machine   = tegra_ardbeg_dt_init,
1278         .restart        = tegra_assert_system_reset,
1279         .dt_compat      = ardbeg_dt_board_compat,
1280         .init_late      = tegra_init_late
1281 MACHINE_END
1282
1283 DT_MACHINE_START(ARDBEG_SATA, "ardbeg_sata")
1284         .atag_offset    = 0x100,
1285         .smp            = smp_ops(tegra_smp_ops),
1286         .map_io         = tegra_map_common_io,
1287         .reserve        = tegra_ardbeg_reserve,
1288         .init_early     = tegra_ardbeg_init_early,
1289         .init_irq       = irqchip_init,
1290         .init_time      = clocksource_of_init,
1291         .init_machine   = tegra_ardbeg_dt_init,
1292         .restart        = tegra_assert_system_reset,
1293         .dt_compat      = ardbeg_sata_dt_board_compat,
1294         .init_late      = tegra_init_late
1295
1296 MACHINE_END