ARM: DT: Add DT entry for PWMs and Backlight
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c.h>
28 #include <linux/i2c/i2c-hid.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/delay.h>
31 #include <linux/i2c-tegra.h>
32 #include <linux/gpio.h>
33 #include <linux/input.h>
34 #include <linux/platform_data/tegra_usb.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/rm31080a_ts.h>
37 #include <linux/maxim_sti.h>
38 #include <linux/memblock.h>
39 #include <linux/spi/spi-tegra.h>
40 #include <linux/nfc/pn544.h>
41 #include <linux/rfkill-gpio.h>
42 #include <linux/skbuff.h>
43 #include <linux/ti_wilink_st.h>
44 #include <linux/regulator/consumer.h>
45 #include <linux/smb349-charger.h>
46 #include <linux/max17048_battery.h>
47 #include <linux/leds.h>
48 #include <linux/i2c/at24.h>
49 #include <linux/of_platform.h>
50 #include <linux/i2c.h>
51 #include <linux/i2c-tegra.h>
52 #include <linux/platform_data/serial-tegra.h>
53 #include <linux/edp.h>
54 #include <linux/usb/tegra_usb_phy.h>
55 #include <linux/mfd/palmas.h>
56 #include <linux/clk/tegra.h>
57 #include <media/tegra_dtv.h>
58 #include <linux/clocksource.h>
59 #include <linux/irqchip.h>
60 #include <linux/irqchip/tegra.h>
61 #include <linux/pci-tegra.h>
62
63 #include <mach/irqs.h>
64 #include <mach/tegra_fiq_debugger.h>
65
66 #include <mach/pinmux.h>
67 #include <mach/pinmux-t12.h>
68 #include <mach/io_dpd.h>
69 #include <mach/i2s.h>
70 #include <mach/isomgr.h>
71 #include <mach/tegra_asoc_pdata.h>
72 #include <asm/mach-types.h>
73 #include <asm/mach/arch.h>
74 #include <mach/gpio-tegra.h>
75 #include <mach/tegra_fiq_debugger.h>
76 #include <mach/xusb.h>
77 #include <linux/platform_data/tegra_usb_modem_power.h>
78 #include <linux/platform_data/tegra_ahci.h>
79 #include <linux/irqchip/tegra.h>
80
81 #include "board.h"
82 #include "board-ardbeg.h"
83 #include "board-common.h"
84 #include "board-touch-raydium.h"
85 #include "board-touch-maxim_sti.h"
86 #include "clock.h"
87 #include "common.h"
88 #include "devices.h"
89 #include "gpio-names.h"
90 #include "iomap.h"
91 #include "pm.h"
92 #include "tegra-board-id.h"
93
94 static struct board_info board_info, display_board_info;
95
96 static struct resource ardbeg_bluedroid_pm_resources[] = {
97         [0] = {
98                 .name   = "shutdown_gpio",
99                 .start  = TEGRA_GPIO_PR1,
100                 .end    = TEGRA_GPIO_PR1,
101                 .flags  = IORESOURCE_IO,
102         },
103         [1] = {
104                 .name = "host_wake",
105                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
106         },
107         [2] = {
108                 .name = "gpio_ext_wake",
109                 .start  = TEGRA_GPIO_PEE1,
110                 .end    = TEGRA_GPIO_PEE1,
111                 .flags  = IORESOURCE_IO,
112         },
113         [3] = {
114                 .name = "gpio_host_wake",
115                 .start  = TEGRA_GPIO_PU6,
116                 .end    = TEGRA_GPIO_PU6,
117                 .flags  = IORESOURCE_IO,
118         },
119         [4] = {
120                 .name = "reset_gpio",
121                 .start  = TEGRA_GPIO_PX1,
122                 .end    = TEGRA_GPIO_PX1,
123                 .flags  = IORESOURCE_IO,
124         },
125 };
126
127 static struct platform_device ardbeg_bluedroid_pm_device = {
128         .name = "bluedroid_pm",
129         .id             = 0,
130         .num_resources  = ARRAY_SIZE(ardbeg_bluedroid_pm_resources),
131         .resource       = ardbeg_bluedroid_pm_resources,
132 };
133
134 static noinline void __init ardbeg_setup_bluedroid_pm(void)
135 {
136         ardbeg_bluedroid_pm_resources[1].start =
137                 ardbeg_bluedroid_pm_resources[1].end =
138                                 gpio_to_irq(TEGRA_GPIO_PU6);
139         platform_device_register(&ardbeg_bluedroid_pm_device);
140 }
141
142 static struct i2c_board_info __initdata rt5639_board_info = {
143         I2C_BOARD_INFO("rt5639", 0x1c),
144 };
145 static struct i2c_board_info __initdata rt5645_board_info = {
146         I2C_BOARD_INFO("rt5645", 0x1a),
147 };
148
149 static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
150         /* name         parent          rate            enabled */
151         { "pll_m",      NULL,           0,              false},
152         { "hda",        "pll_p",        108000000,      false},
153         { "hda2codec_2x", "pll_p",      48000000,       false},
154         { "pwm",        "pll_p",        3187500,        false},
155         { "i2s1",       "pll_a_out0",   0,              false},
156         { "i2s3",       "pll_a_out0",   0,              false},
157         { "i2s4",       "pll_a_out0",   0,              false},
158         { "spdif_out",  "pll_a_out0",   0,              false},
159         { "d_audio",    "clk_m",        12000000,       false},
160         { "dam0",       "clk_m",        12000000,       false},
161         { "dam1",       "clk_m",        12000000,       false},
162         { "dam2",       "clk_m",        12000000,       false},
163         { "audio1",     "i2s1_sync",    0,              false},
164         { "audio3",     "i2s3_sync",    0,              false},
165         { "vi_sensor",  "pll_p",        150000000,      false},
166         { "vi_sensor2", "pll_p",        150000000,      false},
167         { "cilab",      "pll_p",        150000000,      false},
168         { "cilcd",      "pll_p",        150000000,      false},
169         { "cile",       "pll_p",        150000000,      false},
170         { "i2c1",       "pll_p",        3200000,        false},
171         { "i2c2",       "pll_p",        3200000,        false},
172         { "i2c3",       "pll_p",        3200000,        false},
173         { "i2c4",       "pll_p",        3200000,        false},
174         { "i2c5",       "pll_p",        3200000,        false},
175         { "sbc1",       "pll_p",        25000000,       false},
176         { "sbc2",       "pll_p",        25000000,       false},
177         { "sbc3",       "pll_p",        25000000,       false},
178         { "sbc4",       "pll_p",        25000000,       false},
179         { "sbc5",       "pll_p",        25000000,       false},
180         { "sbc6",       "pll_p",        25000000,       false},
181         { "uarta",      "pll_p",        408000000,      false},
182         { "uartb",      "pll_p",        408000000,      false},
183         { "uartc",      "pll_p",        408000000,      false},
184         { "uartd",      "pll_p",        408000000,      false},
185         { NULL,         NULL,           0,              0},
186 };
187
188 static struct i2c_hid_platform_data i2c_keyboard_pdata = {
189         .hid_descriptor_address = 0x0,
190 };
191
192 static struct i2c_board_info __initdata i2c_keyboard_board_info = {
193         I2C_BOARD_INFO("hid", 0x3B),
194         .platform_data  = &i2c_keyboard_pdata,
195 };
196
197 static struct i2c_hid_platform_data i2c_touchpad_pdata = {
198         .hid_descriptor_address = 0x20,
199 };
200
201 static struct i2c_board_info __initdata i2c_touchpad_board_info = {
202         I2C_BOARD_INFO("hid", 0x2C),
203         .platform_data  = &i2c_touchpad_pdata,
204 };
205
206 static void ardbeg_i2c_init(void)
207 {
208         struct board_info board_info;
209         tegra_get_board_info(&board_info);
210
211         i2c_register_board_info(0, &rt5639_board_info, 1);
212         i2c_register_board_info(0, &rt5645_board_info, 1);
213
214         if (board_info.board_id == BOARD_PM359 ||
215                         board_info.board_id == BOARD_PM358 ||
216                         board_info.board_id == BOARD_PM363) {
217                 i2c_keyboard_board_info.irq = gpio_to_irq(I2C_KB_IRQ);
218                 i2c_register_board_info(1, &i2c_keyboard_board_info , 1);
219
220                 i2c_touchpad_board_info.irq = gpio_to_irq(I2C_TP_IRQ);
221                 i2c_register_board_info(1, &i2c_touchpad_board_info , 1);
222         }
223 }
224
225 #ifndef CONFIG_USE_OF
226 static struct platform_device *ardbeg_uart_devices[] __initdata = {
227         &tegra_uarta_device,
228         &tegra_uartb_device,
229         &tegra_uartc_device,
230 };
231
232 static struct tegra_serial_platform_data ardbeg_uarta_pdata = {
233         .dma_req_selector = 8,
234         .modem_interrupt = false,
235 };
236
237 static struct tegra_serial_platform_data ardbeg_uartb_pdata = {
238         .dma_req_selector = 9,
239         .modem_interrupt = false,
240 };
241
242 static struct tegra_serial_platform_data ardbeg_uartc_pdata = {
243         .dma_req_selector = 10,
244         .modem_interrupt = false,
245 };
246 #endif
247
248 static struct tegra_serial_platform_data ardbeg_uartd_pdata = {
249         .dma_req_selector = 19,
250         .modem_interrupt = false,
251 };
252
253 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
254         .gpio_hp_det = TEGRA_GPIO_HP_DET,
255         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
256         .gpio_spkr_en = -1,
257         .gpio_int_mic_en = -1,
258         .gpio_ext_mic_en = -1,
259         .gpio_hp_mute = -1,
260         .gpio_codec1 = -1,
261         .gpio_codec2 = -1,
262         .gpio_codec3 = -1,
263         .edp_support = true,
264         .edp_states = {1530, 765, 0},
265         .i2s_param[HIFI_CODEC]       = {
266                 .audio_port_id = 1,
267                 .is_i2s_master = 0,
268                 .i2s_mode = TEGRA_DAIFMT_I2S,
269         },
270         .i2s_param[BT_SCO] = {
271                 .audio_port_id = 3,
272                 .is_i2s_master = 1,
273                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
274         },
275 };
276
277 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5645 = {
278         .gpio_hp_det = TEGRA_GPIO_HP_DET,
279         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
280         .gpio_spkr_en = -1,
281         .gpio_int_mic_en = -1,
282         .gpio_ext_mic_en = -1,
283         .gpio_hp_mute = -1,
284         .gpio_codec1 = -1,
285         .gpio_codec2 = -1,
286         .gpio_codec3 = -1,
287         .i2s_param[HIFI_CODEC]       = {
288                 .audio_port_id = 1,
289                 .is_i2s_master = 0,
290                 .i2s_mode = TEGRA_DAIFMT_I2S,
291         },
292         .i2s_param[BT_SCO] = {
293                 .audio_port_id = 3,
294                 .is_i2s_master = 1,
295                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
296         },
297 };
298
299 static void ardbeg_audio_init(void)
300 {
301         struct board_info board_info;
302         tegra_get_board_info(&board_info);
303         if (board_info.board_id == BOARD_PM359 ||
304                         board_info.board_id == BOARD_PM358 ||
305                         board_info.board_id == BOARD_PM363) {
306                 /*Laguna*/
307                 ardbeg_audio_pdata_rt5645.gpio_hp_det =
308                         TEGRA_GPIO_HP_DET;
309                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high = 1;
310                 if (board_info.board_id != BOARD_PM363)
311                         ardbeg_audio_pdata_rt5645.gpio_ldo1_en = -1;
312         } else {
313                 /*Ardbeg*/
314                 ardbeg_audio_pdata_rt5645.gpio_hp_det =
315                         TEGRA_GPIO_HP_DET;
316                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high = 0;
317                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en =
318                         TEGRA_GPIO_LDO_EN;
319         }
320
321         ardbeg_audio_pdata_rt5639.gpio_hp_det =
322                 ardbeg_audio_pdata_rt5645.gpio_hp_det;
323
324         ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high =
325                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high;
326
327         ardbeg_audio_pdata_rt5639.gpio_ldo1_en =
328                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en;
329
330         ardbeg_audio_pdata_rt5639.codec_name = "rt5639.0-001c";
331         ardbeg_audio_pdata_rt5639.codec_dai_name = "rt5639-aif1";
332         ardbeg_audio_pdata_rt5645.codec_name = "rt5645.0-001a";
333         ardbeg_audio_pdata_rt5645.codec_dai_name = "rt5645-aif1";
334 }
335
336 static struct platform_device ardbeg_audio_device_rt5645 = {
337         .name = "tegra-snd-rt5645",
338         .id = 0,
339         .dev = {
340                 .platform_data = &ardbeg_audio_pdata_rt5645,
341         },
342 };
343
344 static struct platform_device ardbeg_audio_device_rt5639 = {
345         .name = "tegra-snd-rt5639",
346         .id = 0,
347         .dev = {
348                 .platform_data = &ardbeg_audio_pdata_rt5639,
349         },
350 };
351
352 static void __init ardbeg_uart_init(void)
353 {
354
355 #ifndef CONFIG_USE_OF
356         tegra_uarta_device.dev.platform_data = &ardbeg_uarta_pdata;
357         tegra_uartb_device.dev.platform_data = &ardbeg_uartb_pdata;
358         tegra_uartc_device.dev.platform_data = &ardbeg_uartc_pdata;
359         platform_add_devices(ardbeg_uart_devices,
360                         ARRAY_SIZE(ardbeg_uart_devices));
361 #endif
362         tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
363         if (!is_tegra_debug_uartport_hs()) {
364                 int debug_port_id = uart_console_debug_init(3);
365                 if (debug_port_id < 0)
366                         return;
367
368 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
369                 tegra_serial_debug_init_irq_mode(TEGRA_UARTD_BASE, INT_UARTD, NULL, -1, -1);
370 #else
371                 platform_device_register(uart_console_debug_device);
372 #endif
373         } else {
374                 tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
375                 platform_device_register(&tegra_uartd_device);
376         }
377 }
378
379 static struct resource tegra_rtc_resources[] = {
380         [0] = {
381                 .start = TEGRA_RTC_BASE,
382                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
383                 .flags = IORESOURCE_MEM,
384         },
385         [1] = {
386                 .start = INT_RTC,
387                 .end = INT_RTC,
388                 .flags = IORESOURCE_IRQ,
389         },
390 };
391
392 static struct platform_device tegra_rtc_device = {
393         .name = "tegra_rtc",
394         .id   = -1,
395         .resource = tegra_rtc_resources,
396         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
397 };
398
399 #ifdef CONFIG_SATA_AHCI_TEGRA
400 static struct tegra_ahci_platform_data tegra_ahci_platform_data0 = {
401         .gen2_rx_eq = -1,
402         .pexp_gpio = PMU_TCA6416_GPIO(9),
403 };
404
405 static void ardbeg_sata_init(void)
406 {
407         struct board_info board_info;
408
409         tegra_get_board_info(&board_info);
410         if (board_info.board_id == BOARD_PM363)
411                 tegra_ahci_platform_data0.pexp_gpio = -1;
412
413         tegra_sata_device.dev.platform_data = &tegra_ahci_platform_data0;
414         platform_device_register(&tegra_sata_device);
415 }
416 #else
417 static void ardbeg_sata_init(void) { }
418 #endif
419
420 static struct tegra_pci_platform_data laguna_pcie_platform_data = {
421         .port_status[0] = 1,
422         .port_status[1] = 1,
423         .use_dock_detect        = 1,
424         .gpio   = TEGRA_GPIO_PO1,
425         .gpio_x1_slot   = PMU_TCA6416_GPIO(8),
426         .board_id       = BOARD_PM358,
427 };
428
429 static void laguna_pcie_init(void)
430 {
431         struct board_info board_info;
432
433         tegra_get_board_info(&board_info);
434         /* root port 1(x1 slot) is supported only on of ERS-S board */
435         if (board_info.board_id == BOARD_PM358 ||
436                 board_info.board_id == BOARD_PM363)
437                         laguna_pcie_platform_data.port_status[1] = 0;
438
439         laguna_pcie_platform_data.board_id = board_info.board_id;
440         tegra_pci_device.dev.platform_data = &laguna_pcie_platform_data;
441         platform_device_register(&tegra_pci_device);
442 }
443
444 static struct platform_device *ardbeg_devices[] __initdata = {
445         &tegra_pmu_device,
446         &tegra_rtc_device,
447         &tegra_udc_device,
448 #if defined(CONFIG_TEGRA_WATCHDOG)
449         &tegra_wdt0_device,
450 #endif
451 #if defined(CONFIG_TEGRA_AVP)
452         &tegra_avp_device,
453 #endif
454 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
455         &tegra12_se_device,
456 #endif
457         &tegra_ahub_device,
458         &tegra_dam_device0,
459         &tegra_dam_device1,
460         &tegra_dam_device2,
461         &tegra_i2s_device1,
462         &tegra_i2s_device3,
463         &tegra_i2s_device4,
464         &ardbeg_audio_device_rt5639,
465         &tegra_spdif_device,
466         &spdif_dit_device,
467         &bluetooth_dit_device,
468         &tegra_hda_device,
469 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
470         &tegra_aes_device,
471 #endif
472 };
473
474 static struct tegra_usb_platform_data tegra_udc_pdata = {
475         .port_otg = true,
476         .has_hostpc = true,
477         .unaligned_dma_buf_supported = false,
478         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
479         .op_mode = TEGRA_USB_OPMODE_DEVICE,
480         .u_data.dev = {
481                 .vbus_pmu_irq = 0,
482                 .vbus_gpio = -1,
483                 .charging_supported = false,
484                 .remote_wakeup_supported = false,
485         },
486         .u_cfg.utmi = {
487                 .hssync_start_delay = 0,
488                 .elastic_limit = 16,
489                 .idle_wait_delay = 17,
490                 .term_range_adj = 6,
491                 .xcvr_setup = 8,
492                 .xcvr_lsfslew = 2,
493                 .xcvr_lsrslew = 2,
494                 .xcvr_setup_offset = 0,
495                 .xcvr_use_fuses = 1,
496         },
497 };
498
499 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
500         .port_otg = true,
501         .has_hostpc = true,
502         .unaligned_dma_buf_supported = false,
503         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
504         .op_mode = TEGRA_USB_OPMODE_HOST,
505         .u_data.host = {
506                 .vbus_gpio = -1,
507                 .hot_plug = false,
508                 .remote_wakeup_supported = true,
509                 .power_off_on_suspend = true,
510         },
511         .u_cfg.utmi = {
512                 .hssync_start_delay = 0,
513                 .elastic_limit = 16,
514                 .idle_wait_delay = 17,
515                 .term_range_adj = 6,
516                 .xcvr_setup = 15,
517                 .xcvr_lsfslew = 0,
518                 .xcvr_lsrslew = 3,
519                 .xcvr_setup_offset = 0,
520                 .xcvr_use_fuses = 1,
521                 .vbus_oc_map = 0x4,
522                 .xcvr_hsslew_lsb = 2,
523         },
524 };
525
526 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
527         .port_otg = false,
528         .has_hostpc = true,
529         .unaligned_dma_buf_supported = false,
530         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
531         .op_mode = TEGRA_USB_OPMODE_HOST,
532         .u_data.host = {
533                 .vbus_gpio = -1,
534                 .hot_plug = false,
535                 .remote_wakeup_supported = true,
536                 .power_off_on_suspend = true,
537         },
538         .u_cfg.utmi = {
539                 .hssync_start_delay = 0,
540                 .elastic_limit = 16,
541                 .idle_wait_delay = 17,
542                 .term_range_adj = 6,
543                 .xcvr_setup = 8,
544                 .xcvr_lsfslew = 2,
545                 .xcvr_lsrslew = 2,
546                 .xcvr_setup_offset = 0,
547                 .xcvr_use_fuses = 1,
548                 .vbus_oc_map = 0x5,
549         },
550 };
551
552 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
553         .port_otg = false,
554         .has_hostpc = true,
555         .unaligned_dma_buf_supported = false,
556         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
557         .op_mode = TEGRA_USB_OPMODE_HOST,
558         .u_data.host = {
559                 .vbus_gpio = -1,
560                 .hot_plug = false,
561                 .remote_wakeup_supported = true,
562                 .power_off_on_suspend = true,
563         },
564         .u_cfg.utmi = {
565         .hssync_start_delay = 0,
566                 .elastic_limit = 16,
567                 .idle_wait_delay = 17,
568                 .term_range_adj = 6,
569                 .xcvr_setup = 8,
570                 .xcvr_lsfslew = 2,
571                 .xcvr_lsrslew = 2,
572                 .xcvr_setup_offset = 0,
573                 .xcvr_use_fuses = 1,
574                 .vbus_oc_map = 0x5,
575         },
576 };
577
578 static struct gpio modem_gpios[] = { /* Bruce modem */
579         {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"},
580         {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"},
581         {MDM_SAR0, GPIOF_OUT_INIT_LOW, "MODEM SAR0"},
582 };
583
584 static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = {
585         .port_otg = false,
586         .has_hostpc = true,
587         .unaligned_dma_buf_supported = false,
588         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
589         .op_mode = TEGRA_USB_OPMODE_HOST,
590         .u_data.host = {
591                 .vbus_gpio = -1,
592                 .hot_plug = false,
593                 .remote_wakeup_supported = true,
594                 .power_off_on_suspend = true,
595         },
596 };
597
598 static struct tegra_usb_platform_data tegra_ehci2_hsic_smsc_hub_pdata = {
599         .port_otg = false,
600         .has_hostpc = true,
601         .unaligned_dma_buf_supported = false,
602         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
603         .op_mode        = TEGRA_USB_OPMODE_HOST,
604         .u_data.host = {
605                 .vbus_gpio = -1,
606                 .hot_plug = false,
607                 .remote_wakeup_supported = true,
608                 .power_off_on_suspend = true,
609         },
610 };
611
612
613 static struct tegra_usb_otg_data tegra_otg_pdata = {
614         .ehci_device = &tegra_ehci1_device,
615         .ehci_pdata = &tegra_ehci1_utmi_pdata,
616 };
617
618 static void ardbeg_usb_init(void)
619 {
620         int usb_port_owner_info = tegra_get_usb_port_owner_info();
621         int modem_id = tegra_get_modem_id();
622         struct board_info bi;
623
624         if (board_info.board_id == BOARD_PM359 ||
625                         board_info.board_id == BOARD_PM358 ||
626                         board_info.board_id == BOARD_PM363) {
627                 /* Laguna */
628                 /* Host cable is detected through AMS PMU Interrupt */
629                 tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
630                 tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
631                 tegra_otg_pdata.id_extcon_dev_name = "as3722-extcon";
632         } else {
633                 /* Ardbeg */
634                 tegra_get_pmu_board_info(&bi);
635
636                 switch (bi.board_id) {
637                 case BOARD_E1733:
638                         /* Host cable is detected through PMU Interrupt */
639                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
640                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
641                         tegra_otg_pdata.id_extcon_dev_name = "as3722-extcon";
642                         break;
643                 case BOARD_E1736:
644                 case BOARD_E1769:
645                 case BOARD_E1735:
646                         /* Device cable is detected through PMU Interrupt */
647                         tegra_udc_pdata.support_pmu_vbus = true;
648                         tegra_ehci1_utmi_pdata.support_pmu_vbus = true;
649                         tegra_otg_pdata.vbus_extcon_dev_name = "palmas-extcon";
650                         /* Host cable is detected through PMU Interrupt */
651                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
652                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
653                         tegra_otg_pdata.id_extcon_dev_name = "palmas-extcon";
654                 }
655         }
656
657         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
658                 tegra_otg_pdata.is_xhci = false;
659                 tegra_udc_pdata.u_data.dev.is_xhci = false;
660         } else {
661                 tegra_otg_pdata.is_xhci = true;
662                 tegra_udc_pdata.u_data.dev.is_xhci = true;
663         }
664         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
665         platform_device_register(&tegra_otg_device);
666         /* Setup the udc platform data */
667         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
668
669         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
670                 if (!modem_id) {
671                         tegra_ehci2_device.dev.platform_data =
672                                 &tegra_ehci2_utmi_pdata;
673                         platform_device_register(&tegra_ehci2_device);
674                 }
675         }
676         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
677                 tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
678                 platform_device_register(&tegra_ehci3_device);
679         }
680 }
681
682 static struct tegra_xusb_board_data xusb_bdata = {
683         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_SS_P1 |
684                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_USB2_P2,
685         .supply = {
686                 .utmi_vbuses = {
687                         "usb_vbus0", "usb_vbus1", "usb_vbus2"
688                 },
689                 .s3p3v = "hvdd_usb",
690                 .s1p8v = "avdd_pll_utmip",
691                 .vddio_hsic = "vddio_hsic",
692                 .s1p05v = "avddio_usb",
693         },
694
695         .hsic[0] = {
696                 .rx_strobe_trim = 0x1,
697                 .rx_data_trim = 0x1,
698                 .tx_rtune_n = 0x8,
699                 .tx_rtune_p = 0xa,
700                 .tx_slew_n = 0,
701                 .tx_slew_p = 0,
702                 .auto_term_en = true,
703                 .strb_trim_val = 0x22,
704                 .pretend_connect = false,
705         },
706         .uses_external_pmic = false,
707 };
708
709 static void ardbeg_xusb_init(void)
710 {
711         int usb_port_owner_info = tegra_get_usb_port_owner_info();
712
713         xusb_bdata.lane_owner = (u8) tegra_get_lane_owner_info();
714
715         if (board_info.board_id == BOARD_PM359 ||
716                         board_info.board_id == BOARD_PM358 ||
717                         board_info.board_id == BOARD_PM363) {
718                 /* Laguna */
719                 pr_info("Laguna ERS. 0x%x\n", board_info.board_id);
720                 xusb_bdata.gpio_controls_muxed_ss_lanes = true;
721                 /* D[0:15] = gpio number and D[16:31] = output value */
722                 xusb_bdata.gpio_ss1_sata = PMU_TCA6416_GPIO(9) | (0 << 16);
723                 xusb_bdata.ss_portmap = (TEGRA_XUSB_SS_PORT_MAP_USB2_P0 << 0) |
724                         (TEGRA_XUSB_SS_PORT_MAP_USB2_P1 << 4);
725
726                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
727                         xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
728                                 TEGRA_XUSB_SS_P0);
729
730                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
731                         xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
732                                 TEGRA_XUSB_SS_P1 | TEGRA_XUSB_USB2_P2);
733
734                 /* FIXME Add for UTMIP2 when have odmdata assigend */
735         } else {
736                 /* Ardbeg */
737                 xusb_bdata.gpio_controls_muxed_ss_lanes = false;
738
739                 if (board_info.board_id == BOARD_E1781) {
740                         pr_info("Shield ERS-S. 0x%x\n", board_info.board_id);
741                         /* Shield ERS-S */
742                         xusb_bdata.ss_portmap =
743                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P1 << 0) |
744                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P2 << 4);
745
746                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
747                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
748
749                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
750                                 xusb_bdata.portmap &= ~(
751                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0 |
752                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
753                 } else {
754                         pr_info("Shield ERS 0x%x\n", board_info.board_id);
755                         /* Shield ERS */
756                         xusb_bdata.ss_portmap =
757                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P0 << 0) |
758                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P2 << 4);
759
760                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
761                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
762                                         TEGRA_XUSB_SS_P0);
763
764                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
765                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
766                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
767                 }
768                 /* FIXME Add for UTMIP2 when have odmdata assigend */
769         }
770
771         if (usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)
772                 xusb_bdata.portmap |= TEGRA_XUSB_HSIC_P0;
773
774         if (usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)
775                 xusb_bdata.portmap |= TEGRA_XUSB_HSIC_P1;
776
777         if (xusb_bdata.portmap)
778                 tegra_xusb_init(&xusb_bdata);
779 }
780
781 static int baseband_init(void)
782 {
783         int ret;
784
785         ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios));
786         if (ret) {
787                 pr_warn("%s:gpio request failed\n", __func__);
788                 return ret;
789         }
790
791         /* enable pull-down for MDM_COLD_BOOT */
792         tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4,
793                                     TEGRA_PUPD_PULL_DOWN);
794
795         /* export GPIO for user space access through sysfs */
796         gpio_export(MDM_RST, false);
797         gpio_export(MDM_SAR0, false);
798
799         return 0;
800 }
801
802 static const struct tegra_modem_operations baseband_operations = {
803         .init = baseband_init,
804 };
805
806 static struct tegra_usb_modem_power_platform_data baseband_pdata = {
807         .ops = &baseband_operations,
808         .regulator_name = "vdd_wwan_mdm",
809         .wake_gpio = -1,
810         .boot_gpio = MDM_COLDBOOT,
811         .boot_irq_flags = IRQF_TRIGGER_RISING |
812                                     IRQF_TRIGGER_FALLING |
813                                     IRQF_ONESHOT,
814         .autosuspend_delay = 2000,
815         .short_autosuspend_delay = 50,
816         .tegra_ehci_device = &tegra_ehci2_device,
817         .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata,
818 };
819
820 static struct platform_device icera_bruce_device = {
821         .name = "tegra_usb_modem_power",
822         .id = -1,
823         .dev = {
824                 .platform_data = &baseband_pdata,
825         },
826 };
827
828 static void ardbeg_modem_init(void)
829 {
830         int modem_id = tegra_get_modem_id();
831         struct board_info board_info;
832         struct board_info pmu_board_info;
833         int usb_port_owner_info = tegra_get_usb_port_owner_info();
834
835         tegra_get_board_info(&board_info);
836         tegra_get_pmu_board_info(&pmu_board_info);
837         pr_info("%s: modem_id = %d\n", __func__, modem_id);
838
839         switch (modem_id) {
840         case TEGRA_BB_BRUCE:
841                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
842                         /* Set specific USB wake source for Ardbeg */
843                         if (board_info.board_id == BOARD_E1780)
844                                 tegra_set_wake_source(42, INT_USB2);
845                         if (pmu_board_info.board_id == BOARD_E1736 ||
846                                 pmu_board_info.board_id == BOARD_E1769)
847                                 baseband_pdata.regulator_name = NULL;
848                         platform_device_register(&icera_bruce_device);
849                 }
850                 break;
851         case TEGRA_BB_HSIC_HUB: /* HSIC hub */
852                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
853                         tegra_ehci2_device.dev.platform_data =
854                                 &tegra_ehci2_hsic_smsc_hub_pdata;
855                         /* Set specific USB wake source for Ardbeg */
856                         if (board_info.board_id == BOARD_E1780)
857                                 tegra_set_wake_source(42, INT_USB2);
858                         platform_device_register(&tegra_ehci2_device);
859                 } else
860                         xusb_bdata.hsic[0].pretend_connect = true;
861                 break;
862         default:
863                 return;
864         }
865 }
866
867 #ifndef CONFIG_USE_OF
868 static struct platform_device *ardbeg_spi_devices[] __initdata = {
869         &tegra11_spi_device1,
870         &tegra11_spi_device4,
871 };
872
873 static struct tegra_spi_platform_data ardbeg_spi1_pdata = {
874         .dma_req_sel            = 15,
875         .spi_max_frequency      = 25000000,
876         .clock_always_on        = false,
877 };
878
879 static struct tegra_spi_platform_data ardbeg_spi4_pdata = {
880         .dma_req_sel            = 18,
881         .spi_max_frequency      = 25000000,
882         .clock_always_on        = false,
883 };
884
885 static void __init ardbeg_spi_init(void)
886 {
887         tegra11_spi_device1.dev.platform_data = &ardbeg_spi1_pdata;
888         tegra11_spi_device4.dev.platform_data = &ardbeg_spi4_pdata;
889         platform_add_devices(ardbeg_spi_devices,
890                         ARRAY_SIZE(ardbeg_spi_devices));
891 }
892 #else
893 static void __init ardbeg_spi_init(void)
894 {
895 }
896 #endif
897
898 #ifdef CONFIG_USE_OF
899 static struct of_dev_auxdata ardbeg_auxdata_lookup[] __initdata = {
900         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d400, "spi-tegra114.0",
901                                 NULL),
902         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d600, "spi-tegra114.1",
903                                 NULL),
904         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d800, "spi-tegra114.2",
905                                 NULL),
906         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000da00, "spi-tegra114.3",
907                                 NULL),
908         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000dc00, "spi-tegra114.4",
909                                 NULL),
910         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000de00, "spi-tegra114.5",
911                                 NULL),
912         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
913                                 NULL),
914         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
915                 NULL),
916         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", 0x538F0000, "gk20a", NULL),
917 #ifdef CONFIG_ARCH_TEGRA_VIC
918         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03", NULL),
919 #endif
920         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
921                 NULL),
922         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi", NULL),
923         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp", NULL),
924         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
925         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0",
926                                 NULL),
927         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1",
928                                 NULL),
929         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2",
930                                 NULL),
931         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c000, "tegra12-i2c.0",
932                                 NULL),
933         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c400, "tegra12-i2c.1",
934                                 NULL),
935         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c500, "tegra12-i2c.2",
936                                 NULL),
937         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c700, "tegra12-i2c.3",
938                                 NULL),
939         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000d000, "tegra12-i2c.4",
940                                 NULL),
941         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000d100, "tegra12-i2c.5",
942                                 NULL),
943         OF_DEV_AUXDATA("nvidia,tegra124-pwm", TEGRA_PWFM_BASE, "tegra-pwm",
944                                 NULL),
945         OF_DEV_AUXDATA("pwm-backlight", NULL, "pwm-backlight",
946                                 NULL),
947         {}
948 };
949 #endif
950
951 struct maxim_sti_pdata maxim_sti_pdata = {
952         .touch_fusion         = "/vendor/bin/touch_fusion",
953         .config_file          = "/vendor/firmware/touch_fusion.cfg",
954         .fw_name              = "maxim_fp35.bin",
955         .nl_family            = TF_FAMILY_NAME,
956         .nl_mc_groups         = 5,
957         .chip_access_method   = 2,
958         .default_reset_state  = 0,
959         .tx_buf_size          = 4100,
960         .rx_buf_size          = 4100,
961         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
962         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
963 };
964
965 static struct tegra_spi_device_controller_data maxim_dev_cdata = {
966         .rx_clk_tap_delay = 0,
967         .is_hw_based_cs = true,
968         .tx_clk_tap_delay = 0,
969 };
970
971 struct spi_board_info maxim_sti_spi_board = {
972         .modalias = MAXIM_STI_NAME,
973         .bus_num = TOUCH_SPI_ID,
974         .chip_select = TOUCH_SPI_CS,
975         .max_speed_hz = 12 * 1000 * 1000,
976         .mode = SPI_MODE_0,
977         .platform_data = &maxim_sti_pdata,
978         .controller_data = &maxim_dev_cdata,
979 };
980
981 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
982         /* name         parent          rate            enabled */
983         { "extern2",    "pll_p",        41000000,       false},
984         { "clk_out_2",  "extern2",      40800000,       false},
985         { NULL,         NULL,           0,              0},
986 };
987
988 static struct rm_spi_ts_platform_data rm31080ts_ardbeg_data = {
989         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
990         .config = 0,
991         .platform_id = RM_PLATFORM_A010,
992         .name_of_clock = "clk_out_2",
993         .name_of_clock_con = "extern2",
994 };
995
996 static struct tegra_spi_device_controller_data dev_cdata = {
997         .rx_clk_tap_delay = 0,
998         .tx_clk_tap_delay = 16,
999 };
1000
1001 static struct spi_board_info rm31080a_ardbeg_spi_board[1] = {
1002         {
1003                 .modalias = "rm_ts_spidev",
1004                 .bus_num = TOUCH_SPI_ID,
1005                 .chip_select = TOUCH_SPI_CS,
1006                 .max_speed_hz = 12 * 1000 * 1000,
1007                 .mode = SPI_MODE_0,
1008                 .controller_data = &dev_cdata,
1009                 .platform_data = &rm31080ts_ardbeg_data,
1010         },
1011 };
1012
1013 static int __init ardbeg_touch_init(void)
1014 {
1015         if (tegra_get_touch_vendor_id() == MAXIM_TOUCH) {
1016                 pr_info("%s init maxim touch\n", __func__);
1017 #if defined(CONFIG_TOUCHSCREEN_MAXIM_STI) || \
1018         defined(CONFIG_TOUCHSCREEN_MAXIM_STI_MODULE)
1019                 (void)touch_init_maxim_sti(&maxim_sti_spi_board);
1020 #endif
1021         } else if (tegra_get_touch_vendor_id() == RAYDIUM_TOUCH) {
1022                 pr_info("%s init raydium touch\n", __func__);
1023                 tegra_clk_init_from_table(touch_clk_init_table);
1024                 rm31080a_ardbeg_spi_board[0].irq =
1025                         gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1026                 touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1027                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
1028                                 &rm31080ts_ardbeg_data,
1029                                 &rm31080a_ardbeg_spi_board[0],
1030                                 ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1031         }
1032         return 0;
1033 }
1034
1035 static void __init ardbeg_sysedp_init(void)
1036 {
1037         struct board_info bi;
1038
1039         tegra_get_board_info(&bi);
1040
1041         switch (bi.board_id) {
1042         case BOARD_E1780:
1043                 if (bi.sku == 1100) {
1044                         tn8_new_sysedp_init();
1045                 }
1046                 break;
1047         case BOARD_PM358:
1048         case BOARD_PM359:
1049         default:
1050                 break;
1051         }
1052 }
1053
1054 static void __init ardbeg_sysedp_dynamic_capping_init(void)
1055 {
1056         struct board_info bi;
1057
1058         tegra_get_board_info(&bi);
1059
1060         switch (bi.board_id) {
1061         case BOARD_E1780:
1062                 if (bi.sku == 1100)
1063                         tn8_sysedp_dynamic_capping_init();
1064                 break;
1065         case BOARD_PM358:
1066         case BOARD_PM359:
1067         default:
1068                 break;
1069         }
1070 }
1071
1072 static void __init ardbeg_sysedp_batmon_init(void)
1073 {
1074         struct board_info bi;
1075
1076         if (!IS_ENABLED(CONFIG_SYSEDP_FRAMEWORK))
1077                 return;
1078
1079         tegra_get_board_info(&bi);
1080
1081         switch (bi.board_id) {
1082         case BOARD_E1780:
1083                 if (bi.sku == 1100)
1084                         tn8_sysedp_batmon_init();
1085                 break;
1086         case BOARD_PM358:
1087         case BOARD_PM359:
1088         default:
1089                 break;
1090         }
1091 }
1092
1093
1094
1095 static void __init edp_init(void)
1096 {
1097         struct board_info bi;
1098
1099         tegra_get_board_info(&bi);
1100
1101         switch (bi.board_id) {
1102         case BOARD_E1780:
1103                 if (bi.sku == 1100)
1104                         tn8_edp_init();
1105                 else
1106                         ardbeg_edp_init();
1107                 break;
1108         case BOARD_PM358:
1109         case BOARD_PM359:
1110                         laguna_edp_init();
1111                         break;
1112         default:
1113                         ardbeg_edp_init();
1114                         break;
1115         }
1116 }
1117
1118 static void __init tegra_ardbeg_early_init(void)
1119 {
1120         ardbeg_sysedp_init();
1121         tegra_clk_init_from_table(ardbeg_clk_init_table);
1122         tegra_clk_verify_parents();
1123         if (of_machine_is_compatible("nvidia,laguna"))
1124                 tegra_soc_device_init("laguna");
1125         else if (of_machine_is_compatible("nvidia,tn8"))
1126                 tegra_soc_device_init("tn8");
1127         else
1128                 tegra_soc_device_init("ardbeg");
1129 }
1130
1131 static struct tegra_dtv_platform_data ardbeg_dtv_pdata = {
1132         .dma_req_selector = 11,
1133 };
1134
1135 static void __init ardbeg_dtv_init(void)
1136 {
1137         tegra_dtv_device.dev.platform_data = &ardbeg_dtv_pdata;
1138         platform_device_register(&tegra_dtv_device);
1139 }
1140
1141 static struct tegra_io_dpd pexbias_io = {
1142         .name                   = "PEX_BIAS",
1143         .io_dpd_reg_index       = 0,
1144         .io_dpd_bit             = 4,
1145 };
1146 static struct tegra_io_dpd pexclk1_io = {
1147         .name                   = "PEX_CLK1",
1148         .io_dpd_reg_index       = 0,
1149         .io_dpd_bit             = 5,
1150 };
1151 static struct tegra_io_dpd pexclk2_io = {
1152         .name                   = "PEX_CLK2",
1153         .io_dpd_reg_index       = 0,
1154         .io_dpd_bit             = 6,
1155 };
1156
1157 static void __init tegra_ardbeg_late_init(void)
1158 {
1159         struct board_info board_info;
1160         tegra_get_board_info(&board_info);
1161         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1162                 board_info.board_id, board_info.sku,
1163                 board_info.fab, board_info.major_revision,
1164                 board_info.minor_revision);
1165         platform_device_register(&tegra_pinmux_device);
1166         if (board_info.board_id == BOARD_PM359 ||
1167                         board_info.board_id == BOARD_PM358 ||
1168                         board_info.board_id == BOARD_PM363)
1169                 laguna_pinmux_init();
1170         else
1171                 ardbeg_pinmux_init();
1172
1173         ardbeg_uart_init();
1174         ardbeg_usb_init();
1175         ardbeg_modem_init();
1176         ardbeg_xusb_init();
1177         ardbeg_i2c_init();
1178         ardbeg_spi_init();
1179         ardbeg_audio_init();
1180         platform_add_devices(ardbeg_devices, ARRAY_SIZE(ardbeg_devices));
1181         //tegra_ram_console_debug_init();
1182         tegra_io_dpd_init();
1183         ardbeg_sdhci_init();
1184         if (board_info.board_id == BOARD_PM359 ||
1185                         board_info.board_id == BOARD_PM358 ||
1186                         board_info.board_id == BOARD_PM363)
1187                 laguna_regulator_init();
1188         else
1189                 ardbeg_regulator_init();
1190         ardbeg_dtv_init();
1191         ardbeg_suspend_init();
1192 /* TODO: add support for laguna board when dvfs table is ready */
1193         if ((board_info.board_id == BOARD_E1780 &&
1194                 (tegra_get_memory_type() == 0)) ||
1195                 (board_info.board_id == BOARD_E1792))
1196                 ardbeg_emc_init();
1197
1198         edp_init();
1199         isomgr_init();
1200         ardbeg_touch_init();
1201         ardbeg_panel_init();
1202         ardbeg_kbc_init();
1203         if (board_info.board_id == BOARD_PM358)
1204                 laguna_pm358_pmon_init();
1205         else
1206                 ardbeg_pmon_init();
1207         if (board_info.board_id == BOARD_PM359 ||
1208                         board_info.board_id == BOARD_PM358 ||
1209                         board_info.board_id == BOARD_PM363)
1210                 laguna_pcie_init();
1211         else {
1212                 /* put PEX pads into DPD mode to save additional power */
1213                 tegra_io_dpd_enable(&pexbias_io);
1214                 tegra_io_dpd_enable(&pexclk1_io);
1215                 tegra_io_dpd_enable(&pexclk2_io);
1216         }
1217
1218 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1219         tegra_wdt_recovery_init();
1220 #endif
1221
1222         ardbeg_sensors_init();
1223
1224         ardbeg_soctherm_init();
1225
1226         ardbeg_setup_bluedroid_pm();
1227         tegra_register_fuse();
1228
1229         ardbeg_sysedp_dynamic_capping_init();
1230         ardbeg_sysedp_batmon_init();
1231 }
1232
1233 static void __init ardbeg_ramconsole_reserve(unsigned long size)
1234 {
1235         tegra_ram_console_debug_reserve(SZ_1M);
1236 }
1237
1238 static void __init tegra_ardbeg_init_early(void)
1239 {
1240         ardbeg_rail_alignment_init();
1241         tegra12x_init_early();
1242 }
1243
1244 static void __init tegra_ardbeg_dt_init(void)
1245 {
1246         tegra_get_board_info(&board_info);
1247         tegra_get_display_board_info(&display_board_info);
1248
1249         tegra_ardbeg_early_init();
1250 #ifdef CONFIG_USE_OF
1251         of_platform_populate(NULL,
1252                 of_default_bus_match_table, ardbeg_auxdata_lookup,
1253                 &platform_bus);
1254 #endif
1255
1256         tegra_ardbeg_late_init();
1257 }
1258
1259 static void __init tegra_ardbeg_reserve(void)
1260 {
1261 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) || \
1262                 defined(CONFIG_TEGRA_NO_CARVEOUT)
1263         /* 1920*1200*4*2 = 18432000 bytes */
1264         tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
1265 #else
1266         tegra_reserve(SZ_1G, SZ_16M + SZ_2M, SZ_4M);
1267 #endif
1268         ardbeg_ramconsole_reserve(SZ_1M);
1269 }
1270
1271 static const char * const ardbeg_dt_board_compat[] = {
1272         "nvidia,ardbeg",
1273         NULL
1274 };
1275
1276 static const char * const laguna_dt_board_compat[] = {
1277         "nvidia,laguna",
1278         NULL
1279 };
1280
1281 static const char * const tn8_dt_board_compat[] = {
1282         "nvidia,tn8",
1283         NULL
1284 };
1285
1286 DT_MACHINE_START(LAGUNA, "laguna")
1287         .atag_offset    = 0x100,
1288         .smp            = smp_ops(tegra_smp_ops),
1289         .map_io         = tegra_map_common_io,
1290         .reserve        = tegra_ardbeg_reserve,
1291         .init_early     = tegra_ardbeg_init_early,
1292         .init_irq       = irqchip_init,
1293         .init_time      = clocksource_of_init,
1294         .init_machine   = tegra_ardbeg_dt_init,
1295         .restart        = tegra_assert_system_reset,
1296         .dt_compat      = laguna_dt_board_compat,
1297         .init_late      = tegra_init_late
1298 MACHINE_END
1299
1300 DT_MACHINE_START(TN8, "tn8")
1301         .atag_offset    = 0x100,
1302         .smp            = smp_ops(tegra_smp_ops),
1303         .map_io         = tegra_map_common_io,
1304         .reserve        = tegra_ardbeg_reserve,
1305         .init_early     = tegra_ardbeg_init_early,
1306         .init_irq       = irqchip_init,
1307         .init_time      = clocksource_of_init,
1308         .init_machine   = tegra_ardbeg_dt_init,
1309         .restart        = tegra_assert_system_reset,
1310         .dt_compat      = tn8_dt_board_compat,
1311         .init_late      = tegra_init_late
1312 MACHINE_END
1313
1314 DT_MACHINE_START(ARDBEG, "ardbeg")
1315         .atag_offset    = 0x100,
1316         .smp            = smp_ops(tegra_smp_ops),
1317         .map_io         = tegra_map_common_io,
1318         .reserve        = tegra_ardbeg_reserve,
1319         .init_early     = tegra_ardbeg_init_early,
1320         .init_irq       = irqchip_init,
1321         .init_time      = clocksource_of_init,
1322         .init_machine   = tegra_ardbeg_dt_init,
1323         .restart        = tegra_assert_system_reset,
1324         .dt_compat      = ardbeg_dt_board_compat,
1325         .init_late      = tegra_init_late
1326 MACHINE_END