36e9c59d11010e7ce69af626201eff8abb7fb35e
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg.c
3  *
4  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c.h>
28 #include <linux/i2c/i2c-hid.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/delay.h>
31 #include <linux/i2c-tegra.h>
32 #include <linux/gpio.h>
33 #include <linux/input.h>
34 #include <linux/platform_data/tegra_usb.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/rm31080a_ts.h>
37 #include <linux/maxim_sti.h>
38 #include <linux/memblock.h>
39 #include <linux/spi/spi-tegra.h>
40 #include <linux/nfc/pn544.h>
41 #include <linux/rfkill-gpio.h>
42 #include <linux/skbuff.h>
43 #include <linux/ti_wilink_st.h>
44 #include <linux/regulator/consumer.h>
45 #include <linux/smb349-charger.h>
46 #include <linux/max17048_battery.h>
47 #include <linux/leds.h>
48 #include <linux/i2c/at24.h>
49 #include <linux/of_platform.h>
50 #include <linux/i2c.h>
51 #include <linux/i2c-tegra.h>
52 #include <linux/platform_data/serial-tegra.h>
53 #include <linux/edp.h>
54 #include <linux/usb/tegra_usb_phy.h>
55 #include <linux/mfd/palmas.h>
56 #include <linux/clk/tegra.h>
57 #include <media/tegra_dtv.h>
58 #include <linux/clocksource.h>
59 #include <linux/irqchip.h>
60 #include <linux/irqchip/tegra.h>
61 #include <linux/pci-tegra.h>
62 #include <linux/tegra-soc.h>
63 #include <sound/max98090.h>
64 #include <linux/tegra_fiq_debugger.h>
65 #include <linux/platform_data/tegra_usb_modem_power.h>
66 #include <linux/platform_data/tegra_ahci.h>
67 #include <linux/irqchip/tegra.h>
68 #include <linux/i2c/pca954x.h>
69
70 #include <mach/irqs.h>
71 #include <mach/pinmux.h>
72 #include <mach/pinmux-t12.h>
73 #include <mach/io_dpd.h>
74 #include <mach/i2s.h>
75 #include <mach/isomgr.h>
76 #include <mach/tegra_asoc_pdata.h>
77 #include <mach/dc.h>
78 #include <mach/tegra_usb_pad_ctrl.h>
79
80 #include <asm/mach-types.h>
81 #include <asm/mach/arch.h>
82 #include <mach/gpio-tegra.h>
83 #include <mach/xusb.h>
84
85 #include "board.h"
86 #include "board-ardbeg.h"
87 #include "board-common.h"
88 #include "board-touch-raydium.h"
89 #include "board-touch-maxim_sti.h"
90 #include "clock.h"
91 #include "common.h"
92 #include "devices.h"
93 #include "gpio-names.h"
94 #include "iomap.h"
95 #include "pm.h"
96 #include "tegra-board-id.h"
97 #include "tegra-of-dev-auxdata.h"
98
99 static struct board_info board_info, display_board_info;
100
101 static struct resource ardbeg_bluedroid_pm_resources[] = {
102         [0] = {
103                 .name   = "shutdown_gpio",
104                 .start  = TEGRA_GPIO_PR1,
105                 .end    = TEGRA_GPIO_PR1,
106                 .flags  = IORESOURCE_IO,
107         },
108         [1] = {
109                 .name = "host_wake",
110                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
111         },
112         [2] = {
113                 .name = "gpio_ext_wake",
114                 .start  = TEGRA_GPIO_PEE1,
115                 .end    = TEGRA_GPIO_PEE1,
116                 .flags  = IORESOURCE_IO,
117         },
118         [3] = {
119                 .name = "gpio_host_wake",
120                 .start  = TEGRA_GPIO_PU6,
121                 .end    = TEGRA_GPIO_PU6,
122                 .flags  = IORESOURCE_IO,
123         },
124         [4] = {
125                 .name = "reset_gpio",
126                 .start  = TEGRA_GPIO_PX1,
127                 .end    = TEGRA_GPIO_PX1,
128                 .flags  = IORESOURCE_IO,
129         },
130 };
131
132 static struct platform_device ardbeg_bluedroid_pm_device = {
133         .name = "bluedroid_pm",
134         .id             = 0,
135         .num_resources  = ARRAY_SIZE(ardbeg_bluedroid_pm_resources),
136         .resource       = ardbeg_bluedroid_pm_resources,
137 };
138
139 static noinline void __init ardbeg_setup_bluedroid_pm(void)
140 {
141         ardbeg_bluedroid_pm_resources[1].start =
142                 ardbeg_bluedroid_pm_resources[1].end =
143                                 gpio_to_irq(TEGRA_GPIO_PU6);
144         platform_device_register(&ardbeg_bluedroid_pm_device);
145 }
146
147 static struct i2c_board_info __initdata rt5639_board_info = {
148         I2C_BOARD_INFO("rt5639", 0x1c),
149 };
150
151 static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
152         /* name         parent          rate            enabled */
153         { "pll_m",      NULL,           0,              false},
154         { "hda",        "pll_p",        108000000,      false},
155         { "hda2codec_2x", "pll_p",      48000000,       false},
156         { "pwm",        "pll_p",        3187500,        false},
157         { "i2s1",       "pll_a_out0",   0,              false},
158         { "i2s3",       "pll_a_out0",   0,              false},
159         { "i2s4",       "pll_a_out0",   0,              false},
160         { "spdif_out",  "pll_a_out0",   0,              false},
161         { "d_audio",    "clk_m",        12000000,       false},
162         { "dam0",       "clk_m",        12000000,       false},
163         { "dam1",       "clk_m",        12000000,       false},
164         { "dam2",       "clk_m",        12000000,       false},
165         { "audio1",     "i2s1_sync",    0,              false},
166         { "audio3",     "i2s3_sync",    0,              false},
167         { "vi_sensor",  "pll_p",        150000000,      false},
168         { "vi_sensor2", "pll_p",        150000000,      false},
169         { "cilab",      "pll_p",        150000000,      false},
170         { "cilcd",      "pll_p",        150000000,      false},
171         { "cile",       "pll_p",        150000000,      false},
172         { "i2c1",       "pll_p",        3200000,        false},
173         { "i2c2",       "pll_p",        3200000,        false},
174         { "i2c3",       "pll_p",        3200000,        false},
175         { "i2c4",       "pll_p",        3200000,        false},
176         { "i2c5",       "pll_p",        3200000,        false},
177         { "sbc1",       "pll_p",        25000000,       false},
178         { "sbc2",       "pll_p",        25000000,       false},
179         { "sbc3",       "pll_p",        25000000,       false},
180         { "sbc4",       "pll_p",        25000000,       false},
181         { "sbc5",       "pll_p",        25000000,       false},
182         { "sbc6",       "pll_p",        25000000,       false},
183         { "uarta",      "pll_p",        408000000,      false},
184         { "uartb",      "pll_p",        408000000,      false},
185         { "uartc",      "pll_p",        408000000,      false},
186         { "uartd",      "pll_p",        408000000,      false},
187         { NULL,         NULL,           0,              0},
188 };
189
190 static struct pca954x_platform_mode ardbeg_pca954x_modes[] = {
191         { .adap_id = PCA954x_I2C_BUS0, .deselect_on_exit = true, },
192         { .adap_id = PCA954x_I2C_BUS1, .deselect_on_exit = true, },
193         { .adap_id = PCA954x_I2C_BUS2, .deselect_on_exit = true, },
194         { .adap_id = PCA954x_I2C_BUS3, .deselect_on_exit = true, },
195 };
196
197 static struct pca954x_platform_data ardbeg_pca954x_data = {
198         .modes    = ardbeg_pca954x_modes,
199         .num_modes      = ARRAY_SIZE(ardbeg_pca954x_modes),
200 };
201
202 static const struct i2c_board_info laguna_erss_i2c1_board_info[] = {
203         {
204                 I2C_BOARD_INFO("pca9546", 0x70),
205                 .platform_data = &ardbeg_pca954x_data,
206         },
207 };
208
209 static struct i2c_hid_platform_data i2c_keyboard_pdata = {
210         .hid_descriptor_address = 0x0,
211 };
212
213 /* addresses on i2c1_0 max98090 */
214 enum {
215         LAGUNA_ERSS_MAX_I2C_1_0_ADDR_10,
216 };
217
218 /* addresses on i2c1_1 max98090 */
219 enum {
220         LAGUNA_ERSS_MAX_I2C_1_1_ADDR_10,
221 };
222
223 /* addresses on i2c1_2 max98090 */
224 enum {
225         LAGUNA_ERSS_MAX_I2C_1_2_ADDR_10,
226 };
227
228 /* addresses on i2c1_3 max98090 */
229 enum {
230         LAGUNA_ERSS_MAX_I2C_1_3_ADDR_10,
231 };
232
233 static struct max98090_pdata laguna_max98090_pdata = {
234         /* Microphone Configuration */
235         .digmic_left_mode = 1,
236         .digmic_right_mode = 1,
237 };
238
239 static struct i2c_board_info laguna_i2c1_0_max98090_board_info[] = {
240         [LAGUNA_ERSS_MAX_I2C_1_0_ADDR_10] = {
241                 I2C_BOARD_INFO("max98090", 0x10),
242                 .platform_data  = &laguna_max98090_pdata,
243         },
244 };
245 static struct i2c_board_info laguna_i2c1_1_max98090_board_info[] = {
246         [LAGUNA_ERSS_MAX_I2C_1_1_ADDR_10] = {
247                 I2C_BOARD_INFO("max98090", 0x10),
248                 .platform_data  = &laguna_max98090_pdata,
249         },
250 };
251 static struct i2c_board_info laguna_i2c1_2_max98090_board_info[] = {
252         [LAGUNA_ERSS_MAX_I2C_1_2_ADDR_10] = {
253                 I2C_BOARD_INFO("max98090", 0x10),
254                 .platform_data  = &laguna_max98090_pdata,
255         },
256 };
257 static struct i2c_board_info laguna_i2c1_3_max98090_board_info[] = {
258         [LAGUNA_ERSS_MAX_I2C_1_3_ADDR_10] = {
259                 I2C_BOARD_INFO("max98090", 0x10),
260                 .platform_data  = &laguna_max98090_pdata,
261         },
262 };
263
264 static void laguna_register_max98090(void)
265 {
266         laguna_max98090_pdata.irq = gpio_to_irq(TEGRA_GPIO_PH4);
267
268         i2c_register_board_info(PCA954x_I2C_BUS0,
269                         laguna_i2c1_0_max98090_board_info,
270                         ARRAY_SIZE(laguna_i2c1_0_max98090_board_info));
271         i2c_register_board_info(PCA954x_I2C_BUS1,
272                         laguna_i2c1_1_max98090_board_info,
273                         ARRAY_SIZE(laguna_i2c1_1_max98090_board_info));
274         i2c_register_board_info(PCA954x_I2C_BUS2,
275                         laguna_i2c1_2_max98090_board_info,
276                         ARRAY_SIZE(laguna_i2c1_2_max98090_board_info));
277         i2c_register_board_info(PCA954x_I2C_BUS3,
278                         laguna_i2c1_3_max98090_board_info,
279                         ARRAY_SIZE(laguna_i2c1_3_max98090_board_info));
280 }
281
282 static struct i2c_board_info __initdata i2c_keyboard_board_info = {
283         I2C_BOARD_INFO("hid", 0x3B),
284         .platform_data  = &i2c_keyboard_pdata,
285 };
286
287 static struct i2c_hid_platform_data i2c_touchpad_pdata = {
288         .hid_descriptor_address = 0x20,
289 };
290
291 static struct i2c_board_info __initdata i2c_touchpad_board_info = {
292         I2C_BOARD_INFO("hid", 0x2C),
293         .platform_data  = &i2c_touchpad_pdata,
294 };
295
296 static void ardbeg_i2c_init(void)
297 {
298         struct board_info board_info;
299         tegra_get_board_info(&board_info);
300
301         if (board_info.board_id != BOARD_PM359)
302                 i2c_register_board_info(0, &rt5639_board_info, 1);
303
304         if (board_info.board_id == BOARD_PM359 ||
305                         board_info.board_id == BOARD_PM358 ||
306                         board_info.board_id == BOARD_PM363) {
307                 i2c_keyboard_board_info.irq = gpio_to_irq(I2C_KB_IRQ);
308                 i2c_register_board_info(1, &i2c_keyboard_board_info , 1);
309
310                 i2c_touchpad_board_info.irq = gpio_to_irq(I2C_TP_IRQ);
311                 i2c_register_board_info(1, &i2c_touchpad_board_info , 1);
312         }
313
314         if (board_info.board_id == BOARD_PM359)
315                 i2c_register_board_info(0, laguna_erss_i2c1_board_info,
316                                 ARRAY_SIZE(laguna_erss_i2c1_board_info));
317 }
318
319 #ifndef CONFIG_USE_OF
320 static struct platform_device *ardbeg_uart_devices[] __initdata = {
321         &tegra_uarta_device,
322         &tegra_uartb_device,
323         &tegra_uartc_device,
324 };
325
326 static struct tegra_serial_platform_data ardbeg_uarta_pdata = {
327         .dma_req_selector = 8,
328         .modem_interrupt = false,
329 };
330
331 static struct tegra_serial_platform_data ardbeg_uartb_pdata = {
332         .dma_req_selector = 9,
333         .modem_interrupt = false,
334 };
335
336 static struct tegra_serial_platform_data ardbeg_uartc_pdata = {
337         .dma_req_selector = 10,
338         .modem_interrupt = false,
339 };
340 #endif
341
342 static struct tegra_serial_platform_data ardbeg_uartd_pdata = {
343         .dma_req_selector = 19,
344         .modem_interrupt = false,
345 };
346
347 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
348         .gpio_hp_det = TEGRA_GPIO_HP_DET,
349         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
350         .gpio_spkr_en = -1,
351         .gpio_int_mic_en = -1,
352         .gpio_ext_mic_en = -1,
353         .gpio_hp_mute = -1,
354         .gpio_codec1 = -1,
355         .gpio_codec2 = -1,
356         .gpio_codec3 = -1,
357         .i2s_param[HIFI_CODEC]       = {
358                 .audio_port_id = 1,
359                 .is_i2s_master = 1,
360                 .i2s_mode = TEGRA_DAIFMT_I2S,
361                 .sample_size    = 16,
362                 .channels       = 2,
363         },
364         .i2s_param[BT_SCO] = {
365                 .audio_port_id = 3,
366                 .is_i2s_master = 1,
367                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
368         },
369         .i2s_param[BASEBAND]    = {
370                 .audio_port_id  = 0,
371                 .is_i2s_master  = 1,
372                 .i2s_mode       = TEGRA_DAIFMT_I2S,
373                 .sample_size    = 16,
374                 .rate           = 16000,
375                 .channels       = 2,
376                 .bit_clk        = 1024000,
377         },
378 };
379
380 static struct tegra_asoc_platform_data laguna_audio_pdata_max98090 = {
381         .gpio_hp_det = TEGRA_GPIO_HP_DET,
382         .gpio_hp_mute = -1,
383         .edp_support            = true,
384         .edp_states             = {1080, 842, 0},
385         .i2s_param[HIFI_CODEC]  = {
386                 .audio_port_id  = 1,
387                 .is_i2s_master  = 1,
388                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
389                 .sample_size    = 16,
390                 .channels       = 2,
391                 .bit_clk        = 1536000,
392         },
393 };
394
395 static void ardbeg_audio_init(void)
396 {
397         struct board_info board_info;
398         tegra_get_board_info(&board_info);
399
400         if (board_info.board_id == BOARD_PM359)
401                 laguna_register_max98090();
402
403         if (board_info.board_id == BOARD_PM359 ||
404                         board_info.board_id == BOARD_PM358 ||
405                         board_info.board_id == BOARD_PM370 ||
406                         board_info.board_id == BOARD_PM374 ||
407                         board_info.board_id == BOARD_PM375 ||
408                         board_info.board_id == BOARD_PM377 ||
409                         board_info.board_id == BOARD_PM363) {
410                 /*Laguna*/
411                 ardbeg_audio_pdata_rt5639.gpio_hp_det = TEGRA_GPIO_HP_DET;
412                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 1;
413                 if (board_info.board_id != BOARD_PM363)
414                         ardbeg_audio_pdata_rt5639.gpio_ldo1_en = -1;
415         } else {
416                 /*Ardbeg*/
417
418                 if (board_info.board_id == BOARD_E1762 ||
419                         board_info.board_id == BOARD_P1761) {
420                         ardbeg_audio_pdata_rt5639.gpio_hp_det =
421                                 TEGRA_GPIO_CDC_IRQ;
422                         ardbeg_audio_pdata_rt5639.use_codec_jd_irq = true;
423                 } else {
424                         ardbeg_audio_pdata_rt5639.gpio_hp_det =
425                                 TEGRA_GPIO_HP_DET;
426                         ardbeg_audio_pdata_rt5639.use_codec_jd_irq = false;
427                 }
428                 ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high = 0;
429                 ardbeg_audio_pdata_rt5639.gpio_ldo1_en = TEGRA_GPIO_LDO_EN;
430         }
431
432         ardbeg_audio_pdata_rt5639.codec_name = "rt5639.0-001c";
433         ardbeg_audio_pdata_rt5639.codec_dai_name = "rt5639-aif1";
434
435         laguna_audio_pdata_max98090.codec_name = "max98090.7-0010";
436         laguna_audio_pdata_max98090.codec_dai_name = "HiFi";
437 }
438
439 static struct platform_device ardbeg_audio_device_rt5639 = {
440         .name = "tegra-snd-rt5639",
441         .id = 0,
442         .dev = {
443                 .platform_data = &ardbeg_audio_pdata_rt5639,
444         },
445 };
446
447 static struct platform_device laguna_audio_device_max98090 = {
448         .name = "tegra-snd-max98090",
449         .id = 0,
450         .dev = {
451                 .platform_data = &laguna_audio_pdata_max98090,
452         },
453 };
454
455 static void __init ardbeg_uart_init(void)
456 {
457
458 #ifndef CONFIG_USE_OF
459         tegra_uarta_device.dev.platform_data = &ardbeg_uarta_pdata;
460         tegra_uartb_device.dev.platform_data = &ardbeg_uartb_pdata;
461         tegra_uartc_device.dev.platform_data = &ardbeg_uartc_pdata;
462         platform_add_devices(ardbeg_uart_devices,
463                         ARRAY_SIZE(ardbeg_uart_devices));
464 #endif
465         tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
466         if (!is_tegra_debug_uartport_hs()) {
467                 int debug_port_id = uart_console_debug_init(3);
468                 if (debug_port_id < 0)
469                         return;
470
471 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
472                 tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
473 #else
474                 platform_device_register(uart_console_debug_device);
475 #endif
476         } else {
477                 tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
478                 platform_device_register(&tegra_uartd_device);
479         }
480 }
481
482 static struct resource tegra_rtc_resources[] = {
483         [0] = {
484                 .start = TEGRA_RTC_BASE,
485                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
486                 .flags = IORESOURCE_MEM,
487         },
488         [1] = {
489                 .start = INT_RTC,
490                 .end = INT_RTC,
491                 .flags = IORESOURCE_IRQ,
492         },
493 };
494
495 static struct platform_device tegra_rtc_device = {
496         .name = "tegra_rtc",
497         .id   = -1,
498         .resource = tegra_rtc_resources,
499         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
500 };
501
502 static struct tegra_pci_platform_data laguna_pcie_platform_data = {
503         .port_status[0] = 1,
504         .port_status[1] = 0,
505         /* Laguna platforms does not support CLKREQ# feature */
506         .has_clkreq     = 0,
507         .gpio_hot_plug  = TEGRA_GPIO_PO1,
508         .gpio_wake      = TEGRA_GPIO_PDD3,
509         .gpio_x1_slot   = -1,
510 };
511
512 static void laguna_pcie_init(void)
513 {
514         struct board_info board_info;
515         int lane_owner = tegra_get_lane_owner_info() >> 1;
516
517         tegra_get_board_info(&board_info);
518         /* root port 1(x1 slot) is supported only on of ERS-S board */
519         if (board_info.board_id == BOARD_PM359) {
520                 laguna_pcie_platform_data.port_status[1] = 1;
521                 /* enable x1 slot for PM359 if all lanes config'd for PCIe */
522                 if (lane_owner == PCIE_LANES_X4_X1)
523                         laguna_pcie_platform_data.gpio_x1_slot =
524                                         PMU_TCA6416_GPIO(8);
525         } else if (board_info.board_id == BOARD_PM375) {
526                 laguna_pcie_platform_data.port_status[1] = 1;
527                 laguna_pcie_platform_data.gpio_hot_plug = TEGRA_GPIO_INVALID;
528                 laguna_pcie_platform_data.gpio_wake = TEGRA_GPIO_INVALID;
529         }
530         tegra_pci_device.dev.platform_data = &laguna_pcie_platform_data;
531         platform_device_register(&tegra_pci_device);
532 }
533
534 static struct platform_device *ardbeg_devices[] __initdata = {
535         &tegra_pmu_device,
536         &tegra_rtc_device,
537 #if defined(CONFIG_TEGRA_WAKEUP_MONITOR)
538         &tegratab_tegra_wakeup_monitor_device,
539 #endif
540         &tegra_udc_device,
541 #if defined(CONFIG_TEGRA_WATCHDOG)
542         &tegra_wdt0_device,
543 #endif
544 #if defined(CONFIG_TEGRA_AVP)
545         &tegra_avp_device,
546 #endif
547 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) && !defined(CONFIG_USE_OF)
548         &tegra12_se_device,
549 #endif
550         &tegra_ahub_device,
551         &tegra_dam_device0,
552         &tegra_dam_device1,
553         &tegra_dam_device2,
554         &tegra_i2s_device0,
555         &tegra_i2s_device1,
556         &tegra_i2s_device3,
557         &tegra_i2s_device4,
558         &tegra_spdif_device,
559         &spdif_dit_device,
560         &bluetooth_dit_device,
561         &baseband_dit_device,
562         &tegra_hda_device,
563 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
564         &tegra_aes_device,
565 #endif
566 };
567
568 static struct tegra_usb_platform_data tegra_udc_pdata = {
569         .port_otg = true,
570         .has_hostpc = true,
571         .unaligned_dma_buf_supported = false,
572         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
573         .op_mode = TEGRA_USB_OPMODE_DEVICE,
574         .u_data.dev = {
575                 .vbus_pmu_irq = 0,
576                 .vbus_gpio = -1,
577                 .charging_supported = false,
578                 .remote_wakeup_supported = false,
579         },
580         .u_cfg.utmi = {
581                 .hssync_start_delay = 0,
582                 .elastic_limit = 16,
583                 .idle_wait_delay = 17,
584                 .term_range_adj = 6,
585                 .xcvr_setup = 8,
586                 .xcvr_lsfslew = 2,
587                 .xcvr_lsrslew = 2,
588                 .xcvr_setup_offset = 0,
589                 .xcvr_use_fuses = 1,
590         },
591 };
592
593 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
594         .port_otg = true,
595         .has_hostpc = true,
596         .unaligned_dma_buf_supported = false,
597         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
598         .op_mode = TEGRA_USB_OPMODE_HOST,
599         .u_data.host = {
600                 .vbus_gpio = -1,
601                 .hot_plug = false,
602                 .remote_wakeup_supported = true,
603                 .power_off_on_suspend = true,
604         },
605         .u_cfg.utmi = {
606                 .hssync_start_delay = 0,
607                 .elastic_limit = 16,
608                 .idle_wait_delay = 17,
609                 .term_range_adj = 6,
610                 .xcvr_setup = 15,
611                 .xcvr_lsfslew = 0,
612                 .xcvr_lsrslew = 3,
613                 .xcvr_setup_offset = 0,
614                 .xcvr_use_fuses = 1,
615                 .vbus_oc_map = 0x4,
616                 .xcvr_hsslew_lsb = 2,
617         },
618 };
619
620 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
621         .port_otg = false,
622         .has_hostpc = true,
623         .unaligned_dma_buf_supported = false,
624         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
625         .op_mode = TEGRA_USB_OPMODE_HOST,
626         .u_data.host = {
627                 .vbus_gpio = -1,
628                 .hot_plug = false,
629                 .remote_wakeup_supported = true,
630                 .power_off_on_suspend = true,
631         },
632         .u_cfg.utmi = {
633                 .hssync_start_delay = 0,
634                 .elastic_limit = 16,
635                 .idle_wait_delay = 17,
636                 .term_range_adj = 6,
637                 .xcvr_setup = 8,
638                 .xcvr_lsfslew = 2,
639                 .xcvr_lsrslew = 2,
640                 .xcvr_setup_offset = 0,
641                 .xcvr_use_fuses = 1,
642                 .vbus_oc_map = 0x5,
643         },
644 };
645
646 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
647         .port_otg = false,
648         .has_hostpc = true,
649         .unaligned_dma_buf_supported = false,
650         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
651         .op_mode = TEGRA_USB_OPMODE_HOST,
652         .u_data.host = {
653                 .vbus_gpio = -1,
654                 .hot_plug = false,
655                 .remote_wakeup_supported = true,
656                 .power_off_on_suspend = true,
657         },
658         .u_cfg.utmi = {
659         .hssync_start_delay = 0,
660                 .elastic_limit = 16,
661                 .idle_wait_delay = 17,
662                 .term_range_adj = 6,
663                 .xcvr_setup = 8,
664                 .xcvr_lsfslew = 2,
665                 .xcvr_lsrslew = 2,
666                 .xcvr_setup_offset = 0,
667                 .xcvr_use_fuses = 1,
668                 .vbus_oc_map = 0x5,
669         },
670 };
671
672 static struct gpio modem_gpios[] = { /* Bruce modem */
673         {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"},
674         {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"},
675         {MDM_SAR0, GPIOF_OUT_INIT_LOW, "MODEM SAR0"},
676 };
677
678 static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = {
679         .port_otg = false,
680         .has_hostpc = true,
681         .unaligned_dma_buf_supported = false,
682         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
683         .op_mode = TEGRA_USB_OPMODE_HOST,
684         .u_data.host = {
685                 .vbus_gpio = -1,
686                 .hot_plug = false,
687                 .remote_wakeup_supported = true,
688                 .power_off_on_suspend = true,
689         },
690 };
691
692 static struct tegra_usb_platform_data tegra_ehci2_hsic_smsc_hub_pdata = {
693         .port_otg = false,
694         .has_hostpc = true,
695         .unaligned_dma_buf_supported = false,
696         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
697         .op_mode        = TEGRA_USB_OPMODE_HOST,
698         .u_data.host = {
699                 .vbus_gpio = -1,
700                 .hot_plug = false,
701                 .remote_wakeup_supported = true,
702                 .power_off_on_suspend = true,
703         },
704 };
705
706
707 static struct tegra_usb_otg_data tegra_otg_pdata = {
708         .ehci_device = &tegra_ehci1_device,
709         .ehci_pdata = &tegra_ehci1_utmi_pdata,
710 };
711
712 static void ardbeg_usb_init(void)
713 {
714         int usb_port_owner_info = tegra_get_usb_port_owner_info();
715         int modem_id = tegra_get_modem_id();
716         struct board_info bi;
717         tegra_get_pmu_board_info(&bi);
718
719         if (board_info.sku == 1100)
720                 tegra_ehci1_utmi_pdata.u_data.host.turn_off_vbus_on_lp0 = true;
721
722         if (board_info.board_id == BOARD_PM359 ||
723                         board_info.board_id == BOARD_PM358 ||
724                         board_info.board_id == BOARD_PM370 ||
725                         board_info.board_id == BOARD_PM374 ||
726                         board_info.board_id == BOARD_PM375 ||
727                         board_info.board_id == BOARD_PM377 ||
728                         board_info.board_id == BOARD_PM363) {
729                 /* Laguna */
730                 /* Host cable is detected through AMS PMU Interrupt */
731                 if (board_info.major_revision >= 'A' &&
732                         board_info.major_revision <= 'D') {
733                         tegra_udc_pdata.id_det_type = TEGRA_USB_VIRTUAL_ID;
734                         tegra_ehci1_utmi_pdata.id_det_type =
735                                                 TEGRA_USB_VIRTUAL_ID;
736                 } else {
737                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
738                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
739                 }
740                 tegra_ehci1_utmi_pdata.id_extcon_dev_name = "as3722-extcon";
741         } else {
742                 /* Ardbeg */
743                 switch (bi.board_id) {
744                 case BOARD_E1733:
745                         /* Host cable is detected through PMU Interrupt */
746                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
747                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
748                         tegra_ehci1_utmi_pdata.id_extcon_dev_name =
749                                                          "as3722-extcon";
750                         break;
751                 case BOARD_E1736:
752                 case BOARD_E1769:
753                 case BOARD_E1735:
754                 case BOARD_E1936:
755                 case BOARD_P1761:
756                         /* Device cable is detected through PMU Interrupt */
757                         tegra_udc_pdata.support_pmu_vbus = true;
758                         tegra_udc_pdata.vbus_extcon_dev_name = "palmas-extcon";
759                         tegra_ehci1_utmi_pdata.support_pmu_vbus = true;
760                         tegra_ehci1_utmi_pdata.vbus_extcon_dev_name =
761                                                          "palmas-extcon";
762                         /* Host cable is detected through PMU Interrupt */
763                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
764                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
765                         tegra_ehci1_utmi_pdata.id_extcon_dev_name =
766                                                          "palmas-extcon";
767                 }
768         }
769
770         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
771                 tegra_otg_pdata.is_xhci = false;
772                 tegra_udc_pdata.u_data.dev.is_xhci = false;
773         } else {
774                 tegra_otg_pdata.is_xhci = true;
775                 tegra_udc_pdata.u_data.dev.is_xhci = true;
776         }
777         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
778         platform_device_register(&tegra_otg_device);
779         /* Setup the udc platform data */
780         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
781
782         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
783                 if (!modem_id) {
784                         if ((bi.board_id != BOARD_P1761) &&
785                             (bi.board_id != BOARD_E1922) &&
786                             (bi.board_id != BOARD_E1784)) {
787                                 tegra_ehci2_device.dev.platform_data =
788                                         &tegra_ehci2_utmi_pdata;
789                                 platform_device_register(&tegra_ehci2_device);
790                         }
791                 }
792         }
793
794         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
795                 if ((bi.board_id != BOARD_P1761) &&
796                     (bi.board_id != BOARD_E1922) &&
797                     (bi.board_id != BOARD_E1784)) {
798                         tegra_ehci3_device.dev.platform_data =
799                                 &tegra_ehci3_utmi_pdata;
800                         platform_device_register(&tegra_ehci3_device);
801                 }
802         }
803
804 }
805
806 static struct tegra_xusb_platform_data xusb_pdata = {
807         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_SS_P1 |
808                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_USB2_P2,
809 };
810
811 static void ardbeg_xusb_init(void)
812 {
813         int usb_port_owner_info = tegra_get_usb_port_owner_info();
814
815         xusb_pdata.lane_owner = (u8) tegra_get_lane_owner_info();
816
817         if (board_info.board_id == BOARD_PM359 ||
818                         board_info.board_id == BOARD_PM358 ||
819                         board_info.board_id == BOARD_PM370 ||
820                         board_info.board_id == BOARD_PM374 ||
821                         board_info.board_id == BOARD_PM377 ||
822                         board_info.board_id == BOARD_PM363) {
823                 /* Laguna */
824                 pr_info("Laguna ERS. 0x%x\n", board_info.board_id);
825
826                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
827                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
828                                 TEGRA_XUSB_SS_P0);
829
830                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
831                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
832                                 TEGRA_XUSB_SS_P1 | TEGRA_XUSB_USB2_P2);
833
834                 /* FIXME Add for UTMIP2 when have odmdata assigend */
835         } else if (board_info.board_id == BOARD_PM375) {
836                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
837                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
838                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
839                         xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P2 |
840                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0);
841                 xusb_pdata.portmap &= ~(TEGRA_XUSB_SS_P1);
842         } else {
843                 /* Ardbeg */
844                 if (board_info.board_id == BOARD_E1781) {
845                         pr_info("Shield ERS-S. 0x%x\n", board_info.board_id);
846                         /* Shield ERS-S */
847                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
848                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
849
850                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
851                                 xusb_pdata.portmap &= ~(
852                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0 |
853                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
854                 } else {
855                         pr_info("Shield ERS 0x%x\n", board_info.board_id);
856                         /* Shield ERS */
857                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
858                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
859                                         TEGRA_XUSB_SS_P0);
860
861                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
862                                 xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
863                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
864                 }
865                 /* FIXME Add for UTMIP2 when have odmdata assigend */
866         }
867
868         if (usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)
869                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P0;
870
871         if (usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)
872                 xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P1;
873 }
874
875 static int baseband_init(void)
876 {
877         int ret;
878
879         ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios));
880         if (ret) {
881                 pr_warn("%s:gpio request failed\n", __func__);
882                 return ret;
883         }
884
885         /* enable pull-down for MDM_COLD_BOOT */
886         tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4,
887                                     TEGRA_PUPD_PULL_DOWN);
888
889         /* export GPIO for user space access through sysfs */
890         gpio_export(MDM_RST, false);
891         gpio_export(MDM_SAR0, false);
892
893         return 0;
894 }
895
896 static const struct tegra_modem_operations baseband_operations = {
897         .init = baseband_init,
898 };
899
900 static struct tegra_usb_modem_power_platform_data baseband_pdata = {
901         .ops = &baseband_operations,
902         .regulator_name = "vdd_wwan_mdm",
903         .wake_gpio = -1,
904         .boot_gpio = MDM_COLDBOOT,
905         .boot_irq_flags = IRQF_TRIGGER_RISING |
906                                     IRQF_TRIGGER_FALLING |
907                                     IRQF_ONESHOT,
908         .autosuspend_delay = 2000,
909         .short_autosuspend_delay = 50,
910         .tegra_ehci_device = &tegra_ehci2_device,
911         .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata,
912         .sysedpc_name = "modem",
913 };
914
915 static struct platform_device icera_bruce_device = {
916         .name = "tegra_usb_modem_power",
917         .id = -1,
918         .dev = {
919                 .platform_data = &baseband_pdata,
920         },
921 };
922
923 static void ardbeg_modem_init(void)
924 {
925         int modem_id = tegra_get_modem_id();
926         struct board_info board_info;
927         struct board_info pmu_board_info;
928         int usb_port_owner_info = tegra_get_usb_port_owner_info();
929
930         tegra_get_board_info(&board_info);
931         tegra_get_pmu_board_info(&pmu_board_info);
932         pr_info("%s: modem_id = %d\n", __func__, modem_id);
933
934         switch (modem_id) {
935         case TEGRA_BB_BRUCE:
936                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
937                         /* Set specific USB wake source for Ardbeg */
938                         if (board_info.board_id == BOARD_E1780)
939                                 tegra_set_wake_source(42, INT_USB2);
940                         if (pmu_board_info.board_id == BOARD_E1736 ||
941                                 pmu_board_info.board_id == BOARD_E1769)
942                                 baseband_pdata.regulator_name = NULL;
943                         platform_device_register(&icera_bruce_device);
944                 }
945                 break;
946         case TEGRA_BB_HSIC_HUB: /* HSIC hub */
947                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
948                         tegra_ehci2_device.dev.platform_data =
949                                 &tegra_ehci2_hsic_smsc_hub_pdata;
950                         /* Set specific USB wake source for Ardbeg */
951                         if (board_info.board_id == BOARD_E1780)
952                                 tegra_set_wake_source(42, INT_USB2);
953                         platform_device_register(&tegra_ehci2_device);
954                 } else
955                         xusb_pdata.pretend_connect_0 = true;
956                 break;
957         default:
958                 return;
959         }
960 }
961
962 #ifdef CONFIG_USE_OF
963 static struct of_dev_auxdata ardbeg_auxdata_lookup[] __initdata = {
964         T124_SPI_OF_DEV_AUXDATA,
965         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
966                                 NULL),
967         OF_DEV_AUXDATA("nvidia,tegra124-se", 0x70012000, "tegra12-se", NULL),
968         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
969                 NULL),
970         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", TEGRA_GK20A_BAR0_BASE,
971                 "gk20a.0", NULL),
972 #ifdef CONFIG_ARCH_TEGRA_VIC
973         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03.0", NULL),
974 #endif
975         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
976                 NULL),
977         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi.0", NULL),
978         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp.0", NULL),
979         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISPB_BASE, "isp.1", NULL),
980         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
981         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0",
982                                 NULL),
983         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1",
984                                 NULL),
985         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2",
986                                 NULL),
987         T124_I2C_OF_DEV_AUXDATA,
988         OF_DEV_AUXDATA("nvidia,tegra124-xhci", 0x70090000, "tegra-xhci",
989                                 &xusb_pdata),
990         OF_DEV_AUXDATA("nvidia,tegra124-dc", TEGRA_DISPLAY_BASE, "tegradc.0",
991                 NULL),
992         OF_DEV_AUXDATA("nvidia,tegra124-dc", TEGRA_DISPLAY2_BASE, "tegradc.1",
993                 NULL),
994         {}
995 };
996 #endif
997
998 struct maxim_sti_pdata maxim_sti_pdata = {
999         .touch_fusion         = "/vendor/bin/touch_fusion",
1000         .config_file          = "/vendor/firmware/touch_fusion.cfg",
1001         .fw_name              = "maxim_fp35.bin",
1002         .nl_family            = TF_FAMILY_NAME,
1003         .nl_mc_groups         = 5,
1004         .chip_access_method   = 2,
1005         .default_reset_state  = 0,
1006         .tx_buf_size          = 4100,
1007         .rx_buf_size          = 4100,
1008         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
1009         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
1010 };
1011
1012 struct maxim_sti_pdata maxim_sti_pdata_rd = {
1013         .touch_fusion         = "/vendor/bin/touch_fusion_rd",
1014         .config_file          = "/vendor/firmware/touch_fusion.cfg",
1015         .fw_name              = "maxim_fp35.bin",
1016         .nl_family            = TF_FAMILY_NAME,
1017         .nl_mc_groups         = 5,
1018         .chip_access_method   = 2,
1019         .default_reset_state  = 0,
1020         .tx_buf_size          = 4100,
1021         .rx_buf_size          = 4100,
1022         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
1023         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
1024 };
1025
1026 static struct tegra_spi_device_controller_data maxim_dev_cdata = {
1027         .rx_clk_tap_delay = 0,
1028         .is_hw_based_cs = true,
1029         .tx_clk_tap_delay = 0,
1030 };
1031
1032 struct spi_board_info maxim_sti_spi_board = {
1033         .modalias = MAXIM_STI_NAME,
1034         .bus_num = TOUCH_SPI_ID,
1035         .chip_select = TOUCH_SPI_CS,
1036         .max_speed_hz = 12 * 1000 * 1000,
1037         .mode = SPI_MODE_0,
1038         .platform_data = &maxim_sti_pdata,
1039         .controller_data = &maxim_dev_cdata,
1040 };
1041
1042 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
1043         /* name         parent          rate            enabled */
1044         { "extern2",    "pll_p",        41000000,       false},
1045         { "clk_out_2",  "extern2",      40800000,       false},
1046         { NULL,         NULL,           0,              0},
1047 };
1048
1049 static struct rm_spi_ts_platform_data rm31080ts_ardbeg_data = {
1050         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1051         .config = 0,
1052         .platform_id = RM_PLATFORM_A010,
1053         .name_of_clock = "clk_out_2",
1054         .name_of_clock_con = "extern2",
1055 };
1056
1057 static struct rm_spi_ts_platform_data rm31080ts_norrin_data = {
1058         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
1059         .config = 0,
1060         .platform_id = RM_PLATFORM_P140,
1061         .name_of_clock = "clk_out_2",
1062         .name_of_clock_con = "extern2",
1063 };
1064
1065 static struct tegra_spi_device_controller_data dev_cdata = {
1066         .rx_clk_tap_delay = 0,
1067         .tx_clk_tap_delay = 16,
1068 };
1069
1070 static struct spi_board_info rm31080a_ardbeg_spi_board[1] = {
1071         {
1072                 .modalias = "rm_ts_spidev",
1073                 .bus_num = TOUCH_SPI_ID,
1074                 .chip_select = TOUCH_SPI_CS,
1075                 .max_speed_hz = 12 * 1000 * 1000,
1076                 .mode = SPI_MODE_0,
1077                 .controller_data = &dev_cdata,
1078                 .platform_data = &rm31080ts_ardbeg_data,
1079         },
1080 };
1081
1082 static struct spi_board_info rm31080a_norrin_spi_board[1] = {
1083         {
1084                 .modalias = "rm_ts_spidev",
1085                 .bus_num = NORRIN_TOUCH_SPI_ID,
1086                 .chip_select = NORRIN_TOUCH_SPI_CS,
1087                 .max_speed_hz = 12 * 1000 * 1000,
1088                 .mode = SPI_MODE_0,
1089                 .controller_data = &dev_cdata,
1090                 .platform_data = &rm31080ts_norrin_data,
1091         },
1092 };
1093
1094 static int __init ardbeg_touch_init(void)
1095 {
1096         tegra_get_board_info(&board_info);
1097
1098         if (tegra_get_touch_vendor_id() == MAXIM_TOUCH) {
1099                 pr_info("%s init maxim touch\n", __func__);
1100 #if defined(CONFIG_TOUCHSCREEN_MAXIM_STI) || \
1101         defined(CONFIG_TOUCHSCREEN_MAXIM_STI_MODULE)
1102                 if (tegra_get_touch_panel_id() == TOUCHPANEL_TN7)
1103                         maxim_sti_spi_board.platform_data = &maxim_sti_pdata_rd;
1104                 (void)touch_init_maxim_sti(&maxim_sti_spi_board);
1105 #endif
1106         } else if (tegra_get_touch_vendor_id() == RAYDIUM_TOUCH) {
1107                 pr_info("%s init raydium touch\n", __func__);
1108                 tegra_clk_init_from_table(touch_clk_init_table);
1109                 if (board_info.board_id == BOARD_PM374) {
1110                         rm31080a_norrin_spi_board[0].irq =
1111                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1112                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1113                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1114                                         &rm31080ts_norrin_data,
1115                                         &rm31080a_norrin_spi_board[0],
1116                                         ARRAY_SIZE(rm31080a_norrin_spi_board));
1117                 } else {
1118                         rm31080a_ardbeg_spi_board[0].irq =
1119                                 gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1120                         touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1121                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1122                                         &rm31080ts_ardbeg_data,
1123                                         &rm31080a_ardbeg_spi_board[0],
1124                                         ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1125                 }
1126         }
1127         return 0;
1128 }
1129
1130 static void __init ardbeg_sysedp_init(void)
1131 {
1132         struct board_info bi;
1133
1134         tegra_get_board_info(&bi);
1135
1136         switch (bi.board_id) {
1137         case BOARD_E1780:
1138                 if (bi.sku == 1100) {
1139                         tn8_new_sysedp_init();
1140                 }
1141                 else
1142                         shield_new_sysedp_init();
1143                 break;
1144         case BOARD_E1922:
1145         case BOARD_E1784:
1146         case BOARD_P1761:
1147                 tn8_new_sysedp_init();
1148                 break;
1149         case BOARD_PM358:
1150         case BOARD_PM359:
1151         default:
1152                 break;
1153         }
1154 }
1155
1156 static void __init ardbeg_sysedp_dynamic_capping_init(void)
1157 {
1158         struct board_info bi;
1159
1160         tegra_get_board_info(&bi);
1161
1162         switch (bi.board_id) {
1163         case BOARD_E1780:
1164                 if (bi.sku == 1100)
1165                         tn8_sysedp_dynamic_capping_init();
1166                 else
1167                         shield_sysedp_dynamic_capping_init();
1168                 break;
1169         case BOARD_E1922:
1170         case BOARD_E1784:
1171         case BOARD_P1761:
1172                 tn8_sysedp_dynamic_capping_init();
1173                 break;
1174         case BOARD_PM358:
1175         case BOARD_PM359:
1176         default:
1177                 break;
1178         }
1179 }
1180
1181 static void __init ardbeg_sysedp_batmon_init(void)
1182 {
1183         struct board_info bi;
1184
1185         if (!IS_ENABLED(CONFIG_SYSEDP_FRAMEWORK))
1186                 return;
1187
1188         tegra_get_board_info(&bi);
1189
1190         switch (bi.board_id) {
1191         case BOARD_E1780:
1192                 if (bi.sku != 1100)
1193                         shield_sysedp_batmon_init();
1194                 break;
1195         case BOARD_PM358:
1196         case BOARD_PM359:
1197         case BOARD_PM375:
1198         case BOARD_PM377:
1199         default:
1200                 break;
1201         }
1202 }
1203
1204
1205
1206 static void __init edp_init(void)
1207 {
1208         struct board_info bi;
1209
1210         tegra_get_board_info(&bi);
1211
1212         switch (bi.board_id) {
1213         case BOARD_E1780:
1214                 if (bi.sku == 1100)
1215                         tn8_edp_init();
1216                 else
1217                         ardbeg_edp_init();
1218                 break;
1219         case BOARD_P1761:
1220                         tn8_edp_init();
1221                         break;
1222         case BOARD_PM358:
1223         case BOARD_PM359:
1224         case BOARD_PM375:
1225         case BOARD_PM377:
1226                         laguna_edp_init();
1227                         break;
1228         default:
1229                         ardbeg_edp_init();
1230                         break;
1231         }
1232 }
1233
1234 static void __init tegra_ardbeg_early_init(void)
1235 {
1236         ardbeg_sysedp_init();
1237         tegra_clk_init_from_table(ardbeg_clk_init_table);
1238         tegra_clk_verify_parents();
1239         if (of_machine_is_compatible("nvidia,jetson-tk1"))
1240                 tegra_soc_device_init("jetson-tk1");
1241         else if (of_machine_is_compatible("nvidia,laguna"))
1242                 tegra_soc_device_init("laguna");
1243         else if (of_machine_is_compatible("nvidia,tn8"))
1244                 tegra_soc_device_init("tn8");
1245         else if (of_machine_is_compatible("nvidia,ardbeg_sata"))
1246                 tegra_soc_device_init("ardbeg_sata");
1247         else if (of_machine_is_compatible("nvidia,norrin"))
1248                 tegra_soc_device_init("norrin");
1249         else
1250                 tegra_soc_device_init("ardbeg");
1251 }
1252
1253 static struct tegra_dtv_platform_data ardbeg_dtv_pdata = {
1254         .dma_req_selector = 11,
1255 };
1256
1257 static void __init ardbeg_dtv_init(void)
1258 {
1259         tegra_dtv_device.dev.platform_data = &ardbeg_dtv_pdata;
1260         platform_device_register(&tegra_dtv_device);
1261 }
1262
1263 static struct tegra_io_dpd pexbias_io = {
1264         .name                   = "PEX_BIAS",
1265         .io_dpd_reg_index       = 0,
1266         .io_dpd_bit             = 4,
1267 };
1268 static struct tegra_io_dpd pexclk1_io = {
1269         .name                   = "PEX_CLK1",
1270         .io_dpd_reg_index       = 0,
1271         .io_dpd_bit             = 5,
1272 };
1273 static struct tegra_io_dpd pexclk2_io = {
1274         .name                   = "PEX_CLK2",
1275         .io_dpd_reg_index       = 0,
1276         .io_dpd_bit             = 6,
1277 };
1278
1279 static void __init tegra_ardbeg_late_init(void)
1280 {
1281         struct board_info board_info;
1282         tegra_get_board_info(&board_info);
1283         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1284                 board_info.board_id, board_info.sku,
1285                 board_info.fab, board_info.major_revision,
1286                 board_info.minor_revision);
1287
1288         ardbeg_display_init();
1289         ardbeg_uart_init();
1290         ardbeg_usb_init();
1291         ardbeg_modem_init();
1292         ardbeg_xusb_init();
1293         ardbeg_i2c_init();
1294         ardbeg_audio_init();
1295         platform_add_devices(ardbeg_devices, ARRAY_SIZE(ardbeg_devices));
1296
1297         if (board_info.board_id == BOARD_PM359) /* Laguna ERS-S */
1298                 platform_device_register(&laguna_audio_device_max98090);
1299         else
1300                 platform_device_register(&ardbeg_audio_device_rt5639);
1301
1302         tegra_io_dpd_init();
1303         ardbeg_sdhci_init();
1304         if (board_info.board_id == BOARD_PM359 ||
1305                         board_info.board_id == BOARD_PM358 ||
1306                         board_info.board_id == BOARD_PM363 ||
1307                         board_info.board_id == BOARD_PM375 ||
1308                         board_info.board_id == BOARD_PM377 ||
1309                         board_info.board_id == BOARD_E1782)
1310                 ardbeg_sata_init();
1311         else
1312                 arbdeg_sata_clk_gate();
1313         if (board_info.board_id == BOARD_PM359 ||
1314                         board_info.board_id == BOARD_PM358 ||
1315                         board_info.board_id == BOARD_PM370 ||
1316                         board_info.board_id == BOARD_PM375 ||
1317                         board_info.board_id == BOARD_PM377 ||
1318                         board_info.board_id == BOARD_PM363)
1319                 laguna_regulator_init();
1320         else if (board_info.board_id == BOARD_PM374)
1321                 norrin_regulator_init();
1322         else
1323                 ardbeg_regulator_init();
1324         ardbeg_dtv_init();
1325         ardbeg_suspend_init();
1326         ardbeg_emc_init();
1327         edp_init();
1328         isomgr_init();
1329         if ((board_info.board_id != BOARD_PM375) &&
1330                 (board_info.board_id != BOARD_PM377))
1331                 ardbeg_touch_init();
1332         ardbeg_panel_init();
1333         switch (board_info.board_id) {
1334         case BOARD_PM358:
1335                 laguna_pm358_pmon_init();
1336                 break;
1337         case BOARD_PM359:
1338                 ; /* powermon not present in Laguna ERS-S */
1339                 break;
1340         case BOARD_P1761:
1341                 tn8_p1761_pmon_init();
1342                 break;
1343         default:
1344                 ardbeg_pmon_init();
1345                 break;
1346         }
1347         if (board_info.board_id == BOARD_PM359 ||
1348                         board_info.board_id == BOARD_PM358 ||
1349                         board_info.board_id == BOARD_PM375 ||
1350                         board_info.board_id == BOARD_PM377 ||
1351                         board_info.board_id == BOARD_PM363)
1352                 laguna_pcie_init();
1353         else {
1354                 /* put PEX pads into DPD mode to save additional power */
1355                 tegra_io_dpd_enable(&pexbias_io);
1356                 tegra_io_dpd_enable(&pexclk1_io);
1357                 tegra_io_dpd_enable(&pexclk2_io);
1358         }
1359
1360 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1361         tegra_wdt_recovery_init();
1362 #endif
1363
1364         ardbeg_sensors_init();
1365
1366         ardbeg_soctherm_init();
1367
1368         ardbeg_setup_bluedroid_pm();
1369         tegra_register_fuse();
1370
1371         ardbeg_sysedp_dynamic_capping_init();
1372         ardbeg_sysedp_batmon_init();
1373 }
1374
1375 static void __init ardbeg_ramconsole_reserve(unsigned long size)
1376 {
1377         tegra_reserve_ramoops_memory(SZ_1M);
1378 }
1379
1380 static void __init tegra_ardbeg_init_early(void)
1381 {
1382         ardbeg_rail_alignment_init();
1383         tegra12x_init_early();
1384 }
1385
1386 static void __init tegra_ardbeg_dt_init(void)
1387 {
1388         tegra_get_board_info(&board_info);
1389         tegra_get_display_board_info(&display_board_info);
1390
1391         tegra_ardbeg_early_init();
1392 #ifdef CONFIG_USE_OF
1393         of_platform_populate(NULL,
1394                 of_default_bus_match_table, ardbeg_auxdata_lookup,
1395                 &platform_bus);
1396 #endif
1397
1398         tegra_ardbeg_late_init();
1399 }
1400
1401 static void __init tegra_ardbeg_reserve(void)
1402 {
1403         unsigned long fb1_size, fb2_size, carveout_size;
1404
1405 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
1406         fb1_size = SZ_16M + SZ_2M; /* 1920*1200*4*2 = 18432000 bytes */
1407         fb2_size = SZ_64M + SZ_4M; /* 3840*2160*4*2 = 66355200 bytes */
1408 #else
1409         fb1_size = SZ_64M + SZ_4M; /* 3840*2160*4*2 = 66355200 bytes */
1410         fb2_size = SZ_16M + SZ_2M; /* 1920*1200*4*2 = 18432000 bytes */
1411 #endif
1412
1413 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) || \
1414                 defined(CONFIG_TEGRA_NO_CARVEOUT)
1415         carveout_size = 0;
1416 #else
1417         carveout_size = SZ_1G;
1418 #endif
1419
1420         tegra_reserve(carveout_size, fb1_size, fb2_size);
1421         ardbeg_ramconsole_reserve(SZ_1M);
1422 }
1423
1424 static const char * const ardbeg_dt_board_compat[] = {
1425         "nvidia,ardbeg",
1426         NULL
1427 };
1428
1429 static const char * const laguna_dt_board_compat[] = {
1430         "nvidia,laguna",
1431         NULL
1432 };
1433
1434 static const char * const tn8_dt_board_compat[] = {
1435         "nvidia,tn8",
1436         NULL
1437 };
1438
1439 static const char * const ardbeg_sata_dt_board_compat[] = {
1440         "nvidia,ardbeg_sata",
1441         NULL
1442 };
1443
1444 static const char * const norrin_dt_board_compat[] = {
1445         "nvidia,norrin",
1446         NULL
1447 };
1448
1449 static const char * const jetson_dt_board_compat[] = {
1450         "nvidia,jetson-tk1",
1451         NULL
1452 };
1453
1454 DT_MACHINE_START(LAGUNA, "laguna")
1455         .atag_offset    = 0x100,
1456         .smp            = smp_ops(tegra_smp_ops),
1457         .map_io         = tegra_map_common_io,
1458         .reserve        = tegra_ardbeg_reserve,
1459         .init_early     = tegra_ardbeg_init_early,
1460         .init_irq       = irqchip_init,
1461         .init_time      = clocksource_of_init,
1462         .init_machine   = tegra_ardbeg_dt_init,
1463         .restart        = tegra_assert_system_reset,
1464         .dt_compat      = laguna_dt_board_compat,
1465         .init_late      = tegra_init_late
1466 MACHINE_END
1467
1468 DT_MACHINE_START(TN8, "tn8")
1469         .atag_offset    = 0x100,
1470         .smp            = smp_ops(tegra_smp_ops),
1471         .map_io         = tegra_map_common_io,
1472         .reserve        = tegra_ardbeg_reserve,
1473         .init_early     = tegra_ardbeg_init_early,
1474         .init_irq       = irqchip_init,
1475         .init_time      = clocksource_of_init,
1476         .init_machine   = tegra_ardbeg_dt_init,
1477         .restart        = tegra_assert_system_reset,
1478         .dt_compat      = tn8_dt_board_compat,
1479         .init_late      = tegra_init_late
1480 MACHINE_END
1481
1482 DT_MACHINE_START(NORRIN, "norrin")
1483         .atag_offset    = 0x100,
1484         .smp            = smp_ops(tegra_smp_ops),
1485         .map_io         = tegra_map_common_io,
1486         .reserve        = tegra_ardbeg_reserve,
1487         .init_early     = tegra_ardbeg_init_early,
1488         .init_irq       = irqchip_init,
1489         .init_time      = clocksource_of_init,
1490         .init_machine   = tegra_ardbeg_dt_init,
1491         .restart        = tegra_assert_system_reset,
1492         .dt_compat      = norrin_dt_board_compat,
1493         .init_late      = tegra_init_late
1494 MACHINE_END
1495
1496 DT_MACHINE_START(ARDBEG, "ardbeg")
1497         .atag_offset    = 0x100,
1498         .smp            = smp_ops(tegra_smp_ops),
1499         .map_io         = tegra_map_common_io,
1500         .reserve        = tegra_ardbeg_reserve,
1501         .init_early     = tegra_ardbeg_init_early,
1502         .init_irq       = irqchip_init,
1503         .init_time      = clocksource_of_init,
1504         .init_machine   = tegra_ardbeg_dt_init,
1505         .restart        = tegra_assert_system_reset,
1506         .dt_compat      = ardbeg_dt_board_compat,
1507         .init_late      = tegra_init_late
1508 MACHINE_END
1509
1510 DT_MACHINE_START(ARDBEG_SATA, "ardbeg_sata")
1511         .atag_offset    = 0x100,
1512         .smp            = smp_ops(tegra_smp_ops),
1513         .map_io         = tegra_map_common_io,
1514         .reserve        = tegra_ardbeg_reserve,
1515         .init_early     = tegra_ardbeg_init_early,
1516         .init_irq       = irqchip_init,
1517         .init_time      = clocksource_of_init,
1518         .init_machine   = tegra_ardbeg_dt_init,
1519         .restart        = tegra_assert_system_reset,
1520         .dt_compat      = ardbeg_sata_dt_board_compat,
1521         .init_late      = tegra_init_late
1522
1523 MACHINE_END
1524
1525 DT_MACHINE_START(JETSON_TK1, "jetson-tk1")
1526         .atag_offset    = 0x100,
1527         .smp            = smp_ops(tegra_smp_ops),
1528         .map_io         = tegra_map_common_io,
1529         .reserve        = tegra_ardbeg_reserve,
1530         .init_early     = tegra_ardbeg_init_early,
1531         .init_irq       = irqchip_init,
1532         .init_time      = clocksource_of_init,
1533         .init_machine   = tegra_ardbeg_dt_init,
1534         .restart        = tegra_assert_system_reset,
1535         .dt_compat      = jetson_dt_board_compat,
1536         .init_late      = tegra_init_late
1537 MACHINE_END