arch/arm/mach-tegra/board-ardbeg.c

   1 /*
   2  * arch/arm/mach-tegra/board-ardbeg.c
   3  *
   4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/slab.h>
  23 #include <linux/ctype.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/serial_8250.h>
  27 #include <linux/i2c.h>
  28 #include <linux/i2c/i2c-hid.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/delay.h>
  31 #include <linux/i2c-tegra.h>
  32 #include <linux/gpio.h>
  33 #include <linux/input.h>
  34 #include <linux/platform_data/tegra_usb.h>
  35 #include <linux/spi/spi.h>
  36 #include <linux/spi/rm31080a_ts.h>
  37 #include <linux/maxim_sti.h>
  38 #include <linux/memblock.h>
  39 #include <linux/spi/spi-tegra.h>
  40 #include <linux/nfc/pn544.h>
  41 #include <linux/rfkill-gpio.h>
  42 #include <linux/skbuff.h>
  43 #include <linux/ti_wilink_st.h>
  44 #include <linux/regulator/consumer.h>
  45 #include <linux/smb349-charger.h>
  46 #include <linux/max17048_battery.h>
  47 #include <linux/leds.h>
  48 #include <linux/i2c/at24.h>
  49 #include <linux/of_platform.h>
  50 #include <linux/i2c.h>
  51 #include <linux/i2c-tegra.h>
  52 #include <linux/platform_data/serial-tegra.h>
  53 #include <linux/edp.h>
  54 #include <linux/usb/tegra_usb_phy.h>
  55 #include <linux/mfd/palmas.h>
  56 #include <linux/clk/tegra.h>
  57 #include <media/tegra_dtv.h>
  58 #include <linux/clocksource.h>
  59 #include <linux/irqchip.h>
  60 #include <linux/irqchip/tegra.h>
  61 #include <linux/pci-tegra.h>
  62
  63 #include <mach/irqs.h>
  64 #include <mach/tegra_fiq_debugger.h>
  65
  66 #include <mach/pinmux.h>
  67 #include <mach/pinmux-t12.h>
  68 #include <mach/io_dpd.h>
  69 #include <mach/i2s.h>
  70 #include <mach/isomgr.h>
  71 #include <mach/tegra_asoc_pdata.h>
  72 #include <asm/mach-types.h>
  73 #include <asm/mach/arch.h>
  74 #include <mach/gpio-tegra.h>
  75 #include <mach/tegra_fiq_debugger.h>
  76 #include <mach/xusb.h>
  77 #include <linux/platform_data/tegra_usb_modem_power.h>
  78 #include <linux/platform_data/tegra_ahci.h>
  79 #include <linux/irqchip/tegra.h>
  80
  81 #include "board.h"
  82 #include "board-ardbeg.h"
  83 #include "board-common.h"
  84 #include "board-touch-raydium.h"
  85 #include "board-touch-maxim_sti.h"
  86 #include "clock.h"
  87 #include "common.h"
  88 #include "devices.h"
  89 #include "gpio-names.h"
  90 #include "iomap.h"
  91 #include "pm.h"
  92 #include "tegra-board-id.h"
  93
  94 static struct board_info board_info, display_board_info;
  95
  96 static struct resource ardbeg_bluedroid_pm_resources[] = {
  97         [0] = {
  98                 .name   = "shutdown_gpio",
  99                 .start  = TEGRA_GPIO_PR1,
 100                 .end    = TEGRA_GPIO_PR1,
 101                 .flags  = IORESOURCE_IO,
 102         },
 103         [1] = {
 104                 .name = "host_wake",
 105                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 106         },
 107         [2] = {
 108                 .name = "gpio_ext_wake",
 109                 .start  = TEGRA_GPIO_PEE1,
 110                 .end    = TEGRA_GPIO_PEE1,
 111                 .flags  = IORESOURCE_IO,
 112         },
 113         [3] = {
 114                 .name = "gpio_host_wake",
 115                 .start  = TEGRA_GPIO_PU6,
 116                 .end    = TEGRA_GPIO_PU6,
 117                 .flags  = IORESOURCE_IO,
 118         },
 119         [4] = {
 120                 .name = "reset_gpio",
 121                 .start  = TEGRA_GPIO_PX1,
 122                 .end    = TEGRA_GPIO_PX1,
 123                 .flags  = IORESOURCE_IO,
 124         },
 125 };
 126
 127 static struct platform_device ardbeg_bluedroid_pm_device = {
 128         .name = "bluedroid_pm",
 129         .id             = 0,
 130         .num_resources  = ARRAY_SIZE(ardbeg_bluedroid_pm_resources),
 131         .resource       = ardbeg_bluedroid_pm_resources,
 132 };
 133
 134 static noinline void __init ardbeg_setup_bluedroid_pm(void)
 135 {
 136         ardbeg_bluedroid_pm_resources[1].start =
 137                 ardbeg_bluedroid_pm_resources[1].end =
 138                                 gpio_to_irq(TEGRA_GPIO_PU6);
 139         platform_device_register(&ardbeg_bluedroid_pm_device);
 140 }
 141
 142 static struct i2c_board_info __initdata rt5639_board_info = {
 143         I2C_BOARD_INFO("rt5639", 0x1c),
 144 };
 145 static struct i2c_board_info __initdata rt5645_board_info = {
 146         I2C_BOARD_INFO("rt5645", 0x1a),
 147 };
 148
 149 static __initdata struct tegra_clk_init_table ardbeg_clk_init_table[] = {
 150         /* name         parent          rate            enabled */
 151         { "pll_m",      NULL,           0,              false},
 152         { "hda",        "pll_p",        108000000,      false},
 153         { "hda2codec_2x", "pll_p",      48000000,       false},
 154         { "pwm",        "pll_p",        3187500,        false},
 155         { "i2s1",       "pll_a_out0",   0,              false},
 156         { "i2s3",       "pll_a_out0",   0,              false},
 157         { "i2s4",       "pll_a_out0",   0,              false},
 158         { "spdif_out",  "pll_a_out0",   0,              false},
 159         { "d_audio",    "clk_m",        12000000,       false},
 160         { "dam0",       "clk_m",        12000000,       false},
 161         { "dam1",       "clk_m",        12000000,       false},
 162         { "dam2",       "clk_m",        12000000,       false},
 163         { "audio1",     "i2s1_sync",    0,              false},
 164         { "audio3",     "i2s3_sync",    0,              false},
 165         { "vi_sensor",  "pll_p",        150000000,      false},
 166         { "vi_sensor2", "pll_p",        150000000,      false},
 167         { "cilab",      "pll_p",        150000000,      false},
 168         { "cilcd",      "pll_p",        150000000,      false},
 169         { "cile",       "pll_p",        150000000,      false},
 170         { "i2c1",       "pll_p",        3200000,        false},
 171         { "i2c2",       "pll_p",        3200000,        false},
 172         { "i2c3",       "pll_p",        3200000,        false},
 173         { "i2c4",       "pll_p",        3200000,        false},
 174         { "i2c5",       "pll_p",        3200000,        false},
 175         { "sbc1",       "pll_p",        25000000,       false},
 176         { "sbc2",       "pll_p",        25000000,       false},
 177         { "sbc3",       "pll_p",        25000000,       false},
 178         { "sbc4",       "pll_p",        25000000,       false},
 179         { "sbc5",       "pll_p",        25000000,       false},
 180         { "sbc6",       "pll_p",        25000000,       false},
 181         { "uarta",      "pll_p",        408000000,      false},
 182         { "uartb",      "pll_p",        408000000,      false},
 183         { "uartc",      "pll_p",        408000000,      false},
 184         { "uartd",      "pll_p",        408000000,      false},
 185         { NULL,         NULL,           0,              0},
 186 };
 187
 188 static struct i2c_hid_platform_data i2c_keyboard_pdata = {
 189         .hid_descriptor_address = 0x0,
 190 };
 191
 192 static struct i2c_board_info __initdata i2c_keyboard_board_info = {
 193         I2C_BOARD_INFO("hid", 0x3B),
 194         .platform_data  = &i2c_keyboard_pdata,
 195 };
 196
 197 static struct i2c_hid_platform_data i2c_touchpad_pdata = {
 198         .hid_descriptor_address = 0x20,
 199 };
 200
 201 static struct i2c_board_info __initdata i2c_touchpad_board_info = {
 202         I2C_BOARD_INFO("hid", 0x2C),
 203         .platform_data  = &i2c_touchpad_pdata,
 204 };
 205
 206 static void ardbeg_i2c_init(void)
 207 {
 208         struct board_info board_info;
 209         tegra_get_board_info(&board_info);
 210
 211         i2c_register_board_info(0, &rt5639_board_info, 1);
 212         i2c_register_board_info(0, &rt5645_board_info, 1);
 213
 214         if (board_info.board_id == BOARD_PM359 ||
 215                         board_info.board_id == BOARD_PM358 ||
 216                         board_info.board_id == BOARD_PM363) {
 217                 i2c_keyboard_board_info.irq = gpio_to_irq(I2C_KB_IRQ);
 218                 i2c_register_board_info(1, &i2c_keyboard_board_info , 1);
 219
 220                 i2c_touchpad_board_info.irq = gpio_to_irq(I2C_TP_IRQ);
 221                 i2c_register_board_info(1, &i2c_touchpad_board_info , 1);
 222         }
 223 }
 224
 225 #ifndef CONFIG_USE_OF
 226 static struct platform_device *ardbeg_uart_devices[] __initdata = {
 227         &tegra_uarta_device,
 228         &tegra_uartb_device,
 229         &tegra_uartc_device,
 230 };
 231
 232 static struct tegra_serial_platform_data ardbeg_uarta_pdata = {
 233         .dma_req_selector = 8,
 234         .modem_interrupt = false,
 235 };
 236
 237 static struct tegra_serial_platform_data ardbeg_uartb_pdata = {
 238         .dma_req_selector = 9,
 239         .modem_interrupt = false,
 240 };
 241
 242 static struct tegra_serial_platform_data ardbeg_uartc_pdata = {
 243         .dma_req_selector = 10,
 244         .modem_interrupt = false,
 245 };
 246 #endif
 247
 248 static struct tegra_serial_platform_data ardbeg_uartd_pdata = {
 249         .dma_req_selector = 19,
 250         .modem_interrupt = false,
 251 };
 252
 253 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5639 = {
 254         .gpio_hp_det = TEGRA_GPIO_HP_DET,
 255         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
 256         .gpio_spkr_en = -1,
 257         .gpio_int_mic_en = -1,
 258         .gpio_ext_mic_en = -1,
 259         .gpio_hp_mute = -1,
 260         .gpio_codec1 = -1,
 261         .gpio_codec2 = -1,
 262         .gpio_codec3 = -1,
 263         .edp_support = true,
 264         .edp_states = {1530, 765, 0},
 265         .i2s_param[HIFI_CODEC]       = {
 266                 .audio_port_id = 1,
 267                 .is_i2s_master = 0,
 268                 .i2s_mode = TEGRA_DAIFMT_I2S,
 269         },
 270         .i2s_param[BT_SCO] = {
 271                 .audio_port_id = 3,
 272                 .is_i2s_master = 1,
 273                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
 274         },
 275 };
 276
 277 static struct tegra_asoc_platform_data ardbeg_audio_pdata_rt5645 = {
 278         .gpio_hp_det = TEGRA_GPIO_HP_DET,
 279         .gpio_ldo1_en = TEGRA_GPIO_LDO_EN,
 280         .gpio_spkr_en = -1,
 281         .gpio_int_mic_en = -1,
 282         .gpio_ext_mic_en = -1,
 283         .gpio_hp_mute = -1,
 284         .gpio_codec1 = -1,
 285         .gpio_codec2 = -1,
 286         .gpio_codec3 = -1,
 287         .i2s_param[HIFI_CODEC]       = {
 288                 .audio_port_id = 1,
 289                 .is_i2s_master = 0,
 290                 .i2s_mode = TEGRA_DAIFMT_I2S,
 291         },
 292         .i2s_param[BT_SCO] = {
 293                 .audio_port_id = 3,
 294                 .is_i2s_master = 1,
 295                 .i2s_mode = TEGRA_DAIFMT_DSP_A,
 296         },
 297 };
 298
 299 static void ardbeg_audio_init(void)
 300 {
 301         struct board_info board_info;
 302         tegra_get_board_info(&board_info);
 303         if (board_info.board_id == BOARD_PM359 ||
 304                         board_info.board_id == BOARD_PM358 ||
 305                         board_info.board_id == BOARD_PM363) {
 306                 /*Laguna*/
 307                 ardbeg_audio_pdata_rt5645.gpio_hp_det =
 308                         TEGRA_GPIO_HP_DET;
 309                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high = 1;
 310                 if (board_info.board_id != BOARD_PM363)
 311                         ardbeg_audio_pdata_rt5645.gpio_ldo1_en = -1;
 312         } else {
 313                 /*Ardbeg*/
 314                 ardbeg_audio_pdata_rt5645.gpio_hp_det =
 315                         TEGRA_GPIO_HP_DET;
 316                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high = 0;
 317                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en =
 318                         TEGRA_GPIO_LDO_EN;
 319         }
 320
 321         ardbeg_audio_pdata_rt5639.gpio_hp_det =
 322                 ardbeg_audio_pdata_rt5645.gpio_hp_det;
 323
 324         ardbeg_audio_pdata_rt5639.gpio_hp_det_active_high =
 325                 ardbeg_audio_pdata_rt5645.gpio_hp_det_active_high;
 326
 327         ardbeg_audio_pdata_rt5639.gpio_ldo1_en =
 328                 ardbeg_audio_pdata_rt5645.gpio_ldo1_en;
 329
 330         ardbeg_audio_pdata_rt5639.codec_name = "rt5639.0-001c";
 331         ardbeg_audio_pdata_rt5639.codec_dai_name = "rt5639-aif1";
 332         ardbeg_audio_pdata_rt5645.codec_name = "rt5645.0-001a";
 333         ardbeg_audio_pdata_rt5645.codec_dai_name = "rt5645-aif1";
 334 }
 335
 336 static struct platform_device ardbeg_audio_device_rt5645 = {
 337         .name = "tegra-snd-rt5645",
 338         .id = 0,
 339         .dev = {
 340                 .platform_data = &ardbeg_audio_pdata_rt5645,
 341         },
 342 };
 343
 344 static struct platform_device ardbeg_audio_device_rt5639 = {
 345         .name = "tegra-snd-rt5639",
 346         .id = 0,
 347         .dev = {
 348                 .platform_data = &ardbeg_audio_pdata_rt5639,
 349         },
 350 };
 351
 352 static void __init ardbeg_uart_init(void)
 353 {
 354
 355 #ifndef CONFIG_USE_OF
 356         tegra_uarta_device.dev.platform_data = &ardbeg_uarta_pdata;
 357         tegra_uartb_device.dev.platform_data = &ardbeg_uartb_pdata;
 358         tegra_uartc_device.dev.platform_data = &ardbeg_uartc_pdata;
 359         platform_add_devices(ardbeg_uart_devices,
 360                         ARRAY_SIZE(ardbeg_uart_devices));
 361 #endif
 362         tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
 363         if (!is_tegra_debug_uartport_hs()) {
 364                 int debug_port_id = uart_console_debug_init(3);
 365                 if (debug_port_id < 0)
 366                         return;
 367
 368 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
 369                 tegra_serial_debug_init_irq_mode(TEGRA_UARTD_BASE, INT_UARTD, NULL, -1, -1);
 370 #else
 371                 platform_device_register(uart_console_debug_device);
 372 #endif
 373         } else {
 374                 tegra_uartd_device.dev.platform_data = &ardbeg_uartd_pdata;
 375                 platform_device_register(&tegra_uartd_device);
 376         }
 377 }
 378
 379 static struct resource tegra_rtc_resources[] = {
 380         [0] = {
 381                 .start = TEGRA_RTC_BASE,
 382                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
 383                 .flags = IORESOURCE_MEM,
 384         },
 385         [1] = {
 386                 .start = INT_RTC,
 387                 .end = INT_RTC,
 388                 .flags = IORESOURCE_IRQ,
 389         },
 390 };
 391
 392 static struct platform_device tegra_rtc_device = {
 393         .name = "tegra_rtc",
 394         .id   = -1,
 395         .resource = tegra_rtc_resources,
 396         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
 397 };
 398
 399 #ifdef CONFIG_SATA_AHCI_TEGRA
 400 static struct tegra_ahci_platform_data tegra_ahci_platform_data0 = {
 401         .gen2_rx_eq = -1,
 402         .pexp_gpio = PMU_TCA6416_GPIO(9),
 403 };
 404
 405 static void ardbeg_sata_init(void)
 406 {
 407         struct board_info board_info;
 408
 409         tegra_get_board_info(&board_info);
 410         if (board_info.board_id == BOARD_PM363)
 411                 tegra_ahci_platform_data0.pexp_gpio = -1;
 412
 413         tegra_sata_device.dev.platform_data = &tegra_ahci_platform_data0;
 414         platform_device_register(&tegra_sata_device);
 415 }
 416 #else
 417 static void ardbeg_sata_init(void) { }
 418 #endif
 419
 420 static struct tegra_pci_platform_data laguna_pcie_platform_data = {
 421         .port_status[0] = 1,
 422         .port_status[1] = 1,
 423         .use_dock_detect        = 1,
 424         .gpio   = TEGRA_GPIO_PO1,
 425         .gpio_x1_slot   = PMU_TCA6416_GPIO(8),
 426         .board_id       = BOARD_PM358,
 427 };
 428
 429 static void laguna_pcie_init(void)
 430 {
 431         struct board_info board_info;
 432
 433         tegra_get_board_info(&board_info);
 434         /* root port 1(x1 slot) is supported only on of ERS-S board */
 435         if (board_info.board_id == BOARD_PM358 ||
 436                 board_info.board_id == BOARD_PM363)
 437                         laguna_pcie_platform_data.port_status[1] = 0;
 438
 439         laguna_pcie_platform_data.board_id = board_info.board_id;
 440         tegra_pci_device.dev.platform_data = &laguna_pcie_platform_data;
 441         platform_device_register(&tegra_pci_device);
 442 }
 443
 444 static struct platform_device *ardbeg_devices[] __initdata = {
 445         &tegra_pmu_device,
 446         &tegra_rtc_device,
 447         &tegra_udc_device,
 448 #if defined(CONFIG_TEGRA_WATCHDOG)
 449         &tegra_wdt0_device,
 450 #endif
 451 #if defined(CONFIG_TEGRA_AVP)
 452         &tegra_avp_device,
 453 #endif
 454 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
 455         &tegra12_se_device,
 456 #endif
 457         &tegra_ahub_device,
 458         &tegra_dam_device0,
 459         &tegra_dam_device1,
 460         &tegra_dam_device2,
 461         &tegra_i2s_device1,
 462         &tegra_i2s_device3,
 463         &tegra_i2s_device4,
 464         &ardbeg_audio_device_rt5639,
 465         &tegra_spdif_device,
 466         &spdif_dit_device,
 467         &bluetooth_dit_device,
 468         &tegra_hda_device,
 469 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
 470         &tegra_aes_device,
 471 #endif
 472 };
 473
 474 static struct tegra_usb_platform_data tegra_udc_pdata = {
 475         .port_otg = true,
 476         .has_hostpc = true,
 477         .unaligned_dma_buf_supported = false,
 478         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 479         .op_mode = TEGRA_USB_OPMODE_DEVICE,
 480         .u_data.dev = {
 481                 .vbus_pmu_irq = 0,
 482                 .vbus_gpio = -1,
 483                 .charging_supported = false,
 484                 .remote_wakeup_supported = false,
 485         },
 486         .u_cfg.utmi = {
 487                 .hssync_start_delay = 0,
 488                 .elastic_limit = 16,
 489                 .idle_wait_delay = 17,
 490                 .term_range_adj = 6,
 491                 .xcvr_setup = 8,
 492                 .xcvr_lsfslew = 2,
 493                 .xcvr_lsrslew = 2,
 494                 .xcvr_setup_offset = 0,
 495                 .xcvr_use_fuses = 1,
 496         },
 497 };
 498
 499 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
 500         .port_otg = true,
 501         .has_hostpc = true,
 502         .unaligned_dma_buf_supported = false,
 503         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 504         .op_mode = TEGRA_USB_OPMODE_HOST,
 505         .u_data.host = {
 506                 .vbus_gpio = -1,
 507                 .hot_plug = false,
 508                 .remote_wakeup_supported = true,
 509                 .power_off_on_suspend = true,
 510         },
 511         .u_cfg.utmi = {
 512                 .hssync_start_delay = 0,
 513                 .elastic_limit = 16,
 514                 .idle_wait_delay = 17,
 515                 .term_range_adj = 6,
 516                 .xcvr_setup = 15,
 517                 .xcvr_lsfslew = 0,
 518                 .xcvr_lsrslew = 3,
 519                 .xcvr_setup_offset = 0,
 520                 .xcvr_use_fuses = 1,
 521                 .vbus_oc_map = 0x4,
 522                 .xcvr_hsslew_lsb = 2,
 523         },
 524 };
 525
 526 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
 527         .port_otg = false,
 528         .has_hostpc = true,
 529         .unaligned_dma_buf_supported = false,
 530         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 531         .op_mode = TEGRA_USB_OPMODE_HOST,
 532         .u_data.host = {
 533                 .vbus_gpio = -1,
 534                 .hot_plug = false,
 535                 .remote_wakeup_supported = true,
 536                 .power_off_on_suspend = true,
 537         },
 538         .u_cfg.utmi = {
 539                 .hssync_start_delay = 0,
 540                 .elastic_limit = 16,
 541                 .idle_wait_delay = 17,
 542                 .term_range_adj = 6,
 543                 .xcvr_setup = 8,
 544                 .xcvr_lsfslew = 2,
 545                 .xcvr_lsrslew = 2,
 546                 .xcvr_setup_offset = 0,
 547                 .xcvr_use_fuses = 1,
 548                 .vbus_oc_map = 0x5,
 549         },
 550 };
 551
 552 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
 553         .port_otg = false,
 554         .has_hostpc = true,
 555         .unaligned_dma_buf_supported = false,
 556         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
 557         .op_mode = TEGRA_USB_OPMODE_HOST,
 558         .u_data.host = {
 559                 .vbus_gpio = -1,
 560                 .hot_plug = false,
 561                 .remote_wakeup_supported = true,
 562                 .power_off_on_suspend = true,
 563         },
 564         .u_cfg.utmi = {
 565         .hssync_start_delay = 0,
 566                 .elastic_limit = 16,
 567                 .idle_wait_delay = 17,
 568                 .term_range_adj = 6,
 569                 .xcvr_setup = 8,
 570                 .xcvr_lsfslew = 2,
 571                 .xcvr_lsrslew = 2,
 572                 .xcvr_setup_offset = 0,
 573                 .xcvr_use_fuses = 1,
 574                 .vbus_oc_map = 0x5,
 575         },
 576 };
 577
 578 static struct gpio modem_gpios[] = { /* Bruce modem */
 579         {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"},
 580         {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"},
 581         {MDM_SAR0, GPIOF_OUT_INIT_LOW, "MODEM SAR0"},
 582 };
 583
 584 static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = {
 585         .port_otg = false,
 586         .has_hostpc = true,
 587         .unaligned_dma_buf_supported = false,
 588         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
 589         .op_mode = TEGRA_USB_OPMODE_HOST,
 590         .u_data.host = {
 591                 .vbus_gpio = -1,
 592                 .hot_plug = false,
 593                 .remote_wakeup_supported = true,
 594                 .power_off_on_suspend = true,
 595         },
 596 };
 597
 598 static struct tegra_usb_platform_data tegra_ehci2_hsic_smsc_hub_pdata = {
 599         .port_otg = false,
 600         .has_hostpc = true,
 601         .unaligned_dma_buf_supported = false,
 602         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
 603         .op_mode        = TEGRA_USB_OPMODE_HOST,
 604         .u_data.host = {
 605                 .vbus_gpio = -1,
 606                 .hot_plug = false,
 607                 .remote_wakeup_supported = true,
 608                 .power_off_on_suspend = true,
 609         },
 610 };
 611
 612
 613 static struct tegra_usb_otg_data tegra_otg_pdata = {
 614         .ehci_device = &tegra_ehci1_device,
 615         .ehci_pdata = &tegra_ehci1_utmi_pdata,
 616 };
 617
 618 static void ardbeg_usb_init(void)
 619 {
 620         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 621         int modem_id = tegra_get_modem_id();
 622         struct board_info bi;
 623
 624         if (board_info.board_id == BOARD_PM359 ||
 625                         board_info.board_id == BOARD_PM358 ||
 626                         board_info.board_id == BOARD_PM363) {
 627                 /* Laguna */
 628                 /* Host cable is detected through AMS PMU Interrupt */
 629                 tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 630                 tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 631                 tegra_otg_pdata.id_extcon_dev_name = "as3722-extcon";
 632         } else {
 633                 /* Ardbeg */
 634                 tegra_get_pmu_board_info(&bi);
 635
 636                 switch (bi.board_id) {
 637                 case BOARD_E1733:
 638                         /* Host cable is detected through PMU Interrupt */
 639                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 640                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 641                         tegra_otg_pdata.id_extcon_dev_name = "as3722-extcon";
 642                         break;
 643                 case BOARD_E1736:
 644                 case BOARD_E1769:
 645                 case BOARD_E1735:
 646                         /* Device cable is detected through PMU Interrupt */
 647                         tegra_udc_pdata.support_pmu_vbus = true;
 648                         tegra_ehci1_utmi_pdata.support_pmu_vbus = true;
 649                         tegra_otg_pdata.vbus_extcon_dev_name = "palmas-extcon";
 650                         /* Host cable is detected through PMU Interrupt */
 651                         tegra_udc_pdata.id_det_type = TEGRA_USB_PMU_ID;
 652                         tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_PMU_ID;
 653                         tegra_otg_pdata.id_extcon_dev_name = "palmas-extcon";
 654                 }
 655         }
 656
 657         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
 658                 tegra_otg_pdata.is_xhci = false;
 659                 tegra_udc_pdata.u_data.dev.is_xhci = false;
 660         } else {
 661                 tegra_otg_pdata.is_xhci = true;
 662                 tegra_udc_pdata.u_data.dev.is_xhci = true;
 663         }
 664         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
 665         platform_device_register(&tegra_otg_device);
 666         /* Setup the udc platform data */
 667         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
 668
 669         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
 670                 if (!modem_id) {
 671                         tegra_ehci2_device.dev.platform_data =
 672                                 &tegra_ehci2_utmi_pdata;
 673                         platform_device_register(&tegra_ehci2_device);
 674                 }
 675         }
 676         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
 677                 tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
 678                 platform_device_register(&tegra_ehci3_device);
 679         }
 680 }
 681
 682 static struct tegra_xusb_board_data xusb_bdata = {
 683         .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_SS_P1 |
 684                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_USB2_P2,
 685         .supply = {
 686                 .utmi_vbuses = {
 687                         "usb_vbus0", "usb_vbus1", "usb_vbus2"
 688                 },
 689                 .s3p3v = "hvdd_usb",
 690                 .s1p8v = "avdd_pll_utmip",
 691                 .vddio_hsic = "vddio_hsic",
 692                 .s1p05v = "avddio_usb",
 693         },
 694
 695         .hsic[0] = {
 696                 .rx_strobe_trim = 0x1,
 697                 .rx_data_trim = 0x1,
 698                 .tx_rtune_n = 0x8,
 699                 .tx_rtune_p = 0xa,
 700                 .tx_slew_n = 0,
 701                 .tx_slew_p = 0,
 702                 .auto_term_en = true,
 703                 .strb_trim_val = 0x22,
 704                 .pretend_connect = false,
 705         },
 706         .uses_external_pmic = false,
 707 };
 708
 709 static void ardbeg_xusb_init(void)
 710 {
 711         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 712
 713         xusb_bdata.lane_owner = (u8) tegra_get_lane_owner_info();
 714
 715         if (board_info.board_id == BOARD_PM359 ||
 716                         board_info.board_id == BOARD_PM358 ||
 717                         board_info.board_id == BOARD_PM363) {
 718                 /* Laguna */
 719                 pr_info("Laguna ERS. 0x%x\n", board_info.board_id);
 720                 xusb_bdata.gpio_controls_muxed_ss_lanes = true;
 721                 /* D[0:15] = gpio number and D[16:31] = output value */
 722                 xusb_bdata.gpio_ss1_sata = PMU_TCA6416_GPIO(9) | (0 << 16);
 723                 xusb_bdata.ss_portmap = (TEGRA_XUSB_SS_PORT_MAP_USB2_P0 << 0) |
 724                         (TEGRA_XUSB_SS_PORT_MAP_USB2_P1 << 4);
 725
 726                 if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 727                         xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
 728                                 TEGRA_XUSB_SS_P0);
 729
 730                 if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 731                         xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
 732                                 TEGRA_XUSB_SS_P1 | TEGRA_XUSB_USB2_P2);
 733
 734                 /* FIXME Add for UTMIP2 when have odmdata assigend */
 735         } else {
 736                 /* Ardbeg */
 737                 xusb_bdata.gpio_controls_muxed_ss_lanes = false;
 738
 739                 if (board_info.board_id == BOARD_E1781) {
 740                         pr_info("Shield ERS-S. 0x%x\n", board_info.board_id);
 741                         /* Shield ERS-S */
 742                         xusb_bdata.ss_portmap =
 743                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P1 << 0) |
 744                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P2 << 4);
 745
 746                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 747                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
 748
 749                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 750                                 xusb_bdata.portmap &= ~(
 751                                         TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0 |
 752                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
 753                 } else {
 754                         pr_info("Shield ERS 0x%x\n", board_info.board_id);
 755                         /* Shield ERS */
 756                         xusb_bdata.ss_portmap =
 757                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P0 << 0) |
 758                                 (TEGRA_XUSB_SS_PORT_MAP_USB2_P2 << 4);
 759
 760                         if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
 761                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P0 |
 762                                         TEGRA_XUSB_SS_P0);
 763
 764                         if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
 765                                 xusb_bdata.portmap &= ~(TEGRA_XUSB_USB2_P1 |
 766                                         TEGRA_XUSB_USB2_P2 | TEGRA_XUSB_SS_P1);
 767                 }
 768                 /* FIXME Add for UTMIP2 when have odmdata assigend */
 769         }
 770
 771         if (usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)
 772                 xusb_bdata.portmap |= TEGRA_XUSB_HSIC_P0;
 773
 774         if (usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)
 775                 xusb_bdata.portmap |= TEGRA_XUSB_HSIC_P1;
 776
 777         if (xusb_bdata.portmap)
 778                 tegra_xusb_init(&xusb_bdata);
 779 }
 780
 781 static int baseband_init(void)
 782 {
 783         int ret;
 784
 785         ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios));
 786         if (ret) {
 787                 pr_warn("%s:gpio request failed\n", __func__);
 788                 return ret;
 789         }
 790
 791         /* enable pull-down for MDM_COLD_BOOT */
 792         tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4,
 793                                     TEGRA_PUPD_PULL_DOWN);
 794
 795         /* export GPIO for user space access through sysfs */
 796         gpio_export(MDM_RST, false);
 797         gpio_export(MDM_SAR0, false);
 798
 799         return 0;
 800 }
 801
 802 static const struct tegra_modem_operations baseband_operations = {
 803         .init = baseband_init,
 804 };
 805
 806 static struct tegra_usb_modem_power_platform_data baseband_pdata = {
 807         .ops = &baseband_operations,
 808         .regulator_name = "vdd_wwan_mdm",
 809         .wake_gpio = -1,
 810         .boot_gpio = MDM_COLDBOOT,
 811         .boot_irq_flags = IRQF_TRIGGER_RISING |
 812                                     IRQF_TRIGGER_FALLING |
 813                                     IRQF_ONESHOT,
 814         .autosuspend_delay = 2000,
 815         .short_autosuspend_delay = 50,
 816         .tegra_ehci_device = &tegra_ehci2_device,
 817         .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata,
 818 };
 819
 820 static struct platform_device icera_bruce_device = {
 821         .name = "tegra_usb_modem_power",
 822         .id = -1,
 823         .dev = {
 824                 .platform_data = &baseband_pdata,
 825         },
 826 };
 827
 828 static void ardbeg_modem_init(void)
 829 {
 830         int modem_id = tegra_get_modem_id();
 831         struct board_info board_info;
 832         struct board_info pmu_board_info;
 833         int usb_port_owner_info = tegra_get_usb_port_owner_info();
 834
 835         tegra_get_board_info(&board_info);
 836         tegra_get_pmu_board_info(&pmu_board_info);
 837         pr_info("%s: modem_id = %d\n", __func__, modem_id);
 838
 839         switch (modem_id) {
 840         case TEGRA_BB_BRUCE:
 841                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
 842                         /* Set specific USB wake source for Ardbeg */
 843                         if (board_info.board_id == BOARD_E1780)
 844                                 tegra_set_wake_source(42, INT_USB2);
 845                         if (pmu_board_info.board_id == BOARD_E1736 ||
 846                                 pmu_board_info.board_id == BOARD_E1769)
 847                                 baseband_pdata.regulator_name = NULL;
 848                         platform_device_register(&icera_bruce_device);
 849                 }
 850                 break;
 851         case TEGRA_BB_HSIC_HUB: /* HSIC hub */
 852                 if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) {
 853                         tegra_ehci2_device.dev.platform_data =
 854                                 &tegra_ehci2_hsic_smsc_hub_pdata;
 855                         /* Set specific USB wake source for Ardbeg */
 856                         if (board_info.board_id == BOARD_E1780)
 857                                 tegra_set_wake_source(42, INT_USB2);
 858                         platform_device_register(&tegra_ehci2_device);
 859                 } else
 860                         xusb_bdata.hsic[0].pretend_connect = true;
 861                 break;
 862         default:
 863                 return;
 864         }
 865 }
 866
 867 #ifndef CONFIG_USE_OF
 868 static struct platform_device *ardbeg_spi_devices[] __initdata = {
 869         &tegra11_spi_device1,
 870         &tegra11_spi_device4,
 871 };
 872
 873 static struct tegra_spi_platform_data ardbeg_spi1_pdata = {
 874         .dma_req_sel            = 15,
 875         .spi_max_frequency      = 25000000,
 876         .clock_always_on        = false,
 877 };
 878
 879 static struct tegra_spi_platform_data ardbeg_spi4_pdata = {
 880         .dma_req_sel            = 18,
 881         .spi_max_frequency      = 25000000,
 882         .clock_always_on        = false,
 883 };
 884
 885 static void __init ardbeg_spi_init(void)
 886 {
 887         tegra11_spi_device1.dev.platform_data = &ardbeg_spi1_pdata;
 888         tegra11_spi_device4.dev.platform_data = &ardbeg_spi4_pdata;
 889         platform_add_devices(ardbeg_spi_devices,
 890                         ARRAY_SIZE(ardbeg_spi_devices));
 891 }
 892 #else
 893 static void __init ardbeg_spi_init(void)
 894 {
 895 }
 896 #endif
 897
 898 #ifdef CONFIG_USE_OF
 899 static struct of_dev_auxdata ardbeg_auxdata_lookup[] __initdata = {
 900         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d400, "spi-tegra114.0",
 901                                 NULL),
 902         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d600, "spi-tegra114.1",
 903                                 NULL),
 904         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000d800, "spi-tegra114.2",
 905                                 NULL),
 906         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000da00, "spi-tegra114.3",
 907                                 NULL),
 908         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000dc00, "spi-tegra114.4",
 909                                 NULL),
 910         OF_DEV_AUXDATA("nvidia,tegra114-spi", 0x7000de00, "spi-tegra114.5",
 911                                 NULL),
 912         OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
 913                                 NULL),
 914         OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
 915                 NULL),
 916         OF_DEV_AUXDATA("nvidia,tegra124-gk20a", 0x538F0000, "gk20a", NULL),
 917 #ifdef CONFIG_ARCH_TEGRA_VIC
 918         OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03", NULL),
 919 #endif
 920         OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
 921                 NULL),
 922         OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi", NULL),
 923         OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp", NULL),
 924         OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
 925         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0",
 926                                 NULL),
 927         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1",
 928                                 NULL),
 929         OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2",
 930                                 NULL),
 931         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c000, "tegra12-i2c.0",
 932                                 NULL),
 933         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c400, "tegra12-i2c.1",
 934                                 NULL),
 935         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c500, "tegra12-i2c.2",
 936                                 NULL),
 937         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000c700, "tegra12-i2c.3",
 938                                 NULL),
 939         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000d000, "tegra12-i2c.4",
 940                                 NULL),
 941         OF_DEV_AUXDATA("nvidia,tegra124-i2c", 0x7000d100, "tegra12-i2c.5",
 942                                 NULL),
 943         {}
 944 };
 945 #endif
 946
 947 struct maxim_sti_pdata maxim_sti_pdata = {
 948         .touch_fusion         = "/vendor/bin/touch_fusion",
 949         .config_file          = "/vendor/firmware/touch_fusion.cfg",
 950         .fw_name              = "maxim_fp35.bin",
 951         .nl_family            = TF_FAMILY_NAME,
 952         .nl_mc_groups         = 5,
 953         .chip_access_method   = 2,
 954         .default_reset_state  = 0,
 955         .tx_buf_size          = 4100,
 956         .rx_buf_size          = 4100,
 957         .gpio_reset           = TOUCH_GPIO_RST_MAXIM_STI_SPI,
 958         .gpio_irq             = TOUCH_GPIO_IRQ_MAXIM_STI_SPI
 959 };
 960
 961 static struct tegra_spi_device_controller_data maxim_dev_cdata = {
 962         .rx_clk_tap_delay = 0,
 963         .is_hw_based_cs = true,
 964         .tx_clk_tap_delay = 0,
 965 };
 966
 967 struct spi_board_info maxim_sti_spi_board = {
 968         .modalias = MAXIM_STI_NAME,
 969         .bus_num = TOUCH_SPI_ID,
 970         .chip_select = TOUCH_SPI_CS,
 971         .max_speed_hz = 12 * 1000 * 1000,
 972         .mode = SPI_MODE_0,
 973         .platform_data = &maxim_sti_pdata,
 974         .controller_data = &maxim_dev_cdata,
 975 };
 976
 977 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
 978         /* name         parent          rate            enabled */
 979         { "extern2",    "pll_p",        41000000,       false},
 980         { "clk_out_2",  "extern2",      40800000,       false},
 981         { NULL,         NULL,           0,              0},
 982 };
 983
 984 static struct rm_spi_ts_platform_data rm31080ts_ardbeg_data = {
 985         .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
 986         .config = 0,
 987         .platform_id = RM_PLATFORM_A010,
 988         .name_of_clock = "clk_out_2",
 989         .name_of_clock_con = "extern2",
 990 };
 991
 992 static struct tegra_spi_device_controller_data dev_cdata = {
 993         .rx_clk_tap_delay = 0,
 994         .tx_clk_tap_delay = 16,
 995 };
 996
 997 static struct spi_board_info rm31080a_ardbeg_spi_board[1] = {
 998         {
 999                 .modalias = "rm_ts_spidev",
1000                 .bus_num = TOUCH_SPI_ID,
1001                 .chip_select = TOUCH_SPI_CS,
1002                 .max_speed_hz = 12 * 1000 * 1000,
1003                 .mode = SPI_MODE_0,
1004                 .controller_data = &dev_cdata,
1005                 .platform_data = &rm31080ts_ardbeg_data,
1006         },
1007 };
1008
1009 static int __init ardbeg_touch_init(void)
1010 {
1011         if (tegra_get_touch_vendor_id() == MAXIM_TOUCH) {
1012                 pr_info("%s init maxim touch\n", __func__);
1013 #if defined(CONFIG_TOUCHSCREEN_MAXIM_STI) || \
1014         defined(CONFIG_TOUCHSCREEN_MAXIM_STI_MODULE)
1015                 (void)touch_init_maxim_sti(&maxim_sti_spi_board);
1016 #endif
1017         } else if (tegra_get_touch_vendor_id() == RAYDIUM_TOUCH) {
1018                 pr_info("%s init raydium touch\n", __func__);
1019                 tegra_clk_init_from_table(touch_clk_init_table);
1020                 rm31080a_ardbeg_spi_board[0].irq =
1021                         gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1022                 touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1023                                 TOUCH_GPIO_RST_RAYDIUM_SPI,
1024                                 &rm31080ts_ardbeg_data,
1025                                 &rm31080a_ardbeg_spi_board[0],
1026                                 ARRAY_SIZE(rm31080a_ardbeg_spi_board));
1027         }
1028         return 0;
1029 }
1030
1031 static void __init ardbeg_sysedp_init(void)
1032 {
1033         struct board_info bi;
1034
1035         tegra_get_board_info(&bi);
1036
1037         switch (bi.board_id) {
1038         case BOARD_E1780:
1039                 if (bi.sku == 1100) {
1040                         tn8_new_sysedp_init();
1041                 }
1042                 break;
1043         case BOARD_PM358:
1044         case BOARD_PM359:
1045         default:
1046                 break;
1047         }
1048 }
1049
1050 static void __init ardbeg_sysedp_dynamic_capping_init(void)
1051 {
1052         struct board_info bi;
1053
1054         tegra_get_board_info(&bi);
1055
1056         switch (bi.board_id) {
1057         case BOARD_E1780:
1058                 if (bi.sku == 1100)
1059                         tn8_sysedp_dynamic_capping_init();
1060                 break;
1061         case BOARD_PM358:
1062         case BOARD_PM359:
1063         default:
1064                 break;
1065         }
1066 }
1067
1068 static void __init ardbeg_sysedp_batmon_init(void)
1069 {
1070         struct board_info bi;
1071
1072         if (!IS_ENABLED(CONFIG_SYSEDP_FRAMEWORK))
1073                 return;
1074
1075         tegra_get_board_info(&bi);
1076
1077         switch (bi.board_id) {
1078         case BOARD_E1780:
1079                 if (bi.sku == 1100)
1080                         tn8_sysedp_batmon_init();
1081                 break;
1082         case BOARD_PM358:
1083         case BOARD_PM359:
1084         default:
1085                 break;
1086         }
1087 }
1088
1089
1090
1091 static void __init edp_init(void)
1092 {
1093         struct board_info bi;
1094
1095         tegra_get_board_info(&bi);
1096
1097         switch (bi.board_id) {
1098         case BOARD_E1780:
1099                 if (bi.sku == 1100)
1100                         tn8_edp_init();
1101                 else
1102                         ardbeg_edp_init();
1103                 break;
1104         case BOARD_PM358:
1105         case BOARD_PM359:
1106                         laguna_edp_init();
1107                         break;
1108         default:
1109                         ardbeg_edp_init();
1110                         break;
1111         }
1112 }
1113
1114 static void __init tegra_ardbeg_early_init(void)
1115 {
1116         ardbeg_sysedp_init();
1117         tegra_clk_init_from_table(ardbeg_clk_init_table);
1118         tegra_clk_verify_parents();
1119         if (of_machine_is_compatible("nvidia,laguna"))
1120                 tegra_soc_device_init("laguna");
1121         else if (of_machine_is_compatible("nvidia,tn8"))
1122                 tegra_soc_device_init("tn8");
1123         else
1124                 tegra_soc_device_init("ardbeg");
1125 }
1126
1127 static struct tegra_dtv_platform_data ardbeg_dtv_pdata = {
1128         .dma_req_selector = 11,
1129 };
1130
1131 static void __init ardbeg_dtv_init(void)
1132 {
1133         tegra_dtv_device.dev.platform_data = &ardbeg_dtv_pdata;
1134         platform_device_register(&tegra_dtv_device);
1135 }
1136
1137 static struct tegra_io_dpd pexbias_io = {
1138         .name                   = "PEX_BIAS",
1139         .io_dpd_reg_index       = 0,
1140         .io_dpd_bit             = 4,
1141 };
1142 static struct tegra_io_dpd pexclk1_io = {
1143         .name                   = "PEX_CLK1",
1144         .io_dpd_reg_index       = 0,
1145         .io_dpd_bit             = 5,
1146 };
1147 static struct tegra_io_dpd pexclk2_io = {
1148         .name                   = "PEX_CLK2",
1149         .io_dpd_reg_index       = 0,
1150         .io_dpd_bit             = 6,
1151 };
1152
1153 static void __init tegra_ardbeg_late_init(void)
1154 {
1155         struct board_info board_info;
1156         tegra_get_board_info(&board_info);
1157         pr_info("board_info: id:sku:fab:major:minor = 0x%04x:0x%04x:0x%02x:0x%02x:0x%02x\n",
1158                 board_info.board_id, board_info.sku,
1159                 board_info.fab, board_info.major_revision,
1160                 board_info.minor_revision);
1161         platform_device_register(&tegra_pinmux_device);
1162         if (board_info.board_id == BOARD_PM359 ||
1163                         board_info.board_id == BOARD_PM358 ||
1164                         board_info.board_id == BOARD_PM363)
1165                 laguna_pinmux_init();
1166         else
1167                 ardbeg_pinmux_init();
1168
1169         ardbeg_uart_init();
1170         ardbeg_usb_init();
1171         ardbeg_modem_init();
1172         ardbeg_xusb_init();
1173         ardbeg_i2c_init();
1174         ardbeg_spi_init();
1175         ardbeg_audio_init();
1176         platform_add_devices(ardbeg_devices, ARRAY_SIZE(ardbeg_devices));
1177         //tegra_ram_console_debug_init();
1178         tegra_io_dpd_init();
1179         ardbeg_sdhci_init();
1180         if (board_info.board_id == BOARD_PM359 ||
1181                         board_info.board_id == BOARD_PM358 ||
1182                         board_info.board_id == BOARD_PM363)
1183                 laguna_regulator_init();
1184         else
1185                 ardbeg_regulator_init();
1186         ardbeg_dtv_init();
1187         ardbeg_suspend_init();
1188 /* TODO: add support for laguna board when dvfs table is ready */
1189         if ((board_info.board_id == BOARD_E1780 &&
1190                 (tegra_get_memory_type() == 0)) ||
1191                 (board_info.board_id == BOARD_E1792))
1192                 ardbeg_emc_init();
1193
1194         edp_init();
1195         isomgr_init();
1196         ardbeg_touch_init();
1197         ardbeg_panel_init();
1198         ardbeg_kbc_init();
1199         if (board_info.board_id == BOARD_PM358)
1200                 laguna_pm358_pmon_init();
1201         else
1202                 ardbeg_pmon_init();
1203         if (board_info.board_id == BOARD_PM359 ||
1204                         board_info.board_id == BOARD_PM358 ||
1205                         board_info.board_id == BOARD_PM363)
1206                 laguna_pcie_init();
1207         else {
1208                 /* put PEX pads into DPD mode to save additional power */
1209                 tegra_io_dpd_enable(&pexbias_io);
1210                 tegra_io_dpd_enable(&pexclk1_io);
1211                 tegra_io_dpd_enable(&pexclk2_io);
1212         }
1213
1214 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1215         tegra_wdt_recovery_init();
1216 #endif
1217
1218         ardbeg_sensors_init();
1219
1220         ardbeg_soctherm_init();
1221
1222         ardbeg_setup_bluedroid_pm();
1223         tegra_register_fuse();
1224
1225         ardbeg_sysedp_dynamic_capping_init();
1226         ardbeg_sysedp_batmon_init();
1227 }
1228
1229 static void __init ardbeg_ramconsole_reserve(unsigned long size)
1230 {
1231         tegra_ram_console_debug_reserve(SZ_1M);
1232 }
1233
1234 static void __init tegra_ardbeg_init_early(void)
1235 {
1236         ardbeg_rail_alignment_init();
1237         tegra12x_init_early();
1238 }
1239
1240 static void __init tegra_ardbeg_dt_init(void)
1241 {
1242         tegra_get_board_info(&board_info);
1243         tegra_get_display_board_info(&display_board_info);
1244
1245         tegra_ardbeg_early_init();
1246 #ifdef CONFIG_USE_OF
1247         of_platform_populate(NULL,
1248                 of_default_bus_match_table, ardbeg_auxdata_lookup,
1249                 &platform_bus);
1250 #endif
1251
1252         tegra_ardbeg_late_init();
1253 }
1254
1255 static void __init tegra_ardbeg_reserve(void)
1256 {
1257 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) || \
1258                 defined(CONFIG_TEGRA_NO_CARVEOUT)
1259         /* 1920*1200*4*2 = 18432000 bytes */
1260         tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M);
1261 #else
1262         tegra_reserve(SZ_1G, SZ_16M + SZ_2M, SZ_4M);
1263 #endif
1264         ardbeg_ramconsole_reserve(SZ_1M);
1265 }
1266
1267 static const char * const ardbeg_dt_board_compat[] = {
1268         "nvidia,ardbeg",
1269         NULL
1270 };
1271
1272 static const char * const laguna_dt_board_compat[] = {
1273         "nvidia,laguna",
1274         NULL
1275 };
1276
1277 static const char * const tn8_dt_board_compat[] = {
1278         "nvidia,tn8",
1279         NULL
1280 };
1281
1282 DT_MACHINE_START(LAGUNA, "laguna")
1283         .atag_offset    = 0x100,
1284         .smp            = smp_ops(tegra_smp_ops),
1285         .map_io         = tegra_map_common_io,
1286         .reserve        = tegra_ardbeg_reserve,
1287         .init_early     = tegra_ardbeg_init_early,
1288         .init_irq       = irqchip_init,
1289         .init_time      = clocksource_of_init,
1290         .init_machine   = tegra_ardbeg_dt_init,
1291         .restart        = tegra_assert_system_reset,
1292         .dt_compat      = laguna_dt_board_compat,
1293         .init_late      = tegra_init_late
1294 MACHINE_END
1295
1296 DT_MACHINE_START(TN8, "tn8")
1297         .atag_offset    = 0x100,
1298         .smp            = smp_ops(tegra_smp_ops),
1299         .map_io         = tegra_map_common_io,
1300         .reserve        = tegra_ardbeg_reserve,
1301         .init_early     = tegra_ardbeg_init_early,
1302         .init_irq       = irqchip_init,
1303         .init_time      = clocksource_of_init,
1304         .init_machine   = tegra_ardbeg_dt_init,
1305         .restart        = tegra_assert_system_reset,
1306         .dt_compat      = tn8_dt_board_compat,
1307         .init_late      = tegra_init_late
1308 MACHINE_END
1309
1310 DT_MACHINE_START(ARDBEG, "ardbeg")
1311         .atag_offset    = 0x100,
1312         .smp            = smp_ops(tegra_smp_ops),
1313         .map_io         = tegra_map_common_io,
1314         .reserve        = tegra_ardbeg_reserve,
1315         .init_early     = tegra_ardbeg_init_early,
1316         .init_irq       = irqchip_init,
1317         .init_time      = clocksource_of_init,
1318         .init_machine   = tegra_ardbeg_dt_init,
1319         .restart        = tegra_assert_system_reset,
1320         .dt_compat      = ardbeg_dt_board_compat,
1321         .init_late      = tegra_init_late
1322 MACHINE_END