ARM: tegra: ardbeg: Enable SDR104 mode for SD
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-sdhci.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-sdhci.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/resource.h>
20 #include <linux/platform_device.h>
21 #include <linux/wlan_plat.h>
22 #include <linux/delay.h>
23 #include <linux/gpio.h>
24 #include <linux/clk.h>
25 #include <linux/err.h>
26 #include <linux/mmc/host.h>
27 #include <linux/wl12xx.h>
28 #include <linux/platform_data/mmc-sdhci-tegra.h>
29 #include <linux/mfd/max77660/max77660-core.h>
30
31 #include <asm/mach-types.h>
32 #include <mach/irqs.h>
33 #include <mach/gpio-tegra.h>
34
35 #include "gpio-names.h"
36 #include "board.h"
37 #include "board-ardbeg.h"
38 #include "dvfs.h"
39 #include "iomap.h"
40 #include "tegra-board-id.h"
41
42 #define ARDBEG_WLAN_RST TEGRA_GPIO_PCC5
43 #define ARDBEG_WLAN_PWR TEGRA_GPIO_PX7
44 #define ARDBEG_WLAN_WOW TEGRA_GPIO_PU5
45
46 #define ARDBEG_SD_CD    TEGRA_GPIO_PV2
47
48 static void (*wifi_status_cb)(int card_present, void *dev_id);
49 static void *wifi_status_cb_devid;
50 static int ardbeg_wifi_status_register(void (*callback)(int , void *), void *);
51
52 static int ardbeg_wifi_reset(int on);
53 static int ardbeg_wifi_power(int on);
54 static int ardbeg_wifi_set_carddetect(int val);
55
56 static struct wifi_platform_data ardbeg_wifi_control = {
57         .set_power      = ardbeg_wifi_power,
58         .set_reset      = ardbeg_wifi_reset,
59         .set_carddetect = ardbeg_wifi_set_carddetect,
60 };
61
62 static struct resource wifi_resource[] = {
63         [0] = {
64                 .name   = "bcm4329_wlan_irq",
65                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
66                                 | IORESOURCE_IRQ_SHAREABLE,
67         },
68 };
69
70 static struct platform_device ardbeg_wifi_device = {
71         .name           = "bcm4329_wlan",
72         .id             = 1,
73         .num_resources  = 1,
74         .resource       = wifi_resource,
75         .dev            = {
76                 .platform_data = &ardbeg_wifi_control,
77         },
78 };
79
80 static struct resource sdhci_resource0[] = {
81         [0] = {
82                 .start  = INT_SDMMC1,
83                 .end    = INT_SDMMC1,
84                 .flags  = IORESOURCE_IRQ,
85         },
86         [1] = {
87                 .start  = TEGRA_SDMMC1_BASE,
88                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
89                 .flags  = IORESOURCE_MEM,
90         },
91 };
92
93 static struct resource sdhci_resource2[] = {
94         [0] = {
95                 .start  = INT_SDMMC3,
96                 .end    = INT_SDMMC3,
97                 .flags  = IORESOURCE_IRQ,
98         },
99         [1] = {
100                 .start  = TEGRA_SDMMC3_BASE,
101                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
102                 .flags  = IORESOURCE_MEM,
103         },
104 };
105
106 static struct resource sdhci_resource3[] = {
107         [0] = {
108                 .start  = INT_SDMMC4,
109                 .end    = INT_SDMMC4,
110                 .flags  = IORESOURCE_IRQ,
111         },
112         [1] = {
113                 .start  = TEGRA_SDMMC4_BASE,
114                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
115                 .flags  = IORESOURCE_MEM,
116         },
117 };
118
119 #ifdef CONFIG_MMC_EMBEDDED_SDIO
120 static struct embedded_sdio_data embedded_sdio_data0 = {
121         .cccr   = {
122                 .sdio_vsn       = 2,
123                 .multi_block    = 1,
124                 .low_speed      = 0,
125                 .wide_bus       = 0,
126                 .high_power     = 1,
127                 .high_speed     = 1,
128         },
129         .cis  = {
130                 .vendor  = 0x02d0,
131                 .device  = 0x4329,
132         },
133 };
134 #endif
135
136 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
137         .mmc_data = {
138                 .register_status_notify = ardbeg_wifi_status_register,
139 #ifdef CONFIG_MMC_EMBEDDED_SDIO
140                 .embedded_sdio = &embedded_sdio_data0,
141 #endif
142                 .built_in = 0,
143                 .ocr_mask = MMC_OCR_1V8_MASK,
144         },
145         .cd_gpio = -1,
146         .wp_gpio = -1,
147         .power_gpio = -1,
148         .tap_delay = 0,
149         .trim_delay = 0x2,
150         .ddr_clk_limit = 41000000,
151 /*FIXME: Enable UHS modes for WiFI */
152         .uhs_mask = MMC_UHS_MASK_SDR104 | MMC_UHS_MASK_SDR12 | MMC_UHS_MASK_SDR25 |
153                 MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
154         .calib_3v3_offsets = 0x7676,
155         .calib_1v8_offsets = 0x7676,
156         .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50,
157 };
158
159 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
160         .cd_gpio = ARDBEG_SD_CD,
161         .wp_gpio = -1,
162         .power_gpio = -1,
163         .tap_delay = 0,
164         .trim_delay = 0x3,
165 /*FIXME: Enable UHS modes for SD */
166         .uhs_mask = MMC_UHS_MASK_SDR12 | MMC_UHS_MASK_SDR25 |
167                 MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
168         .calib_3v3_offsets = 0x7676,
169         .calib_1v8_offsets = 0x7676,
170         .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50,
171 };
172
173 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
174         .cd_gpio = -1,
175         .wp_gpio = -1,
176         .power_gpio = -1,
177         .is_8bit = 1,
178         .tap_delay = 0x4,
179         .trim_delay = 0x4,
180         .ddr_trim_delay = 0x4,
181         .mmc_data = {
182                 .built_in = 1,
183                 .ocr_mask = MMC_OCR_1V8_MASK,
184         },
185         .ddr_clk_limit = 51000000,
186         .max_clk_limit = 102000000,
187         .calib_3v3_offsets = 0x0202,
188         .calib_1v8_offsets = 0x0202,
189         .calib_1v8_offsets_uhs_modes = MMC_1V8_CALIB_OFFSET_DDR50 |
190                 MMC_1V8_CALIB_OFFSET_HS200,
191 };
192
193 static struct platform_device tegra_sdhci_device0 = {
194         .name           = "sdhci-tegra",
195         .id             = 0,
196         .resource       = sdhci_resource0,
197         .num_resources  = ARRAY_SIZE(sdhci_resource0),
198         .dev = {
199                 .platform_data = &tegra_sdhci_platform_data0,
200         },
201 };
202
203 static struct platform_device tegra_sdhci_device2 = {
204         .name           = "sdhci-tegra",
205         .id             = 2,
206         .resource       = sdhci_resource2,
207         .num_resources  = ARRAY_SIZE(sdhci_resource2),
208         .dev = {
209                 .platform_data = &tegra_sdhci_platform_data2,
210         },
211 };
212
213 static struct platform_device tegra_sdhci_device3 = {
214         .name           = "sdhci-tegra",
215         .id             = 3,
216         .resource       = sdhci_resource3,
217         .num_resources  = ARRAY_SIZE(sdhci_resource3),
218         .dev = {
219                 .platform_data = &tegra_sdhci_platform_data3,
220         },
221 };
222
223 static int ardbeg_wifi_status_register(
224                 void (*callback)(int card_present, void *dev_id),
225                 void *dev_id)
226 {
227         if (wifi_status_cb)
228                 return -EAGAIN;
229         wifi_status_cb = callback;
230         wifi_status_cb_devid = dev_id;
231         return 0;
232 }
233
234 static int ardbeg_wifi_set_carddetect(int val)
235 {
236         pr_debug("%s: %d\n", __func__, val);
237         if (wifi_status_cb)
238                 wifi_status_cb(val, wifi_status_cb_devid);
239         else
240                 pr_warn("%s: Nobody to notify\n", __func__);
241         return 0;
242 }
243
244 static int ardbeg_wifi_power(int on)
245 {
246         pr_err("%s: %d\n", __func__, on);
247
248         gpio_set_value(ARDBEG_WLAN_PWR, on);
249         gpio_set_value(ARDBEG_WLAN_RST, on);
250         mdelay(100);
251
252         return 0;
253 }
254
255 static int ardbeg_wifi_reset(int on)
256 {
257         pr_debug("%s: do nothing\n", __func__);
258         return 0;
259 }
260
261 static int __init ardbeg_wifi_init(void)
262 {
263         int rc;
264
265         rc = gpio_request(ARDBEG_WLAN_PWR, "wlan_power");
266         if (rc)
267                 pr_err("WLAN_PWR gpio request failed:%d\n", rc);
268         rc = gpio_request(ARDBEG_WLAN_RST, "wlan_rst");
269         if (rc)
270                 pr_err("WLAN_RST gpio request failed:%d\n", rc);
271         rc = gpio_request(ARDBEG_WLAN_WOW, "bcmsdh_sdmmc");
272         if (rc)
273                 pr_err("WLAN_WOW gpio request failed:%d\n", rc);
274
275         rc = gpio_direction_output(ARDBEG_WLAN_PWR, 0);
276         if (rc)
277                 pr_err("WLAN_PWR gpio direction configuration failed:%d\n", rc);
278         rc = gpio_direction_output(ARDBEG_WLAN_RST, 0);
279         if (rc)
280                 pr_err("WLAN_RST gpio direction configuration failed:%d\n", rc);
281
282         rc = gpio_direction_input(ARDBEG_WLAN_WOW);
283         if (rc)
284                 pr_err("WLAN_WOW gpio direction configuration failed:%d\n", rc);
285
286         wifi_resource[0].start = wifi_resource[0].end =
287                 gpio_to_irq(ARDBEG_WLAN_WOW);
288
289         platform_device_register(&ardbeg_wifi_device);
290         return 0;
291 }
292
293 #ifdef CONFIG_TEGRA_PREPOWER_WIFI
294 static int __init ardbeg_wifi_prepower(void)
295 {
296         if (!of_machine_is_compatible("nvidia,ardbeg") &&
297                 !of_machine_is_compatible("nvidia,laguna") &&
298                 !of_machine_is_compatible("nvidia,tn8"))
299                 return 0;
300         ardbeg_wifi_power(1);
301
302         return 0;
303 }
304
305 subsys_initcall_sync(ardbeg_wifi_prepower);
306 #endif
307
308 int __init ardbeg_sdhci_init(void)
309 {
310         int nominal_core_mv;
311         int min_vcore_override_mv;
312         int boot_vcore_mv;
313         struct board_info board_info;
314
315         nominal_core_mv =
316                 tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail);
317         if (nominal_core_mv) {
318                 tegra_sdhci_platform_data0.nominal_vcore_mv = nominal_core_mv;
319                 tegra_sdhci_platform_data2.nominal_vcore_mv = nominal_core_mv;
320                 tegra_sdhci_platform_data3.nominal_vcore_mv = nominal_core_mv;
321         }
322         min_vcore_override_mv =
323                 tegra_dvfs_rail_get_override_floor(tegra_core_rail);
324         if (min_vcore_override_mv) {
325                 tegra_sdhci_platform_data0.min_vcore_override_mv =
326                         min_vcore_override_mv;
327                 tegra_sdhci_platform_data2.min_vcore_override_mv =
328                         min_vcore_override_mv;
329                 tegra_sdhci_platform_data3.min_vcore_override_mv =
330                         min_vcore_override_mv;
331         }
332         boot_vcore_mv = tegra_dvfs_rail_get_boot_level(tegra_core_rail);
333         if (boot_vcore_mv) {
334                 tegra_sdhci_platform_data0.boot_vcore_mv = boot_vcore_mv;
335                 tegra_sdhci_platform_data2.boot_vcore_mv = boot_vcore_mv;
336                 tegra_sdhci_platform_data3.boot_vcore_mv = boot_vcore_mv;
337         }
338
339         tegra_get_board_info(&board_info);
340         if (board_info.board_id == BOARD_E1780) {
341                 tegra_sdhci_platform_data3.max_clk_limit = 200000000;
342                 tegra_sdhci_platform_data2.max_clk_limit = 204000000;
343         } else {
344                 tegra_sdhci_platform_data3.uhs_mask = MMC_MASK_HS200;
345         }
346
347         platform_device_register(&tegra_sdhci_device3);
348         platform_device_register(&tegra_sdhci_device2);
349         platform_device_register(&tegra_sdhci_device0);
350         ardbeg_wifi_init();
351
352         return 0;
353 }