ARM: tegra: ardbeg/loki: Fix calibration offsets
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-sdhci.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-sdhci.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/resource.h>
20 #include <linux/platform_device.h>
21 #include <linux/wlan_plat.h>
22 #include <linux/delay.h>
23 #include <linux/gpio.h>
24 #include <linux/clk.h>
25 #include <linux/err.h>
26 #include <linux/mmc/host.h>
27 #include <linux/wl12xx.h>
28 #include <linux/platform_data/mmc-sdhci-tegra.h>
29 #include <linux/mfd/max77660/max77660-core.h>
30
31 #include <asm/mach-types.h>
32 #include <mach/irqs.h>
33 #include <mach/gpio-tegra.h>
34
35 #include "gpio-names.h"
36 #include "board.h"
37 #include "board-ardbeg.h"
38 #include "dvfs.h"
39 #include "iomap.h"
40 #include "tegra-board-id.h"
41
42 #define ARDBEG_WLAN_RST TEGRA_GPIO_PCC5
43 #define ARDBEG_WLAN_PWR TEGRA_GPIO_PX7
44 #define ARDBEG_WLAN_WOW TEGRA_GPIO_PU5
45
46 #define ARDBEG_SD_CD    TEGRA_GPIO_PV2
47
48 static void (*wifi_status_cb)(int card_present, void *dev_id);
49 static void *wifi_status_cb_devid;
50 static int ardbeg_wifi_status_register(void (*callback)(int , void *), void *);
51
52 static int ardbeg_wifi_reset(int on);
53 static int ardbeg_wifi_power(int on);
54 static int ardbeg_wifi_set_carddetect(int val);
55
56 static struct wifi_platform_data ardbeg_wifi_control = {
57         .set_power      = ardbeg_wifi_power,
58         .set_reset      = ardbeg_wifi_reset,
59         .set_carddetect = ardbeg_wifi_set_carddetect,
60 };
61
62 static struct resource wifi_resource[] = {
63         [0] = {
64                 .name   = "bcm4329_wlan_irq",
65                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
66                                 | IORESOURCE_IRQ_SHAREABLE,
67         },
68 };
69
70 static struct platform_device ardbeg_wifi_device = {
71         .name           = "bcm4329_wlan",
72         .id             = 1,
73         .num_resources  = 1,
74         .resource       = wifi_resource,
75         .dev            = {
76                 .platform_data = &ardbeg_wifi_control,
77         },
78 };
79
80 static struct resource mrvl_wifi_resource[] = {
81         [0] = {
82                 .name   = "mrvl_wlan_irq",
83                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL | IORESOURCE_IRQ_SHAREABLE,
84         },
85 };
86
87 static struct platform_device marvell_wifi_device = {
88         .name           = "mrvl_wlan",
89         .id             = 1,
90         .num_resources  = 1,
91         .resource       = mrvl_wifi_resource,
92         .dev            = {
93                 .platform_data = &ardbeg_wifi_control,
94         },
95 };
96
97 static struct resource sdhci_resource0[] = {
98         [0] = {
99                 .start  = INT_SDMMC1,
100                 .end    = INT_SDMMC1,
101                 .flags  = IORESOURCE_IRQ,
102         },
103         [1] = {
104                 .start  = TEGRA_SDMMC1_BASE,
105                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
106                 .flags  = IORESOURCE_MEM,
107         },
108 };
109
110 static struct resource sdhci_resource2[] = {
111         [0] = {
112                 .start  = INT_SDMMC3,
113                 .end    = INT_SDMMC3,
114                 .flags  = IORESOURCE_IRQ,
115         },
116         [1] = {
117                 .start  = TEGRA_SDMMC3_BASE,
118                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
119                 .flags  = IORESOURCE_MEM,
120         },
121 };
122
123 static struct resource sdhci_resource3[] = {
124         [0] = {
125                 .start  = INT_SDMMC4,
126                 .end    = INT_SDMMC4,
127                 .flags  = IORESOURCE_IRQ,
128         },
129         [1] = {
130                 .start  = TEGRA_SDMMC4_BASE,
131                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
132                 .flags  = IORESOURCE_MEM,
133         },
134 };
135
136 #ifdef CONFIG_MMC_EMBEDDED_SDIO
137 static struct embedded_sdio_data embedded_sdio_data0 = {
138         .cccr   = {
139                 .sdio_vsn       = 2,
140                 .multi_block    = 1,
141                 .low_speed      = 0,
142                 .wide_bus       = 0,
143                 .high_power     = 1,
144                 .high_speed     = 1,
145         },
146         .cis  = {
147                 .vendor  = 0x02d0,
148                 .device  = 0x4329,
149         },
150 };
151 #endif
152
153 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
154         .mmc_data = {
155                 .register_status_notify = ardbeg_wifi_status_register,
156 #ifdef CONFIG_MMC_EMBEDDED_SDIO
157                 .embedded_sdio = &embedded_sdio_data0,
158 #endif
159                 .built_in = 0,
160                 .ocr_mask = MMC_OCR_1V8_MASK,
161         },
162         .cd_gpio = -1,
163         .wp_gpio = -1,
164         .power_gpio = -1,
165         .tap_delay = 0,
166         .trim_delay = 0x2,
167         .ddr_clk_limit = 41000000,
168 /*FIXME: Enable UHS modes for WiFI */
169         .uhs_mask = MMC_UHS_MASK_SDR104 | MMC_UHS_MASK_SDR12 | MMC_UHS_MASK_SDR25 |
170                 MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
171         .calib_3v3_offsets = 0x7676,
172         .calib_1v8_offsets = 0x7676,
173 };
174
175 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
176         .cd_gpio = ARDBEG_SD_CD,
177         .wp_gpio = -1,
178         .power_gpio = -1,
179         .tap_delay = 0,
180         .trim_delay = 0x3,
181 /*FIXME: Enable UHS modes for SD */
182         .uhs_mask = MMC_UHS_MASK_SDR12 | MMC_UHS_MASK_SDR25 |
183                 MMC_UHS_MASK_SDR104 | MMC_UHS_MASK_DDR50 |
184                 MMC_UHS_MASK_SDR50,
185         .calib_3v3_offsets = 0x7676,
186         .calib_1v8_offsets = 0x7676,
187 };
188
189 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
190         .cd_gpio = -1,
191         .wp_gpio = -1,
192         .power_gpio = -1,
193         .is_8bit = 1,
194         .tap_delay = 0x4,
195         .trim_delay = 0x4,
196         .ddr_trim_delay = 0x4,
197         .mmc_data = {
198                 .built_in = 1,
199                 .ocr_mask = MMC_OCR_1V8_MASK,
200         },
201         .ddr_clk_limit = 51000000,
202         .max_clk_limit = 102000000,
203         .calib_3v3_offsets = 0x0202,
204         .calib_1v8_offsets = 0x0202,
205 };
206
207 static struct platform_device tegra_sdhci_device0 = {
208         .name           = "sdhci-tegra",
209         .id             = 0,
210         .resource       = sdhci_resource0,
211         .num_resources  = ARRAY_SIZE(sdhci_resource0),
212         .dev = {
213                 .platform_data = &tegra_sdhci_platform_data0,
214         },
215 };
216
217 static struct platform_device tegra_sdhci_device2 = {
218         .name           = "sdhci-tegra",
219         .id             = 2,
220         .resource       = sdhci_resource2,
221         .num_resources  = ARRAY_SIZE(sdhci_resource2),
222         .dev = {
223                 .platform_data = &tegra_sdhci_platform_data2,
224         },
225 };
226
227 static struct platform_device tegra_sdhci_device3 = {
228         .name           = "sdhci-tegra",
229         .id             = 3,
230         .resource       = sdhci_resource3,
231         .num_resources  = ARRAY_SIZE(sdhci_resource3),
232         .dev = {
233                 .platform_data = &tegra_sdhci_platform_data3,
234         },
235 };
236
237 static int ardbeg_wifi_status_register(
238                 void (*callback)(int card_present, void *dev_id),
239                 void *dev_id)
240 {
241         if (wifi_status_cb)
242                 return -EAGAIN;
243         wifi_status_cb = callback;
244         wifi_status_cb_devid = dev_id;
245         return 0;
246 }
247
248 static int ardbeg_wifi_set_carddetect(int val)
249 {
250         pr_debug("%s: %d\n", __func__, val);
251         if (wifi_status_cb)
252                 wifi_status_cb(val, wifi_status_cb_devid);
253         else
254                 pr_warn("%s: Nobody to notify\n", __func__);
255         return 0;
256 }
257
258 static int ardbeg_wifi_power(int on)
259 {
260         pr_err("%s: %d\n", __func__, on);
261
262         gpio_set_value(ARDBEG_WLAN_PWR, on);
263         gpio_set_value(ARDBEG_WLAN_RST, on);
264         mdelay(100);
265
266         return 0;
267 }
268
269 static int ardbeg_wifi_reset(int on)
270 {
271         pr_debug("%s: do nothing\n", __func__);
272         return 0;
273 }
274
275 static int __init ardbeg_wifi_init(void)
276 {
277         int rc;
278
279         rc = gpio_request(ARDBEG_WLAN_PWR, "wlan_power");
280         if (rc)
281                 pr_err("WLAN_PWR gpio request failed:%d\n", rc);
282         rc = gpio_request(ARDBEG_WLAN_RST, "wlan_rst");
283         if (rc)
284                 pr_err("WLAN_RST gpio request failed:%d\n", rc);
285         rc = gpio_request(ARDBEG_WLAN_WOW, "bcmsdh_sdmmc");
286         if (rc)
287                 pr_err("WLAN_WOW gpio request failed:%d\n", rc);
288
289         rc = gpio_direction_output(ARDBEG_WLAN_PWR, 0);
290         if (rc)
291                 pr_err("WLAN_PWR gpio direction configuration failed:%d\n", rc);
292         rc = gpio_direction_output(ARDBEG_WLAN_RST, 0);
293         if (rc)
294                 pr_err("WLAN_RST gpio direction configuration failed:%d\n", rc);
295
296         rc = gpio_direction_input(ARDBEG_WLAN_WOW);
297         if (rc)
298                 pr_err("WLAN_WOW gpio direction configuration failed:%d\n", rc);
299
300         wifi_resource[0].start = wifi_resource[0].end =
301                 gpio_to_irq(ARDBEG_WLAN_WOW);
302
303         platform_device_register(&ardbeg_wifi_device);
304
305         mrvl_wifi_resource[0].start = mrvl_wifi_resource[0].end =
306                 gpio_to_irq(ARDBEG_WLAN_WOW);
307         platform_device_register(&marvell_wifi_device);
308
309         return 0;
310 }
311
312 #ifdef CONFIG_TEGRA_PREPOWER_WIFI
313 static int __init ardbeg_wifi_prepower(void)
314 {
315         if (!of_machine_is_compatible("nvidia,ardbeg") &&
316                 !of_machine_is_compatible("nvidia,laguna") &&
317                 !of_machine_is_compatible("nvidia,tn8"))
318                 return 0;
319         ardbeg_wifi_power(1);
320
321         return 0;
322 }
323
324 subsys_initcall_sync(ardbeg_wifi_prepower);
325 #endif
326
327 int __init ardbeg_sdhci_init(void)
328 {
329         int nominal_core_mv;
330         int min_vcore_override_mv;
331         int boot_vcore_mv;
332         struct board_info board_info;
333
334         nominal_core_mv =
335                 tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail);
336         if (nominal_core_mv) {
337                 tegra_sdhci_platform_data0.nominal_vcore_mv = nominal_core_mv;
338                 tegra_sdhci_platform_data2.nominal_vcore_mv = nominal_core_mv;
339                 tegra_sdhci_platform_data3.nominal_vcore_mv = nominal_core_mv;
340         }
341         min_vcore_override_mv =
342                 tegra_dvfs_rail_get_override_floor(tegra_core_rail);
343         if (min_vcore_override_mv) {
344                 tegra_sdhci_platform_data0.min_vcore_override_mv =
345                         min_vcore_override_mv;
346                 tegra_sdhci_platform_data2.min_vcore_override_mv =
347                         min_vcore_override_mv;
348                 tegra_sdhci_platform_data3.min_vcore_override_mv =
349                         min_vcore_override_mv;
350         }
351         boot_vcore_mv = tegra_dvfs_rail_get_boot_level(tegra_core_rail);
352         if (boot_vcore_mv) {
353                 tegra_sdhci_platform_data0.boot_vcore_mv = boot_vcore_mv;
354                 tegra_sdhci_platform_data2.boot_vcore_mv = boot_vcore_mv;
355                 tegra_sdhci_platform_data3.boot_vcore_mv = boot_vcore_mv;
356         }
357
358         tegra_get_board_info(&board_info);
359         if (board_info.board_id == BOARD_E1780) {
360                 tegra_sdhci_platform_data3.max_clk_limit = 200000000;
361                 tegra_sdhci_platform_data2.max_clk_limit = 204000000;
362         } else {
363                 tegra_sdhci_platform_data3.uhs_mask = MMC_MASK_HS200;
364         }
365
366         platform_device_register(&tegra_sdhci_device3);
367         platform_device_register(&tegra_sdhci_device2);
368         platform_device_register(&tegra_sdhci_device0);
369         ardbeg_wifi_init();
370
371         return 0;
372 }