ARM: tegra12: Change resistor value based on reworked/nonreowrked
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-powermon.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-powermon.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/ina219.h>
22 #include <linux/platform_data/ina230.h>
23 #include <linux/i2c/pca954x.h>
24
25 #include "board.h"
26 #include "board-ardbeg.h"
27 #include "tegra-board-id.h"
28
29 #define PRECISION_MULTIPLIER_ARDBEG     1000
30 #define ARDBEG_POWER_REWORKED_CONFIG    0x10
31 #define VDD_SOC_SD1_REWORKED            10
32 #define VDD_CPU_BUCKCPU_REWORKED        10
33 #define VDD_1V35_SD2_REWORKED           10
34
35 /* unused rail */
36 enum {
37         UNUSED_RAIL,
38 };
39
40 /* following rails are present on Ardbeg */
41 /* rails on i2c2_1 */
42 enum {
43         VDD_SYS_BAT,
44         VDD_RTC_LDO5,
45         VDD_3V3A_SMPS1_2,
46         VDD_SOC_SMPS1_2,
47         VDD_SYS_BUCKCPU,
48         VDD_CPU_BUCKCPU,
49         VDD_1V8A_SMPS3,
50         VDD_1V8B_SMPS9,
51         VDD_GPU_BUCKGPU,
52         VDD_1V35_SMPS6,
53         VDD_3V3A_SMPS1_2_2,
54         VDD_3V3B_SMPS9,
55         VDD_LCD_1V8B_DIS,
56         VDD_1V05_SMPS8,
57 };
58
59 /* rails on i2c2_2 */
60 enum {
61         VDD_SYS_BL,
62         AVDD_1V05_LDO2,
63 };
64
65 /* following rails are present on Ardbeg A01 and onward boards */
66 /* rails on i2c2_1 */
67 enum {
68         ARDBEG_A01_VDD_SYS_BAT,
69         ARDBEG_A01_VDD_RTC_LDO3,
70         ARDBEG_A01_VDD_SYS_BUCKSOC,
71         ARDBEG_A01_VDD_SOC_SD1,
72         ARDBEG_A01_VDD_SYS_BUCKCPU,
73         ARDBEG_A01_VDD_CPU_BUCKCPU,
74         ARDBEG_A01_VDD_1V8_SD5,
75         ARDBEG_A01_VDD_3V3A_LDO1_6,
76         ARDBEG_A01_VDD_DIS_3V3_LCD,
77         ARDBEG_A01_VDD_1V35_SD2,
78         ARDBEG_A01_VDD_SYS_BUCKGPU,
79         ARDBEG_A01_VDD_LCD_1V8B_DIS,
80         ARDBEG_A01_VDD_1V05_LDO0,
81 };
82
83 /* rails on i2c2_2 */
84 enum {
85         ARDBEG_A01_VDD_1V05_SD4,
86         ARDBEG_A01_VDD_1V8A_LDO2_5_7,
87         ARDBEG_A01_VDD_SYS_BL,
88 };
89
90 static struct ina219_platform_data power_mon_info_0[] = {
91         /* All unused INA219 devices use below data */
92         [UNUSED_RAIL] = {
93                 .calibration_data = 0x369c,
94                 .power_lsb = 3.051979018 * PRECISION_MULTIPLIER_ARDBEG,
95                 .rail_name = "unused_rail",
96                 .divisor = 20,
97                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
98         },
99 };
100
101 /* following are power monitor parameters for Ardbeg */
102 static struct ina230_platform_data power_mon_info_1[] = {
103         [VDD_SYS_BAT] = {
104                 .calibration_data  = 0x1366,
105                 .power_lsb = 2.577527185 * PRECISION_MULTIPLIER_ARDBEG,
106                 .rail_name = "VDD_SYS_BAT",
107                 .divisor = 25,
108                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
109         },
110
111         [VDD_RTC_LDO5] = {
112                 .calibration_data  = 0x7FFF,
113                 .power_lsb = 0.078127384 * PRECISION_MULTIPLIER_ARDBEG,
114                 .rail_name = "VDD_RTC_LDO5",
115                 .divisor = 25,
116                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
117         },
118
119         [VDD_3V3A_SMPS1_2] = {
120                 .calibration_data  = 0x4759,
121                 .power_lsb = 1.401587736 * PRECISION_MULTIPLIER_ARDBEG,
122                 .rail_name = "VDD_3V3A_SMPS1_2",
123                 .divisor = 25,
124                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
125         },
126
127         [VDD_SOC_SMPS1_2] = {
128                 .calibration_data  = 0x7FFF,
129                 .power_lsb = 3.906369213 * PRECISION_MULTIPLIER_ARDBEG,
130                 .rail_name = "VDD_SOC_SMPS1_2",
131                 .divisor = 25,
132                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
133         },
134
135         [VDD_SYS_BUCKCPU] = {
136                 .calibration_data  = 0x1AC5,
137                 .power_lsb = 1.867795126 * PRECISION_MULTIPLIER_ARDBEG,
138                 .rail_name = "VDD_SYS_BUCKCPU",
139                 .divisor = 25,
140                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
141         },
142
143         [VDD_CPU_BUCKCPU] = {
144                 .calibration_data  = 0x2ECF,
145                 .power_lsb = 10.68179922 * PRECISION_MULTIPLIER_ARDBEG,
146                 .rail_name = "VDD_CPU_BUCKCPU",
147                 .divisor = 25,
148                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
149         },
150
151         [VDD_1V8A_SMPS3] = {
152                 .calibration_data  = 0x5BA7,
153                 .power_lsb = 0.545539786 * PRECISION_MULTIPLIER_ARDBEG,
154                 .rail_name = "VDD_1V8A_SMPS3",
155                 .divisor = 25,
156                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
157         },
158
159         [VDD_1V8B_SMPS9] = {
160                 .calibration_data  = 0x50B4,
161                 .power_lsb = 0.309777348 * PRECISION_MULTIPLIER_ARDBEG,
162                 .rail_name = "VDD_1V8B_SMPS9",
163                 .divisor = 25,
164                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
165         },
166
167         [VDD_GPU_BUCKGPU] = {
168                 .calibration_data  = 0x369C,
169                 .power_lsb = 9.155937053 * PRECISION_MULTIPLIER_ARDBEG,
170                 .rail_name = "VDD_GPU_BUCKGPU",
171                 .divisor = 25,
172                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
173         },
174
175         [VDD_1V35_SMPS6] = {
176                 .calibration_data  = 0x7FFF,
177                 .power_lsb = 3.906369213 * PRECISION_MULTIPLIER_ARDBEG,
178                 .rail_name = "VDD_1V35_SMPS6",
179                 .divisor = 25,
180                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
181         },
182
183         /* following rail is duplicate of VDD_3V3A_SMPS1_2 hence mark unused */
184         [VDD_3V3A_SMPS1_2_2] = {
185                 .calibration_data  = 0x4759,
186                 .power_lsb = 1.401587736 * PRECISION_MULTIPLIER_ARDBEG,
187                 .rail_name = "unused_rail",
188                 .divisor = 25,
189                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
190         },
191
192         [VDD_3V3B_SMPS9] = {
193                 .calibration_data  = 0x3269,
194                 .power_lsb = 0.198372724 * PRECISION_MULTIPLIER_ARDBEG,
195                 .rail_name = "VDD_3V3B_SMPS9",
196                 .divisor = 25,
197                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
198         },
199
200         [VDD_LCD_1V8B_DIS] = {
201                 .calibration_data  = 0x7FFF,
202                 .power_lsb = 0.039063692 * PRECISION_MULTIPLIER_ARDBEG,
203                 .rail_name = "VDD_LCD_1V8B_DIS",
204                 .divisor = 25,
205                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
206         },
207
208         [VDD_1V05_SMPS8] = {
209                 .calibration_data  = 0x7FFF,
210                 .power_lsb = 0.130212307 * PRECISION_MULTIPLIER_ARDBEG,
211                 .rail_name = "VDD_1V05_SMPS8",
212                 .divisor = 25,
213                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
214         },
215 };
216
217 static struct ina230_platform_data power_mon_info_2[] = {
218         [VDD_SYS_BL] = {
219                 .calibration_data  = 0x1A29,
220                 .power_lsb = 0.63710119 * PRECISION_MULTIPLIER_ARDBEG,
221                 .rail_name = "VDD_SYS_BL",
222                 .divisor = 25,
223                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
224         },
225
226         [AVDD_1V05_LDO2] = {
227                 .calibration_data  = 0x7FFF,
228                 .power_lsb = 0.390636921 * PRECISION_MULTIPLIER_ARDBEG,
229                 .rail_name = "AVDD_1V05_LDO2",
230                 .divisor = 25,
231                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
232         },
233 };
234
235 /* following are power monitor parameters for Ardbeg A01*/
236 static struct ina230_platform_data ardbeg_A01_power_mon_info_1[] = {
237         [ARDBEG_A01_VDD_SYS_BAT] = {
238                 .calibration_data  = 0x1366,
239                 .power_lsb = 2.577527185 * PRECISION_MULTIPLIER_ARDBEG,
240                 .rail_name = "VDD_SYS_BAT",
241                 .divisor = 25,
242                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
243                 .resistor = 10,
244         },
245
246         [ARDBEG_A01_VDD_RTC_LDO3] = {
247                 .calibration_data  = 0x7FFF,
248                 .power_lsb = 0.078127384 * PRECISION_MULTIPLIER_ARDBEG,
249                 .rail_name = "VDD_RTC_LDO3",
250                 .divisor = 25,
251                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
252                 .resistor = 50,
253         },
254
255         [ARDBEG_A01_VDD_SYS_BUCKSOC] = {
256                 .calibration_data  = 0x1AAC,
257                 .power_lsb = 0.624877954 * PRECISION_MULTIPLIER_ARDBEG,
258                 .rail_name = "VDD_SYS_BUCKSOC",
259                 .divisor = 25,
260                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
261                 .resistor = 30,
262         },
263
264         [ARDBEG_A01_VDD_SOC_SD1] = {
265                 .calibration_data  = 0x7FFF,
266                 .power_lsb = 3.906369213 * PRECISION_MULTIPLIER_ARDBEG,
267                 .rail_name = "VDD_SOC_SD1",
268                 .divisor = 25,
269                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
270                 .resistor = 1,
271         },
272
273         [ARDBEG_A01_VDD_SYS_BUCKCPU] = {
274                 .calibration_data  = 0x1AC5,
275                 .power_lsb = 1.867795126 * PRECISION_MULTIPLIER_ARDBEG,
276                 .rail_name = "VDD_SYS_BUCKCPU",
277                 .divisor = 25,
278                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
279                 .resistor = 10,
280         },
281
282         [ARDBEG_A01_VDD_CPU_BUCKCPU] = {
283                 .calibration_data  = 0x2ECF,
284                 .power_lsb = 10.68179922 * PRECISION_MULTIPLIER_ARDBEG,
285                 .rail_name = "VDD_CPU_BUCKCPU",
286                 .divisor = 25,
287                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
288                 .resistor = 1,
289         },
290
291         [ARDBEG_A01_VDD_1V8_SD5] = {
292                 .calibration_data  = 0x45F0,
293                 .power_lsb = 0.714924039 * PRECISION_MULTIPLIER_ARDBEG,
294                 .rail_name = "VDD_1V8_SD5",
295                 .divisor = 25,
296                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
297                 .resistor = 10,
298         },
299
300         [ARDBEG_A01_VDD_3V3A_LDO1_6] = {
301                 .calibration_data  = 0x3A83,
302                 .power_lsb = 0.042726484 * PRECISION_MULTIPLIER_ARDBEG,
303                 .rail_name = "VDD_3V3A_LDO1_6",
304                 .divisor = 25,
305                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
306                 .resistor = 200,
307         },
308
309         [ARDBEG_A01_VDD_DIS_3V3_LCD] = {
310                 .calibration_data  = 0x7FFF,
311                 .power_lsb = 0.390636921 * PRECISION_MULTIPLIER_ARDBEG,
312                 .rail_name = "VDD_DIS_3V3_LCD",
313                 .divisor = 25,
314                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
315                 .resistor = 10,
316         },
317
318         [ARDBEG_A01_VDD_1V35_SD2] = {
319                 .calibration_data  = 0x7FFF,
320                 .power_lsb = 3.906369213 * PRECISION_MULTIPLIER_ARDBEG,
321                 .rail_name = "VDD_1V35_SD2",
322                 .divisor = 25,
323                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
324                 .resistor = 1,
325         },
326
327         [ARDBEG_A01_VDD_SYS_BUCKGPU] = {
328                 .calibration_data  = 0x1F38,
329                 .power_lsb = 1.601601602 * PRECISION_MULTIPLIER_ARDBEG,
330                 .rail_name = "VDD_SYS_BUCKGPU",
331                 .divisor = 25,
332                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
333                 .resistor = 10,
334         },
335
336         [ARDBEG_A01_VDD_LCD_1V8B_DIS] = {
337                 .calibration_data  = 0x7FFF,
338                 .power_lsb = 0.039063692 * PRECISION_MULTIPLIER_ARDBEG,
339                 .rail_name = "VDD_LCD_1V8B_DIS",
340                 .divisor = 25,
341                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
342                 .resistor = 100,
343         },
344
345         [ARDBEG_A01_VDD_1V05_LDO0] = {
346                 .calibration_data  = 0x7FFF,
347                 .power_lsb = 0.130212307 * PRECISION_MULTIPLIER_ARDBEG,
348                 .rail_name = "VDD_1V05_LDO0",
349                 .divisor = 25,
350                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
351                 .resistor = 30,
352         },
353 };
354
355 static struct ina230_platform_data ardbeg_A01_power_mon_info_2[] = {
356         [ARDBEG_A01_VDD_1V05_SD4] = {
357                 .calibration_data  = 0x7FFF,
358                 .power_lsb = 0.390636921 * PRECISION_MULTIPLIER_ARDBEG,
359                 .rail_name = "VDD_1V05_SD4",
360                 .divisor = 25,
361                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
362                 .resistor = 10,
363         },
364
365         [ARDBEG_A01_VDD_1V8A_LDO2_5_7] = {
366                 .calibration_data  = 0x5A04,
367                 .power_lsb = 0.277729561 * PRECISION_MULTIPLIER_ARDBEG,
368                 .rail_name = "VDD_1V8A_LDO2_5_7",
369                 .divisor = 25,
370                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
371                 .resistor = 20,
372         },
373
374         [ARDBEG_A01_VDD_SYS_BL] = {
375                 .calibration_data  = 0x2468,
376                 .power_lsb = 0.274678112 * PRECISION_MULTIPLIER_ARDBEG,
377                 .rail_name = "VDD_SYS_BL",
378                 .divisor = 25,
379                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
380                 .resistor = 50,
381         },
382 };
383
384 /* i2c addresses of rails present on Ardbeg */
385 /* addresses on i2c2_0 */
386 enum {
387         INA_I2C_2_0_ADDR_40,
388         INA_I2C_2_0_ADDR_41,
389         INA_I2C_2_0_ADDR_42,
390         INA_I2C_2_0_ADDR_43,
391 };
392
393 /* addresses on i2c2_1 */
394 enum {
395         INA_I2C_2_1_ADDR_40,
396         INA_I2C_2_1_ADDR_41,
397         INA_I2C_2_1_ADDR_42,
398         INA_I2C_2_1_ADDR_43,
399         INA_I2C_2_1_ADDR_44,
400         INA_I2C_2_1_ADDR_45,
401         INA_I2C_2_1_ADDR_46,
402         INA_I2C_2_1_ADDR_47,
403         INA_I2C_2_1_ADDR_48,
404         INA_I2C_2_1_ADDR_49,
405         INA_I2C_2_1_ADDR_4B,
406         INA_I2C_2_1_ADDR_4C,
407         INA_I2C_2_1_ADDR_4E,
408         INA_I2C_2_1_ADDR_4F,
409 };
410
411 /* addresses on i2c2_2 */
412 enum {
413         INA_I2C_2_2_ADDR_49,
414         INA_I2C_2_2_ADDR_4C,
415 };
416
417 /* i2c addresses of rails present on Ardbeg A01*/
418 /* addresses on i2c2_1 */
419 enum {
420         ARDBEG_A01_INA_I2C_2_1_ADDR_40,
421         ARDBEG_A01_INA_I2C_2_1_ADDR_41,
422         ARDBEG_A01_INA_I2C_2_1_ADDR_42,
423         ARDBEG_A01_INA_I2C_2_1_ADDR_43,
424         ARDBEG_A01_INA_I2C_2_1_ADDR_44,
425         ARDBEG_A01_INA_I2C_2_1_ADDR_45,
426         ARDBEG_A01_INA_I2C_2_1_ADDR_46,
427         ARDBEG_A01_INA_I2C_2_1_ADDR_47,
428         ARDBEG_A01_INA_I2C_2_1_ADDR_48,
429         ARDBEG_A01_INA_I2C_2_1_ADDR_49,
430         ARDBEG_A01_INA_I2C_2_1_ADDR_4B,
431         ARDBEG_A01_INA_I2C_2_1_ADDR_4E,
432         ARDBEG_A01_INA_I2C_2_1_ADDR_4F,
433 };
434
435 /* addresses on i2c2_2 */
436 enum {
437         ARDBEG_A01_INA_I2C_2_2_ADDR_40,
438         ARDBEG_A01_INA_I2C_2_2_ADDR_41,
439         ARDBEG_A01_INA_I2C_2_2_ADDR_49,
440 };
441
442 /* following is the i2c board info for Ardbeg */
443 static struct i2c_board_info ardbeg_i2c2_0_ina219_board_info[] = {
444         [INA_I2C_2_0_ADDR_40] = {
445                 I2C_BOARD_INFO("ina219", 0x40),
446                 .platform_data = &power_mon_info_0[UNUSED_RAIL],
447                 .irq = -1,
448         },
449
450         [INA_I2C_2_0_ADDR_41] = {
451                 I2C_BOARD_INFO("ina219", 0x41),
452                 .platform_data = &power_mon_info_0[UNUSED_RAIL],
453                 .irq = -1,
454         },
455
456         [INA_I2C_2_0_ADDR_42] = {
457                 I2C_BOARD_INFO("ina219", 0x42),
458                 .platform_data = &power_mon_info_0[UNUSED_RAIL],
459                 .irq = -1,
460         },
461
462         [INA_I2C_2_0_ADDR_43] = {
463                 I2C_BOARD_INFO("ina219", 0x43),
464                 .platform_data = &power_mon_info_0[UNUSED_RAIL],
465                 .irq = -1,
466         },
467 };
468
469 static struct i2c_board_info ardbeg_i2c2_1_ina230_board_info[] = {
470         [INA_I2C_2_1_ADDR_40] = {
471                 I2C_BOARD_INFO("ina230", 0x40),
472                 .platform_data = &power_mon_info_1[VDD_SYS_BAT],
473                 .irq = -1,
474         },
475
476         [INA_I2C_2_1_ADDR_41] = {
477                 I2C_BOARD_INFO("ina230", 0x41),
478                 .platform_data = &power_mon_info_1[VDD_RTC_LDO5],
479                 .irq = -1,
480         },
481
482         [INA_I2C_2_1_ADDR_42] = {
483                 I2C_BOARD_INFO("ina230", 0x42),
484                 .platform_data = &power_mon_info_1[VDD_3V3A_SMPS1_2],
485                 .irq = -1,
486         },
487
488         [INA_I2C_2_1_ADDR_43] = {
489                 I2C_BOARD_INFO("ina230", 0x43),
490                 .platform_data = &power_mon_info_1[VDD_SOC_SMPS1_2],
491                 .irq = -1,
492         },
493
494         [INA_I2C_2_1_ADDR_44] = {
495                 I2C_BOARD_INFO("ina230", 0x44),
496                 .platform_data = &power_mon_info_1[VDD_SYS_BUCKCPU],
497                 .irq = -1,
498         },
499
500         [INA_I2C_2_1_ADDR_45] = {
501                 I2C_BOARD_INFO("ina230", 0x45),
502                 .platform_data = &power_mon_info_1[VDD_CPU_BUCKCPU],
503                 .irq = -1,
504         },
505
506         [INA_I2C_2_1_ADDR_46] = {
507                 I2C_BOARD_INFO("ina230", 0x46),
508                 .platform_data = &power_mon_info_1[VDD_1V8A_SMPS3],
509                 .irq = -1,
510         },
511
512         [INA_I2C_2_1_ADDR_47] = {
513                 I2C_BOARD_INFO("ina230", 0x47),
514                 .platform_data = &power_mon_info_1[VDD_1V8B_SMPS9],
515                 .irq = -1,
516         },
517
518         [INA_I2C_2_1_ADDR_48] = {
519                 I2C_BOARD_INFO("ina230", 0x48),
520                 .platform_data = &power_mon_info_1[VDD_GPU_BUCKGPU],
521                 .irq = -1,
522         },
523
524         [INA_I2C_2_1_ADDR_49] = {
525                 I2C_BOARD_INFO("ina230", 0x49),
526                 .platform_data = &power_mon_info_1[VDD_1V35_SMPS6],
527                 .irq = -1,
528         },
529
530         [INA_I2C_2_1_ADDR_4B] = {
531                 I2C_BOARD_INFO("ina230", 0x4B),
532                 .platform_data = &power_mon_info_1[VDD_3V3A_SMPS1_2_2],
533                 .irq = -1,
534         },
535
536         [INA_I2C_2_1_ADDR_4C] = {
537                 I2C_BOARD_INFO("ina230", 0x4C),
538                 .platform_data = &power_mon_info_1[VDD_3V3B_SMPS9],
539                 .irq = -1,
540         },
541
542         [INA_I2C_2_1_ADDR_4E] = {
543                 I2C_BOARD_INFO("ina230", 0x4E),
544                 .platform_data = &power_mon_info_1[VDD_LCD_1V8B_DIS],
545                 .irq = -1,
546         },
547
548         [INA_I2C_2_1_ADDR_4F] = {
549                 I2C_BOARD_INFO("ina230", 0x4F),
550                 .platform_data = &power_mon_info_1[VDD_1V05_SMPS8],
551                 .irq = -1,
552         },
553 };
554
555 static struct i2c_board_info ardbeg_i2c2_2_ina230_board_info[] = {
556         [INA_I2C_2_2_ADDR_49] = {
557                 I2C_BOARD_INFO("ina230", 0x49),
558                 .platform_data = &power_mon_info_2[VDD_SYS_BL],
559                 .irq = -1,
560         },
561
562         [INA_I2C_2_2_ADDR_4C] = {
563                 I2C_BOARD_INFO("ina230", 0x4C),
564                 .platform_data = &power_mon_info_2[AVDD_1V05_LDO2],
565                 .irq = -1,
566         },
567
568 };
569
570 /* following is the i2c board info for Ardbeg A01 */
571 static struct i2c_board_info ardbeg_A01_i2c2_1_ina230_board_info[] = {
572         [ARDBEG_A01_INA_I2C_2_1_ADDR_40] = {
573                 I2C_BOARD_INFO("ina230", 0x40),
574                 .platform_data =
575                         &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SYS_BAT],
576                 .irq = -1,
577         },
578
579         [ARDBEG_A01_INA_I2C_2_1_ADDR_41] = {
580                 I2C_BOARD_INFO("ina230", 0x41),
581                 .platform_data =
582                         &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_RTC_LDO3],
583                 .irq = -1,
584         },
585
586         [ARDBEG_A01_INA_I2C_2_1_ADDR_42] = {
587                 I2C_BOARD_INFO("ina230", 0x42),
588                 .platform_data =
589                 &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SYS_BUCKSOC],
590                 .irq = -1,
591         },
592
593         [ARDBEG_A01_INA_I2C_2_1_ADDR_43] = {
594                 I2C_BOARD_INFO("ina230", 0x43),
595                 .platform_data =
596                         &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SOC_SD1],
597                 .irq = -1,
598         },
599
600         [ARDBEG_A01_INA_I2C_2_1_ADDR_44] = {
601                 I2C_BOARD_INFO("ina230", 0x44),
602                 .platform_data =
603                 &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SYS_BUCKCPU],
604                 .irq = -1,
605         },
606
607         [ARDBEG_A01_INA_I2C_2_1_ADDR_45] = {
608                 I2C_BOARD_INFO("ina230", 0x45),
609                 .platform_data =
610                 &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_CPU_BUCKCPU],
611                 .irq = -1,
612         },
613
614         [ARDBEG_A01_INA_I2C_2_1_ADDR_46] = {
615                 I2C_BOARD_INFO("ina230", 0x46),
616                 .platform_data =
617                         &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_1V8_SD5],
618                 .irq = -1,
619         },
620
621         [ARDBEG_A01_INA_I2C_2_1_ADDR_47] = {
622                 I2C_BOARD_INFO("ina230", 0x47),
623                 .platform_data =
624                 &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_3V3A_LDO1_6],
625                 .irq = -1,
626         },
627
628         [ARDBEG_A01_INA_I2C_2_1_ADDR_48] = {
629                 I2C_BOARD_INFO("ina230", 0x48),
630                 .platform_data =
631                 &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_DIS_3V3_LCD],
632                 .irq = -1,
633         },
634
635         [ARDBEG_A01_INA_I2C_2_1_ADDR_49] = {
636                 I2C_BOARD_INFO("ina230", 0x49),
637                 .platform_data =
638                         &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_1V35_SD2],
639                 .irq = -1,
640         },
641
642         [ARDBEG_A01_INA_I2C_2_1_ADDR_4B] = {
643                 I2C_BOARD_INFO("ina230", 0x4B),
644                 .platform_data =
645                 &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SYS_BUCKGPU],
646                 .irq = -1,
647         },
648
649         [ARDBEG_A01_INA_I2C_2_1_ADDR_4E] = {
650                 I2C_BOARD_INFO("ina230", 0x4E),
651                 .platform_data =
652                 &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_LCD_1V8B_DIS],
653                 .irq = -1,
654         },
655
656         [ARDBEG_A01_INA_I2C_2_1_ADDR_4F] = {
657                 I2C_BOARD_INFO("ina230", 0x4F),
658                 .platform_data =
659                         &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_1V05_LDO0],
660                 .irq = -1,
661         },
662 };
663
664 static struct i2c_board_info ardbeg_A01_i2c2_2_ina230_board_info[] = {
665         [ARDBEG_A01_INA_I2C_2_2_ADDR_40] = {
666                 I2C_BOARD_INFO("ina230", 0x40),
667                 .platform_data =
668                         &ardbeg_A01_power_mon_info_2[ARDBEG_A01_VDD_1V05_SD4],
669                 .irq = -1,
670         },
671
672         [ARDBEG_A01_INA_I2C_2_2_ADDR_41] = {
673                 I2C_BOARD_INFO("ina230", 0x41),
674                 .platform_data =
675                 &ardbeg_A01_power_mon_info_2[ARDBEG_A01_VDD_1V8A_LDO2_5_7],
676                 .irq = -1,
677         },
678
679         [ARDBEG_A01_INA_I2C_2_2_ADDR_49] = {
680                 I2C_BOARD_INFO("ina230", 0x49),
681                 .platform_data =
682                         &ardbeg_A01_power_mon_info_2[ARDBEG_A01_VDD_SYS_BL],
683                 .irq = -1,
684         },
685 };
686
687 static struct pca954x_platform_mode ardbeg_pca954x_modes[] = {
688         { .adap_id = PCA954x_I2C_BUS0, .deselect_on_exit = true, },
689         { .adap_id = PCA954x_I2C_BUS1, .deselect_on_exit = true, },
690         { .adap_id = PCA954x_I2C_BUS2, .deselect_on_exit = true, },
691         { .adap_id = PCA954x_I2C_BUS3, .deselect_on_exit = true, },
692 };
693
694 static struct pca954x_platform_data ardbeg_pca954x_data = {
695         .modes    = ardbeg_pca954x_modes,
696         .num_modes      = ARRAY_SIZE(ardbeg_pca954x_modes),
697 };
698
699 static const struct i2c_board_info ardbeg_i2c2_board_info[] = {
700         {
701                 I2C_BOARD_INFO("pca9546", 0x71),
702                 .platform_data = &ardbeg_pca954x_data,
703         },
704 };
705
706 static void __init register_devices_ardbeg_A01(void)
707 {
708         i2c_register_board_info(PCA954x_I2C_BUS1,
709                         ardbeg_A01_i2c2_1_ina230_board_info,
710                         ARRAY_SIZE(ardbeg_A01_i2c2_1_ina230_board_info));
711
712         i2c_register_board_info(PCA954x_I2C_BUS2,
713                         ardbeg_A01_i2c2_2_ina230_board_info,
714                         ARRAY_SIZE(ardbeg_A01_i2c2_2_ina230_board_info));
715 }
716
717 static void __init register_devices_ardbeg(void)
718 {
719         i2c_register_board_info(PCA954x_I2C_BUS1,
720                         ardbeg_i2c2_1_ina230_board_info,
721                         ARRAY_SIZE(ardbeg_i2c2_1_ina230_board_info));
722
723         i2c_register_board_info(PCA954x_I2C_BUS2,
724                         ardbeg_i2c2_2_ina230_board_info,
725                         ARRAY_SIZE(ardbeg_i2c2_2_ina230_board_info));
726 }
727
728 static void modify_reworked_rail_data(void)
729 {
730         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_1V35_SD2].resistor
731                                         = VDD_1V35_SD2_REWORKED;
732         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_CPU_BUCKCPU].resistor
733                                         = VDD_CPU_BUCKCPU_REWORKED;
734         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SOC_SD1].resistor
735                                         = VDD_SOC_SD1_REWORKED;
736 }
737
738 int __init ardbeg_pmon_init(void)
739 {
740         /*
741         * Get power_config of board and check whether
742         * board is power reworked or not.
743         * In case board is reworked, modify rail data
744         * for which rework was done.
745         */
746         u8 power_config;
747         struct board_info bi;
748         power_config = get_power_config();
749         if (power_config & ARDBEG_POWER_REWORKED_CONFIG)
750                 modify_reworked_rail_data();
751
752         tegra_get_board_info(&bi);
753
754         i2c_register_board_info(1, ardbeg_i2c2_board_info,
755                 ARRAY_SIZE(ardbeg_i2c2_board_info));
756
757         i2c_register_board_info(PCA954x_I2C_BUS0,
758                         ardbeg_i2c2_0_ina219_board_info,
759                         ARRAY_SIZE(ardbeg_i2c2_0_ina219_board_info));
760
761         if (bi.fab >= BOARD_FAB_A01)
762                 register_devices_ardbeg_A01();
763         else
764                 register_devices_ardbeg();
765
766         return 0;
767 }
768