ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-powermon.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-powermon.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/platform_data/ina230.h>
22
23 #include "board.h"
24 #include "board-ardbeg.h"
25 #include "tegra-board-id.h"
26
27 #define PRECISION_MULTIPLIER_ARDBEG     1000
28 #define ARDBEG_POWER_REWORKED_CONFIG    0x10
29 #define VDD_SOC_SD1_REWORKED            10
30 #define VDD_CPU_BUCKCPU_REWORKED        10
31 #define VDD_1V35_SD2_REWORKED           10
32
33 #define AVG_SAMPLES (2 << 9) /* 16 samples */
34
35 /* AVG is specified from platform data */
36 #define INA230_CONT_CONFIG      (AVG_SAMPLES | INA230_VBUS_CT | \
37                                 INA230_VSH_CT | INA230_CONT_MODE)
38 #define INA230_TRIG_CONFIG      (AVG_SAMPLES | INA230_VBUS_CT | \
39                                 INA230_VSH_CT | INA230_TRIG_MODE)
40
41 /* rails on i2c2_0 */
42 enum {
43         VDD_BAT_0,
44         VDD_SYS_BUCKCPU_0,
45         VDD_SYS_BUCKSOC_0,
46         VDD_SYS_BUCKGPU_0,
47 };
48
49 /* following rails are present on Ardbeg */
50 /* rails on i2c2_1 */
51 enum {
52         VDD_SYS_BAT,
53         VDD_RTC_LDO5,
54         VDD_3V3A_SMPS1_2,
55         VDD_SOC_SMPS1_2,
56         VDD_SYS_BUCKCPU,
57         VDD_CPU_BUCKCPU,
58         VDD_1V8A_SMPS3,
59         VDD_1V8B_SMPS9,
60         VDD_GPU_BUCKGPU,
61         VDD_1V35_SMPS6,
62         VDD_3V3A_SMPS1_2_2,
63         VDD_3V3B_SMPS9,
64         VDD_LCD_1V8B_DIS,
65         VDD_1V05_SMPS8,
66 };
67
68 /* rails on i2c2_2 */
69 enum {
70         VDD_SYS_BL,
71         AVDD_1V05_LDO2,
72 };
73
74 /* following rails are present on Ardbeg A01 and onward boards */
75 /* rails on i2c2_1 */
76 enum {
77         ARDBEG_A01_VDD_SYS_BAT,
78         ARDBEG_A01_VDD_RTC_LDO3,
79         ARDBEG_A01_VDD_SYS_BUCKSOC,
80         ARDBEG_A01_VDD_SOC_SD1,
81         ARDBEG_A01_VDD_SYS_BUCKCPU,
82         ARDBEG_A01_VDD_CPU_BUCKCPU,
83         ARDBEG_A01_VDD_1V8_SD5,
84         ARDBEG_A01_VDD_3V3A_LDO1_6,
85         ARDBEG_A01_VDD_DIS_3V3_LCD,
86         ARDBEG_A01_VDD_1V35_SD2,
87         ARDBEG_A01_VDD_SYS_BUCKGPU,
88         ARDBEG_A01_VDD_LCD_1V8B_DIS,
89         ARDBEG_A01_VDD_1V05_LDO0,
90 };
91
92 /* rails on i2c2_2 */
93 enum {
94         ARDBEG_A01_VDD_1V05_SD4,
95         ARDBEG_A01_VDD_1V8A_LDO2_5_7,
96         ARDBEG_A01_VDD_SYS_BL,
97 };
98
99 static struct ina230_platform_data power_mon_info_0[] = {
100         /* E1780-A02 (Shield ERS) */
101         [VDD_BAT_0] = {
102                 .calibration_data = 0x1366,
103                 .power_lsb = 2.577527185 * PRECISION_MULTIPLIER_ARDBEG,
104                 .rail_name = "__VDD_BAT",
105                 .trig_conf = INA230_TRIG_CONFIG,
106                 .cont_conf = INA230_CONT_CONFIG,
107                 .divisor = 25,
108                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
109                 .resistor = 10,
110         },
111         [VDD_SYS_BUCKCPU_0] = {
112                 .calibration_data = 0x1AC5,
113                 .power_lsb = 1.867795126 * PRECISION_MULTIPLIER_ARDBEG,
114                 .rail_name = "__VDD_SYS_BUCKCPU",
115                 .trig_conf = INA230_TRIG_CONFIG,
116                 .cont_conf = INA230_CONT_CONFIG,
117                 .divisor = 25,
118                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
119                 .resistor = 10,
120         },
121         [VDD_SYS_BUCKSOC_0] = {
122                 .calibration_data = 0x2802,
123                 .power_lsb = 0.624877954 * PRECISION_MULTIPLIER_ARDBEG,
124                 .rail_name = "__VDD_SYS_BUCKSOC",
125                 .trig_conf = INA230_TRIG_CONFIG,
126                 .cont_conf = INA230_CONT_CONFIG,
127                 .divisor = 25,
128                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
129                 .resistor = 20,
130         },
131         [VDD_SYS_BUCKGPU_0] = {
132                 .calibration_data = 0x1F38,
133                 .power_lsb = 1.601601602 * PRECISION_MULTIPLIER_ARDBEG,
134                 .rail_name = "__VDD_SYS_BUCKGPU",
135                 .trig_conf = INA230_TRIG_CONFIG,
136                 .cont_conf = INA230_CONT_CONFIG,
137                 .divisor = 25,
138                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
139                 .resistor = 10,
140         },
141 };
142
143 /* following are power monitor parameters for Ardbeg */
144 static struct ina230_platform_data power_mon_info_1[] = {
145         [VDD_SYS_BAT] = {
146                 .calibration_data  = 0x1366,
147                 .power_lsb = 2.577527185 * PRECISION_MULTIPLIER_ARDBEG,
148                 .rail_name = "VDD_SYS_BAT",
149                 .trig_conf = INA230_TRIG_CONFIG,
150                 .cont_conf = INA230_CONT_CONFIG,
151                 .divisor = 25,
152                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
153         },
154
155         [VDD_RTC_LDO5] = {
156                 .calibration_data  = 0x7FFF,
157                 .power_lsb = 0.078127384 * PRECISION_MULTIPLIER_ARDBEG,
158                 .rail_name = "VDD_RTC_LDO5",
159                 .trig_conf = INA230_TRIG_CONFIG,
160                 .cont_conf = INA230_CONT_CONFIG,
161                 .divisor = 25,
162                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
163         },
164
165         [VDD_3V3A_SMPS1_2] = {
166                 .calibration_data  = 0x4759,
167                 .power_lsb = 1.401587736 * PRECISION_MULTIPLIER_ARDBEG,
168                 .rail_name = "VDD_3V3A_SMPS1_2",
169                 .trig_conf = INA230_TRIG_CONFIG,
170                 .cont_conf = INA230_CONT_CONFIG,
171                 .divisor = 25,
172                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
173         },
174
175         [VDD_SOC_SMPS1_2] = {
176                 .calibration_data  = 0x7FFF,
177                 .power_lsb = 3.906369213 * PRECISION_MULTIPLIER_ARDBEG,
178                 .rail_name = "VDD_SOC_SMPS1_2",
179                 .trig_conf = INA230_TRIG_CONFIG,
180                 .cont_conf = INA230_CONT_CONFIG,
181                 .divisor = 25,
182                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
183         },
184
185         [VDD_SYS_BUCKCPU] = {
186                 .calibration_data  = 0x1AC5,
187                 .power_lsb = 1.867795126 * PRECISION_MULTIPLIER_ARDBEG,
188                 .rail_name = "VDD_SYS_BUCKCPU",
189                 .trig_conf = INA230_TRIG_CONFIG,
190                 .cont_conf = INA230_CONT_CONFIG,
191                 .divisor = 25,
192                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
193         },
194
195         [VDD_CPU_BUCKCPU] = {
196                 .calibration_data  = 0x2ECF,
197                 .power_lsb = 10.68179922 * PRECISION_MULTIPLIER_ARDBEG,
198                 .rail_name = "VDD_CPU_BUCKCPU",
199                 .trig_conf = INA230_TRIG_CONFIG,
200                 .cont_conf = INA230_CONT_CONFIG,
201                 .divisor = 25,
202                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
203         },
204
205         [VDD_1V8A_SMPS3] = {
206                 .calibration_data  = 0x5BA7,
207                 .power_lsb = 0.545539786 * PRECISION_MULTIPLIER_ARDBEG,
208                 .rail_name = "VDD_1V8A_SMPS3",
209                 .trig_conf = INA230_TRIG_CONFIG,
210                 .cont_conf = INA230_CONT_CONFIG,
211                 .divisor = 25,
212                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
213         },
214
215         [VDD_1V8B_SMPS9] = {
216                 .calibration_data  = 0x50B4,
217                 .power_lsb = 0.309777348 * PRECISION_MULTIPLIER_ARDBEG,
218                 .rail_name = "VDD_1V8B_SMPS9",
219                 .trig_conf = INA230_TRIG_CONFIG,
220                 .cont_conf = INA230_CONT_CONFIG,
221                 .divisor = 25,
222                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
223         },
224
225         [VDD_GPU_BUCKGPU] = {
226                 .calibration_data  = 0x369C,
227                 .power_lsb = 9.155937053 * PRECISION_MULTIPLIER_ARDBEG,
228                 .rail_name = "VDD_GPU_BUCKGPU",
229                 .trig_conf = INA230_TRIG_CONFIG,
230                 .cont_conf = INA230_CONT_CONFIG,
231                 .divisor = 25,
232                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
233         },
234
235         [VDD_1V35_SMPS6] = {
236                 .calibration_data  = 0x7FFF,
237                 .power_lsb = 3.906369213 * PRECISION_MULTIPLIER_ARDBEG,
238                 .rail_name = "VDD_1V35_SMPS6",
239                 .trig_conf = INA230_TRIG_CONFIG,
240                 .cont_conf = INA230_CONT_CONFIG,
241                 .divisor = 25,
242                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
243         },
244
245         /* following rail is duplicate of VDD_3V3A_SMPS1_2 hence mark unused */
246         [VDD_3V3A_SMPS1_2_2] = {
247                 .calibration_data  = 0x4759,
248                 .power_lsb = 1.401587736 * PRECISION_MULTIPLIER_ARDBEG,
249                 .rail_name = "unused_rail",
250                 .trig_conf = INA230_TRIG_CONFIG,
251                 .cont_conf = INA230_CONT_CONFIG,
252                 .divisor = 25,
253                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
254         },
255
256         [VDD_3V3B_SMPS9] = {
257                 .calibration_data  = 0x3269,
258                 .power_lsb = 0.198372724 * PRECISION_MULTIPLIER_ARDBEG,
259                 .rail_name = "VDD_3V3B_SMPS9",
260                 .trig_conf = INA230_TRIG_CONFIG,
261                 .cont_conf = INA230_CONT_CONFIG,
262                 .divisor = 25,
263                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
264         },
265
266         [VDD_LCD_1V8B_DIS] = {
267                 .calibration_data  = 0x7FFF,
268                 .power_lsb = 0.039063692 * PRECISION_MULTIPLIER_ARDBEG,
269                 .rail_name = "VDD_LCD_1V8B_DIS",
270                 .trig_conf = INA230_TRIG_CONFIG,
271                 .cont_conf = INA230_CONT_CONFIG,
272                 .divisor = 25,
273                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
274         },
275
276         [VDD_1V05_SMPS8] = {
277                 .calibration_data  = 0x7FFF,
278                 .power_lsb = 0.130212307 * PRECISION_MULTIPLIER_ARDBEG,
279                 .rail_name = "VDD_1V05_SMPS8",
280                 .trig_conf = INA230_TRIG_CONFIG,
281                 .cont_conf = INA230_CONT_CONFIG,
282                 .divisor = 25,
283                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
284         },
285 };
286
287 static struct ina230_platform_data power_mon_info_2[] = {
288         [VDD_SYS_BL] = {
289                 .calibration_data  = 0x1A29,
290                 .power_lsb = 0.63710119 * PRECISION_MULTIPLIER_ARDBEG,
291                 .rail_name = "VDD_SYS_BL",
292                 .trig_conf = INA230_TRIG_CONFIG,
293                 .cont_conf = INA230_CONT_CONFIG,
294                 .divisor = 25,
295                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
296         },
297
298         [AVDD_1V05_LDO2] = {
299                 .calibration_data  = 0x7FFF,
300                 .power_lsb = 0.390636921 * PRECISION_MULTIPLIER_ARDBEG,
301                 .rail_name = "AVDD_1V05_LDO2",
302                 .trig_conf = INA230_TRIG_CONFIG,
303                 .cont_conf = INA230_CONT_CONFIG,
304                 .divisor = 25,
305                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
306         },
307 };
308
309 /* following are power monitor parameters for Ardbeg A01*/
310 static struct ina230_platform_data ardbeg_A01_power_mon_info_1[] = {
311         [ARDBEG_A01_VDD_SYS_BAT] = {
312                 .calibration_data  = 0x1366,
313                 .power_lsb = 2.577527185 * PRECISION_MULTIPLIER_ARDBEG,
314                 .rail_name = "VDD_SYS_BAT",
315                 .trig_conf = INA230_TRIG_CONFIG,
316                 .cont_conf = INA230_CONT_CONFIG,
317                 .divisor = 25,
318                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
319                 .resistor = 10,
320         },
321
322         [ARDBEG_A01_VDD_RTC_LDO3] = {
323                 .calibration_data  = 0x7FFF,
324                 .power_lsb = 0.078127384 * PRECISION_MULTIPLIER_ARDBEG,
325                 .rail_name = "VDD_RTC_LDO3",
326                 .trig_conf = INA230_TRIG_CONFIG,
327                 .cont_conf = INA230_CONT_CONFIG,
328                 .divisor = 25,
329                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
330                 .resistor = 50,
331         },
332
333         [ARDBEG_A01_VDD_SYS_BUCKSOC] = {
334                 .calibration_data  = 0x1AAC,
335                 .power_lsb = 0.624877954 * PRECISION_MULTIPLIER_ARDBEG,
336                 .rail_name = "VDD_SYS_BUCKSOC",
337                 .trig_conf = INA230_TRIG_CONFIG,
338                 .cont_conf = INA230_CONT_CONFIG,
339                 .divisor = 25,
340                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
341                 .resistor = 30,
342         },
343
344         [ARDBEG_A01_VDD_SOC_SD1] = {
345                 .calibration_data  = 0x7FFF,
346                 .power_lsb = 3.906369213 * PRECISION_MULTIPLIER_ARDBEG,
347                 .rail_name = "VDD_SOC_SD1",
348                 .trig_conf = INA230_TRIG_CONFIG,
349                 .cont_conf = INA230_CONT_CONFIG,
350                 .divisor = 25,
351                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
352                 .resistor = 1,
353         },
354
355         [ARDBEG_A01_VDD_SYS_BUCKCPU] = {
356                 .calibration_data  = 0x1AC5,
357                 .power_lsb = 1.867795126 * PRECISION_MULTIPLIER_ARDBEG,
358                 .rail_name = "VDD_SYS_BUCKCPU",
359                 .trig_conf = INA230_TRIG_CONFIG,
360                 .cont_conf = INA230_CONT_CONFIG,
361                 .divisor = 25,
362                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
363                 .resistor = 10,
364         },
365
366         [ARDBEG_A01_VDD_CPU_BUCKCPU] = {
367                 .calibration_data  = 0x2ECF,
368                 .power_lsb = 10.68179922 * PRECISION_MULTIPLIER_ARDBEG,
369                 .rail_name = "VDD_CPU_BUCKCPU",
370                 .trig_conf = INA230_TRIG_CONFIG,
371                 .cont_conf = INA230_CONT_CONFIG,
372                 .divisor = 25,
373                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
374                 .resistor = 1,
375         },
376
377         [ARDBEG_A01_VDD_1V8_SD5] = {
378                 .calibration_data  = 0x45F0,
379                 .power_lsb = 0.714924039 * PRECISION_MULTIPLIER_ARDBEG,
380                 .rail_name = "VDD_1V8_SD5",
381                 .trig_conf = INA230_TRIG_CONFIG,
382                 .cont_conf = INA230_CONT_CONFIG,
383                 .divisor = 25,
384                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
385                 .resistor = 10,
386         },
387
388         [ARDBEG_A01_VDD_3V3A_LDO1_6] = {
389                 .calibration_data  = 0x3A83,
390                 .power_lsb = 0.042726484 * PRECISION_MULTIPLIER_ARDBEG,
391                 .rail_name = "VDD_3V3A_LDO1_6",
392                 .trig_conf = INA230_TRIG_CONFIG,
393                 .cont_conf = INA230_CONT_CONFIG,
394                 .divisor = 25,
395                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
396                 .resistor = 200,
397         },
398
399         [ARDBEG_A01_VDD_DIS_3V3_LCD] = {
400                 .calibration_data  = 0x7FFF,
401                 .power_lsb = 0.390636921 * PRECISION_MULTIPLIER_ARDBEG,
402                 .rail_name = "VDD_DIS_3V3_LCD",
403                 .trig_conf = INA230_TRIG_CONFIG,
404                 .cont_conf = INA230_CONT_CONFIG,
405                 .divisor = 25,
406                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
407                 .resistor = 10,
408         },
409
410         [ARDBEG_A01_VDD_1V35_SD2] = {
411                 .calibration_data  = 0x7FFF,
412                 .power_lsb = 3.906369213 * PRECISION_MULTIPLIER_ARDBEG,
413                 .rail_name = "VDD_1V35_SD2",
414                 .trig_conf = INA230_TRIG_CONFIG,
415                 .cont_conf = INA230_CONT_CONFIG,
416                 .divisor = 25,
417                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
418                 .resistor = 1,
419         },
420
421         [ARDBEG_A01_VDD_SYS_BUCKGPU] = {
422                 .calibration_data  = 0x1F38,
423                 .power_lsb = 1.601601602 * PRECISION_MULTIPLIER_ARDBEG,
424                 .rail_name = "VDD_SYS_BUCKGPU",
425                 .trig_conf = INA230_TRIG_CONFIG,
426                 .cont_conf = INA230_CONT_CONFIG,
427                 .divisor = 25,
428                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
429                 .resistor = 10,
430         },
431
432         [ARDBEG_A01_VDD_LCD_1V8B_DIS] = {
433                 .calibration_data  = 0x7FFF,
434                 .power_lsb = 0.039063692 * PRECISION_MULTIPLIER_ARDBEG,
435                 .rail_name = "VDD_LCD_1V8B_DIS",
436                 .trig_conf = INA230_TRIG_CONFIG,
437                 .cont_conf = INA230_CONT_CONFIG,
438                 .divisor = 25,
439                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
440                 .resistor = 100,
441         },
442
443         [ARDBEG_A01_VDD_1V05_LDO0] = {
444                 .calibration_data  = 0x7FFF,
445                 .power_lsb = 0.130212307 * PRECISION_MULTIPLIER_ARDBEG,
446                 .rail_name = "VDD_1V05_LDO0",
447                 .trig_conf = INA230_TRIG_CONFIG,
448                 .cont_conf = INA230_CONT_CONFIG,
449                 .divisor = 25,
450                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
451                 .resistor = 30,
452         },
453 };
454
455 static struct ina230_platform_data ardbeg_A01_power_mon_info_2[] = {
456         [ARDBEG_A01_VDD_1V05_SD4] = {
457                 .calibration_data  = 0x7FFF,
458                 .power_lsb = 0.390636921 * PRECISION_MULTIPLIER_ARDBEG,
459                 .rail_name = "VDD_1V05_SD4",
460                 .trig_conf = INA230_TRIG_CONFIG,
461                 .cont_conf = INA230_CONT_CONFIG,
462                 .divisor = 25,
463                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
464                 .resistor = 10,
465         },
466
467         [ARDBEG_A01_VDD_1V8A_LDO2_5_7] = {
468                 .calibration_data  = 0x5A04,
469                 .power_lsb = 0.277729561 * PRECISION_MULTIPLIER_ARDBEG,
470                 .rail_name = "VDD_1V8A_LDO2_5_7",
471                 .trig_conf = INA230_TRIG_CONFIG,
472                 .cont_conf = INA230_CONT_CONFIG,
473                 .divisor = 25,
474                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
475                 .resistor = 20,
476         },
477
478         [ARDBEG_A01_VDD_SYS_BL] = {
479                 .calibration_data  = 0x2468,
480                 .power_lsb = 0.274678112 * PRECISION_MULTIPLIER_ARDBEG,
481                 .rail_name = "VDD_SYS_BL",
482                 .trig_conf = INA230_TRIG_CONFIG,
483                 .cont_conf = INA230_CONT_CONFIG,
484                 .divisor = 25,
485                 .precision_multiplier = PRECISION_MULTIPLIER_ARDBEG,
486                 .resistor = 50,
487         },
488 };
489
490 /* i2c addresses of rails present on Ardbeg */
491 /* addresses on i2c2_0 */
492 enum {
493         INA_I2C_2_0_ADDR_40,
494         INA_I2C_2_0_ADDR_41,
495         INA_I2C_2_0_ADDR_42,
496         INA_I2C_2_0_ADDR_43,
497 };
498
499 /* addresses on i2c2_1 */
500 enum {
501         INA_I2C_2_1_ADDR_40,
502         INA_I2C_2_1_ADDR_41,
503         INA_I2C_2_1_ADDR_42,
504         INA_I2C_2_1_ADDR_43,
505         INA_I2C_2_1_ADDR_44,
506         INA_I2C_2_1_ADDR_45,
507         INA_I2C_2_1_ADDR_46,
508         INA_I2C_2_1_ADDR_47,
509         INA_I2C_2_1_ADDR_48,
510         INA_I2C_2_1_ADDR_49,
511         INA_I2C_2_1_ADDR_4B,
512         INA_I2C_2_1_ADDR_4C,
513         INA_I2C_2_1_ADDR_4E,
514         INA_I2C_2_1_ADDR_4F,
515 };
516
517 /* addresses on i2c2_2 */
518 enum {
519         INA_I2C_2_2_ADDR_49,
520         INA_I2C_2_2_ADDR_4C,
521 };
522
523 /* i2c addresses of rails present on Ardbeg A01*/
524 /* addresses on i2c2_1 */
525 enum {
526         ARDBEG_A01_INA_I2C_2_1_ADDR_40,
527         ARDBEG_A01_INA_I2C_2_1_ADDR_41,
528         ARDBEG_A01_INA_I2C_2_1_ADDR_42,
529         ARDBEG_A01_INA_I2C_2_1_ADDR_43,
530         ARDBEG_A01_INA_I2C_2_1_ADDR_44,
531         ARDBEG_A01_INA_I2C_2_1_ADDR_45,
532         ARDBEG_A01_INA_I2C_2_1_ADDR_46,
533         ARDBEG_A01_INA_I2C_2_1_ADDR_47,
534         ARDBEG_A01_INA_I2C_2_1_ADDR_48,
535         ARDBEG_A01_INA_I2C_2_1_ADDR_49,
536         ARDBEG_A01_INA_I2C_2_1_ADDR_4B,
537         ARDBEG_A01_INA_I2C_2_1_ADDR_4E,
538         ARDBEG_A01_INA_I2C_2_1_ADDR_4F,
539 };
540
541 /* addresses on i2c2_2 */
542 enum {
543         ARDBEG_A01_INA_I2C_2_2_ADDR_40,
544         ARDBEG_A01_INA_I2C_2_2_ADDR_41,
545         ARDBEG_A01_INA_I2C_2_2_ADDR_49,
546 };
547
548 /* following is the i2c board info for Ardbeg */
549 static struct i2c_board_info ardbeg_i2c2_0_ina230_board_info[] = {
550         [INA_I2C_2_0_ADDR_40] = {
551                 I2C_BOARD_INFO("ina230", 0x40),
552                 .platform_data = &power_mon_info_0[VDD_BAT_0],
553                 .irq = -1,
554         },
555
556         [INA_I2C_2_0_ADDR_41] = {
557                 I2C_BOARD_INFO("ina230", 0x41),
558                 .platform_data = &power_mon_info_0[VDD_SYS_BUCKCPU_0],
559                 .irq = -1,
560         },
561
562         [INA_I2C_2_0_ADDR_42] = {
563                 I2C_BOARD_INFO("ina230", 0x42),
564                 .platform_data = &power_mon_info_0[VDD_SYS_BUCKSOC_0],
565                 .irq = -1,
566         },
567
568         [INA_I2C_2_0_ADDR_43] = {
569                 I2C_BOARD_INFO("ina230", 0x43),
570                 .platform_data = &power_mon_info_0[VDD_SYS_BUCKGPU_0],
571                 .irq = -1,
572         },
573 };
574
575 static struct i2c_board_info ardbeg_i2c2_1_ina230_board_info[] = {
576         [INA_I2C_2_1_ADDR_40] = {
577                 I2C_BOARD_INFO("ina230", 0x40),
578                 .platform_data = &power_mon_info_1[VDD_SYS_BAT],
579                 .irq = -1,
580         },
581
582         [INA_I2C_2_1_ADDR_41] = {
583                 I2C_BOARD_INFO("ina230", 0x41),
584                 .platform_data = &power_mon_info_1[VDD_RTC_LDO5],
585                 .irq = -1,
586         },
587
588         [INA_I2C_2_1_ADDR_42] = {
589                 I2C_BOARD_INFO("ina230", 0x42),
590                 .platform_data = &power_mon_info_1[VDD_3V3A_SMPS1_2],
591                 .irq = -1,
592         },
593
594         [INA_I2C_2_1_ADDR_43] = {
595                 I2C_BOARD_INFO("ina230", 0x43),
596                 .platform_data = &power_mon_info_1[VDD_SOC_SMPS1_2],
597                 .irq = -1,
598         },
599
600         [INA_I2C_2_1_ADDR_44] = {
601                 I2C_BOARD_INFO("ina230", 0x44),
602                 .platform_data = &power_mon_info_1[VDD_SYS_BUCKCPU],
603                 .irq = -1,
604         },
605
606         [INA_I2C_2_1_ADDR_45] = {
607                 I2C_BOARD_INFO("ina230", 0x45),
608                 .platform_data = &power_mon_info_1[VDD_CPU_BUCKCPU],
609                 .irq = -1,
610         },
611
612         [INA_I2C_2_1_ADDR_46] = {
613                 I2C_BOARD_INFO("ina230", 0x46),
614                 .platform_data = &power_mon_info_1[VDD_1V8A_SMPS3],
615                 .irq = -1,
616         },
617
618         [INA_I2C_2_1_ADDR_47] = {
619                 I2C_BOARD_INFO("ina230", 0x47),
620                 .platform_data = &power_mon_info_1[VDD_1V8B_SMPS9],
621                 .irq = -1,
622         },
623
624         [INA_I2C_2_1_ADDR_48] = {
625                 I2C_BOARD_INFO("ina230", 0x48),
626                 .platform_data = &power_mon_info_1[VDD_GPU_BUCKGPU],
627                 .irq = -1,
628         },
629
630         [INA_I2C_2_1_ADDR_49] = {
631                 I2C_BOARD_INFO("ina230", 0x49),
632                 .platform_data = &power_mon_info_1[VDD_1V35_SMPS6],
633                 .irq = -1,
634         },
635
636         [INA_I2C_2_1_ADDR_4B] = {
637                 I2C_BOARD_INFO("ina230", 0x4B),
638                 .platform_data = &power_mon_info_1[VDD_3V3A_SMPS1_2_2],
639                 .irq = -1,
640         },
641
642         [INA_I2C_2_1_ADDR_4C] = {
643                 I2C_BOARD_INFO("ina230", 0x4C),
644                 .platform_data = &power_mon_info_1[VDD_3V3B_SMPS9],
645                 .irq = -1,
646         },
647
648         [INA_I2C_2_1_ADDR_4E] = {
649                 I2C_BOARD_INFO("ina230", 0x4E),
650                 .platform_data = &power_mon_info_1[VDD_LCD_1V8B_DIS],
651                 .irq = -1,
652         },
653
654         [INA_I2C_2_1_ADDR_4F] = {
655                 I2C_BOARD_INFO("ina230", 0x4F),
656                 .platform_data = &power_mon_info_1[VDD_1V05_SMPS8],
657                 .irq = -1,
658         },
659 };
660
661 static struct i2c_board_info ardbeg_i2c2_2_ina230_board_info[] = {
662         [INA_I2C_2_2_ADDR_49] = {
663                 I2C_BOARD_INFO("ina230", 0x49),
664                 .platform_data = &power_mon_info_2[VDD_SYS_BL],
665                 .irq = -1,
666         },
667
668         [INA_I2C_2_2_ADDR_4C] = {
669                 I2C_BOARD_INFO("ina230", 0x4C),
670                 .platform_data = &power_mon_info_2[AVDD_1V05_LDO2],
671                 .irq = -1,
672         },
673
674 };
675
676 /* following is the i2c board info for Ardbeg A01 */
677 static struct i2c_board_info ardbeg_A01_i2c2_1_ina230_board_info[] = {
678         [ARDBEG_A01_INA_I2C_2_1_ADDR_40] = {
679                 I2C_BOARD_INFO("ina230", 0x40),
680                 .platform_data =
681                         &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SYS_BAT],
682                 .irq = -1,
683         },
684
685         [ARDBEG_A01_INA_I2C_2_1_ADDR_41] = {
686                 I2C_BOARD_INFO("ina230", 0x41),
687                 .platform_data =
688                         &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_RTC_LDO3],
689                 .irq = -1,
690         },
691
692         [ARDBEG_A01_INA_I2C_2_1_ADDR_42] = {
693                 I2C_BOARD_INFO("ina230", 0x42),
694                 .platform_data =
695                 &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SYS_BUCKSOC],
696                 .irq = -1,
697         },
698
699         [ARDBEG_A01_INA_I2C_2_1_ADDR_43] = {
700                 I2C_BOARD_INFO("ina230", 0x43),
701                 .platform_data =
702                         &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SOC_SD1],
703                 .irq = -1,
704         },
705
706         [ARDBEG_A01_INA_I2C_2_1_ADDR_44] = {
707                 I2C_BOARD_INFO("ina230", 0x44),
708                 .platform_data =
709                 &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SYS_BUCKCPU],
710                 .irq = -1,
711         },
712
713         [ARDBEG_A01_INA_I2C_2_1_ADDR_45] = {
714                 I2C_BOARD_INFO("ina230", 0x45),
715                 .platform_data =
716                 &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_CPU_BUCKCPU],
717                 .irq = -1,
718         },
719
720         [ARDBEG_A01_INA_I2C_2_1_ADDR_46] = {
721                 I2C_BOARD_INFO("ina230", 0x46),
722                 .platform_data =
723                         &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_1V8_SD5],
724                 .irq = -1,
725         },
726
727         [ARDBEG_A01_INA_I2C_2_1_ADDR_47] = {
728                 I2C_BOARD_INFO("ina230", 0x47),
729                 .platform_data =
730                 &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_3V3A_LDO1_6],
731                 .irq = -1,
732         },
733
734         [ARDBEG_A01_INA_I2C_2_1_ADDR_48] = {
735                 I2C_BOARD_INFO("ina230", 0x48),
736                 .platform_data =
737                 &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_DIS_3V3_LCD],
738                 .irq = -1,
739         },
740
741         [ARDBEG_A01_INA_I2C_2_1_ADDR_49] = {
742                 I2C_BOARD_INFO("ina230", 0x49),
743                 .platform_data =
744                         &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_1V35_SD2],
745                 .irq = -1,
746         },
747
748         [ARDBEG_A01_INA_I2C_2_1_ADDR_4B] = {
749                 I2C_BOARD_INFO("ina230", 0x4B),
750                 .platform_data =
751                 &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SYS_BUCKGPU],
752                 .irq = -1,
753         },
754
755         [ARDBEG_A01_INA_I2C_2_1_ADDR_4E] = {
756                 I2C_BOARD_INFO("ina230", 0x4E),
757                 .platform_data =
758                 &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_LCD_1V8B_DIS],
759                 .irq = -1,
760         },
761
762         [ARDBEG_A01_INA_I2C_2_1_ADDR_4F] = {
763                 I2C_BOARD_INFO("ina230", 0x4F),
764                 .platform_data =
765                         &ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_1V05_LDO0],
766                 .irq = -1,
767         },
768 };
769
770 static struct i2c_board_info ardbeg_A01_i2c2_2_ina230_board_info[] = {
771         [ARDBEG_A01_INA_I2C_2_2_ADDR_40] = {
772                 I2C_BOARD_INFO("ina230", 0x40),
773                 .platform_data =
774                         &ardbeg_A01_power_mon_info_2[ARDBEG_A01_VDD_1V05_SD4],
775                 .irq = -1,
776         },
777
778         [ARDBEG_A01_INA_I2C_2_2_ADDR_41] = {
779                 I2C_BOARD_INFO("ina230", 0x41),
780                 .platform_data =
781                 &ardbeg_A01_power_mon_info_2[ARDBEG_A01_VDD_1V8A_LDO2_5_7],
782                 .irq = -1,
783         },
784
785         [ARDBEG_A01_INA_I2C_2_2_ADDR_49] = {
786                 I2C_BOARD_INFO("ina230", 0x49),
787                 .platform_data =
788                         &ardbeg_A01_power_mon_info_2[ARDBEG_A01_VDD_SYS_BL],
789                 .irq = -1,
790         },
791 };
792
793 static void __init register_devices_ardbeg_A01(void)
794 {
795         i2c_register_board_info(PCA954x_I2C_BUS1,
796                         ardbeg_A01_i2c2_1_ina230_board_info,
797                         ARRAY_SIZE(ardbeg_A01_i2c2_1_ina230_board_info));
798
799         i2c_register_board_info(PCA954x_I2C_BUS2,
800                         ardbeg_A01_i2c2_2_ina230_board_info,
801                         ARRAY_SIZE(ardbeg_A01_i2c2_2_ina230_board_info));
802 }
803
804 static void __init register_devices_ardbeg(void)
805 {
806         i2c_register_board_info(PCA954x_I2C_BUS1,
807                         ardbeg_i2c2_1_ina230_board_info,
808                         ARRAY_SIZE(ardbeg_i2c2_1_ina230_board_info));
809
810         i2c_register_board_info(PCA954x_I2C_BUS2,
811                         ardbeg_i2c2_2_ina230_board_info,
812                         ARRAY_SIZE(ardbeg_i2c2_2_ina230_board_info));
813 }
814
815 static void modify_reworked_rail_data(void)
816 {
817         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_1V35_SD2].resistor
818                                         = VDD_1V35_SD2_REWORKED;
819         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_CPU_BUCKCPU].resistor
820                                         = VDD_CPU_BUCKCPU_REWORKED;
821         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SOC_SD1].resistor
822                                         = VDD_SOC_SD1_REWORKED;
823 }
824
825 static void modify_tn8_rail_data(void)
826 {
827         /* E1780-A02 TN8 w/ E1736-A00 PMU*/
828         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SYS_BAT]
829                 .calibration_data  = 0x3547;
830         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SYS_BAT]
831                 .power_lsb = 3.128284087 * PRECISION_MULTIPLIER_ARDBEG;
832         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SYS_BAT]
833                 .resistor = 3;
834
835         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SYS_BUCKSOC]
836                 .calibration_data  = 0x2ED7;
837         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SYS_BUCKSOC]
838                 .power_lsb = 1.067467267 * PRECISION_MULTIPLIER_ARDBEG;
839         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_SYS_BUCKSOC]
840                 .resistor = 10;
841
842         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_3V3A_LDO1_6]
843                 .calibration_data  = 0x7FFF;
844         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_3V3A_LDO1_6]
845                 .power_lsb = 0.390636921 * PRECISION_MULTIPLIER_ARDBEG;
846         ardbeg_A01_power_mon_info_1[ARDBEG_A01_VDD_3V3A_LDO1_6]
847                 .resistor = 10;
848
849         ardbeg_A01_power_mon_info_2[ARDBEG_A01_VDD_1V8A_LDO2_5_7]
850                 .calibration_data  = 0x7FFF;
851         ardbeg_A01_power_mon_info_2[ARDBEG_A01_VDD_1V8A_LDO2_5_7]
852                 .power_lsb = 0.390636921 * PRECISION_MULTIPLIER_ARDBEG;
853         ardbeg_A01_power_mon_info_2[ARDBEG_A01_VDD_1V8A_LDO2_5_7]
854                 .resistor = 10;
855
856         power_mon_info_0[VDD_BAT_0]
857                 .calibration_data = 0x1FF7;
858         power_mon_info_0[VDD_BAT_0]
859                 .power_lsb = 3.128437004 * PRECISION_MULTIPLIER_ARDBEG;
860         power_mon_info_0[VDD_BAT_0]
861                 .resistor = 5;
862
863         power_mon_info_0[VDD_SYS_BUCKSOC_0]
864                 .calibration_data = 0x2ED7;
865         power_mon_info_0[VDD_SYS_BUCKSOC_0]
866                 .power_lsb = 1.067467267 * PRECISION_MULTIPLIER_ARDBEG;
867         power_mon_info_0[VDD_SYS_BUCKSOC_0]
868                 .resistor = 10;
869 }
870
871 int __init ardbeg_pmon_init(void)
872 {
873         /*
874         * Get power_config of board and check whether
875         * board is power reworked or not.
876         * In case board is reworked, modify rail data
877         * for which rework was done.
878         */
879         u8 power_config;
880         struct board_info bi;
881         power_config = get_power_config();
882         if (power_config & ARDBEG_POWER_REWORKED_CONFIG)
883                 modify_reworked_rail_data();
884
885         tegra_get_board_info(&bi);
886
887         if (bi.sku == 1100)
888                 modify_tn8_rail_data();
889
890         i2c_register_board_info(PCA954x_I2C_BUS0,
891                         ardbeg_i2c2_0_ina230_board_info,
892                         ARRAY_SIZE(ardbeg_i2c2_0_ina230_board_info));
893
894         if (bi.fab >= BOARD_FAB_A01)
895                 register_devices_ardbeg_A01();
896         else if ((bi.board_id != BOARD_E1784) &&
897                 (bi.board_id != BOARD_E1922) &&
898                 (bi.board_id != BOARD_E1923))
899                 register_devices_ardbeg();
900
901         return 0;
902 }
903