arch: arm: ardbeg: power regulator for vi
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-power.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-power.c
3  *
4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/resource.h>
23 #include <linux/io.h>
24 #include <mach/irqs.h>
25 #include <mach/hardware.h>
26 #include <linux/regulator/fixed.h>
27 #include <linux/mfd/palmas.h>
28 #include <linux/regulator/tps51632-regulator.h>
29 #include <linux/regulator/machine.h>
30 #include <linux/irq.h>
31
32 #include <asm/mach-types.h>
33
34 #include "pm.h"
35 #include "board.h"
36 #include "board-common.h"
37 #include "board-ardbeg.h"
38 #include "board-pmu-defines.h"
39 #include "devices.h"
40 #include "iomap.h"
41
42 #define PMC_CTRL                0x0
43 #define PMC_CTRL_INTR_LOW       (1 << 17)
44
45
46 /************************ ARDBEG based regulator *****************/
47 static struct regulator_consumer_supply palmas_smps12_supply[] = {
48         REGULATOR_SUPPLY("vdd_core", NULL),
49 };
50
51 static struct regulator_consumer_supply palmas_smps3_supply[] = {
52         REGULATOR_SUPPLY("vdd_modem", NULL),
53 };
54
55 static struct regulator_consumer_supply palmas_smps6_supply[] = {
56         REGULATOR_SUPPLY("vddio_ddr", NULL),
57         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
58         REGULATOR_SUPPLY("vddio_ddr3", NULL),
59         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
60 };
61
62 static struct regulator_consumer_supply palmas_smps8_supply[] = {
63         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
64         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
65         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
66         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
67         REGULATOR_SUPPLY("avdd_pll_m", NULL),
68         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
69         REGULATOR_SUPPLY("avdd_pll_utmip", NULL),
70         REGULATOR_SUPPLY("avdd_pll_x", NULL),
71         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
72         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
73 };
74
75 static struct regulator_consumer_supply palmas_smps9_supply[] = {
76         REGULATOR_SUPPLY("vdd_aud_dgtl", NULL),
77         REGULATOR_SUPPLY("vdd_aud_anlg", NULL),
78         REGULATOR_SUPPLY("vdd_aud_mic", NULL),
79         REGULATOR_SUPPLY("avdd_osc", NULL),
80         REGULATOR_SUPPLY("vddio_sys", NULL),
81         REGULATOR_SUPPLY("vddio_sys_2", NULL),
82         REGULATOR_SUPPLY("vddio_gmi", NULL),
83         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
84         REGULATOR_SUPPLY("vdd_1v8b_pll_utmip", NULL),
85         REGULATOR_SUPPLY("vddio_cam", "vi"),
86         REGULATOR_SUPPLY("vddio_audio", NULL),
87         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
88         REGULATOR_SUPPLY("vddio_uart", NULL),
89         REGULATOR_SUPPLY("vddio_bb", NULL),
90         REGULATOR_SUPPLY("vdd_sys_mb", NULL),
91         REGULATOR_SUPPLY("vdd_gmi_mb", NULL),
92         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
93         REGULATOR_SUPPLY("vdd_1v8b_ts", NULL),
94         REGULATOR_SUPPLY("vdd_1v8b_audio_mb", NULL),
95         REGULATOR_SUPPLY("vdd_1v8b_com_f", NULL),
96         REGULATOR_SUPPLY("vdd_1v8b_gps_f", NULL),
97         REGULATOR_SUPPLY("vdd_1v8b_nfc", NULL),
98         REGULATOR_SUPPLY("vdd_1v8b_uart_mb", NULL),
99         REGULATOR_SUPPLY("vdd_1v8b", "0-0048"),
100         REGULATOR_SUPPLY("vdd_dtv", NULL),
101         REGULATOR_SUPPLY("vdd_1v8_bb_mb", NULL),
102         REGULATOR_SUPPLY("vdd_1v8_uart_mdm", NULL),
103         REGULATOR_SUPPLY("vdd_1v8_eeprom", NULL),
104         REGULATOR_SUPPLY("vdd_1v8_dbg", NULL),
105         REGULATOR_SUPPLY("vdd_1v8_pm", NULL),
106 };
107
108
109 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
110         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
111 };
112
113 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
114         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
115         REGULATOR_SUPPLY("avdd_hdmi", NULL),
116         REGULATOR_SUPPLY("avdd_pex_pll", NULL),
117         REGULATOR_SUPPLY("avddio_pex_pll", NULL),
118         REGULATOR_SUPPLY("dvddio_pex", NULL),
119 };
120
121 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
122         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
123         REGULATOR_SUPPLY("vdd_cam_1v8_cam", NULL),
124 };
125
126 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
127         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
128 };
129
130 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
131         REGULATOR_SUPPLY("vdd_rtc", NULL),
132 };
133
134 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
135         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
136 };
137
138 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
139         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
140 };
141
142 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
143         REGULATOR_SUPPLY("vdd_snsr_mb", NULL),
144         REGULATOR_SUPPLY("vdd_snsr_temp", NULL),
145         REGULATOR_SUPPLY("vdd", "0-0048"),
146         REGULATOR_SUPPLY("vdd_snsr_pm", NULL),
147 };
148
149 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
150         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
151         REGULATOR_SUPPLY("avdd_1v2_hsic_mdm", NULL),
152         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
153         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
154         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
155         REGULATOR_SUPPLY("avdd_1v2_hsic_com", NULL),
156 };
157
158 static struct regulator_consumer_supply palmas_ldo10_supply[] = {
159         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
160 };
161
162 static struct regulator_consumer_supply palmas_ldo11_supply[] = {
163         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
164         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
165         REGULATOR_SUPPLY("avdd_3v3_pex", NULL),
166         REGULATOR_SUPPLY("avdd_3v3_pex_pll", NULL),
167 };
168
169 static struct regulator_consumer_supply palmas_ldo12_supply[] = {
170         REGULATOR_SUPPLY("vdd_lcd_1v8b_dis", NULL),
171 };
172
173 static struct regulator_consumer_supply palmas_ldo13_supply[] = {
174         REGULATOR_SUPPLY("vdd_ts_1v8b_dis", NULL),
175 };
176
177 static struct regulator_consumer_supply palmas_ldo14_supply[] = {
178         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
179 };
180
181 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
182         REGULATOR_SUPPLY("avdd_ts_dis", NULL),
183 };
184
185 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
186         REGULATOR_SUPPLY("vpp_fuse", NULL),
187 };
188
189 static struct regulator_consumer_supply palmas_regen1_supply[] = {
190         REGULATOR_SUPPLY("vdd_com_3v3", NULL),
191         REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
192         REGULATOR_SUPPLY("vdd_nfc_3v3", NULL),
193 };
194
195 static struct regulator_consumer_supply palmas_regen2_supply[] = {
196 };
197
198 static struct regulator_consumer_supply palmas_regen4_supply[] = {
199         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
200 };
201
202 /* TPS51632 DC-DC converter */
203 static struct regulator_consumer_supply tps51632_dcdc_cpu_supply[] = {
204         REGULATOR_SUPPLY("vdd_cpu", NULL),
205 };
206
207 static struct regulator_init_data tps51632_cpu_init_data = {
208         .constraints = {                                                \
209                 .min_uV = 500000,                                       \
210                 .max_uV = 1520000,                                      \
211                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
212                                         REGULATOR_MODE_STANDBY),        \
213                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
214                                         REGULATOR_CHANGE_STATUS |       \
215                                          REGULATOR_CHANGE_CONTROL |     \
216                                         REGULATOR_CHANGE_VOLTAGE),      \
217                 .always_on = 1,                                         \
218                 .boot_on =  1,                                          \
219                 .apply_uV = 0,                                          \
220         },                                                              \
221         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_cpu_supply),  \
222         .consumer_supplies = tps51632_dcdc_cpu_supply,          \
223         .supply_regulator = palmas_rails(regen2),                       \
224 };
225
226 static struct tps51632_regulator_platform_data tps51632_pdata_cpu = {
227         .reg_init_data = &tps51632_cpu_init_data,               \
228         .enable_pwm = false,                            \
229         .max_voltage_uV = 1520000,                      \
230         .base_voltage_uV = 500000,                      \
231         .slew_rate_uv_per_us = 6000,                    \
232 };
233
234 static struct i2c_board_info tps51632_cpu_boardinfo[] = {
235         {
236                 I2C_BOARD_INFO("tps51632_cpu", 0x43),
237                 .platform_data  = &tps51632_pdata_cpu,
238         },
239 };
240
241 static struct regulator_consumer_supply tps51632_dcdc_gpu_supply[] = {
242         REGULATOR_SUPPLY("vdd_gpu", NULL),
243 };
244
245 static struct regulator_init_data tps51632_init_gpu_data = {
246         .constraints = {                                                \
247                 .min_uV = 500000,                                       \
248                 .max_uV = 1520000,                                      \
249                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
250                                         REGULATOR_MODE_STANDBY),        \
251                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
252                                         REGULATOR_CHANGE_STATUS |       \
253                                          REGULATOR_CHANGE_CONTROL |     \
254                                         REGULATOR_CHANGE_VOLTAGE),      \
255                 .always_on = 1,                                         \
256                 .boot_on =  1,                                          \
257                 .apply_uV = 0,                                          \
258         },                                                              \
259         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_gpu_supply),  \
260         .consumer_supplies = tps51632_dcdc_gpu_supply,          \
261         .supply_regulator = palmas_rails(regen2),                       \
262 };
263
264 static struct tps51632_regulator_platform_data tps51632_pdata_gpu = {
265         .reg_init_data = &tps51632_init_gpu_data,               \
266         .enable_pwm = false,                            \
267         .max_voltage_uV = 1520000,                      \
268         .base_voltage_uV = 500000,                      \
269         .slew_rate_uv_per_us = 6000,                    \
270 };
271
272 static struct i2c_board_info tps51632_gpu_boardinfo[] = {
273         {
274                 I2C_BOARD_INFO("tps51632_gpu", 0x45),
275                 .platform_data  = &tps51632_pdata_gpu,
276         },
277 };
278
279 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
280         _boot_on, _apply_uv)                                            \
281         static struct regulator_init_data reg_idata_##_name = {         \
282                 .constraints = {                                        \
283                         .name = palmas_rails(_name),                    \
284                         .min_uV = (_minmv)*1000,                        \
285                         .max_uV = (_maxmv)*1000,                        \
286                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
287                                         REGULATOR_MODE_STANDBY),        \
288                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
289                                         REGULATOR_CHANGE_STATUS |       \
290                                         REGULATOR_CHANGE_VOLTAGE),      \
291                         .always_on = _always_on,                        \
292                         .boot_on = _boot_on,                            \
293                         .apply_uV = _apply_uv,                          \
294                 },                                                      \
295                 .num_consumer_supplies =                                \
296                         ARRAY_SIZE(palmas_##_name##_supply),            \
297                 .consumer_supplies = palmas_##_name##_supply,           \
298                 .supply_regulator = _supply_reg,                        \
299         }
300
301 PALMAS_PDATA_INIT(smps12, 900, 1300, NULL, 0, 0, 0);
302 PALMAS_PDATA_INIT(smps3, 1000, 3300, NULL, 0, 0, 0);
303 PALMAS_PDATA_INIT(smps6, 500, 1650, NULL, 0, 0, 0);
304 PALMAS_PDATA_INIT(smps8, 1000, 3300, NULL, 0, 0, 0);
305 PALMAS_PDATA_INIT(smps9, 1800, 1800, NULL, 0, 0, 0);
306 PALMAS_PDATA_INIT(ldo1, 1050, 1050, palmas_rails(smps3), 0, 0, 1);
307 PALMAS_PDATA_INIT(ldo2, 2800, 3000, palmas_rails(smps6), 0, 0, 0);
308 PALMAS_PDATA_INIT(ldo3, 2800, 3000, NULL, 0, 0, 0);
309 PALMAS_PDATA_INIT(ldo4, 2800, 3000, palmas_rails(smps3), 0, 0, 0);
310 PALMAS_PDATA_INIT(ldo5, 1100, 1100, palmas_rails(smps6), 1, 1, 1);
311 PALMAS_PDATA_INIT(ldo6, 2700, 2700, NULL, 0, 0, 0);
312 PALMAS_PDATA_INIT(ldo7, 2800, 2800, NULL, 0, 0, 0);
313 PALMAS_PDATA_INIT(ldo8, 2800, 3000, NULL, 0, 0, 0);
314 PALMAS_PDATA_INIT(ldo9, 2800, 3000, palmas_rails(smps3), 0, 0, 0);
315 PALMAS_PDATA_INIT(ldo10, 1800, 3300, NULL, 0, 0, 0);
316 PALMAS_PDATA_INIT(ldo11, 3300, 3300, NULL, 0, 0, 0);
317 PALMAS_PDATA_INIT(ldo12, 2800, 3000, palmas_rails(smps9), 0, 0, 0);
318 PALMAS_PDATA_INIT(ldo13, 2800, 3000, palmas_rails(smps9), 0, 0, 0);
319 PALMAS_PDATA_INIT(ldo14, 2800, 3000, NULL, 0, 0, 0);
320 PALMAS_PDATA_INIT(ldoln, 2800, 3000, NULL, 0, 0, 0);
321 PALMAS_PDATA_INIT(ldousb, 2800, 3000, NULL, 0, 0, 0);
322 PALMAS_PDATA_INIT(regen1, 3300, 3300, NULL, 1, 0, 0);
323 PALMAS_PDATA_INIT(regen2, 5000, 5000, NULL, 1, 0, 0);
324 PALMAS_PDATA_INIT(regen4, 5000, 5000, NULL, 0, 0, 0);
325
326 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
327
328 static struct regulator_init_data *ardbeg_reg_data[PALMAS_NUM_REGS] = {
329         PALMAS_REG_PDATA(smps12),
330         NULL,
331         PALMAS_REG_PDATA(smps3),
332         NULL,
333         NULL,
334         PALMAS_REG_PDATA(smps6),
335         NULL,
336         PALMAS_REG_PDATA(smps8),
337         PALMAS_REG_PDATA(smps9),
338         NULL,
339         PALMAS_REG_PDATA(ldo1),
340         PALMAS_REG_PDATA(ldo2),
341         PALMAS_REG_PDATA(ldo3),
342         PALMAS_REG_PDATA(ldo4),
343         PALMAS_REG_PDATA(ldo5),
344         PALMAS_REG_PDATA(ldo6),
345         PALMAS_REG_PDATA(ldo7),
346         PALMAS_REG_PDATA(ldo8),
347         PALMAS_REG_PDATA(ldo9),
348         PALMAS_REG_PDATA(ldo10),
349         PALMAS_REG_PDATA(ldo11),
350         PALMAS_REG_PDATA(ldo12),
351         PALMAS_REG_PDATA(ldo13),
352         PALMAS_REG_PDATA(ldo14),
353         PALMAS_REG_PDATA(ldoln),
354         PALMAS_REG_PDATA(ldousb),
355         PALMAS_REG_PDATA(regen1),
356         PALMAS_REG_PDATA(regen2),
357         NULL,
358         PALMAS_REG_PDATA(regen4),
359         NULL,
360         NULL,
361         NULL,
362         NULL,
363         NULL,
364 };
365
366 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
367                 _tstep, _vsel)                                          \
368         static struct palmas_reg_init reg_init_data_##_name = {         \
369                 .warm_reset = _warm_reset,                              \
370                 .roof_floor =   _roof_floor,                            \
371                 .mode_sleep = _mode_sleep,              \
372                 .tstep = _tstep,                        \
373                 .vsel = _vsel,          \
374         }
375
376 PALMAS_REG_INIT(smps12, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
377 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
378 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
379 PALMAS_REG_INIT(smps45, 0, 0, 0, 0, 0);
380 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
381 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
382 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
383 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
384 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
385 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
386 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
387 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
388 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
389 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
390 PALMAS_REG_INIT(ldo5, 0, PALMAS_EXT_CONTROL_NSLEEP, 1, 0, 0);
391 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
392 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
393 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
394 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
395 PALMAS_REG_INIT(ldo10, 0, 0, 0, 0, 0);
396 PALMAS_REG_INIT(ldo11, 0, 0, 0, 0, 0);
397 PALMAS_REG_INIT(ldo12, 0, 0, 0, 0, 0);
398 PALMAS_REG_INIT(ldo13, 0, 0, 0, 0, 0);
399 PALMAS_REG_INIT(ldo14, 0, 0, 0, 0, 0);
400 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
401 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
402
403 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
404 static struct palmas_reg_init *ardbeg_reg_init[PALMAS_NUM_REGS] = {
405         PALMAS_REG_INIT_DATA(smps12),
406         PALMAS_REG_INIT_DATA(smps123),
407         PALMAS_REG_INIT_DATA(smps3),
408         PALMAS_REG_INIT_DATA(smps45),
409         PALMAS_REG_INIT_DATA(smps457),
410         PALMAS_REG_INIT_DATA(smps6),
411         PALMAS_REG_INIT_DATA(smps7),
412         PALMAS_REG_INIT_DATA(smps8),
413         PALMAS_REG_INIT_DATA(smps9),
414         PALMAS_REG_INIT_DATA(smps10),
415         PALMAS_REG_INIT_DATA(ldo1),
416         PALMAS_REG_INIT_DATA(ldo2),
417         PALMAS_REG_INIT_DATA(ldo3),
418         PALMAS_REG_INIT_DATA(ldo4),
419         PALMAS_REG_INIT_DATA(ldo5),
420         PALMAS_REG_INIT_DATA(ldo6),
421         PALMAS_REG_INIT_DATA(ldo7),
422         PALMAS_REG_INIT_DATA(ldo8),
423         PALMAS_REG_INIT_DATA(ldo9),
424         PALMAS_REG_INIT_DATA(ldo10),
425         PALMAS_REG_INIT_DATA(ldo11),
426         PALMAS_REG_INIT_DATA(ldo12),
427         PALMAS_REG_INIT_DATA(ldo13),
428         PALMAS_REG_INIT_DATA(ldo14),
429         PALMAS_REG_INIT_DATA(ldoln),
430         PALMAS_REG_INIT_DATA(ldousb),
431 };
432
433 /* Macro for defining fixed regulator sub device data */
434 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
435 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
436         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
437         _sdelay)                                                        \
438         static struct regulator_init_data ri_data_##_var =              \
439         {                                                               \
440                 .supply_regulator = _in_supply,                         \
441                 .num_consumer_supplies =                                \
442                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
443                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
444                 .constraints = {                                        \
445                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
446                                         REGULATOR_MODE_STANDBY),        \
447                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
448                                         REGULATOR_CHANGE_STATUS |       \
449                                         REGULATOR_CHANGE_VOLTAGE),      \
450                         .always_on = _always_on,                        \
451                         .boot_on = _boot_on,                            \
452                 },                                                      \
453         };                                                              \
454         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
455         {                                                               \
456                 .supply_name = FIXED_SUPPLY(_name),                     \
457                 .microvolts = _millivolts * 1000,                       \
458                 .gpio = _gpio_nr,                                       \
459                 .gpio_is_open_drain = _open_drain,                      \
460                 .enable_high = _active_high,                            \
461                 .enabled_at_boot = _boot_state,                         \
462                 .init_data = &ri_data_##_var,                           \
463                 .startup_delay = _sdelay                                \
464         };                                                              \
465         static struct platform_device fixed_reg_en_##_var##_dev = {     \
466                 .name = "reg-fixed-voltage",                            \
467                 .id = _id,                                              \
468                 .dev = {                                                \
469                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
470                 },                                                      \
471         }
472
473
474 /* Always ON /Battery regulator */
475 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
476                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
477                 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
478 };
479
480 static struct regulator_consumer_supply fixed_reg_en_vdd_cdc_1v2_aud_supply[] = {
481         REGULATOR_SUPPLY("vdd_cdc_1v2_aud", NULL),
482 };
483
484
485 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v2_dis_supply[] = {
486         REGULATOR_SUPPLY("vdd_cdc_1v2_dis", NULL),
487 };
488
489 static struct regulator_consumer_supply fixed_reg_en_vdd_cdc_3v3a_aud_supply[] = {
490         REGULATOR_SUPPLY("vdd_cdc_3v3a_aud", NULL),
491 };
492
493 static struct regulator_consumer_supply fixed_reg_en_vdd_usb0_5v0_supply[] = {
494         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
495         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
496         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci.1"),
497 };
498
499 static struct regulator_consumer_supply fixed_reg_en_vdd_dis_3v3a_sw_supply[] = {
500         REGULATOR_SUPPLY("vdd_dis_3v3_lcd", NULL),
501         REGULATOR_SUPPLY("vdd_dis_3v3_lvds", NULL),
502         REGULATOR_SUPPLY("avdd_usb", NULL),
503 };
504
505 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
506         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
507 };
508
509 FIXED_REG(0,    battery,        battery,
510         NULL,   0,      0,
511         -1,     false, true,    0,      3300,   0);
512
513 FIXED_REG(1,    vdd_cdc_1v2_aud,        vdd_cdc_1v2_aud,
514         palmas_rails(smps3),    0,      0,
515         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO14, false, true,    0,      1200,
516         0);
517
518 FIXED_REG(2,    vdd_lcd_1v2_dis,        vdd_lcd_1v2_dis,
519         palmas_rails(smps3),    0,      0,
520         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false, true,    0,      1200,
521         0);
522
523 FIXED_REG(3,    vdd_cdc_3v3a_aud,       vdd_cdc_3v3a_aud,
524         NULL,   0,      0,
525         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO10, false, true,    0,      3300,
526         0);
527
528 FIXED_REG(4,    vdd_usb0_5v0,   vdd_usb0_5v0,
529         NULL,   0,      0,
530         TEGRA_GPIO_PN4, true, true,     0,      5000,
531         0);
532
533 FIXED_REG(5,    vdd_dis_3v3a_sw,        vdd_dis_3v3a_sw,
534         NULL,   0,      0,
535         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO3,  true, true,     0,      3300,
536         0);
537
538 FIXED_REG(6,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
539         NULL,   0,      0,
540         TEGRA_GPIO_PH7, true,   true,   0,      5000,   5000);
541
542 /*
543  * Creating fixed regulator device tables
544  */
545 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
546
547 #define E1780_COMMON_FIXED_REG                  \
548         ADD_FIXED_REG(battery),                 \
549         ADD_FIXED_REG(vdd_cdc_1v2_aud),         \
550         ADD_FIXED_REG(vdd_lcd_1v2_dis),         \
551         ADD_FIXED_REG(vdd_cdc_3v3a_aud),        \
552         ADD_FIXED_REG(vdd_usb0_5v0),            \
553         ADD_FIXED_REG(vdd_dis_3v3a_sw),         \
554         ADD_FIXED_REG(vdd_hdmi_5v0),
555
556 /* Gpio switch regulator platform data for ardbeg E1580 */
557 static struct platform_device *pfixed_reg_devs[] = {
558         E1780_COMMON_FIXED_REG
559 };
560
561 static struct palmas_pmic_platform_data pmic_platform = {
562         .enable_ldo8_tracking = false,
563         .disabe_ldo8_tracking_suspend = false,
564 };
565
566 static struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
567         {
568                 .clk32k_id = PALMAS_CLOCK32KG,
569                 .enable = true,
570         }, {
571                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
572                 .enable = true,
573         },
574 };
575
576 static struct palmas_pinctrl_config palmas_pincfg[] = {
577         PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
578         PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
579         PALMAS_PINMUX(GPIO0, ID, DEFAULT, DEFAULT),
580         PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
581         PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
582         PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
583         PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
584         PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
585         PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
586         PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
587         PALMAS_PINMUX(GPIO8, GPIO, DEFAULT, DEFAULT),
588         PALMAS_PINMUX(GPIO9, GPIO, DEFAULT, DEFAULT),
589         PALMAS_PINMUX(GPIO10, GPIO, DEFAULT, DEFAULT),
590         PALMAS_PINMUX(GPIO11, GPIO, DEFAULT, DEFAULT),
591         PALMAS_PINMUX(GPIO12, GPIO, DEFAULT, DEFAULT),
592         PALMAS_PINMUX(GPIO13, GPIO, DEFAULT, DEFAULT),
593         PALMAS_PINMUX(GPIO14, GPIO, DEFAULT, DEFAULT),
594         PALMAS_PINMUX(GPIO15, GPIO, DEFAULT, DEFAULT),
595 };
596
597 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
598         .pincfg = palmas_pincfg,
599         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
600         .dvfs1_enable = false,
601         .dvfs2_enable = false,
602 };
603
604 static struct palmas_platform_data palmas_pdata = {
605         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
606         .irq_base = PALMAS_TEGRA_IRQ_BASE,
607         .pmic_pdata = &pmic_platform,
608         .clk32k_init_data =  palmas_clk32k_idata,
609         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
610         .irq_flags = IRQ_TYPE_LEVEL_HIGH,
611         .use_power_off = true,
612         .pinctrl_pdata = &palmas_pinctrl_pdata,
613 };
614
615 static struct i2c_board_info palma_device[] = {
616         {
617                 I2C_BOARD_INFO("tps80036", 0x58),
618                 .irq            = INT_EXTERNAL_PMU,
619                 .platform_data  = &palmas_pdata,
620         },
621 };
622
623 static struct tegra_suspend_platform_data ardbeg_suspend_data = {
624         .cpu_timer      = 500,
625         .cpu_off_timer  = 300,
626         .suspend_mode   = TEGRA_SUSPEND_LP0,
627         .core_timer     = 0x157e,
628         .core_off_timer = 2000,
629         .corereq_high   = true,
630         .sysclkreq_high = true,
631         .cpu_lp2_min_residency = 1000,
632         .min_residency_crail = 20000,
633 };
634
635 int __init ardbeg_suspend_init(void)
636 {
637         tegra_init_suspend(&ardbeg_suspend_data);
638         return 0;
639 }
640
641 int __init ardbeg_regulator_init(void)
642 {
643         int i;
644         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
645         u32 pmc_ctrl;
646
647         /* configure the power management controller to trigger PMU
648          * interrupts when high */
649         pmc_ctrl = readl(pmc + PMC_CTRL);
650         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
651
652
653         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
654                 pmic_platform.reg_data[i] = ardbeg_reg_data[i];
655                 pmic_platform.reg_init[i] = ardbeg_reg_init[i];
656         }
657
658         i2c_register_board_info(4, palma_device,
659                         ARRAY_SIZE(palma_device));
660         i2c_register_board_info(4, tps51632_cpu_boardinfo, 1);
661         i2c_register_board_info(4, tps51632_gpu_boardinfo, 1);
662         reg_init_data_ldo5.enable_tracking = true;
663         reg_init_data_ldo5.tracking_regulator = PALMAS_REG_SMPS12;
664
665         return 0;
666 }
667
668 static int __init ardbeg_fixed_regulator_init(void)
669 {
670         return platform_add_devices(pfixed_reg_devs,
671                         ARRAY_SIZE(pfixed_reg_devs));
672 }
673
674 subsys_initcall_sync(ardbeg_fixed_regulator_init);