ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-power.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-power.c
3  *
4  * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca954x.h>
22 #include <linux/i2c/pca953x.h>
23 #include <linux/platform_device.h>
24 #include <linux/resource.h>
25 #include <linux/io.h>
26 #include <mach/edp.h>
27 #include <mach/irqs.h>
28 #include <linux/edp.h>
29 #include <linux/platform_data/tegra_edp.h>
30 #include <linux/pid_thermal_gov.h>
31 #include <linux/regulator/fixed.h>
32 #include <linux/mfd/palmas.h>
33 #include <linux/mfd/as3722-plat.h>
34 #include <linux/power/power_supply_extcon.h>
35 #include <linux/regulator/tps51632-regulator.h>
36 #include <linux/regulator/machine.h>
37 #include <linux/irq.h>
38 #include <linux/gpio.h>
39 #include <linux/regulator/tegra-dfll-bypass-regulator.h>
40 #include <linux/power/bq2419x-charger.h>
41 #include <linux/power/bq2477x-charger.h>
42 #include <linux/tegra-fuse.h>
43
44 #include <asm/mach-types.h>
45 #include <mach/pinmux-t12.h>
46
47 #include "pm.h"
48 #include "dvfs.h"
49 #include "board.h"
50 #include "tegra-board-id.h"
51 #include "board-common.h"
52 #include "board-ardbeg.h"
53 #include "board-pmu-defines.h"
54 #include "devices.h"
55 #include "iomap.h"
56 #include "tegra_cl_dvfs.h"
57 #include "tegra11_soctherm.h"
58 #include "tegra3_tsensor.h"
59
60 #define E1735_EMULATE_E1767_SKU 1001
61
62 #define PMC_CTRL                0x0
63 #define PMC_CTRL_INTR_LOW       (1 << 17)
64
65 /************************ ARDBEG E1733 based regulators ***********/
66 static struct regulator_consumer_supply as3722_ldo0_supply[] = {
67         REGULATOR_SUPPLY("avdd_pll_m", NULL),
68         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
69         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
70         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
71         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
72         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
73         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
74         REGULATOR_SUPPLY("avdd_pll_x", NULL),
75         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
76 };
77
78 static struct regulator_consumer_supply as3722_ldo1_supply[] = {
79         REGULATOR_SUPPLY("vdd_cam1_1v8_cam", NULL),
80         REGULATOR_SUPPLY("vdd_cam2_1v8_cam", NULL),
81         REGULATOR_SUPPLY("vif", "2-0010"),
82         REGULATOR_SUPPLY("vif", "2-0036"),
83         REGULATOR_SUPPLY("vdd_i2c", "2-000c"),
84         REGULATOR_SUPPLY("vi2c", "2-0030"),
85         REGULATOR_SUPPLY("vif2", "2-0021"),
86         REGULATOR_SUPPLY("dovdd", "2-0010"),
87         REGULATOR_SUPPLY("vdd", "2-004a"),
88         REGULATOR_SUPPLY("vif", "2-0048"),
89 };
90
91 static struct regulator_consumer_supply as3722_ldo2_supply[] = {
92         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
93         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
94         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
95         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
96         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
97         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.0"),
98         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.1"),
99         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
100         REGULATOR_SUPPLY("avdd_hsic_com", NULL),
101         REGULATOR_SUPPLY("avdd_hsic_mdm", NULL),
102         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
103 };
104
105 static struct regulator_consumer_supply as3722_ldo3_supply[] = {
106         REGULATOR_SUPPLY("vdd_rtc", NULL),
107 };
108
109 static struct regulator_consumer_supply as3722_ldo4_supply[] = {
110         REGULATOR_SUPPLY("vdd_2v7_hv", NULL),
111         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
112         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
113         REGULATOR_SUPPLY("avdd_cam3_cam", NULL),
114         REGULATOR_SUPPLY("vana", "2-0010"),
115         REGULATOR_SUPPLY("avdd_ov5693", "2-0010"),
116 };
117
118 static struct regulator_consumer_supply as3722_ldo5_supply[] = {
119         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
120         REGULATOR_SUPPLY("vdig", "2-0010"),
121         REGULATOR_SUPPLY("vdig", "2-0036"),
122 };
123
124 static struct regulator_consumer_supply as3722_ldo6_supply[] = {
125         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
126         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
127 };
128
129 static struct regulator_consumer_supply as3722_ldo7_supply[] = {
130         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
131         REGULATOR_SUPPLY("imx135_reg2", NULL),
132         REGULATOR_SUPPLY("vdig_lv", "2-0010"),
133         REGULATOR_SUPPLY("dvdd", "2-0010"),
134 };
135
136 static struct regulator_consumer_supply as3722_ldo9_supply[] = {
137         REGULATOR_SUPPLY("avdd", "spi0.0"),
138 };
139
140 static struct regulator_consumer_supply as3722_ldo10_supply[] = {
141         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
142         REGULATOR_SUPPLY("imx135_reg1", NULL),
143         REGULATOR_SUPPLY("vdd", "2-000c"),
144         REGULATOR_SUPPLY("vin", "2-0030"),
145         REGULATOR_SUPPLY("vana", "2-0036"),
146         REGULATOR_SUPPLY("vana", "2-0021"),
147         REGULATOR_SUPPLY("vdd_af1", "2-0010"),
148         REGULATOR_SUPPLY("vin", "2-004a"),
149         REGULATOR_SUPPLY("vana", "2-0048"),
150 };
151
152 static struct regulator_consumer_supply as3722_ldo11_supply[] = {
153         REGULATOR_SUPPLY("vpp_fuse", NULL),
154 };
155
156 static struct regulator_consumer_supply as3722_sd0_supply[] = {
157         REGULATOR_SUPPLY("vdd_cpu", NULL),
158 };
159
160 static struct regulator_consumer_supply as3722_sd1_supply[] = {
161         REGULATOR_SUPPLY("vdd_core", NULL),
162 };
163
164 static struct regulator_consumer_supply as3722_sd2_supply[] = {
165         REGULATOR_SUPPLY("vddio_ddr", NULL),
166         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
167         REGULATOR_SUPPLY("vddio_ddr3", NULL),
168         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
169 };
170
171 static struct regulator_consumer_supply as3722_sd4_supply[] = {
172         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
173         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
174 #ifdef CONFIG_TEGRA_HDMI_PRIMARY
175         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.0"),
176         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.0"),
177 #endif
178         REGULATOR_SUPPLY("avdd_pex_pll", "tegra-pcie"),
179         REGULATOR_SUPPLY("avddio_pex", "tegra-pcie"),
180         REGULATOR_SUPPLY("dvddio_pex", "tegra-pcie"),
181         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
182         REGULATOR_SUPPLY("vddio_pex_sata", "tegra-sata.0"),
183 };
184
185 static struct regulator_consumer_supply as3722_sd5_supply[] = {
186         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639.0"),
187         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645.0"),
188         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639.0"),
189         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645.0"),
190         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639.0"),
191         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645.0"),
192         REGULATOR_SUPPLY("avdd_osc", NULL),
193         REGULATOR_SUPPLY("vddio_sys", NULL),
194         REGULATOR_SUPPLY("vddio_sys_2", NULL),
195         REGULATOR_SUPPLY("vddio_gmi", NULL),
196         REGULATOR_SUPPLY("pwrdet_nand", NULL),
197         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
198         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
199         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
200         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
201         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
202         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
203         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
204         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
205         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
206         REGULATOR_SUPPLY("vddio_audio", NULL),
207         REGULATOR_SUPPLY("pwrdet_audio", NULL),
208         REGULATOR_SUPPLY("vddio_uart", NULL),
209         REGULATOR_SUPPLY("pwrdet_uart", NULL),
210         REGULATOR_SUPPLY("vddio_bb", NULL),
211         REGULATOR_SUPPLY("pwrdet_bb", NULL),
212         REGULATOR_SUPPLY("vdd_1v8b", "0-0048"),
213         REGULATOR_SUPPLY("vdd_dtv", NULL),
214         REGULATOR_SUPPLY("vdd_1v8_eeprom", NULL),
215         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
216         REGULATOR_SUPPLY("vddio_cam", "vi"),
217         REGULATOR_SUPPLY("pwrdet_cam", NULL),
218         REGULATOR_SUPPLY("dvdd", "spi0.0"),
219         REGULATOR_SUPPLY("vlogic", "0-0069"),
220         REGULATOR_SUPPLY("vid", "0-000c"),
221         REGULATOR_SUPPLY("vddio", "0-0077"),
222         REGULATOR_SUPPLY("vdd_sata", "tegra-sata.0"),
223         REGULATOR_SUPPLY("avdd_sata", "tegra-sata.0"),
224         REGULATOR_SUPPLY("avdd_sata_pll", "tegra-sata.0"),
225 };
226
227 static struct regulator_consumer_supply as3722_sd6_supply[] = {
228         REGULATOR_SUPPLY("vdd_gpu", NULL),
229         REGULATOR_SUPPLY("vdd_gpu_simon", NULL),
230 };
231
232
233 AMS_PDATA_INIT(sd0, NULL, 700000, 1400000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE2);
234 AMS_PDATA_INIT(sd1, NULL, 700000, 1400000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
235 AMS_PDATA_INIT(sd2, NULL, 1350000, 1350000, 1, 1, 1, 0);
236 AMS_PDATA_INIT(sd4, NULL, 1050000, 1050000, 0, 1, 1, 0);
237 AMS_PDATA_INIT(sd5, NULL, 1800000, 1800000, 1, 1, 1, 0);
238 AMS_PDATA_INIT(sd6, NULL, 650000, 1400000, 0, 1, 0, 0);
239 AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
240 AMS_PDATA_INIT(ldo1, NULL, 1800000, 1800000, 0, 1, 1, 0);
241 AMS_PDATA_INIT(ldo2, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
242 AMS_PDATA_INIT(ldo3, NULL, 800000, 800000, 1, 1, 1, 0);
243 AMS_PDATA_INIT(ldo4, NULL, 2700000, 2700000, 0, 0, 1, 0);
244 AMS_PDATA_INIT(ldo5, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
245 AMS_PDATA_INIT(ldo6, NULL, 1800000, 3300000, 0, 0, 1, 0);
246 AMS_PDATA_INIT(ldo7, AS3722_SUPPLY(sd5), 1050000, 1050000, 0, 0, 1, 0);
247 AMS_PDATA_INIT(ldo9, NULL, 3300000, 3300000, 0, 0, 1, 0);
248 AMS_PDATA_INIT(ldo10, NULL, 2700000, 2700000, 0, 0, 1, 0);
249 AMS_PDATA_INIT(ldo11, NULL, 1800000, 1800000, 0, 0, 1, 0);
250
251 static struct as3722_pinctrl_platform_data as3722_pctrl_pdata[] = {
252         AS3722_PIN_CONTROL("gpio0", "gpio", "pull-down", NULL, NULL, "output-low"),
253         AS3722_PIN_CONTROL("gpio1", "gpio", NULL, NULL, NULL, "output-high"),
254         AS3722_PIN_CONTROL("gpio2", "gpio", NULL, NULL, NULL, "output-high"),
255         AS3722_PIN_CONTROL("gpio3", "gpio", NULL, NULL, "enabled", NULL),
256         AS3722_PIN_CONTROL("gpio4", "gpio", NULL, NULL, NULL, "output-high"),
257         AS3722_PIN_CONTROL("gpio5", "clk32k-out", NULL, NULL, NULL, NULL),
258         AS3722_PIN_CONTROL("gpio6", "gpio", NULL, NULL, "enabled", NULL),
259         AS3722_PIN_CONTROL("gpio7", "gpio", NULL, NULL, NULL, "output-low"),
260 };
261
262 static struct as3722_adc_extcon_platform_data as3722_adc_extcon_pdata = {
263         .connection_name = "as3722-extcon",
264         .enable_adc1_continuous_mode = true,
265         .enable_low_voltage_range = true,
266         .adc_channel = 12,
267         .hi_threshold =  0x100,
268         .low_threshold = 0x80,
269 };
270
271 static struct as3722_platform_data as3722_pdata = {
272         .reg_pdata[AS3722_SD0] = &as3722_sd0_reg_pdata,
273         .reg_pdata[AS3722_SD1] = &as3722_sd1_reg_pdata,
274         .reg_pdata[AS3722_SD2] = &as3722_sd2_reg_pdata,
275         .reg_pdata[AS3722_SD4] = &as3722_sd4_reg_pdata,
276         .reg_pdata[AS3722_SD5] = &as3722_sd5_reg_pdata,
277         .reg_pdata[AS3722_SD6] = &as3722_sd6_reg_pdata,
278         .reg_pdata[AS3722_LDO0] = &as3722_ldo0_reg_pdata,
279         .reg_pdata[AS3722_LDO1] = &as3722_ldo1_reg_pdata,
280         .reg_pdata[AS3722_LDO2] = &as3722_ldo2_reg_pdata,
281         .reg_pdata[AS3722_LDO3] = &as3722_ldo3_reg_pdata,
282         .reg_pdata[AS3722_LDO4] = &as3722_ldo4_reg_pdata,
283         .reg_pdata[AS3722_LDO5] = &as3722_ldo5_reg_pdata,
284         .reg_pdata[AS3722_LDO6] = &as3722_ldo6_reg_pdata,
285         .reg_pdata[AS3722_LDO7] = &as3722_ldo7_reg_pdata,
286         .reg_pdata[AS3722_LDO9] = &as3722_ldo9_reg_pdata,
287         .reg_pdata[AS3722_LDO10] = &as3722_ldo10_reg_pdata,
288         .reg_pdata[AS3722_LDO11] = &as3722_ldo11_reg_pdata,
289         .gpio_base = AS3722_GPIO_BASE,
290         .irq_base = AS3722_IRQ_BASE,
291         .use_internal_int_pullup = 0,
292         .use_internal_i2c_pullup = 0,
293         .pinctrl_pdata = as3722_pctrl_pdata,
294         .num_pinctrl = ARRAY_SIZE(as3722_pctrl_pdata),
295         .enable_clk32k_out = true,
296         .use_power_off = true,
297         .extcon_pdata = &as3722_adc_extcon_pdata,
298 };
299
300 static struct i2c_board_info __initdata as3722_regulators[] = {
301         {
302                 I2C_BOARD_INFO("as3722", 0x40),
303                 .flags = I2C_CLIENT_WAKE,
304                 .irq = INT_EXTERNAL_PMU,
305                 .platform_data = &as3722_pdata,
306         },
307 };
308
309 int __init ardbeg_as3722_regulator_init(void)
310 {
311         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
312         u32 pmc_ctrl;
313         struct board_info board_info;
314
315         /* AS3722: Normal state of INT request line is LOW.
316          * configure the power management controller to trigger PMU
317          * interrupts when HIGH.
318          */
319         pmc_ctrl = readl(pmc + PMC_CTRL);
320         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
321
322         /* Set vdd_gpu init uV to 1V */
323         as3722_sd6_reg_idata.constraints.init_uV = 900000;
324
325         as3722_sd6_reg_idata.constraints.min_uA = 3500000;
326         as3722_sd6_reg_idata.constraints.max_uA = 3500000;
327
328         as3722_sd0_reg_idata.constraints.min_uA = 3500000;
329         as3722_sd0_reg_idata.constraints.max_uA = 3500000;
330
331         as3722_sd1_reg_idata.constraints.min_uA = 2500000;
332         as3722_sd1_reg_idata.constraints.max_uA = 2500000;
333
334         as3722_ldo3_reg_pdata.enable_tracking = true;
335         as3722_ldo3_reg_pdata.disable_tracking_suspend = true;
336
337         tegra_get_board_info(&board_info);
338         if (board_info.board_id == BOARD_E1792) {
339                 /*Default DDR voltage is 1.35V but lpddr3 supports 1.2V*/
340                 as3722_sd2_reg_idata.constraints.min_uV = 1200000;
341                 as3722_sd2_reg_idata.constraints.max_uV = 1200000;
342         }
343
344         pr_info("%s: i2c_register_board_info\n", __func__);
345         i2c_register_board_info(4, as3722_regulators,
346                         ARRAY_SIZE(as3722_regulators));
347         return 0;
348 }
349
350 int __init ardbeg_ams_regulator_init(void)
351 {
352         ardbeg_as3722_regulator_init();
353         return 0;
354 }
355
356 /**************** ARDBEG-TI913 based regulator ************/
357 #define palmas_ti913_smps123_supply as3722_sd6_supply
358 #define palmas_ti913_smps45_supply as3722_sd1_supply
359 #define palmas_ti913_smps6_supply as3722_sd5_supply
360 #define palmas_ti913_smps7_supply as3722_sd2_supply
361 #define palmas_ti913_smps9_supply as3722_sd4_supply
362 #define palmas_ti913_ldo1_supply as3722_ldo0_supply
363 #define palmas_ti913_ldo2_supply as3722_ldo5_supply
364 #define palmas_ti913_ldo3_supply as3722_ldo9_supply
365 #define palmas_ti913_ldo4_supply as3722_ldo2_supply
366 #define palmas_ti913_ldo5_supply as3722_ldo4_supply
367 #define palmas_ti913_ldo6_supply as3722_ldo1_supply
368 #define palmas_ti913_ldo7_supply as3722_ldo10_supply
369 #define palmas_ti913_ldo8_supply as3722_ldo3_supply
370 #define palmas_ti913_ldo9_supply as3722_ldo6_supply
371 #define palmas_ti913_ldoln_supply as3722_ldo7_supply
372 #define palmas_ti913_ldousb_supply as3722_ldo11_supply
373
374 static struct regulator_consumer_supply palmas_ti913_regen1_supply[] = {
375         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5645.0"),
376 #ifdef CONFIG_TEGRA_HDMI_PRIMARY
377         REGULATOR_SUPPLY("vddio_hv", "tegradc.0"),
378 #endif
379         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
380         REGULATOR_SUPPLY("pwrdet_hv", NULL),
381         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
382         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
383         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
384         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
385         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
386         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
387         REGULATOR_SUPPLY("hvdd_pex", "tegra-pcie"),
388         REGULATOR_SUPPLY("hvdd_pex_pll_e", "tegra-pcie"),
389         REGULATOR_SUPPLY("vddio_pex_ctl", "tegra-pcie"),
390         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
391         REGULATOR_SUPPLY("vdd", "0-0069"),
392         REGULATOR_SUPPLY("vdd", "0-0048"),
393         REGULATOR_SUPPLY("vdd", "stm8t143.2"),
394         REGULATOR_SUPPLY("vdd", "0-000c"),
395         REGULATOR_SUPPLY("vdd", "0-0077"),
396         REGULATOR_SUPPLY("hvdd_sata", "tegra-sata.0"),
397         REGULATOR_SUPPLY("vdd", "1-004c"),
398         REGULATOR_SUPPLY("vdd", "1-004d"),
399         REGULATOR_SUPPLY("vcc", "1-0071"),
400 };
401
402 PALMAS_REGS_PDATA(ti913_smps123, 650, 1400, NULL, 0, 1, 1, NORMAL,
403         0, 0, 0, 0, 0);
404 PALMAS_REGS_PDATA(ti913_smps45, 700, 1400, NULL, 1, 1, 1, NORMAL,
405         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
406 PALMAS_REGS_PDATA(ti913_smps6, 1800, 1800, NULL, 1, 1, 1, NORMAL,
407         0, 0, 0, 0, 0);
408 PALMAS_REGS_PDATA(ti913_smps7, 900, 1350, NULL, 1, 1, 1, NORMAL,
409         0, 0, 0, 0, 0);
410 PALMAS_REGS_PDATA(ti913_smps9, 1050, 1050, NULL, 0, 0, 0, NORMAL,
411         0, 0, 0, 0, 0);
412 PALMAS_REGS_PDATA(ti913_ldo1, 1050, 1250, palmas_rails(ti913_smps7),
413                 1, 1, 1, 0, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
414 PALMAS_REGS_PDATA(ti913_ldo2, 1200, 1200, palmas_rails(ti913_smps6),
415                 0, 0, 1, 0, 0, 0, 0, 0, 0);
416 PALMAS_REGS_PDATA(ti913_ldo3, 3100, 3100, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
417 PALMAS_REGS_PDATA(ti913_ldo4, 1200, 1200, palmas_rails(ti913_smps6),
418                 0, 0, 1, 0, 0, 0, 0, 0, 0);
419 PALMAS_REGS_PDATA(ti913_ldo5, 2700, 2700, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
420 PALMAS_REGS_PDATA(ti913_ldo6, 1800, 1800, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
421 PALMAS_REGS_PDATA(ti913_ldo7, 2700, 2700, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
422 PALMAS_REGS_PDATA(ti913_ldo8, 800, 800, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
423 PALMAS_REGS_PDATA(ti913_ldo9, 1800, 3300, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
424 PALMAS_REGS_PDATA(ti913_ldoln, 1050, 1050, palmas_rails(ti913_smps6),
425                 0, 0, 1, 0, 0, 0, 0, 0, 0);
426 PALMAS_REGS_PDATA(ti913_ldousb, 1800, 1800, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
427 PALMAS_REGS_PDATA(ti913_regen1, 2800, 3300, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
428
429 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
430 static struct regulator_init_data *ardbeg_1735_reg_data[PALMAS_NUM_REGS] = {
431         NULL,
432         PALMAS_REG_PDATA(ti913_smps123),
433         NULL,
434         PALMAS_REG_PDATA(ti913_smps45),
435         NULL,
436         PALMAS_REG_PDATA(ti913_smps6),
437         PALMAS_REG_PDATA(ti913_smps7),
438         NULL,
439         PALMAS_REG_PDATA(ti913_smps9),
440         NULL,
441         NULL,
442         PALMAS_REG_PDATA(ti913_ldo1),
443         PALMAS_REG_PDATA(ti913_ldo2),
444         PALMAS_REG_PDATA(ti913_ldo3),
445         PALMAS_REG_PDATA(ti913_ldo4),
446         PALMAS_REG_PDATA(ti913_ldo5),
447         PALMAS_REG_PDATA(ti913_ldo6),
448         PALMAS_REG_PDATA(ti913_ldo7),
449         PALMAS_REG_PDATA(ti913_ldo8),
450         PALMAS_REG_PDATA(ti913_ldo9),
451         NULL,
452         NULL,
453         NULL,
454         NULL,
455         NULL,
456         PALMAS_REG_PDATA(ti913_ldoln),
457         PALMAS_REG_PDATA(ti913_ldousb),
458         PALMAS_REG_PDATA(ti913_regen1),
459         NULL,
460         NULL,
461         NULL,
462         NULL,
463 };
464
465 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
466 static struct palmas_reg_init *ardbeg_1735_reg_init[PALMAS_NUM_REGS] = {
467         NULL,
468         PALMAS_REG_INIT_DATA(ti913_smps123),
469         NULL,
470         PALMAS_REG_INIT_DATA(ti913_smps45),
471         NULL,
472         PALMAS_REG_INIT_DATA(ti913_smps6),
473         PALMAS_REG_INIT_DATA(ti913_smps7),
474         NULL,
475         PALMAS_REG_INIT_DATA(ti913_smps9),
476         NULL,
477         NULL,
478         PALMAS_REG_INIT_DATA(ti913_ldo1),
479         PALMAS_REG_INIT_DATA(ti913_ldo2),
480         PALMAS_REG_INIT_DATA(ti913_ldo3),
481         PALMAS_REG_INIT_DATA(ti913_ldo4),
482         PALMAS_REG_INIT_DATA(ti913_ldo5),
483         PALMAS_REG_INIT_DATA(ti913_ldo6),
484         PALMAS_REG_INIT_DATA(ti913_ldo7),
485         PALMAS_REG_INIT_DATA(ti913_ldo8),
486         PALMAS_REG_INIT_DATA(ti913_ldo9),
487         NULL,
488         NULL,
489         NULL,
490         NULL,
491         NULL,
492         PALMAS_REG_INIT_DATA(ti913_ldoln),
493         PALMAS_REG_INIT_DATA(ti913_ldousb),
494         PALMAS_REG_INIT_DATA(ti913_regen1),
495         NULL,
496         NULL,
497         NULL,
498         NULL,
499 };
500
501 struct palmas_clk32k_init_data palmas_ti913_clk32k_idata[] = {
502         {
503                 .clk32k_id = PALMAS_CLOCK32KG,
504                 .enable = true,
505         }, {
506                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
507                 .enable = true,
508         },
509 };
510
511 static struct palmas_extcon_platform_data palmas_extcon_pdata = {
512         .connection_name = "palmas-extcon",
513         .enable_vbus_detection = true,
514         .enable_id_pin_detection = true,
515 };
516
517 static struct palmas_pinctrl_config palmas_ti913_pincfg[] = {
518         PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
519         PALMAS_PINMUX("vac", "vac", NULL, NULL),
520         PALMAS_PINMUX("gpio0", "id", "pull-up", NULL),
521         PALMAS_PINMUX("gpio1", "vbus_det", NULL, NULL),
522         PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
523         PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
524         PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
525         PALMAS_PINMUX("gpio5", "clk32kgaudio", NULL, NULL),
526         PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
527         PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
528 };
529
530 static struct palmas_pinctrl_platform_data palmas_ti913_pinctrl_pdata = {
531         .pincfg = palmas_ti913_pincfg,
532         .num_pinctrl = ARRAY_SIZE(palmas_ti913_pincfg),
533         .dvfs1_enable = true,
534         .dvfs2_enable = false,
535 };
536
537 static struct palmas_pmic_platform_data pmic_ti913_platform = {
538 };
539
540 static struct palmas_pm_platform_data palmas_pm_pdata = {
541         .use_power_off = true,
542         .use_power_reset = true,
543 };
544
545 static struct palmas_platform_data palmas_ti913_pdata = {
546         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
547         .irq_base = PALMAS_TEGRA_IRQ_BASE,
548         .pmic_pdata = &pmic_ti913_platform,
549         .pinctrl_pdata = &palmas_ti913_pinctrl_pdata,
550         .clk32k_init_data =  palmas_ti913_clk32k_idata,
551         .clk32k_init_data_size = ARRAY_SIZE(palmas_ti913_clk32k_idata),
552         .extcon_pdata = &palmas_extcon_pdata,
553         .pm_pdata = &palmas_pm_pdata,
554 };
555
556 static struct i2c_board_info palma_ti913_device[] = {
557         {
558                 I2C_BOARD_INFO("tps65913", 0x58),
559                 .irq            = INT_EXTERNAL_PMU,
560                 .platform_data  = &palmas_ti913_pdata,
561         },
562 };
563
564 int __init ardbeg_tps65913_regulator_init(void)
565 {
566         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
567         u32 pmc_ctrl;
568         int i;
569         struct board_info board_info;
570
571         /* TPS65913: Normal state of INT request line is LOW.
572          * configure the power management controller to trigger PMU
573          * interrupts when HIGH.
574          */
575         pmc_ctrl = readl(pmc + PMC_CTRL);
576         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
577
578         /* Tracking configuration */
579         reg_init_data_ti913_ldo8.config_flags =
580                 PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE;
581
582         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
583                 pmic_ti913_platform.reg_data[i] = ardbeg_1735_reg_data[i];
584                 pmic_ti913_platform.reg_init[i] = ardbeg_1735_reg_init[i];
585         }
586
587         /* Set vdd_gpu init uV to 1V */
588         reg_idata_ti913_smps123.constraints.init_uV = 900000;
589
590         tegra_get_board_info(&board_info);
591         if (board_info.board_id == BOARD_E1792) {
592                 /*Default DDR voltage is 1.35V but lpddr3 supports 1.2V*/
593                 reg_idata_ti913_smps7.constraints.min_uV = 1200000;
594                 reg_idata_ti913_smps7.constraints.max_uV = 1200000;
595         }
596
597         i2c_register_board_info(4, palma_ti913_device,
598                         ARRAY_SIZE(palma_ti913_device));
599         return 0;
600 }
601
602 static struct pca953x_platform_data tca6408_pdata = {
603                 .gpio_base = PMU_TCA6416_GPIO_BASE,
604 };
605
606 static const struct i2c_board_info tca6408_expander[] = {
607         {
608                 I2C_BOARD_INFO("tca6408", 0x20),
609                 .platform_data = &tca6408_pdata,
610         },
611 };
612
613 struct bq2477x_platform_data ardbeg_bq2477x_pdata = {
614         .dac_ichg               = 2240,
615         .dac_v                  = 9008,
616         .dac_minsv              = 4608,
617         .dac_iin                = 4992,
618         .wdt_refresh_timeout    = 40,
619         .gpio                   = TEGRA_GPIO_PK5,
620 };
621
622 static struct i2c_board_info __initdata bq2477x_boardinfo[] = {
623         {
624                 I2C_BOARD_INFO("bq2477x", 0x6A),
625                 .platform_data  = &ardbeg_bq2477x_pdata,
626         },
627 };
628
629 static struct tegra_suspend_platform_data ardbeg_suspend_data = {
630         .cpu_timer      = 500,
631         .cpu_off_timer  = 300,
632         .suspend_mode   = TEGRA_SUSPEND_LP0,
633         .core_timer     = 0x157e,
634         .core_off_timer = 10,
635         .corereq_high   = true,
636         .sysclkreq_high = true,
637         .cpu_lp2_min_residency = 1000,
638         .min_residency_vmin_fmin = 1000,
639         .min_residency_ncpu_fast = 8000,
640         .min_residency_ncpu_slow = 5000,
641         .min_residency_mclk_stop = 5000,
642         .min_residency_crail = 20000,
643 };
644
645 static struct power_supply_extcon_plat_data extcon_pdata = {
646         .extcon_name = "tegra-udc",
647 };
648
649 static struct platform_device power_supply_extcon_device = {
650         .name   = "power-supply-extcon",
651         .id     = -1,
652         .dev    = {
653                 .platform_data = &extcon_pdata,
654         },
655 };
656
657 int __init ardbeg_suspend_init(void)
658 {
659         struct board_info pmu_board_info;
660
661         tegra_get_pmu_board_info(&pmu_board_info);
662
663         if ((pmu_board_info.board_id == BOARD_E1735) &&
664             (pmu_board_info.sku != E1735_EMULATE_E1767_SKU)) {
665                 ardbeg_suspend_data.cpu_timer = 2000;
666                 ardbeg_suspend_data.crail_up_early = true;
667         }
668
669         tegra_init_suspend(&ardbeg_suspend_data);
670         return 0;
671 }
672
673 /* Macro for defining fixed regulator sub device data */
674 #define FIXED_SUPPLY(_name) "fixed_reg_en_"#_name
675 #define FIXED_REG(_id, _var, _name, _in_supply,                 \
676         _always_on, _boot_on, _gpio_nr, _open_drain,            \
677         _active_high, _boot_state, _millivolts, _sdelay)        \
678 static struct regulator_init_data ri_data_##_var =              \
679 {                                                               \
680         .supply_regulator = _in_supply,                         \
681         .num_consumer_supplies =                                \
682         ARRAY_SIZE(fixed_reg_en_##_name##_supply),              \
683         .consumer_supplies = fixed_reg_en_##_name##_supply,     \
684         .constraints = {                                        \
685                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
686                                 REGULATOR_MODE_STANDBY),        \
687                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
688                                 REGULATOR_CHANGE_STATUS |       \
689                                 REGULATOR_CHANGE_VOLTAGE),      \
690                 .always_on = _always_on,                        \
691                 .boot_on = _boot_on,                            \
692         },                                                      \
693 };                                                              \
694 static struct fixed_voltage_config fixed_reg_en_##_var##_pdata =        \
695 {                                                               \
696         .supply_name = FIXED_SUPPLY(_name),                     \
697         .microvolts = _millivolts * 1000,                       \
698         .gpio = _gpio_nr,                                       \
699         .gpio_is_open_drain = _open_drain,                      \
700         .enable_high = _active_high,                            \
701         .enabled_at_boot = _boot_state,                         \
702         .init_data = &ri_data_##_var,                           \
703         .startup_delay = _sdelay                                \
704 };                                                              \
705 static struct platform_device fixed_reg_en_##_var##_dev = {     \
706         .name = "reg-fixed-voltage",                            \
707         .id = _id,                                              \
708         .dev = {                                                \
709                 .platform_data = &fixed_reg_en_##_var##_pdata,  \
710         },                                                      \
711 }
712
713 /* Always ON Battery regulator */
714 static struct regulator_consumer_supply fixed_reg_en_battery_ardbeg_supply[] = {
715                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
716 };
717
718 static struct regulator_consumer_supply fixed_reg_en_usb0_vbus_supply[] = {
719         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
720         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
721         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
722 };
723
724 static struct regulator_consumer_supply fixed_reg_en_usb1_vbus_supply[] = {
725         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
726         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
727 };
728
729 static struct regulator_consumer_supply fixed_reg_en_usb2_vbus_supply[] = {
730         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
731         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
732 };
733
734 static struct regulator_consumer_supply fixed_reg_en_vdd_sd_supply[] = {
735         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
736 };
737
738 static struct regulator_consumer_supply fixed_reg_en_vdd_sys_5v0_supply[] = {
739         REGULATOR_SUPPLY("vdd_spk_5v0", NULL),
740         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
741         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
742 };
743
744 static struct regulator_consumer_supply fixed_reg_en_dcdc_1v8_supply[] = {
745         REGULATOR_SUPPLY("avdd_lvds0_pll", NULL),
746         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
747 };
748
749 static struct regulator_consumer_supply fixed_reg_en_lcd_bl_en_supply[] = {
750         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
751 };
752
753 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
754 #ifdef CONFIG_TEGRA_HDMI_PRIMARY
755         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.0"),
756 #endif
757         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
758 };
759
760 #define fixed_reg_en_as3722_gpio2_supply palmas_ti913_regen1_supply
761
762 static struct regulator_consumer_supply fixed_reg_en_as3722_gpio4_supply[] = {
763         REGULATOR_SUPPLY("avdd_lcd", NULL),
764 };
765
766 static struct regulator_consumer_supply fixed_reg_en_tca6408_p2_supply[] = {
767         REGULATOR_SUPPLY("ldoen", "tegra-snd-rt5639.0"),
768 };
769
770 static struct regulator_consumer_supply fixed_reg_en_as3722_gpio1_supply[] = {
771         REGULATOR_SUPPLY("vdd_wwan_mdm", NULL),
772 };
773
774 static struct regulator_consumer_supply fixed_reg_en_tca6408_p6_supply[] = {
775         REGULATOR_SUPPLY("dvdd_lcd", NULL),
776         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
777 };
778
779 static struct regulator_consumer_supply fixed_reg_en_tca6408_p0_supply[] = {
780         REGULATOR_SUPPLY("vdd_lcd_1v2_s", NULL),
781 };
782
783 static struct regulator_consumer_supply fixed_reg_en_vdd_cpu_fixed_supply[] = {
784         REGULATOR_SUPPLY("vdd_cpu_fixed", NULL),
785 };
786
787 static struct regulator_consumer_supply fixed_reg_en_avdd_3v3_dp_supply[] = {
788         REGULATOR_SUPPLY("avdd_3v3_dp", NULL),
789 };
790
791 #define fixed_reg_en_ti913_gpio2_supply fixed_reg_en_as3722_gpio1_supply
792 #define fixed_reg_en_ti913_gpio3_supply fixed_reg_en_as3722_gpio4_supply
793 #define fixed_reg_en_ti913_gpio4_supply fixed_reg_en_tca6408_p0_supply
794 #define fixed_reg_en_ti913_gpio6_supply fixed_reg_en_tca6408_p2_supply
795 #define fixed_reg_en_ti913_gpio7_supply fixed_reg_en_tca6408_p6_supply
796
797 FIXED_REG(0,    battery_ardbeg, battery_ardbeg,
798         NULL,   0,      0,      -1,
799         false,  true,   0,      3300, 0);
800
801 FIXED_REG(1,    usb0_vbus,      usb0_vbus,
802         NULL,   0,      0,      TEGRA_GPIO_PN4,
803         true,   true,   0,      5000,   0);
804
805 FIXED_REG(2,    usb1_vbus,      usb1_vbus,
806         NULL,   0,      0,      TEGRA_GPIO_PN5,
807         true,   true,   0,      5000,   0);
808
809 FIXED_REG(3,    usb2_vbus,      usb2_vbus,
810         NULL,   0,      0,      TEGRA_GPIO_PFF1,
811         true,   true,   0,      5000,   0);
812
813 FIXED_REG(4,    vdd_sd, vdd_sd,
814         NULL,   0,      0,      TEGRA_GPIO_PR0,
815         false,  true,   0,      3300,   0);
816
817 FIXED_REG(5,    vdd_sys_5v0,    vdd_sys_5v0,
818         NULL,   0,      0,      -1,
819         false,  true,   0,      5000, 0);
820
821 FIXED_REG(6,    dcdc_1v8,       dcdc_1v8,
822         NULL,   0,      0,      -1,
823         false,  true,   0,      1800, 0);
824
825 FIXED_REG(7,    lcd_bl_en,      lcd_bl_en,
826         NULL,   0,      0, TEGRA_GPIO_PH2,
827         false,  true,   0,      5000,   0);
828
829 /* EN for LDO1/6/9/10 So keep always_ON */
830 FIXED_REG(8,    as3722_gpio2,   as3722_gpio2,
831         NULL,   1,      1, AS3722_GPIO_BASE + AS3722_GPIO2,
832         false,  true,   0,      3300, 0);
833
834 FIXED_REG(9,    as3722_gpio4,   as3722_gpio4,
835         NULL,   0,      0, AS3722_GPIO_BASE + AS3722_GPIO4,
836         false,  true,   0,      3300,   0);
837
838 FIXED_REG(10,   as3722_gpio1,   as3722_gpio1,
839         NULL,   0,      0,      AS3722_GPIO_BASE + AS3722_GPIO1,
840         false,  true,   0,      3300,   0);
841
842 FIXED_REG(11,   tca6408_p2,     tca6408_p2,
843         AS3722_SUPPLY(sd5),     0,      0,      PMU_TCA6416_GPIO(2),
844         false,  true,   0,      1200, 0);
845
846 FIXED_REG(12,   vdd_hdmi_5v0,   vdd_hdmi_5v0,
847         NULL,   0,      0,
848         TEGRA_GPIO_PK6, false,  true,   0,      5000,   5000);
849
850 FIXED_REG(13,   tca6408_p6,     tca6408_p6,
851         AS3722_SUPPLY(sd5),     0,      0,      PMU_TCA6416_GPIO(6),
852         false,  true,   0,      1800, 0);
853
854 FIXED_REG(14,   tca6408_p0,     tca6408_p0,
855         AS3722_SUPPLY(sd5),     0,      0,      PMU_TCA6416_GPIO(0),
856         false,  true,   0,      1200, 0);
857
858 FIXED_REG(15,   ti913_gpio2,    ti913_gpio2,
859         NULL,   1,      1,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,
860         false,  true,   0,      3300, 0);
861
862 FIXED_REG(16,   ti913_gpio3,    ti913_gpio3,
863         NULL,   0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO3,
864         false,  true,   0,      3300,   0);
865
866 FIXED_REG(17,   ti913_gpio4,    ti913_gpio4,
867         NULL,   0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,
868         false,  true,   0,      1200,   0);
869
870 FIXED_REG(18,   ti913_gpio6,    ti913_gpio6,
871         NULL,   0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,
872         false,  true,   0,      1200,   0);
873
874 FIXED_REG(19,   ti913_gpio7,    ti913_gpio7,
875         NULL,   0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO7,
876         false,  true,   0,      1800,   0);
877
878 FIXED_REG(20,   vdd_cpu_fixed,  vdd_cpu_fixed,
879         NULL,   0,      1,      -1,
880         false,  true,   0,      1000,   0);
881
882 FIXED_REG(21,   avdd_3v3_dp,    avdd_3v3_dp,
883         NULL,   0,      0,      TEGRA_GPIO_PH3,
884         false,  true,   0,      3300,   0);
885
886 /*
887  * Creating fixed regulator device tables
888  */
889 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
890 #define ARDBEG_COMMON_FIXED_REG \
891         ADD_FIXED_REG(battery_ardbeg),          \
892         ADD_FIXED_REG(vdd_hdmi_5v0),            \
893         ADD_FIXED_REG(usb0_vbus),               \
894         ADD_FIXED_REG(usb1_vbus),               \
895         ADD_FIXED_REG(usb2_vbus),               \
896         ADD_FIXED_REG(lcd_bl_en),               \
897         ADD_FIXED_REG(dcdc_1v8),                \
898         ADD_FIXED_REG(vdd_sys_5v0),             \
899         ADD_FIXED_REG(vdd_sd),
900
901 #define ARDBEG_E1733_FIXED_REG                  \
902         ADD_FIXED_REG(as3722_gpio2),            \
903         ADD_FIXED_REG(as3722_gpio4),            \
904         ADD_FIXED_REG(as3722_gpio1),            \
905         ADD_FIXED_REG(tca6408_p2),              \
906         ADD_FIXED_REG(tca6408_p6),              \
907         ADD_FIXED_REG(tca6408_p0),
908
909 #define ARDBEG_E1735_FIXED_REG                  \
910         ADD_FIXED_REG(ti913_gpio2),             \
911         ADD_FIXED_REG(ti913_gpio3),             \
912         ADD_FIXED_REG(ti913_gpio4),             \
913         ADD_FIXED_REG(ti913_gpio6),             \
914         ADD_FIXED_REG(ti913_gpio7),             \
915         ADD_FIXED_REG(vdd_cpu_fixed),
916
917 #define ARDBEG_E1824_FIXED_REG                  \
918         ADD_FIXED_REG(avdd_3v3_dp),
919
920 static struct platform_device *fixed_reg_devs_e1733[] = {
921         ARDBEG_COMMON_FIXED_REG
922         ARDBEG_E1733_FIXED_REG
923 };
924
925 static struct platform_device *fixed_reg_devs_e1735[] = {
926         ARDBEG_COMMON_FIXED_REG
927         ARDBEG_E1735_FIXED_REG
928 };
929
930 static struct platform_device *fixed_reg_devs_e1824[] = {
931         ARDBEG_E1824_FIXED_REG
932 };
933
934 /************************ ARDBEG CL-DVFS DATA *********************/
935 #define E1735_CPU_VDD_MAP_SIZE          33
936 #define E1735_CPU_VDD_MIN_UV            675000
937 #define E1735_CPU_VDD_STEP_UV           18750
938 #define E1735_CPU_VDD_STEP_US           80
939 #define E1735_CPU_VDD_IDLE_MA           5000
940 #define ARDBEG_DEFAULT_CVB_ALIGNMENT    10000
941
942 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
943 /* E1735 board parameters for cpu dfll */
944 static struct tegra_cl_dvfs_cfg_param e1735_cl_dvfs_param = {
945         .sample_rate = 50000,
946
947         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
948         .cf = 10,
949         .ci = 0,
950         .cg = 2,
951
952         .droop_cut_value = 0xF,
953         .droop_restore_ramp = 0x0,
954         .scale_out_ramp = 0x0,
955 };
956
957 /* E1735 RT8812C volatge map */
958 static struct voltage_reg_map e1735_cpu_vdd_map[E1735_CPU_VDD_MAP_SIZE];
959 static inline int e1735_fill_reg_map(int nominal_mv)
960 {
961         int i, uv, nominal_uv = 0;
962         for (i = 0; i < E1735_CPU_VDD_MAP_SIZE; i++) {
963                 e1735_cpu_vdd_map[i].reg_value = i;
964                 e1735_cpu_vdd_map[i].reg_uV = uv =
965                         E1735_CPU_VDD_MIN_UV + E1735_CPU_VDD_STEP_UV * i;
966                 if (!nominal_uv && uv >= nominal_mv * 1000)
967                         nominal_uv = uv;
968         }
969         return nominal_uv;
970 }
971
972 /* E1735 dfll bypass device for legacy dvfs control */
973 static struct regulator_consumer_supply e1735_dfll_bypass_consumers[] = {
974         REGULATOR_SUPPLY("vdd_cpu", NULL),
975 };
976 DFLL_BYPASS(e1735, E1735_CPU_VDD_MIN_UV, E1735_CPU_VDD_STEP_UV,
977             E1735_CPU_VDD_MAP_SIZE, E1735_CPU_VDD_STEP_US, TEGRA_GPIO_PX2);
978
979 static struct tegra_cl_dvfs_platform_data e1735_cl_dvfs_data = {
980         .dfll_clk_name = "dfll_cpu",
981         .pmu_if = TEGRA_CL_DVFS_PMU_PWM,
982         .u.pmu_pwm = {
983                 .pwm_rate = 12750000,
984                 .pwm_pingroup = TEGRA_PINGROUP_DVFS_PWM,
985                 .out_gpio = TEGRA_GPIO_PS5,
986                 .out_enable_high = false,
987 #ifdef CONFIG_REGULATOR_TEGRA_DFLL_BYPASS
988                 .dfll_bypass_dev = &e1735_dfll_bypass_dev,
989 #endif
990         },
991         .vdd_map = e1735_cpu_vdd_map,
992         .vdd_map_size = E1735_CPU_VDD_MAP_SIZE,
993
994         .cfg_param = &e1735_cl_dvfs_param,
995 };
996
997 static void e1735_suspend_dfll_bypass(void)
998 {
999         __gpio_set_value(TEGRA_GPIO_PS5, 1); /* tristate external PWM buffer */
1000 }
1001
1002 static void e1735_resume_dfll_bypass(void)
1003 {
1004         __gpio_set_value(TEGRA_GPIO_PS5, 0); /* enable PWM buffer operations */
1005 }
1006
1007 static void e1767_suspend_dfll_bypass(void)
1008 {
1009         tegra_pinmux_set_tristate(TEGRA_PINGROUP_DVFS_PWM, TEGRA_TRI_TRISTATE);
1010 }
1011
1012 static void e1767_resume_dfll_bypass(void)
1013 {
1014          tegra_pinmux_set_tristate(TEGRA_PINGROUP_DVFS_PWM, TEGRA_TRI_NORMAL);
1015 }
1016
1017 static struct tegra_cl_dvfs_cfg_param e1733_ardbeg_cl_dvfs_param = {
1018         .sample_rate = 12500,
1019
1020         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
1021         .cf = 10,
1022         .ci = 0,
1023         .cg = 2,
1024
1025         .droop_cut_value = 0xF,
1026         .droop_restore_ramp = 0x0,
1027         .scale_out_ramp = 0x0,
1028 };
1029
1030 /* E1733 volatge map. Fixed 10mv steps from 700mv to 1400mv */
1031 #define E1733_CPU_VDD_MAP_SIZE ((1400000 - 700000) / 10000 + 1)
1032 static struct voltage_reg_map e1733_cpu_vdd_map[E1733_CPU_VDD_MAP_SIZE];
1033 static inline void e1733_fill_reg_map(void)
1034 {
1035         int i;
1036         for (i = 0; i < E1733_CPU_VDD_MAP_SIZE; i++) {
1037                 e1733_cpu_vdd_map[i].reg_value = i + 0xa;
1038                 e1733_cpu_vdd_map[i].reg_uV = 700000 + 10000 * i;
1039         }
1040 }
1041
1042 static struct tegra_cl_dvfs_platform_data e1733_cl_dvfs_data = {
1043         .dfll_clk_name = "dfll_cpu",
1044         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
1045         .u.pmu_i2c = {
1046                 .fs_rate = 400000,
1047                 .slave_addr = 0x80,
1048                 .reg = 0x00,
1049         },
1050         .vdd_map = e1733_cpu_vdd_map,
1051         .vdd_map_size = E1733_CPU_VDD_MAP_SIZE,
1052
1053         .cfg_param = &e1733_ardbeg_cl_dvfs_param,
1054 };
1055
1056 static struct tegra_cl_dvfs_cfg_param e1736_ardbeg_cl_dvfs_param = {
1057         .sample_rate = 12500, /* i2c freq */
1058
1059         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
1060         .cf = 10,
1061         .ci = 0,
1062         .cg = 2,
1063
1064         .droop_cut_value = 0xF,
1065         .droop_restore_ramp = 0x0,
1066         .scale_out_ramp = 0x0,
1067 };
1068
1069 /* E1736 volatge map. Fixed 10mv steps from 700mv to 1400mv */
1070 #define E1736_CPU_VDD_MAP_SIZE ((1400000 - 700000) / 10000 + 1)
1071 static struct voltage_reg_map e1736_cpu_vdd_map[E1736_CPU_VDD_MAP_SIZE];
1072 static inline void e1736_fill_reg_map(void)
1073 {
1074         int i;
1075         for (i = 0; i < E1736_CPU_VDD_MAP_SIZE; i++) {
1076                 /* 0.7V corresponds to 0b0011010 = 26 */
1077                 /* 1.4V corresponds to 0b1100000 = 96 */
1078                 e1736_cpu_vdd_map[i].reg_value = i + 26;
1079                 e1736_cpu_vdd_map[i].reg_uV = 700000 + 10000 * i;
1080         }
1081 }
1082
1083 static struct tegra_cl_dvfs_platform_data e1736_cl_dvfs_data = {
1084         .dfll_clk_name = "dfll_cpu",
1085         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
1086         .u.pmu_i2c = {
1087                 .fs_rate = 400000,
1088                 .slave_addr = 0xb0, /* pmu i2c address */
1089                 .reg = 0x23,        /* vdd_cpu rail reg address */
1090         },
1091         .vdd_map = e1736_cpu_vdd_map,
1092         .vdd_map_size = E1736_CPU_VDD_MAP_SIZE,
1093         .pmu_undershoot_gb = 100,
1094
1095         .cfg_param = &e1736_ardbeg_cl_dvfs_param,
1096 };
1097 static int __init ardbeg_cl_dvfs_init(struct board_info *pmu_board_info)
1098 {
1099         u16 pmu_board_id = pmu_board_info->board_id;
1100         struct tegra_cl_dvfs_platform_data *data = NULL;
1101         int v = tegra_dvfs_rail_get_nominal_millivolts(tegra_cpu_rail);
1102
1103         if (pmu_board_id == BOARD_E1735) {
1104                 bool e1767 = pmu_board_info->sku == E1735_EMULATE_E1767_SKU;
1105                 v = e1735_fill_reg_map(v);
1106                 data = &e1735_cl_dvfs_data;
1107
1108                 data->u.pmu_pwm.pwm_bus = e1767 ?
1109                         TEGRA_CL_DVFS_PWM_1WIRE_DIRECT :
1110                         TEGRA_CL_DVFS_PWM_1WIRE_BUFFER;
1111
1112                 if (data->u.pmu_pwm.dfll_bypass_dev) {
1113                         /* this has to be exact to 1uV level from table */
1114                         e1735_dfll_bypass_init_data.constraints.init_uV = v;
1115                         ardbeg_suspend_data.suspend_dfll_bypass = e1767 ?
1116                                 e1767_suspend_dfll_bypass :
1117                                 e1735_suspend_dfll_bypass;
1118                         ardbeg_suspend_data.resume_dfll_bypass = e1767 ?
1119                                 e1767_resume_dfll_bypass :
1120                                 e1735_resume_dfll_bypass;
1121                         tegra_init_cpu_reg_mode_limits(E1735_CPU_VDD_IDLE_MA,
1122                                                        REGULATOR_MODE_IDLE);
1123                 } else {
1124                         (void)e1735_dfll_bypass_dev;
1125                 }
1126         }
1127
1128
1129         if (pmu_board_id == BOARD_E1733) {
1130                 e1733_fill_reg_map();
1131                 data = &e1733_cl_dvfs_data;
1132         }
1133
1134         if (pmu_board_id == BOARD_E1736 ||
1135                 pmu_board_id == BOARD_E1936 ||
1136                 pmu_board_id == BOARD_E1769 ||
1137                 pmu_board_id == BOARD_P1761) {
1138                 e1736_fill_reg_map();
1139                 data = &e1736_cl_dvfs_data;
1140         }
1141
1142         if (data) {
1143                 data->flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
1144                 tegra_cl_dvfs_device.dev.platform_data = data;
1145                 platform_device_register(&tegra_cl_dvfs_device);
1146         }
1147         return 0;
1148 }
1149 #else
1150 static inline int ardbeg_cl_dvfs_init(struct board_info *pmu_board_info)
1151 { return 0; }
1152 #endif
1153
1154 int __init ardbeg_rail_alignment_init(void)
1155 {
1156         struct board_info pmu_board_info;
1157
1158         tegra_get_pmu_board_info(&pmu_board_info);
1159
1160         if (pmu_board_info.board_id == BOARD_E1735)
1161                 tegra12x_vdd_cpu_align(E1735_CPU_VDD_STEP_UV,
1162                                        E1735_CPU_VDD_MIN_UV);
1163         else
1164                 tegra12x_vdd_cpu_align(ARDBEG_DEFAULT_CVB_ALIGNMENT, 0);
1165         return 0;
1166 }
1167
1168 int __init ardbeg_regulator_init(void)
1169 {
1170         struct board_info pmu_board_info;
1171
1172         tegra_get_pmu_board_info(&pmu_board_info);
1173
1174         if ((pmu_board_info.board_id == BOARD_E1733) ||
1175                 (pmu_board_info.board_id == BOARD_E1734)) {
1176                 i2c_register_board_info(0, tca6408_expander,
1177                                 ARRAY_SIZE(tca6408_expander));
1178                 ardbeg_ams_regulator_init();
1179                 regulator_has_full_constraints();
1180         } else if (pmu_board_info.board_id == BOARD_E1735) {
1181                 regulator_has_full_constraints();
1182                 ardbeg_tps65913_regulator_init();
1183         } else if (pmu_board_info.board_id == BOARD_E1736 ||
1184                 pmu_board_info.board_id == BOARD_E1936 ||
1185                 pmu_board_info.board_id == BOARD_E1769 ||
1186                 pmu_board_info.board_id == BOARD_P1761) {
1187                 tn8_regulator_init();
1188                 ardbeg_cl_dvfs_init(&pmu_board_info);
1189                 return tn8_fixed_regulator_init();
1190         } else {
1191                 pr_warn("PMU board id 0x%04x is not supported\n",
1192                         pmu_board_info.board_id);
1193         }
1194
1195         if (get_power_supply_type() == POWER_SUPPLY_TYPE_BATTERY) {
1196                 i2c_register_board_info(1, bq2477x_boardinfo,
1197                         ARRAY_SIZE(bq2477x_boardinfo));
1198         }
1199
1200         platform_device_register(&power_supply_extcon_device);
1201
1202         ardbeg_cl_dvfs_init(&pmu_board_info);
1203         return 0;
1204 }
1205
1206 static int __init ardbeg_fixed_regulator_init(void)
1207 {
1208         struct board_info pmu_board_info;
1209         struct board_info display_board_info;
1210
1211         if ((!of_machine_is_compatible("nvidia,ardbeg")) &&
1212             (!of_machine_is_compatible("nvidia,ardbeg_sata")))
1213                 return 0;
1214
1215         tegra_get_display_board_info(&display_board_info);
1216
1217         if (display_board_info.board_id == BOARD_E1824)
1218                 platform_add_devices(fixed_reg_devs_e1824,
1219                         ARRAY_SIZE(fixed_reg_devs_e1824));
1220
1221         tegra_get_pmu_board_info(&pmu_board_info);
1222
1223         if (pmu_board_info.board_id == BOARD_E1733)
1224                 return platform_add_devices(fixed_reg_devs_e1733,
1225                         ARRAY_SIZE(fixed_reg_devs_e1733));
1226         else if (pmu_board_info.board_id == BOARD_E1735)
1227                 return platform_add_devices(fixed_reg_devs_e1735,
1228                         ARRAY_SIZE(fixed_reg_devs_e1735));
1229         else if (pmu_board_info.board_id == BOARD_E1736 ||
1230                  pmu_board_info.board_id == BOARD_P1761 ||
1231                  pmu_board_info.board_id == BOARD_E1936)
1232                 return 0;
1233         else
1234                 pr_warn("The PMU board id 0x%04x is not supported\n",
1235                         pmu_board_info.board_id);
1236
1237         return 0;
1238 }
1239
1240 subsys_initcall_sync(ardbeg_fixed_regulator_init);
1241
1242 int __init ardbeg_edp_init(void)
1243 {
1244         unsigned int regulator_mA;
1245
1246         regulator_mA = get_maximum_cpu_current_supported();
1247         if (!regulator_mA)
1248                 regulator_mA = 14000;
1249
1250         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1251         tegra_init_cpu_edp_limits(regulator_mA);
1252
1253         /* gpu maximum current */
1254         regulator_mA = 12000;
1255         pr_info("%s: GPU regulator %d mA\n", __func__, regulator_mA);
1256
1257         tegra_init_gpu_edp_limits(regulator_mA);
1258         return 0;
1259 }
1260
1261
1262 static struct pid_thermal_gov_params soctherm_pid_params = {
1263         .max_err_temp = 9000,
1264         .max_err_gain = 1000,
1265
1266         .gain_p = 1000,
1267         .gain_d = 0,
1268
1269         .up_compensation = 20,
1270         .down_compensation = 20,
1271 };
1272
1273 static struct thermal_zone_params soctherm_tzp = {
1274         .governor_name = "pid_thermal_gov",
1275         .governor_params = &soctherm_pid_params,
1276 };
1277
1278 static struct tegra_tsensor_pmu_data tpdata_palmas = {
1279         .reset_tegra = 1,
1280         .pmu_16bit_ops = 0,
1281         .controller_type = 0,
1282         .pmu_i2c_addr = 0x58,
1283         .i2c_controller_id = 4,
1284         .poweroff_reg_addr = 0xa0,
1285         .poweroff_reg_data = 0x0,
1286 };
1287
1288 static struct tegra_tsensor_pmu_data tpdata_as3722 = {
1289         .reset_tegra = 1,
1290         .pmu_16bit_ops = 0,
1291         .controller_type = 0,
1292         .pmu_i2c_addr = 0x40,
1293         .i2c_controller_id = 4,
1294         .poweroff_reg_addr = 0x36,
1295         .poweroff_reg_data = 0x2,
1296 };
1297
1298 static struct soctherm_platform_data ardbeg_soctherm_data = {
1299         .oc_irq_base = TEGRA_SOC_OC_IRQ_BASE,
1300         .num_oc_irqs = TEGRA_SOC_OC_NUM_IRQ,
1301         .therm = {
1302                 [THERM_CPU] = {
1303                         .zone_enable = true,
1304                         .passive_delay = 1000,
1305                         .hotspot_offset = 6000,
1306                         .num_trips = 3,
1307                         .trips = {
1308                                 {
1309                                         .cdev_type = "tegra-shutdown",
1310                                         .trip_temp = 101000,
1311                                         .trip_type = THERMAL_TRIP_CRITICAL,
1312                                         .upper = THERMAL_NO_LIMIT,
1313                                         .lower = THERMAL_NO_LIMIT,
1314                                 },
1315                                 {
1316                                         .cdev_type = "tegra-heavy",
1317                                         .trip_temp = 99000,
1318                                         .trip_type = THERMAL_TRIP_HOT,
1319                                         .upper = THERMAL_NO_LIMIT,
1320                                         .lower = THERMAL_NO_LIMIT,
1321                                 },
1322                                 {
1323                                         .cdev_type = "cpu-balanced",
1324                                         .trip_temp = 90000,
1325                                         .trip_type = THERMAL_TRIP_PASSIVE,
1326                                         .upper = THERMAL_NO_LIMIT,
1327                                         .lower = THERMAL_NO_LIMIT,
1328                                 },
1329                         },
1330                         .tzp = &soctherm_tzp,
1331                 },
1332                 [THERM_GPU] = {
1333                         .zone_enable = true,
1334                         .passive_delay = 1000,
1335                         .hotspot_offset = 6000,
1336                         .num_trips = 3,
1337                         .trips = {
1338                                 {
1339                                         .cdev_type = "tegra-shutdown",
1340                                         .trip_temp = 101000,
1341                                         .trip_type = THERMAL_TRIP_CRITICAL,
1342                                         .upper = THERMAL_NO_LIMIT,
1343                                         .lower = THERMAL_NO_LIMIT,
1344                                 },
1345                                 {
1346                                         .cdev_type = "tegra-heavy",
1347                                         .trip_temp = 99000,
1348                                         .trip_type = THERMAL_TRIP_HOT,
1349                                         .upper = THERMAL_NO_LIMIT,
1350                                         .lower = THERMAL_NO_LIMIT,
1351                                 },
1352                                 {
1353                                         .cdev_type = "gpu-balanced",
1354                                         .trip_temp = 90000,
1355                                         .trip_type = THERMAL_TRIP_PASSIVE,
1356                                         .upper = THERMAL_NO_LIMIT,
1357                                         .lower = THERMAL_NO_LIMIT,
1358                                 },
1359                         },
1360                         .tzp = &soctherm_tzp,
1361                 },
1362                 [THERM_MEM] = {
1363                         .zone_enable = true,
1364                         .num_trips = 1,
1365                         .trips = {
1366                                 {
1367                                         .cdev_type = "tegra-shutdown",
1368                                         .trip_temp = 101000, /* = GPU shut */
1369                                         .trip_type = THERMAL_TRIP_CRITICAL,
1370                                         .upper = THERMAL_NO_LIMIT,
1371                                         .lower = THERMAL_NO_LIMIT,
1372                                 },
1373                         },
1374                         .tzp = &soctherm_tzp,
1375                 },
1376                 [THERM_PLL] = {
1377                         .zone_enable = true,
1378                         .tzp = &soctherm_tzp,
1379                 },
1380         },
1381         .throttle = {
1382                 [THROTTLE_HEAVY] = {
1383                         .priority = 100,
1384                         .devs = {
1385                                 [THROTTLE_DEV_CPU] = {
1386                                         .enable = true,
1387                                         .depth = 80,
1388                                 },
1389                                 [THROTTLE_DEV_GPU] = {
1390                                         .enable = true,
1391                                         .throttling_depth = "heavy_throttling",
1392                                 },
1393                         },
1394                 },
1395         },
1396         .tshut_pmu_trip_data = &tpdata_palmas,
1397 };
1398
1399 struct soctherm_throttle battery_oc_throttle = {
1400         .throt_mode = BRIEF,
1401         .polarity = 1,
1402         .priority = 100,
1403         .devs = {
1404                 [THROTTLE_DEV_CPU] = {
1405                         .enable = true,
1406                         .depth = 50,
1407                 },
1408                 [THROTTLE_DEV_GPU] = {
1409                         .enable = true,
1410                         .throttling_depth = "medium_throttling",
1411                 },
1412         },
1413 };
1414
1415 struct soctherm_throttle voltmon_throttle = {
1416         .throt_mode = BRIEF,
1417         .polarity = 1,
1418         .priority = 50,
1419         .devs = {
1420                 [THROTTLE_DEV_CPU] = {
1421                         .enable = true,
1422                         .depth = 75,
1423                 },
1424                 [THROTTLE_DEV_GPU] = {
1425                         .enable = true,
1426                         .throttling_depth = "medium_throttling",
1427                 },
1428         },
1429 };
1430
1431 int __init ardbeg_soctherm_init(void)
1432 {
1433         s32 base_cp, shft_cp;
1434         u32 base_ft, shft_ft;
1435         struct board_info pmu_board_info;
1436
1437         /* do this only for supported CP,FT fuses */
1438         if ((tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) >= 0) &&
1439             (tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) >= 0)) {
1440                 tegra_platform_edp_init(
1441                         ardbeg_soctherm_data.therm[THERM_CPU].trips,
1442                         &ardbeg_soctherm_data.therm[THERM_CPU].num_trips,
1443                         7000); /* edp temperature margin */
1444                 tegra_platform_gpu_edp_init(
1445                         ardbeg_soctherm_data.therm[THERM_GPU].trips,
1446                         &ardbeg_soctherm_data.therm[THERM_GPU].num_trips,
1447                         7000);
1448                 tegra_add_cpu_vmax_trips(
1449                         ardbeg_soctherm_data.therm[THERM_CPU].trips,
1450                         &ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
1451                 tegra_add_tgpu_trips(
1452                         ardbeg_soctherm_data.therm[THERM_GPU].trips,
1453                         &ardbeg_soctherm_data.therm[THERM_GPU].num_trips);
1454                 tegra_add_vc_trips(
1455                         ardbeg_soctherm_data.therm[THERM_CPU].trips,
1456                         &ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
1457                 tegra_add_core_vmax_trips(
1458                         ardbeg_soctherm_data.therm[THERM_PLL].trips,
1459                         &ardbeg_soctherm_data.therm[THERM_PLL].num_trips);
1460         }
1461
1462         tegra_get_pmu_board_info(&pmu_board_info);
1463
1464         if ((pmu_board_info.board_id == BOARD_E1733) ||
1465                 (pmu_board_info.board_id == BOARD_E1734))
1466                 ardbeg_soctherm_data.tshut_pmu_trip_data = &tpdata_as3722;
1467         else if (pmu_board_info.board_id == BOARD_E1735 ||
1468                  pmu_board_info.board_id == BOARD_E1736 ||
1469                  pmu_board_info.board_id == BOARD_E1769 ||
1470                  pmu_board_info.board_id == BOARD_E1936)
1471                 ;/* tpdata_palmas is default */
1472         else
1473                 pr_warn("soctherm THERMTRIP is not supported on this PMIC\n");
1474
1475         /* Enable soc_therm OC throttling on selected platforms */
1476         switch (pmu_board_info.board_id) {
1477         case BOARD_P1761:
1478                 memcpy(&ardbeg_soctherm_data.throttle[THROTTLE_OC4],
1479                        &battery_oc_throttle,
1480                        sizeof(battery_oc_throttle));
1481                 memcpy(&ardbeg_soctherm_data.throttle[THROTTLE_OC1],
1482                        &voltmon_throttle,
1483                        sizeof(voltmon_throttle));
1484
1485                 break;
1486         default:
1487                 break;
1488         }
1489
1490         return tegra11_soctherm_init(&ardbeg_soctherm_data);
1491 }