ARM: tegra: add machine check for fix reg init
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-power.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-power.c
3  *
4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/resource.h>
23 #include <linux/io.h>
24 #include <mach/irqs.h>
25 #include <mach/hardware.h>
26 #include <linux/regulator/fixed.h>
27 #include <linux/mfd/palmas.h>
28 #include <linux/regulator/tps51632-regulator.h>
29 #include <linux/regulator/machine.h>
30 #include <linux/irq.h>
31
32 #include <asm/mach-types.h>
33
34 #include "pm.h"
35 #include "board.h"
36 #include "tegra-board-id.h"
37 #include "board-common.h"
38 #include "board-ardbeg.h"
39 #include "board-pmu-defines.h"
40 #include "devices.h"
41 #include "iomap.h"
42
43 #define PMC_CTRL                0x0
44 #define PMC_CTRL_INTR_LOW       (1 << 17)
45
46
47 /************************ ARDBEG based regulator *****************/
48 static struct regulator_consumer_supply palmas_smps12_supply[] = {
49         REGULATOR_SUPPLY("vdd_core", NULL),
50 };
51
52 static struct regulator_consumer_supply palmas_smps3_supply[] = {
53         REGULATOR_SUPPLY("vdd_modem", NULL),
54 };
55
56 static struct regulator_consumer_supply palmas_smps6_supply[] = {
57         REGULATOR_SUPPLY("vddio_ddr", NULL),
58         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
59         REGULATOR_SUPPLY("vddio_ddr3", NULL),
60         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
61 };
62
63 static struct regulator_consumer_supply palmas_smps8_supply[] = {
64         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
65         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
66         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
67         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
68         REGULATOR_SUPPLY("avdd_pll_m", NULL),
69         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
70         REGULATOR_SUPPLY("avdd_pll_utmip", NULL),
71         REGULATOR_SUPPLY("avdd_pll_x", NULL),
72         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
73         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
74 };
75
76 static struct regulator_consumer_supply palmas_smps9_supply[] = {
77         REGULATOR_SUPPLY("vdd_aud_dgtl", NULL),
78         REGULATOR_SUPPLY("vdd_aud_anlg", NULL),
79         REGULATOR_SUPPLY("vdd_aud_mic", NULL),
80         REGULATOR_SUPPLY("avdd_osc", NULL),
81         REGULATOR_SUPPLY("vddio_sys", NULL),
82         REGULATOR_SUPPLY("vddio_sys_2", NULL),
83         REGULATOR_SUPPLY("vddio_gmi", NULL),
84         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
85         REGULATOR_SUPPLY("vdd_1v8b_pll_utmip", NULL),
86         REGULATOR_SUPPLY("vddio_cam", "vi"),
87         REGULATOR_SUPPLY("vddio_audio", NULL),
88         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
89         REGULATOR_SUPPLY("vddio_uart", NULL),
90         REGULATOR_SUPPLY("vddio_bb", NULL),
91         REGULATOR_SUPPLY("vdd_sys_mb", NULL),
92         REGULATOR_SUPPLY("vdd_gmi_mb", NULL),
93         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
94         REGULATOR_SUPPLY("vdd_1v8b_ts", NULL),
95         REGULATOR_SUPPLY("vdd_1v8b_audio_mb", NULL),
96         REGULATOR_SUPPLY("vdd_1v8b_com_f", NULL),
97         REGULATOR_SUPPLY("vdd_1v8b_gps_f", NULL),
98         REGULATOR_SUPPLY("vdd_1v8b_nfc", NULL),
99         REGULATOR_SUPPLY("vdd_1v8b_uart_mb", NULL),
100         REGULATOR_SUPPLY("vdd_1v8b", "0-0048"),
101         REGULATOR_SUPPLY("vdd_dtv", NULL),
102         REGULATOR_SUPPLY("vdd_1v8_bb_mb", NULL),
103         REGULATOR_SUPPLY("vdd_1v8_uart_mdm", NULL),
104         REGULATOR_SUPPLY("vdd_1v8_eeprom", NULL),
105         REGULATOR_SUPPLY("vdd_1v8_dbg", NULL),
106         REGULATOR_SUPPLY("vdd_1v8_pm", NULL),
107 };
108
109
110 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
111         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
112 };
113
114 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
115         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
116         REGULATOR_SUPPLY("avdd_hdmi", NULL),
117         REGULATOR_SUPPLY("avdd_pex_pll", NULL),
118         REGULATOR_SUPPLY("avddio_pex_pll", NULL),
119         REGULATOR_SUPPLY("dvddio_pex", NULL),
120 };
121
122 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
123         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
124         REGULATOR_SUPPLY("vdd_cam_1v8_cam", NULL),
125         REGULATOR_SUPPLY("vif", "2-0010"),
126         REGULATOR_SUPPLY("vdd_i2c", "2-000e"),
127 };
128
129 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
130         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
131         REGULATOR_SUPPLY("vdig", "2-0010"),
132 };
133
134 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
135         REGULATOR_SUPPLY("vdd_rtc", NULL),
136 };
137
138 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
139         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
140         REGULATOR_SUPPLY("vana", "2-0010"),
141 };
142
143 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
144         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
145 };
146
147 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
148         REGULATOR_SUPPLY("vdd_snsr_mb", NULL),
149         REGULATOR_SUPPLY("vdd_snsr_temp", NULL),
150         REGULATOR_SUPPLY("vdd", "0-0048"),
151         REGULATOR_SUPPLY("vdd_snsr_pm", NULL),
152         REGULATOR_SUPPLY("vdd_pca", "1-0071"),
153 };
154
155 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
156         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
157         REGULATOR_SUPPLY("avdd_1v2_hsic_mdm", NULL),
158         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
159         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
160         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
161         REGULATOR_SUPPLY("avdd_1v2_hsic_com", NULL),
162         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
163 };
164
165 static struct regulator_consumer_supply palmas_ldo10_supply[] = {
166         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
167 };
168
169 static struct regulator_consumer_supply palmas_ldo11_supply[] = {
170         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
171         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
172         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
173         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
174         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
175         REGULATOR_SUPPLY("avdd_3v3_pex", NULL),
176         REGULATOR_SUPPLY("avdd_3v3_pex_pll", NULL),
177 };
178
179 static struct regulator_consumer_supply palmas_ldo12_supply[] = {
180         REGULATOR_SUPPLY("vdd_lcd_1v8b_dis", NULL),
181         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
182         REGULATOR_SUPPLY("dvdd_lcd", NULL),
183 };
184
185 static struct regulator_consumer_supply palmas_ldo13_supply[] = {
186         REGULATOR_SUPPLY("dvdd", "spi0.0"),
187 };
188
189 static struct regulator_consumer_supply palmas_ldo14_supply[] = {
190         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
191         REGULATOR_SUPPLY("imx135_reg1", NULL),
192         REGULATOR_SUPPLY("vdd", "2-000e"),
193 };
194
195 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
196         REGULATOR_SUPPLY("avdd", "spi0.0"),
197 };
198
199 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
200         REGULATOR_SUPPLY("vpp_fuse", NULL),
201 };
202
203 static struct regulator_consumer_supply palmas_regen1_supply[] = {
204         REGULATOR_SUPPLY("vdd_com_3v3", NULL),
205         REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
206         REGULATOR_SUPPLY("vdd_nfc_3v3", NULL),
207 };
208
209 static struct regulator_consumer_supply palmas_regen2_supply[] = {
210 };
211
212 static struct regulator_consumer_supply palmas_regen4_supply[] = {
213         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
214 };
215
216 /* TPS51632 DC-DC converter */
217 static struct regulator_consumer_supply tps51632_dcdc_cpu_supply[] = {
218         REGULATOR_SUPPLY("vdd_cpu", NULL),
219 };
220
221 static struct regulator_init_data tps51632_cpu_init_data = {
222         .constraints = {                                                \
223                 .min_uV = 500000,                                       \
224                 .max_uV = 1520000,                                      \
225                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
226                                         REGULATOR_MODE_STANDBY),        \
227                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
228                                         REGULATOR_CHANGE_STATUS |       \
229                                          REGULATOR_CHANGE_CONTROL |     \
230                                         REGULATOR_CHANGE_VOLTAGE),      \
231                 .always_on = 1,                                         \
232                 .boot_on =  1,                                          \
233                 .apply_uV = 0,                                          \
234         },                                                              \
235         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_cpu_supply),  \
236         .consumer_supplies = tps51632_dcdc_cpu_supply,          \
237         .supply_regulator = palmas_rails(regen2),                       \
238 };
239
240 static struct tps51632_regulator_platform_data tps51632_pdata_cpu = {
241         .reg_init_data = &tps51632_cpu_init_data,               \
242         .enable_pwm = false,                            \
243         .max_voltage_uV = 1520000,                      \
244         .base_voltage_uV = 500000,                      \
245         .slew_rate_uv_per_us = 6000,                    \
246 };
247
248 static struct i2c_board_info tps51632_cpu_boardinfo[] = {
249         {
250                 I2C_BOARD_INFO("tps51632_cpu", 0x43),
251                 .platform_data  = &tps51632_pdata_cpu,
252         },
253 };
254
255 static struct regulator_consumer_supply tps51632_dcdc_gpu_supply[] = {
256         REGULATOR_SUPPLY("vdd_gpu", NULL),
257 };
258
259 static struct regulator_init_data tps51632_init_gpu_data = {
260         .constraints = {                                                \
261                 .min_uV = 500000,                                       \
262                 .max_uV = 1520000,                                      \
263                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
264                                         REGULATOR_MODE_STANDBY),        \
265                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
266                                         REGULATOR_CHANGE_STATUS |       \
267                                          REGULATOR_CHANGE_CONTROL |     \
268                                         REGULATOR_CHANGE_VOLTAGE),      \
269                 .always_on = 1,                                         \
270                 .boot_on =  1,                                          \
271                 .apply_uV = 0,                                          \
272         },                                                              \
273         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_gpu_supply),  \
274         .consumer_supplies = tps51632_dcdc_gpu_supply,          \
275         .supply_regulator = palmas_rails(regen2),                       \
276 };
277
278 static struct tps51632_regulator_platform_data tps51632_pdata_gpu = {
279         .reg_init_data = &tps51632_init_gpu_data,               \
280         .enable_pwm = false,                            \
281         .max_voltage_uV = 1520000,                      \
282         .base_voltage_uV = 500000,                      \
283         .slew_rate_uv_per_us = 6000,                    \
284 };
285
286 static struct i2c_board_info tps51632_gpu_boardinfo[] = {
287         {
288                 I2C_BOARD_INFO("tps51632_gpu", 0x45),
289                 .platform_data  = &tps51632_pdata_gpu,
290         },
291 };
292
293 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
294         _boot_on, _apply_uv)                                            \
295         static struct regulator_init_data reg_idata_##_name = {         \
296                 .constraints = {                                        \
297                         .name = palmas_rails(_name),                    \
298                         .min_uV = (_minmv)*1000,                        \
299                         .max_uV = (_maxmv)*1000,                        \
300                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
301                                         REGULATOR_MODE_STANDBY),        \
302                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
303                                         REGULATOR_CHANGE_STATUS |       \
304                                         REGULATOR_CHANGE_VOLTAGE),      \
305                         .always_on = _always_on,                        \
306                         .boot_on = _boot_on,                            \
307                         .apply_uV = _apply_uv,                          \
308                 },                                                      \
309                 .num_consumer_supplies =                                \
310                         ARRAY_SIZE(palmas_##_name##_supply),            \
311                 .consumer_supplies = palmas_##_name##_supply,           \
312                 .supply_regulator = _supply_reg,                        \
313         }
314
315 PALMAS_PDATA_INIT(smps12, 900, 1300, NULL, 0, 0, 0);
316 PALMAS_PDATA_INIT(smps3, 1000, 3300, NULL, 1, 1, 0);
317 PALMAS_PDATA_INIT(smps6, 500, 1650, NULL, 0, 0, 0);
318 PALMAS_PDATA_INIT(smps8, 1000, 3300, NULL, 0, 0, 0);
319 PALMAS_PDATA_INIT(smps9, 1800, 1800, NULL, 1, 1, 0);
320 PALMAS_PDATA_INIT(ldo1, 1050, 1050, palmas_rails(smps3), 0, 0, 1);
321 PALMAS_PDATA_INIT(ldo2, 2800, 3000, palmas_rails(smps6), 0, 0, 0);
322 PALMAS_PDATA_INIT(ldo3, 2800, 3000, NULL, 0, 0, 0);
323 PALMAS_PDATA_INIT(ldo4, 2800, 3000, palmas_rails(smps3), 0, 0, 0);
324 PALMAS_PDATA_INIT(ldo5, 1100, 1100, palmas_rails(smps6), 1, 1, 1);
325 PALMAS_PDATA_INIT(ldo6, 2700, 2700, NULL, 0, 0, 0);
326 PALMAS_PDATA_INIT(ldo7, 2800, 2800, NULL, 0, 0, 0);
327 PALMAS_PDATA_INIT(ldo8, 2800, 3000, NULL, 0, 0, 0);
328 PALMAS_PDATA_INIT(ldo9, 2800, 3000, palmas_rails(smps3), 1, 1, 0);
329 PALMAS_PDATA_INIT(ldo10, 1800, 3300, NULL, 0, 0, 0);
330 PALMAS_PDATA_INIT(ldo11, 3300, 3300, NULL, 0, 0, 0);
331 PALMAS_PDATA_INIT(ldo12, 2800, 3000, palmas_rails(smps9), 1, 1, 0);
332 PALMAS_PDATA_INIT(ldo13, 1800, 1800, palmas_rails(smps9), 1, 1, 1);
333 PALMAS_PDATA_INIT(ldo14, 2800, 3000, NULL, 0, 0, 0);
334 PALMAS_PDATA_INIT(ldoln, 3300, 3300, NULL, 1, 1, 1);
335 PALMAS_PDATA_INIT(ldousb, 2800, 3000, NULL, 0, 0, 0);
336 PALMAS_PDATA_INIT(regen1, 3300, 3300, NULL, 1, 0, 0);
337 PALMAS_PDATA_INIT(regen2, 5000, 5000, NULL, 1, 0, 0);
338 PALMAS_PDATA_INIT(regen4, 5000, 5000, NULL, 0, 0, 0);
339
340 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
341
342 static struct regulator_init_data *ardbeg_reg_data[PALMAS_NUM_REGS] = {
343         PALMAS_REG_PDATA(smps12),
344         NULL,
345         PALMAS_REG_PDATA(smps3),
346         NULL,
347         NULL,
348         PALMAS_REG_PDATA(smps6),
349         NULL,
350         PALMAS_REG_PDATA(smps8),
351         PALMAS_REG_PDATA(smps9),
352         NULL,
353         PALMAS_REG_PDATA(ldo1),
354         PALMAS_REG_PDATA(ldo2),
355         PALMAS_REG_PDATA(ldo3),
356         PALMAS_REG_PDATA(ldo4),
357         PALMAS_REG_PDATA(ldo5),
358         PALMAS_REG_PDATA(ldo6),
359         PALMAS_REG_PDATA(ldo7),
360         PALMAS_REG_PDATA(ldo8),
361         PALMAS_REG_PDATA(ldo9),
362         PALMAS_REG_PDATA(ldo10),
363         PALMAS_REG_PDATA(ldo11),
364         PALMAS_REG_PDATA(ldo12),
365         PALMAS_REG_PDATA(ldo13),
366         PALMAS_REG_PDATA(ldo14),
367         PALMAS_REG_PDATA(ldoln),
368         PALMAS_REG_PDATA(ldousb),
369         PALMAS_REG_PDATA(regen1),
370         PALMAS_REG_PDATA(regen2),
371         NULL,
372         PALMAS_REG_PDATA(regen4),
373         NULL,
374         NULL,
375         NULL,
376         NULL,
377         NULL,
378 };
379
380 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
381                 _tstep, _vsel)                                          \
382         static struct palmas_reg_init reg_init_data_##_name = {         \
383                 .warm_reset = _warm_reset,                              \
384                 .roof_floor =   _roof_floor,                            \
385                 .mode_sleep = _mode_sleep,              \
386                 .tstep = _tstep,                        \
387                 .vsel = _vsel,          \
388         }
389
390 PALMAS_REG_INIT(smps12, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
391 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
392 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
393 PALMAS_REG_INIT(smps45, 0, 0, 0, 0, 0);
394 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
395 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
396 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
397 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
398 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
399 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
400 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
401 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
402 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
403 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
404 PALMAS_REG_INIT(ldo5, 0, PALMAS_EXT_CONTROL_NSLEEP, 1, 0, 0);
405 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
406 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
407 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
408 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
409 PALMAS_REG_INIT(ldo10, 0, 0, 0, 0, 0);
410 PALMAS_REG_INIT(ldo11, 0, 0, 0, 0, 0);
411 PALMAS_REG_INIT(ldo12, 0, 0, 0, 0, 0);
412 PALMAS_REG_INIT(ldo13, 0, 0, 0, 0, 0);
413 PALMAS_REG_INIT(ldo14, 0, 0, 0, 0, 0);
414 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
415 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
416
417 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
418 static struct palmas_reg_init *ardbeg_reg_init[PALMAS_NUM_REGS] = {
419         PALMAS_REG_INIT_DATA(smps12),
420         PALMAS_REG_INIT_DATA(smps123),
421         PALMAS_REG_INIT_DATA(smps3),
422         PALMAS_REG_INIT_DATA(smps45),
423         PALMAS_REG_INIT_DATA(smps457),
424         PALMAS_REG_INIT_DATA(smps6),
425         PALMAS_REG_INIT_DATA(smps7),
426         PALMAS_REG_INIT_DATA(smps8),
427         PALMAS_REG_INIT_DATA(smps9),
428         PALMAS_REG_INIT_DATA(smps10),
429         PALMAS_REG_INIT_DATA(ldo1),
430         PALMAS_REG_INIT_DATA(ldo2),
431         PALMAS_REG_INIT_DATA(ldo3),
432         PALMAS_REG_INIT_DATA(ldo4),
433         PALMAS_REG_INIT_DATA(ldo5),
434         PALMAS_REG_INIT_DATA(ldo6),
435         PALMAS_REG_INIT_DATA(ldo7),
436         PALMAS_REG_INIT_DATA(ldo8),
437         PALMAS_REG_INIT_DATA(ldo9),
438         PALMAS_REG_INIT_DATA(ldo10),
439         PALMAS_REG_INIT_DATA(ldo11),
440         PALMAS_REG_INIT_DATA(ldo12),
441         PALMAS_REG_INIT_DATA(ldo13),
442         PALMAS_REG_INIT_DATA(ldo14),
443         PALMAS_REG_INIT_DATA(ldoln),
444         PALMAS_REG_INIT_DATA(ldousb),
445 };
446
447 /* Macro for defining fixed regulator sub device data */
448 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
449 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
450         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
451         _sdelay)                                                        \
452         static struct regulator_init_data ri_data_##_var =              \
453         {                                                               \
454                 .supply_regulator = _in_supply,                         \
455                 .num_consumer_supplies =                                \
456                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
457                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
458                 .constraints = {                                        \
459                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
460                                         REGULATOR_MODE_STANDBY),        \
461                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
462                                         REGULATOR_CHANGE_STATUS |       \
463                                         REGULATOR_CHANGE_VOLTAGE),      \
464                         .always_on = _always_on,                        \
465                         .boot_on = _boot_on,                            \
466                 },                                                      \
467         };                                                              \
468         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
469         {                                                               \
470                 .supply_name = FIXED_SUPPLY(_name),                     \
471                 .microvolts = _millivolts * 1000,                       \
472                 .gpio = _gpio_nr,                                       \
473                 .gpio_is_open_drain = _open_drain,                      \
474                 .enable_high = _active_high,                            \
475                 .enabled_at_boot = _boot_state,                         \
476                 .init_data = &ri_data_##_var,                           \
477                 .startup_delay = _sdelay                                \
478         };                                                              \
479         static struct platform_device fixed_reg_en_##_var##_dev = {     \
480                 .name = "reg-fixed-voltage",                            \
481                 .id = _id,                                              \
482                 .dev = {                                                \
483                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
484                 },                                                      \
485         }
486
487
488 /* Always ON /Battery regulator */
489 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
490                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
491                 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
492                 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"),
493 };
494
495 static struct regulator_consumer_supply fixed_reg_en_vdd_cdc_1v2_aud_supply[] = {
496         REGULATOR_SUPPLY("vdd_cdc_1v2_aud", NULL),
497 };
498
499
500 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v2_dis_supply[] = {
501         REGULATOR_SUPPLY("vdd_cdc_1v2_dis", NULL),
502 };
503
504 static struct regulator_consumer_supply fixed_reg_en_vdd_cdc_3v3a_aud_supply[] = {
505         REGULATOR_SUPPLY("vdd_cdc_3v3a_aud", NULL),
506 };
507
508 static struct regulator_consumer_supply fixed_reg_en_vdd_usb0_5v0_supply[] = {
509         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
510         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
511         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci.1"),
512 };
513
514 static struct regulator_consumer_supply fixed_reg_en_vdd_dis_3v3a_sw_supply[] = {
515         REGULATOR_SUPPLY("vdd_dis_3v3_lcd", NULL),
516         REGULATOR_SUPPLY("vdd_dis_3v3_lvds", NULL),
517         REGULATOR_SUPPLY("avdd_lcd", NULL),
518 };
519
520 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
521         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
522 };
523
524 FIXED_REG(0,    battery,        battery,
525         NULL,   0,      0,
526         -1,     false, true,    0,      3300,   0);
527
528 FIXED_REG(1,    vdd_cdc_1v2_aud,        vdd_cdc_1v2_aud,
529         palmas_rails(smps3),    0,      0,
530         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO14, false, true,    0,      1200,
531         0);
532
533 FIXED_REG(2,    vdd_lcd_1v2_dis,        vdd_lcd_1v2_dis,
534         palmas_rails(smps3),    1,      1,
535         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false, true,    0,      1200,
536         0);
537
538 FIXED_REG(3,    vdd_cdc_3v3a_aud,       vdd_cdc_3v3a_aud,
539         NULL,   0,      0,
540         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO10, false, true,    0,      3300,
541         0);
542
543 FIXED_REG(4,    vdd_usb0_5v0,   vdd_usb0_5v0,
544         NULL,   0,      0,
545         TEGRA_GPIO_PN4, true, true,     0,      5000,
546         0);
547
548 FIXED_REG(5,    vdd_dis_3v3a_sw,        vdd_dis_3v3a_sw,
549         NULL,   1,      1,
550         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO3,  true, true,     0,      3300,
551         0);
552
553 FIXED_REG(6,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
554         NULL,   0,      0,
555         TEGRA_GPIO_PH7, true,   true,   0,      5000,   5000);
556
557 /*
558  * Creating fixed regulator device tables
559  */
560 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
561
562 #define E1780_COMMON_FIXED_REG                  \
563         ADD_FIXED_REG(battery),                 \
564         ADD_FIXED_REG(vdd_cdc_1v2_aud),         \
565         ADD_FIXED_REG(vdd_lcd_1v2_dis),         \
566         ADD_FIXED_REG(vdd_cdc_3v3a_aud),        \
567         ADD_FIXED_REG(vdd_usb0_5v0),            \
568         ADD_FIXED_REG(vdd_dis_3v3a_sw),         \
569         ADD_FIXED_REG(vdd_hdmi_5v0),
570
571 /* Gpio switch regulator platform data for ardbeg E1580 */
572 static struct platform_device *pfixed_reg_devs[] = {
573         E1780_COMMON_FIXED_REG
574 };
575
576 static struct palmas_pmic_platform_data pmic_platform = {
577         .enable_ldo8_tracking = false,
578         .disabe_ldo8_tracking_suspend = false,
579 };
580
581 static struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
582         {
583                 .clk32k_id = PALMAS_CLOCK32KG,
584                 .enable = true,
585         }, {
586                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
587                 .enable = true,
588         },
589 };
590
591 static struct palmas_pinctrl_config palmas_pincfg[] = {
592         PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
593         PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
594         PALMAS_PINMUX(GPIO0, ID, DEFAULT, DEFAULT),
595         PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
596         PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
597         PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
598         PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
599         PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
600         PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
601         PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
602         PALMAS_PINMUX(GPIO8, GPIO, DEFAULT, DEFAULT),
603         PALMAS_PINMUX(GPIO9, GPIO, DEFAULT, DEFAULT),
604         PALMAS_PINMUX(GPIO10, GPIO, DEFAULT, DEFAULT),
605         PALMAS_PINMUX(GPIO11, GPIO, DEFAULT, DEFAULT),
606         PALMAS_PINMUX(GPIO12, GPIO, DEFAULT, DEFAULT),
607         PALMAS_PINMUX(GPIO13, GPIO, DEFAULT, DEFAULT),
608         PALMAS_PINMUX(GPIO14, GPIO, DEFAULT, DEFAULT),
609         PALMAS_PINMUX(GPIO15, GPIO, DEFAULT, DEFAULT),
610 };
611
612 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
613         .pincfg = palmas_pincfg,
614         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
615         .dvfs1_enable = false,
616         .dvfs2_enable = false,
617 };
618
619 static struct palmas_platform_data palmas_pdata = {
620         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
621         .irq_base = PALMAS_TEGRA_IRQ_BASE,
622         .pmic_pdata = &pmic_platform,
623         .clk32k_init_data =  palmas_clk32k_idata,
624         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
625         .irq_flags = IRQ_TYPE_LEVEL_HIGH,
626         .use_power_off = true,
627         .pinctrl_pdata = &palmas_pinctrl_pdata,
628 };
629
630 static struct i2c_board_info palma_device[] = {
631         {
632                 I2C_BOARD_INFO("tps80036", 0x58),
633                 .irq            = INT_EXTERNAL_PMU,
634                 .platform_data  = &palmas_pdata,
635         },
636 };
637
638 static struct tegra_suspend_platform_data ardbeg_suspend_data = {
639         .cpu_timer      = 500,
640         .cpu_off_timer  = 300,
641         .suspend_mode   = TEGRA_SUSPEND_LP0,
642         .core_timer     = 0x157e,
643         .core_off_timer = 2000,
644         .corereq_high   = true,
645         .sysclkreq_high = true,
646         .cpu_lp2_min_residency = 1000,
647         .min_residency_crail = 20000,
648 };
649
650 int __init ardbeg_suspend_init(void)
651 {
652         tegra_init_suspend(&ardbeg_suspend_data);
653         return 0;
654 }
655
656 int __init ardbeg_regulator_init(void)
657 {
658         int i;
659         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
660         u32 pmc_ctrl;
661
662         /* configure the power management controller to trigger PMU
663          * interrupts when high */
664         pmc_ctrl = readl(pmc + PMC_CTRL);
665         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
666
667
668         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
669                 pmic_platform.reg_data[i] = ardbeg_reg_data[i];
670                 pmic_platform.reg_init[i] = ardbeg_reg_init[i];
671         }
672
673         i2c_register_board_info(4, palma_device,
674                         ARRAY_SIZE(palma_device));
675         i2c_register_board_info(4, tps51632_cpu_boardinfo, 1);
676         i2c_register_board_info(4, tps51632_gpu_boardinfo, 1);
677         reg_init_data_ldo5.enable_tracking = true;
678         reg_init_data_ldo5.tracking_regulator = PALMAS_REG_SMPS12;
679
680         return 0;
681 }
682
683 static int __init ardbeg_fixed_regulator_init(void)
684 {
685         struct board_info board_info;
686
687         if (!of_machine_is_compatible("nvidia,ardbeg"))
688                 return 0;
689
690         tegra_get_board_info(&board_info);
691         if (board_info.board_id == BOARD_E1780)
692                 return platform_add_devices(pfixed_reg_devs,
693                                 ARRAY_SIZE(pfixed_reg_devs));
694 }
695
696 subsys_initcall_sync(ardbeg_fixed_regulator_init);