4900b554f322b0cb3490522015676adad0857f53
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-power.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-power.c
3  *
4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca954x.h>
22 #include <linux/i2c/pca953x.h>
23 #include <linux/platform_device.h>
24 #include <linux/resource.h>
25 #include <linux/io.h>
26 #include <mach/edp.h>
27 #include <mach/irqs.h>
28 #include <linux/edp.h>
29 #include <linux/platform_data/tegra_edp.h>
30 #include <linux/pid_thermal_gov.h>
31 #include <linux/regulator/fixed.h>
32 #include <linux/mfd/palmas.h>
33 #include <linux/mfd/as3722-plat.h>
34 #include <linux/power/power_supply_extcon.h>
35 #include <linux/regulator/tps51632-regulator.h>
36 #include <linux/regulator/machine.h>
37 #include <linux/irq.h>
38 #include <linux/gpio.h>
39 #include <linux/regulator/tegra-dfll-bypass-regulator.h>
40 #include <linux/power/bq2471x-charger.h>
41 #include <linux/power/bq2477x-charger.h>
42 #include <linux/tegra-fuse.h>
43
44 #include <asm/mach-types.h>
45 #include <mach/pinmux-t12.h>
46
47 #include "pm.h"
48 #include "dvfs.h"
49 #include "board.h"
50 #include "tegra-board-id.h"
51 #include "board-common.h"
52 #include "board-ardbeg.h"
53 #include "board-pmu-defines.h"
54 #include "devices.h"
55 #include "iomap.h"
56 #include "tegra_cl_dvfs.h"
57 #include "tegra11_soctherm.h"
58 #include "tegra3_tsensor.h"
59
60 #define E1735_EMULATE_E1767_SKU 1001
61
62 #define PMC_CTRL                0x0
63 #define PMC_CTRL_INTR_LOW       (1 << 17)
64
65 /************************ ARDBEG E1733 based regulators ***********/
66 static struct regulator_consumer_supply as3722_ldo0_supply[] = {
67         REGULATOR_SUPPLY("avdd_pll_m", NULL),
68         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
69         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
70         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
71         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
72         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
73         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
74         REGULATOR_SUPPLY("avdd_pll_x", NULL),
75         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
76 };
77
78 static struct regulator_consumer_supply as3722_ldo1_supply[] = {
79         REGULATOR_SUPPLY("vdd_cam1_1v8_cam", NULL),
80         REGULATOR_SUPPLY("vdd_cam2_1v8_cam", NULL),
81         REGULATOR_SUPPLY("vif", "2-0010"),
82         REGULATOR_SUPPLY("vif", "2-0036"),
83         REGULATOR_SUPPLY("vdd_i2c", "2-000c"),
84         REGULATOR_SUPPLY("vi2c", "2-0030"),
85         REGULATOR_SUPPLY("vif2", "2-0021"),
86         REGULATOR_SUPPLY("dovdd", "2-0010"),
87         REGULATOR_SUPPLY("vdd", "2-004a"),
88         REGULATOR_SUPPLY("vif", "2-0048"),
89 };
90
91 static struct regulator_consumer_supply as3722_ldo2_supply[] = {
92         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
93         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
94         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
95         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
96         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
97         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.0"),
98         REGULATOR_SUPPLY("avdd_dsi_csi", "vi.1"),
99         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
100         REGULATOR_SUPPLY("avdd_hsic_com", NULL),
101         REGULATOR_SUPPLY("avdd_hsic_mdm", NULL),
102         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
103         REGULATOR_SUPPLY("vdd", "1-004c"),
104         REGULATOR_SUPPLY("vdd", "1-004d"),
105 };
106
107 static struct regulator_consumer_supply as3722_ldo3_supply[] = {
108         REGULATOR_SUPPLY("vdd_rtc", NULL),
109 };
110
111 static struct regulator_consumer_supply as3722_ldo4_supply[] = {
112         REGULATOR_SUPPLY("vdd_2v7_hv", NULL),
113         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
114         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
115         REGULATOR_SUPPLY("avdd_cam3_cam", NULL),
116         REGULATOR_SUPPLY("vana", "2-0010"),
117         REGULATOR_SUPPLY("avdd_ov5693", "2-0010"),
118 };
119
120 static struct regulator_consumer_supply as3722_ldo5_supply[] = {
121         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
122         REGULATOR_SUPPLY("vdig", "2-0010"),
123         REGULATOR_SUPPLY("vdig", "2-0036"),
124 };
125
126 static struct regulator_consumer_supply as3722_ldo6_supply[] = {
127         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
128         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
129 };
130
131 static struct regulator_consumer_supply as3722_ldo7_supply[] = {
132         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
133         REGULATOR_SUPPLY("imx135_reg2", NULL),
134         REGULATOR_SUPPLY("vdig_lv", "2-0010"),
135         REGULATOR_SUPPLY("dvdd", "2-0010"),
136 };
137
138 static struct regulator_consumer_supply as3722_ldo9_supply[] = {
139         REGULATOR_SUPPLY("avdd", "spi0.0"),
140 };
141
142 static struct regulator_consumer_supply as3722_ldo10_supply[] = {
143         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
144         REGULATOR_SUPPLY("imx135_reg1", NULL),
145         REGULATOR_SUPPLY("vdd", "2-000c"),
146         REGULATOR_SUPPLY("vin", "2-0030"),
147         REGULATOR_SUPPLY("vana", "2-0036"),
148         REGULATOR_SUPPLY("vana", "2-0021"),
149         REGULATOR_SUPPLY("vdd_af1", "2-0010"),
150         REGULATOR_SUPPLY("vin", "2-004a"),
151         REGULATOR_SUPPLY("vana", "2-0048"),
152 };
153
154 static struct regulator_consumer_supply as3722_ldo11_supply[] = {
155         REGULATOR_SUPPLY("vpp_fuse", NULL),
156 };
157
158 static struct regulator_consumer_supply as3722_sd0_supply[] = {
159         REGULATOR_SUPPLY("vdd_cpu", NULL),
160 };
161
162 static struct regulator_consumer_supply as3722_sd1_supply[] = {
163         REGULATOR_SUPPLY("vdd_core", NULL),
164 };
165
166 static struct regulator_consumer_supply as3722_sd2_supply[] = {
167         REGULATOR_SUPPLY("vddio_ddr", NULL),
168         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
169         REGULATOR_SUPPLY("vddio_ddr3", NULL),
170         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
171 };
172
173 static struct regulator_consumer_supply as3722_sd4_supply[] = {
174         REGULATOR_SUPPLY("avdd_hdmi","tegradc.1"),
175         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
176         REGULATOR_SUPPLY("avdd_pex_pll", "tegra-pcie"),
177         REGULATOR_SUPPLY("avddio_pex", "tegra-pcie"),
178         REGULATOR_SUPPLY("dvddio_pex", "tegra-pcie"),
179         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
180         REGULATOR_SUPPLY("vddio_pex_sata", "tegra-sata.0"),
181 };
182
183 static struct regulator_consumer_supply as3722_sd5_supply[] = {
184         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639.0"),
185         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645.0"),
186         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639.0"),
187         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645.0"),
188         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639.0"),
189         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645.0"),
190         REGULATOR_SUPPLY("avdd_osc", NULL),
191         REGULATOR_SUPPLY("vddio_sys", NULL),
192         REGULATOR_SUPPLY("vddio_sys_2", NULL),
193         REGULATOR_SUPPLY("vddio_gmi", NULL),
194         REGULATOR_SUPPLY("pwrdet_nand", NULL),
195         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
196         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
197         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
198         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
199         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
200         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
201         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
202         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
203         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
204         REGULATOR_SUPPLY("vddio_audio", NULL),
205         REGULATOR_SUPPLY("pwrdet_audio", NULL),
206         REGULATOR_SUPPLY("vddio_uart", NULL),
207         REGULATOR_SUPPLY("pwrdet_uart", NULL),
208         REGULATOR_SUPPLY("vddio_bb", NULL),
209         REGULATOR_SUPPLY("pwrdet_bb", NULL),
210         REGULATOR_SUPPLY("vdd_1v8b", "0-0048"),
211         REGULATOR_SUPPLY("vdd_dtv", NULL),
212         REGULATOR_SUPPLY("vdd_1v8_eeprom", NULL),
213         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
214         REGULATOR_SUPPLY("vddio_cam", "vi"),
215         REGULATOR_SUPPLY("pwrdet_cam", NULL),
216         REGULATOR_SUPPLY("dvdd", "spi0.0"),
217         REGULATOR_SUPPLY("vlogic", "0-0069"),
218         REGULATOR_SUPPLY("vid", "0-000c"),
219         REGULATOR_SUPPLY("vddio", "0-0077"),
220         REGULATOR_SUPPLY("vdd_sata", "tegra-sata.0"),
221         REGULATOR_SUPPLY("avdd_sata", "tegra-sata.0"),
222         REGULATOR_SUPPLY("avdd_sata_pll", "tegra-sata.0"),
223 };
224
225 static struct regulator_consumer_supply as3722_sd6_supply[] = {
226         REGULATOR_SUPPLY("vdd_gpu", NULL),
227 };
228
229
230 AMS_PDATA_INIT(sd0, NULL, 700000, 1400000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE2);
231 AMS_PDATA_INIT(sd1, NULL, 700000, 1400000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
232 AMS_PDATA_INIT(sd2, NULL, 1350000, 1350000, 1, 1, 1, 0);
233 AMS_PDATA_INIT(sd4, NULL, 1050000, 1050000, 0, 1, 1, 0);
234 AMS_PDATA_INIT(sd5, NULL, 1800000, 1800000, 1, 1, 1, 0);
235 AMS_PDATA_INIT(sd6, NULL, 650000, 1400000, 0, 1, 0, 0);
236 AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
237 AMS_PDATA_INIT(ldo1, NULL, 1800000, 1800000, 0, 1, 1, 0);
238 AMS_PDATA_INIT(ldo2, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
239 AMS_PDATA_INIT(ldo3, NULL, 800000, 800000, 1, 1, 1, 0);
240 AMS_PDATA_INIT(ldo4, NULL, 2700000, 2700000, 0, 0, 1, 0);
241 AMS_PDATA_INIT(ldo5, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
242 AMS_PDATA_INIT(ldo6, NULL, 1800000, 3300000, 0, 0, 1, 0);
243 AMS_PDATA_INIT(ldo7, AS3722_SUPPLY(sd5), 1050000, 1050000, 0, 0, 1, 0);
244 AMS_PDATA_INIT(ldo9, NULL, 3300000, 3300000, 0, 0, 1, 0);
245 AMS_PDATA_INIT(ldo10, NULL, 2700000, 2700000, 0, 0, 1, 0);
246 AMS_PDATA_INIT(ldo11, NULL, 1800000, 1800000, 0, 0, 1, 0);
247
248 static struct as3722_pinctrl_platform_data as3722_pctrl_pdata[] = {
249         AS3722_PIN_CONTROL("gpio0", "gpio", "pull-down", NULL, NULL, "output-low"),
250         AS3722_PIN_CONTROL("gpio1", "gpio", NULL, NULL, NULL, "output-high"),
251         AS3722_PIN_CONTROL("gpio2", "gpio", NULL, NULL, NULL, "output-high"),
252         AS3722_PIN_CONTROL("gpio3", "gpio", NULL, NULL, "enabled", NULL),
253         AS3722_PIN_CONTROL("gpio4", "gpio", NULL, NULL, NULL, "output-high"),
254         AS3722_PIN_CONTROL("gpio5", "clk32k-out", "pull-down", NULL, NULL, NULL),
255         AS3722_PIN_CONTROL("gpio6", "gpio", NULL, NULL, "enabled", NULL),
256         AS3722_PIN_CONTROL("gpio7", "gpio", NULL, NULL, NULL, "output-low"),
257 };
258
259 static struct as3722_adc_extcon_platform_data as3722_adc_extcon_pdata = {
260         .connection_name = "as3722-extcon",
261         .enable_adc1_continuous_mode = true,
262         .enable_low_voltage_range = true,
263         .adc_channel = 12,
264         .hi_threshold =  0x100,
265         .low_threshold = 0x80,
266 };
267
268 static struct as3722_platform_data as3722_pdata = {
269         .reg_pdata[AS3722_SD0] = &as3722_sd0_reg_pdata,
270         .reg_pdata[AS3722_SD1] = &as3722_sd1_reg_pdata,
271         .reg_pdata[AS3722_SD2] = &as3722_sd2_reg_pdata,
272         .reg_pdata[AS3722_SD4] = &as3722_sd4_reg_pdata,
273         .reg_pdata[AS3722_SD5] = &as3722_sd5_reg_pdata,
274         .reg_pdata[AS3722_SD6] = &as3722_sd6_reg_pdata,
275         .reg_pdata[AS3722_LDO0] = &as3722_ldo0_reg_pdata,
276         .reg_pdata[AS3722_LDO1] = &as3722_ldo1_reg_pdata,
277         .reg_pdata[AS3722_LDO2] = &as3722_ldo2_reg_pdata,
278         .reg_pdata[AS3722_LDO3] = &as3722_ldo3_reg_pdata,
279         .reg_pdata[AS3722_LDO4] = &as3722_ldo4_reg_pdata,
280         .reg_pdata[AS3722_LDO5] = &as3722_ldo5_reg_pdata,
281         .reg_pdata[AS3722_LDO6] = &as3722_ldo6_reg_pdata,
282         .reg_pdata[AS3722_LDO7] = &as3722_ldo7_reg_pdata,
283         .reg_pdata[AS3722_LDO9] = &as3722_ldo9_reg_pdata,
284         .reg_pdata[AS3722_LDO10] = &as3722_ldo10_reg_pdata,
285         .reg_pdata[AS3722_LDO11] = &as3722_ldo11_reg_pdata,
286         .gpio_base = AS3722_GPIO_BASE,
287         .irq_base = AS3722_IRQ_BASE,
288         .use_internal_int_pullup = 0,
289         .use_internal_i2c_pullup = 0,
290         .pinctrl_pdata = as3722_pctrl_pdata,
291         .num_pinctrl = ARRAY_SIZE(as3722_pctrl_pdata),
292         .enable_clk32k_out = true,
293         .use_power_off = true,
294         .extcon_pdata = &as3722_adc_extcon_pdata,
295 };
296
297 static struct i2c_board_info __initdata as3722_regulators[] = {
298         {
299                 I2C_BOARD_INFO("as3722", 0x40),
300                 .flags = I2C_CLIENT_WAKE,
301                 .irq = INT_EXTERNAL_PMU,
302                 .platform_data = &as3722_pdata,
303         },
304 };
305
306 int __init ardbeg_as3722_regulator_init(void)
307 {
308         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
309         u32 pmc_ctrl;
310         struct board_info board_info;
311
312         /* AS3722: Normal state of INT request line is LOW.
313          * configure the power management controller to trigger PMU
314          * interrupts when HIGH.
315          */
316         pmc_ctrl = readl(pmc + PMC_CTRL);
317         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
318
319         /* Set vdd_gpu init uV to 1V */
320         as3722_sd6_reg_idata.constraints.init_uV = 900000;
321
322         as3722_sd6_reg_idata.constraints.min_uA = 3500000;
323         as3722_sd6_reg_idata.constraints.max_uA = 3500000;
324
325         as3722_sd0_reg_idata.constraints.min_uA = 3500000;
326         as3722_sd0_reg_idata.constraints.max_uA = 3500000;
327
328         as3722_sd1_reg_idata.constraints.min_uA = 2500000;
329         as3722_sd1_reg_idata.constraints.max_uA = 2500000;
330
331         as3722_ldo3_reg_pdata.enable_tracking = true;
332         as3722_ldo3_reg_pdata.disable_tracking_suspend = true;
333
334         tegra_get_board_info(&board_info);
335         if (board_info.board_id == BOARD_E1792) {
336                 /*Default DDR voltage is 1.35V but lpddr3 supports 1.2V*/
337                 as3722_sd2_reg_idata.constraints.min_uV = 1200000;
338                 as3722_sd2_reg_idata.constraints.max_uV = 1200000;
339         }
340
341         pr_info("%s: i2c_register_board_info\n", __func__);
342         i2c_register_board_info(4, as3722_regulators,
343                         ARRAY_SIZE(as3722_regulators));
344         return 0;
345 }
346
347 int __init ardbeg_ams_regulator_init(void)
348 {
349         ardbeg_as3722_regulator_init();
350         return 0;
351 }
352
353 /**************** ARDBEG-TI913 based regulator ************/
354 #define palmas_ti913_smps123_supply as3722_sd6_supply
355 #define palmas_ti913_smps45_supply as3722_sd1_supply
356 #define palmas_ti913_smps6_supply as3722_sd5_supply
357 #define palmas_ti913_smps7_supply as3722_sd2_supply
358 #define palmas_ti913_smps9_supply as3722_sd4_supply
359 #define palmas_ti913_ldo1_supply as3722_ldo0_supply
360 #define palmas_ti913_ldo2_supply as3722_ldo5_supply
361 #define palmas_ti913_ldo3_supply as3722_ldo9_supply
362 #define palmas_ti913_ldo4_supply as3722_ldo2_supply
363 #define palmas_ti913_ldo5_supply as3722_ldo4_supply
364 #define palmas_ti913_ldo6_supply as3722_ldo1_supply
365 #define palmas_ti913_ldo7_supply as3722_ldo10_supply
366 #define palmas_ti913_ldo8_supply as3722_ldo3_supply
367 #define palmas_ti913_ldo9_supply as3722_ldo6_supply
368 #define palmas_ti913_ldoln_supply as3722_ldo7_supply
369 #define palmas_ti913_ldousb_supply as3722_ldo11_supply
370
371 static struct regulator_consumer_supply palmas_ti913_regen1_supply[] = {
372         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5645.0"),
373         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
374         REGULATOR_SUPPLY("pwrdet_hv", NULL),
375         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
376         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
377         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
378         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
379         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
380         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
381         REGULATOR_SUPPLY("hvdd_pex", "tegra-pcie"),
382         REGULATOR_SUPPLY("hvdd_pex_pll_e", "tegra-pcie"),
383         REGULATOR_SUPPLY("vddio_pex_ctl", "tegra-pcie"),
384         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
385         REGULATOR_SUPPLY("vdd", "0-0069"),
386         REGULATOR_SUPPLY("vdd", "0-0048"),
387         REGULATOR_SUPPLY("vdd", "stm8t143.2"),
388         REGULATOR_SUPPLY("vdd", "0-000c"),
389         REGULATOR_SUPPLY("vdd", "0-0077"),
390         REGULATOR_SUPPLY("hvdd_sata", "tegra-sata.0"),
391 };
392
393 PALMAS_REGS_PDATA(ti913_smps123, 650, 1400, NULL, 0, 1, 1, NORMAL,
394         0, 0, 0, 0, 0);
395 PALMAS_REGS_PDATA(ti913_smps45, 700, 1400, NULL, 1, 1, 1, NORMAL,
396         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
397 PALMAS_REGS_PDATA(ti913_smps6, 1800, 1800, NULL, 1, 1, 1, NORMAL,
398         0, 0, 0, 0, 0);
399 PALMAS_REGS_PDATA(ti913_smps7, 900, 1350, NULL, 1, 1, 1, NORMAL,
400         0, 0, 0, 0, 0);
401 PALMAS_REGS_PDATA(ti913_smps9, 1050, 1050, NULL, 0, 0, 0, NORMAL,
402         0, 0, 0, 0, 0);
403 PALMAS_REGS_PDATA(ti913_ldo1, 1050, 1250, palmas_rails(ti913_smps7),
404                 1, 1, 1, 0, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
405 PALMAS_REGS_PDATA(ti913_ldo2, 1200, 1200, palmas_rails(ti913_smps6),
406                 0, 0, 1, 0, 0, 0, 0, 0, 0);
407 PALMAS_REGS_PDATA(ti913_ldo3, 3100, 3100, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
408 PALMAS_REGS_PDATA(ti913_ldo4, 1200, 1200, palmas_rails(ti913_smps6),
409                 0, 0, 1, 0, 0, 0, 0, 0, 0);
410 PALMAS_REGS_PDATA(ti913_ldo5, 2700, 2700, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
411 PALMAS_REGS_PDATA(ti913_ldo6, 1800, 1800, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
412 PALMAS_REGS_PDATA(ti913_ldo7, 2700, 2700, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
413 PALMAS_REGS_PDATA(ti913_ldo8, 800, 800, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
414 PALMAS_REGS_PDATA(ti913_ldo9, 1800, 3300, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
415 PALMAS_REGS_PDATA(ti913_ldoln, 1050, 1050, palmas_rails(ti913_smps6),
416                 0, 0, 1, 0, 0, 0, 0, 0, 0);
417 PALMAS_REGS_PDATA(ti913_ldousb, 1800, 1800, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
418 PALMAS_REGS_PDATA(ti913_regen1, 2800, 3300, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
419
420 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
421 static struct regulator_init_data *ardbeg_1735_reg_data[PALMAS_NUM_REGS] = {
422         NULL,
423         PALMAS_REG_PDATA(ti913_smps123),
424         NULL,
425         PALMAS_REG_PDATA(ti913_smps45),
426         NULL,
427         PALMAS_REG_PDATA(ti913_smps6),
428         PALMAS_REG_PDATA(ti913_smps7),
429         NULL,
430         PALMAS_REG_PDATA(ti913_smps9),
431         NULL,
432         NULL,
433         PALMAS_REG_PDATA(ti913_ldo1),
434         PALMAS_REG_PDATA(ti913_ldo2),
435         PALMAS_REG_PDATA(ti913_ldo3),
436         PALMAS_REG_PDATA(ti913_ldo4),
437         PALMAS_REG_PDATA(ti913_ldo5),
438         PALMAS_REG_PDATA(ti913_ldo6),
439         PALMAS_REG_PDATA(ti913_ldo7),
440         PALMAS_REG_PDATA(ti913_ldo8),
441         PALMAS_REG_PDATA(ti913_ldo9),
442         NULL,
443         NULL,
444         NULL,
445         NULL,
446         NULL,
447         PALMAS_REG_PDATA(ti913_ldoln),
448         PALMAS_REG_PDATA(ti913_ldousb),
449         PALMAS_REG_PDATA(ti913_regen1),
450         NULL,
451         NULL,
452         NULL,
453         NULL,
454 };
455
456 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
457 static struct palmas_reg_init *ardbeg_1735_reg_init[PALMAS_NUM_REGS] = {
458         NULL,
459         PALMAS_REG_INIT_DATA(ti913_smps123),
460         NULL,
461         PALMAS_REG_INIT_DATA(ti913_smps45),
462         NULL,
463         PALMAS_REG_INIT_DATA(ti913_smps6),
464         PALMAS_REG_INIT_DATA(ti913_smps7),
465         NULL,
466         PALMAS_REG_INIT_DATA(ti913_smps9),
467         NULL,
468         NULL,
469         PALMAS_REG_INIT_DATA(ti913_ldo1),
470         PALMAS_REG_INIT_DATA(ti913_ldo2),
471         PALMAS_REG_INIT_DATA(ti913_ldo3),
472         PALMAS_REG_INIT_DATA(ti913_ldo4),
473         PALMAS_REG_INIT_DATA(ti913_ldo5),
474         PALMAS_REG_INIT_DATA(ti913_ldo6),
475         PALMAS_REG_INIT_DATA(ti913_ldo7),
476         PALMAS_REG_INIT_DATA(ti913_ldo8),
477         PALMAS_REG_INIT_DATA(ti913_ldo9),
478         NULL,
479         NULL,
480         NULL,
481         NULL,
482         NULL,
483         PALMAS_REG_INIT_DATA(ti913_ldoln),
484         PALMAS_REG_INIT_DATA(ti913_ldousb),
485         PALMAS_REG_INIT_DATA(ti913_regen1),
486         NULL,
487         NULL,
488         NULL,
489         NULL,
490 };
491
492 struct palmas_clk32k_init_data palmas_ti913_clk32k_idata[] = {
493         {
494                 .clk32k_id = PALMAS_CLOCK32KG,
495                 .enable = true,
496         }, {
497                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
498                 .enable = true,
499         },
500 };
501
502 static struct palmas_extcon_platform_data palmas_extcon_pdata = {
503         .connection_name = "palmas-extcon",
504         .enable_vbus_detection = true,
505         .enable_id_pin_detection = true,
506 };
507
508 static struct palmas_pinctrl_config palmas_ti913_pincfg[] = {
509         PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
510         PALMAS_PINMUX("vac", "vac", NULL, NULL),
511         PALMAS_PINMUX("gpio0", "id", "pull-up", NULL),
512         PALMAS_PINMUX("gpio1", "vbus_det", NULL, NULL),
513         PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
514         PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
515         PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
516         PALMAS_PINMUX("gpio5", "clk32kgaudio", NULL, NULL),
517         PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
518         PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
519 };
520
521 static struct palmas_pinctrl_platform_data palmas_ti913_pinctrl_pdata = {
522         .pincfg = palmas_ti913_pincfg,
523         .num_pinctrl = ARRAY_SIZE(palmas_ti913_pincfg),
524         .dvfs1_enable = true,
525         .dvfs2_enable = false,
526 };
527
528 static struct palmas_pmic_platform_data pmic_ti913_platform = {
529 };
530
531 static struct palmas_pm_platform_data palmas_pm_pdata = {
532         .use_power_off = true,
533         .use_power_reset = true,
534 };
535
536 static struct palmas_platform_data palmas_ti913_pdata = {
537         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
538         .irq_base = PALMAS_TEGRA_IRQ_BASE,
539         .pmic_pdata = &pmic_ti913_platform,
540         .pinctrl_pdata = &palmas_ti913_pinctrl_pdata,
541         .clk32k_init_data =  palmas_ti913_clk32k_idata,
542         .clk32k_init_data_size = ARRAY_SIZE(palmas_ti913_clk32k_idata),
543         .extcon_pdata = &palmas_extcon_pdata,
544         .pm_pdata = &palmas_pm_pdata,
545 };
546
547 static struct i2c_board_info palma_ti913_device[] = {
548         {
549                 I2C_BOARD_INFO("tps65913", 0x58),
550                 .irq            = INT_EXTERNAL_PMU,
551                 .platform_data  = &palmas_ti913_pdata,
552         },
553 };
554
555 int __init ardbeg_tps65913_regulator_init(void)
556 {
557         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
558         u32 pmc_ctrl;
559         int i;
560         struct board_info board_info;
561
562         /* TPS65913: Normal state of INT request line is LOW.
563          * configure the power management controller to trigger PMU
564          * interrupts when HIGH.
565          */
566         pmc_ctrl = readl(pmc + PMC_CTRL);
567         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
568
569         /* Tracking configuration */
570         reg_init_data_ti913_ldo8.config_flags =
571                 PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE;
572
573         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
574                 pmic_ti913_platform.reg_data[i] = ardbeg_1735_reg_data[i];
575                 pmic_ti913_platform.reg_init[i] = ardbeg_1735_reg_init[i];
576         }
577
578         /* Set vdd_gpu init uV to 1V */
579         reg_idata_ti913_smps123.constraints.init_uV = 900000;
580
581         tegra_get_board_info(&board_info);
582         if (board_info.board_id == BOARD_E1792) {
583                 /*Default DDR voltage is 1.35V but lpddr3 supports 1.2V*/
584                 reg_idata_ti913_smps7.constraints.min_uV = 1200000;
585                 reg_idata_ti913_smps7.constraints.max_uV = 1200000;
586         }
587
588         i2c_register_board_info(4, palma_ti913_device,
589                         ARRAY_SIZE(palma_ti913_device));
590         return 0;
591 }
592
593 static struct pca953x_platform_data tca6408_pdata = {
594                 .gpio_base = PMU_TCA6416_GPIO_BASE,
595 };
596
597 static const struct i2c_board_info tca6408_expander[] = {
598         {
599                 I2C_BOARD_INFO("tca6408", 0x20),
600                 .platform_data = &tca6408_pdata,
601         },
602 };
603
604 struct bq2471x_platform_data ardbeg_bq2471x_pdata = {
605         .dac_ichg               = 2240,
606         .dac_v                  = 9008,
607         .dac_minsv              = 4608,
608         .dac_iin                = 4992,
609         .wdt_refresh_timeout    = 40,
610         .gpio                   = TEGRA_GPIO_PK5,
611 };
612
613 static struct i2c_board_info __initdata bq2471x_boardinfo[] = {
614         {
615                 I2C_BOARD_INFO("bq2471x", 0x09),
616                 .platform_data  = &ardbeg_bq2471x_pdata,
617         },
618 };
619
620 struct bq2477x_platform_data ardbeg_bq2477x_pdata = {
621         .dac_ichg               = 2240,
622         .dac_v                  = 9008,
623         .dac_minsv              = 4608,
624         .dac_iin                = 4992,
625         .wdt_refresh_timeout    = 40,
626         .gpio                   = TEGRA_GPIO_PK5,
627 };
628
629 static struct i2c_board_info __initdata bq2477x_boardinfo[] = {
630         {
631                 I2C_BOARD_INFO("bq2477x", 0x6A),
632                 .platform_data  = &ardbeg_bq2477x_pdata,
633         },
634 };
635
636 static struct tegra_suspend_platform_data ardbeg_suspend_data = {
637         .cpu_timer      = 500,
638         .cpu_off_timer  = 300,
639         .suspend_mode   = TEGRA_SUSPEND_LP0,
640         .core_timer     = 0x157e,
641         .core_off_timer = 2000,
642         .corereq_high   = true,
643         .sysclkreq_high = true,
644         .cpu_lp2_min_residency = 1000,
645         .min_residency_vmin_fmin = 1000,
646         .min_residency_ncpu_fast = 8000,
647         .min_residency_ncpu_slow = 5000,
648         .min_residency_mclk_stop = 5000,
649         .min_residency_crail = 20000,
650 };
651
652 static struct power_supply_extcon_plat_data extcon_pdata = {
653         .extcon_name = "tegra-udc",
654 };
655
656 static struct platform_device power_supply_extcon_device = {
657         .name   = "power-supply-extcon",
658         .id     = -1,
659         .dev    = {
660                 .platform_data = &extcon_pdata,
661         },
662 };
663
664 int __init ardbeg_suspend_init(void)
665 {
666         struct board_info pmu_board_info;
667
668         tegra_get_pmu_board_info(&pmu_board_info);
669
670         if ((pmu_board_info.board_id == BOARD_E1735) &&
671             (pmu_board_info.sku != E1735_EMULATE_E1767_SKU)) {
672                 ardbeg_suspend_data.cpu_timer = 2000;
673                 ardbeg_suspend_data.crail_up_early = true;
674         }
675
676         tegra_init_suspend(&ardbeg_suspend_data);
677         return 0;
678 }
679
680 /* Macro for defining fixed regulator sub device data */
681 #define FIXED_SUPPLY(_name) "fixed_reg_en_"#_name
682 #define FIXED_REG(_id, _var, _name, _in_supply,                 \
683         _always_on, _boot_on, _gpio_nr, _open_drain,            \
684         _active_high, _boot_state, _millivolts, _sdelay)        \
685 static struct regulator_init_data ri_data_##_var =              \
686 {                                                               \
687         .supply_regulator = _in_supply,                         \
688         .num_consumer_supplies =                                \
689         ARRAY_SIZE(fixed_reg_en_##_name##_supply),              \
690         .consumer_supplies = fixed_reg_en_##_name##_supply,     \
691         .constraints = {                                        \
692                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
693                                 REGULATOR_MODE_STANDBY),        \
694                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
695                                 REGULATOR_CHANGE_STATUS |       \
696                                 REGULATOR_CHANGE_VOLTAGE),      \
697                 .always_on = _always_on,                        \
698                 .boot_on = _boot_on,                            \
699         },                                                      \
700 };                                                              \
701 static struct fixed_voltage_config fixed_reg_en_##_var##_pdata =        \
702 {                                                               \
703         .supply_name = FIXED_SUPPLY(_name),                     \
704         .microvolts = _millivolts * 1000,                       \
705         .gpio = _gpio_nr,                                       \
706         .gpio_is_open_drain = _open_drain,                      \
707         .enable_high = _active_high,                            \
708         .enabled_at_boot = _boot_state,                         \
709         .init_data = &ri_data_##_var,                           \
710         .startup_delay = _sdelay                                \
711 };                                                              \
712 static struct platform_device fixed_reg_en_##_var##_dev = {     \
713         .name = "reg-fixed-voltage",                            \
714         .id = _id,                                              \
715         .dev = {                                                \
716                 .platform_data = &fixed_reg_en_##_var##_pdata,  \
717         },                                                      \
718 }
719
720 /* Always ON Battery regulator */
721 static struct regulator_consumer_supply fixed_reg_en_battery_ardbeg_supply[] = {
722                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
723 };
724
725 static struct regulator_consumer_supply fixed_reg_en_usb0_vbus_supply[] = {
726         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
727         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
728         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
729 };
730
731 static struct regulator_consumer_supply fixed_reg_en_usb1_vbus_supply[] = {
732         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
733         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
734 };
735
736 static struct regulator_consumer_supply fixed_reg_en_usb2_vbus_supply[] = {
737         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
738         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
739 };
740
741 static struct regulator_consumer_supply fixed_reg_en_vdd_sd_supply[] = {
742         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
743 };
744
745 static struct regulator_consumer_supply fixed_reg_en_vdd_sys_5v0_supply[] = {
746         REGULATOR_SUPPLY("vdd_spk_5v0", NULL),
747         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
748         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
749 };
750
751 static struct regulator_consumer_supply fixed_reg_en_dcdc_1v8_supply[] = {
752         REGULATOR_SUPPLY("avdd_lvds0_pll", NULL),
753         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
754 };
755
756 static struct regulator_consumer_supply fixed_reg_en_lcd_bl_en_supply[] = {
757         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
758 };
759
760 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
761         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
762 };
763
764 #define fixed_reg_en_as3722_gpio2_supply palmas_ti913_regen1_supply
765
766 static struct regulator_consumer_supply fixed_reg_en_as3722_gpio4_supply[] = {
767         REGULATOR_SUPPLY("avdd_lcd", NULL),
768 };
769
770 static struct regulator_consumer_supply fixed_reg_en_tca6408_p2_supply[] = {
771         REGULATOR_SUPPLY("ldoen", "tegra-snd-rt5639.0"),
772 };
773
774 static struct regulator_consumer_supply fixed_reg_en_as3722_gpio1_supply[] = {
775         REGULATOR_SUPPLY("vdd_wwan_mdm", NULL),
776 };
777
778 static struct regulator_consumer_supply fixed_reg_en_tca6408_p6_supply[] = {
779         REGULATOR_SUPPLY("dvdd_lcd", NULL),
780         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
781 };
782
783 static struct regulator_consumer_supply fixed_reg_en_tca6408_p0_supply[] = {
784         REGULATOR_SUPPLY("vdd_lcd_1v2_s", NULL),
785 };
786
787 static struct regulator_consumer_supply fixed_reg_en_vdd_cpu_fixed_supply[] = {
788         REGULATOR_SUPPLY("vdd_cpu_fixed", NULL),
789 };
790
791 static struct regulator_consumer_supply fixed_reg_en_avdd_3v3_dp_supply[] = {
792         REGULATOR_SUPPLY("avdd_3v3_dp", NULL),
793 };
794
795 #define fixed_reg_en_ti913_gpio2_supply fixed_reg_en_as3722_gpio1_supply
796 #define fixed_reg_en_ti913_gpio3_supply fixed_reg_en_as3722_gpio4_supply
797 #define fixed_reg_en_ti913_gpio4_supply fixed_reg_en_tca6408_p0_supply
798 #define fixed_reg_en_ti913_gpio6_supply fixed_reg_en_tca6408_p2_supply
799 #define fixed_reg_en_ti913_gpio7_supply fixed_reg_en_tca6408_p6_supply
800
801 FIXED_REG(0,    battery_ardbeg, battery_ardbeg,
802         NULL,   0,      0,      -1,
803         false,  true,   0,      3300, 0);
804
805 FIXED_REG(1,    usb0_vbus,      usb0_vbus,
806         NULL,   0,      0,      TEGRA_GPIO_PN4,
807         true,   true,   0,      5000,   0);
808
809 FIXED_REG(2,    usb1_vbus,      usb1_vbus,
810         NULL,   0,      0,      TEGRA_GPIO_PN5,
811         true,   true,   0,      5000,   0);
812
813 FIXED_REG(3,    usb2_vbus,      usb2_vbus,
814         NULL,   0,      0,      TEGRA_GPIO_PFF1,
815         true,   true,   0,      5000,   0);
816
817 FIXED_REG(4,    vdd_sd, vdd_sd,
818         NULL,   0,      0,      TEGRA_GPIO_PR0,
819         false,  true,   0,      3300,   0);
820
821 FIXED_REG(5,    vdd_sys_5v0,    vdd_sys_5v0,
822         NULL,   0,      0,      -1,
823         false,  true,   0,      5000, 0);
824
825 FIXED_REG(6,    dcdc_1v8,       dcdc_1v8,
826         NULL,   0,      0,      -1,
827         false,  true,   0,      1800, 0);
828
829 FIXED_REG(7,    lcd_bl_en,      lcd_bl_en,
830         NULL,   0,      0, TEGRA_GPIO_PH2,
831         false,  true,   0,      5000,   0);
832
833 /* EN for LDO1/6/9/10 So keep always_ON */
834 FIXED_REG(8,    as3722_gpio2,   as3722_gpio2,
835         NULL,   1,      1, AS3722_GPIO_BASE + AS3722_GPIO2,
836         false,  true,   0,      3300, 0);
837
838 FIXED_REG(9,    as3722_gpio4,   as3722_gpio4,
839         NULL,   0,      0, AS3722_GPIO_BASE + AS3722_GPIO4,
840         false,  true,   0,      3300,   0);
841
842 FIXED_REG(10,   as3722_gpio1,   as3722_gpio1,
843         NULL,   0,      0,      AS3722_GPIO_BASE + AS3722_GPIO1,
844         false,  true,   0,      3300,   0);
845
846 FIXED_REG(11,   tca6408_p2,     tca6408_p2,
847         AS3722_SUPPLY(sd5),     0,      0,      PMU_TCA6416_GPIO(2),
848         false,  true,   0,      1200, 0);
849
850 FIXED_REG(12,   vdd_hdmi_5v0,   vdd_hdmi_5v0,
851         NULL,   0,      0,
852         TEGRA_GPIO_PK6, false,  true,   0,      5000,   5000);
853
854 FIXED_REG(13,   tca6408_p6,     tca6408_p6,
855         AS3722_SUPPLY(sd5),     0,      0,      PMU_TCA6416_GPIO(6),
856         false,  true,   0,      1800, 0);
857
858 FIXED_REG(14,   tca6408_p0,     tca6408_p0,
859         AS3722_SUPPLY(sd5),     0,      0,      PMU_TCA6416_GPIO(0),
860         false,  true,   0,      1200, 0);
861
862 FIXED_REG(15,   ti913_gpio2,    ti913_gpio2,
863         NULL,   1,      1,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,
864         false,  true,   0,      3300, 0);
865
866 FIXED_REG(16,   ti913_gpio3,    ti913_gpio3,
867         NULL,   0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO3,
868         false,  true,   0,      3300,   0);
869
870 FIXED_REG(17,   ti913_gpio4,    ti913_gpio4,
871         NULL,   0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,
872         false,  true,   0,      1200,   0);
873
874 FIXED_REG(18,   ti913_gpio6,    ti913_gpio6,
875         NULL,   0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,
876         false,  true,   0,      1200,   0);
877
878 FIXED_REG(19,   ti913_gpio7,    ti913_gpio7,
879         NULL,   0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO7,
880         false,  true,   0,      1800,   0);
881
882 FIXED_REG(20,   vdd_cpu_fixed,  vdd_cpu_fixed,
883         NULL,   0,      1,      -1,
884         false,  true,   0,      1000,   0);
885
886 FIXED_REG(21,   avdd_3v3_dp,    avdd_3v3_dp,
887         NULL,   0,      0,      TEGRA_GPIO_PH3,
888         false,  true,   0,      3300,   0);
889
890 /*
891  * Creating fixed regulator device tables
892  */
893 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
894 #define ARDBEG_COMMON_FIXED_REG \
895         ADD_FIXED_REG(battery_ardbeg),          \
896         ADD_FIXED_REG(vdd_hdmi_5v0),            \
897         ADD_FIXED_REG(usb0_vbus),               \
898         ADD_FIXED_REG(usb1_vbus),               \
899         ADD_FIXED_REG(usb2_vbus),               \
900         ADD_FIXED_REG(lcd_bl_en),               \
901         ADD_FIXED_REG(dcdc_1v8),                \
902         ADD_FIXED_REG(vdd_sys_5v0),             \
903         ADD_FIXED_REG(vdd_sd),
904
905 #define ARDBEG_E1733_FIXED_REG                  \
906         ADD_FIXED_REG(as3722_gpio2),            \
907         ADD_FIXED_REG(as3722_gpio4),            \
908         ADD_FIXED_REG(as3722_gpio1),            \
909         ADD_FIXED_REG(tca6408_p2),              \
910         ADD_FIXED_REG(tca6408_p6),              \
911         ADD_FIXED_REG(tca6408_p0),
912
913 #define ARDBEG_E1735_FIXED_REG                  \
914         ADD_FIXED_REG(ti913_gpio2),             \
915         ADD_FIXED_REG(ti913_gpio3),             \
916         ADD_FIXED_REG(ti913_gpio4),             \
917         ADD_FIXED_REG(ti913_gpio6),             \
918         ADD_FIXED_REG(ti913_gpio7),             \
919         ADD_FIXED_REG(vdd_cpu_fixed),
920
921 #define ARDBEG_E1824_FIXED_REG                  \
922         ADD_FIXED_REG(avdd_3v3_dp),
923
924 static struct platform_device *fixed_reg_devs_e1733[] = {
925         ARDBEG_COMMON_FIXED_REG
926         ARDBEG_E1733_FIXED_REG
927 };
928
929 static struct platform_device *fixed_reg_devs_e1735[] = {
930         ARDBEG_COMMON_FIXED_REG
931         ARDBEG_E1735_FIXED_REG
932 };
933
934 static struct platform_device *fixed_reg_devs_e1824[] = {
935         ARDBEG_E1824_FIXED_REG
936 };
937
938 /************************ ARDBEG CL-DVFS DATA *********************/
939 #define E1735_CPU_VDD_MAP_SIZE          33
940 #define E1735_CPU_VDD_MIN_UV            675000
941 #define E1735_CPU_VDD_STEP_UV           18750
942 #define E1735_CPU_VDD_STEP_US           80
943 #define E1735_CPU_VDD_IDLE_MA           5000
944 #define ARDBEG_DEFAULT_CVB_ALIGNMENT    10000
945
946 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
947 /* E1735 board parameters for cpu dfll */
948 static struct tegra_cl_dvfs_cfg_param e1735_cl_dvfs_param = {
949         .sample_rate = 50000,
950
951         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
952         .cf = 10,
953         .ci = 0,
954         .cg = 2,
955
956         .droop_cut_value = 0xF,
957         .droop_restore_ramp = 0x0,
958         .scale_out_ramp = 0x0,
959 };
960
961 /* E1735 RT8812C volatge map */
962 static struct voltage_reg_map e1735_cpu_vdd_map[E1735_CPU_VDD_MAP_SIZE];
963 static inline int e1735_fill_reg_map(int nominal_mv)
964 {
965         int i, uv, nominal_uv = 0;
966         for (i = 0; i < E1735_CPU_VDD_MAP_SIZE; i++) {
967                 e1735_cpu_vdd_map[i].reg_value = i;
968                 e1735_cpu_vdd_map[i].reg_uV = uv =
969                         E1735_CPU_VDD_MIN_UV + E1735_CPU_VDD_STEP_UV * i;
970                 if (!nominal_uv && uv >= nominal_mv * 1000)
971                         nominal_uv = uv;
972         }
973         return nominal_uv;
974 }
975
976 /* E1735 dfll bypass device for legacy dvfs control */
977 static struct regulator_consumer_supply e1735_dfll_bypass_consumers[] = {
978         REGULATOR_SUPPLY("vdd_cpu", NULL),
979 };
980 DFLL_BYPASS(e1735, E1735_CPU_VDD_MIN_UV, E1735_CPU_VDD_STEP_UV,
981             E1735_CPU_VDD_MAP_SIZE, E1735_CPU_VDD_STEP_US, TEGRA_GPIO_PX2);
982
983 static struct tegra_cl_dvfs_platform_data e1735_cl_dvfs_data = {
984         .dfll_clk_name = "dfll_cpu",
985         .pmu_if = TEGRA_CL_DVFS_PMU_PWM,
986         .u.pmu_pwm = {
987                 .pwm_rate = 12750000,
988                 .pwm_pingroup = TEGRA_PINGROUP_DVFS_PWM,
989                 .out_gpio = TEGRA_GPIO_PS5,
990                 .out_enable_high = false,
991 #ifdef CONFIG_REGULATOR_TEGRA_DFLL_BYPASS
992                 .dfll_bypass_dev = &e1735_dfll_bypass_dev,
993 #endif
994         },
995         .vdd_map = e1735_cpu_vdd_map,
996         .vdd_map_size = E1735_CPU_VDD_MAP_SIZE,
997
998         .cfg_param = &e1735_cl_dvfs_param,
999 };
1000
1001 static void e1735_suspend_dfll_bypass(void)
1002 {
1003         __gpio_set_value(TEGRA_GPIO_PS5, 1); /* tristate external PWM buffer */
1004 }
1005
1006 static void e1735_resume_dfll_bypass(void)
1007 {
1008         __gpio_set_value(TEGRA_GPIO_PS5, 0); /* enable PWM buffer operations */
1009 }
1010
1011 static void e1767_suspend_dfll_bypass(void)
1012 {
1013         tegra_pinmux_set_tristate(TEGRA_PINGROUP_DVFS_PWM, TEGRA_TRI_TRISTATE);
1014 }
1015
1016 static void e1767_resume_dfll_bypass(void)
1017 {
1018          tegra_pinmux_set_tristate(TEGRA_PINGROUP_DVFS_PWM, TEGRA_TRI_NORMAL);
1019 }
1020
1021 static struct tegra_cl_dvfs_cfg_param e1733_ardbeg_cl_dvfs_param = {
1022         .sample_rate = 12500,
1023
1024         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
1025         .cf = 10,
1026         .ci = 0,
1027         .cg = 2,
1028
1029         .droop_cut_value = 0xF,
1030         .droop_restore_ramp = 0x0,
1031         .scale_out_ramp = 0x0,
1032 };
1033
1034 /* E1733 volatge map. Fixed 10mv steps from 700mv to 1400mv */
1035 #define E1733_CPU_VDD_MAP_SIZE ((1400000 - 700000) / 10000 + 1)
1036 static struct voltage_reg_map e1733_cpu_vdd_map[E1733_CPU_VDD_MAP_SIZE];
1037 static inline void e1733_fill_reg_map(void)
1038 {
1039         int i;
1040         for (i = 0; i < E1733_CPU_VDD_MAP_SIZE; i++) {
1041                 e1733_cpu_vdd_map[i].reg_value = i + 0xa;
1042                 e1733_cpu_vdd_map[i].reg_uV = 700000 + 10000 * i;
1043         }
1044 }
1045
1046 static struct tegra_cl_dvfs_platform_data e1733_cl_dvfs_data = {
1047         .dfll_clk_name = "dfll_cpu",
1048         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
1049         .u.pmu_i2c = {
1050                 .fs_rate = 400000,
1051                 .slave_addr = 0x80,
1052                 .reg = 0x00,
1053         },
1054         .vdd_map = e1733_cpu_vdd_map,
1055         .vdd_map_size = E1733_CPU_VDD_MAP_SIZE,
1056
1057         .cfg_param = &e1733_ardbeg_cl_dvfs_param,
1058 };
1059
1060 static struct tegra_cl_dvfs_cfg_param e1736_ardbeg_cl_dvfs_param = {
1061         .sample_rate = 12500, /* i2c freq */
1062
1063         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
1064         .cf = 10,
1065         .ci = 0,
1066         .cg = 2,
1067
1068         .droop_cut_value = 0xF,
1069         .droop_restore_ramp = 0x0,
1070         .scale_out_ramp = 0x0,
1071 };
1072
1073 /* E1736 volatge map. Fixed 10mv steps from 700mv to 1400mv */
1074 #define E1736_CPU_VDD_MAP_SIZE ((1400000 - 700000) / 10000 + 1)
1075 static struct voltage_reg_map e1736_cpu_vdd_map[E1736_CPU_VDD_MAP_SIZE];
1076 static inline void e1736_fill_reg_map(void)
1077 {
1078         int i;
1079         for (i = 0; i < E1736_CPU_VDD_MAP_SIZE; i++) {
1080                 /* 0.7V corresponds to 0b0011010 = 26 */
1081                 /* 1.4V corresponds to 0b1100000 = 96 */
1082                 e1736_cpu_vdd_map[i].reg_value = i + 26;
1083                 e1736_cpu_vdd_map[i].reg_uV = 700000 + 10000 * i;
1084         }
1085 }
1086
1087 static struct tegra_cl_dvfs_platform_data e1736_cl_dvfs_data = {
1088         .dfll_clk_name = "dfll_cpu",
1089         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
1090         .u.pmu_i2c = {
1091                 .fs_rate = 400000,
1092                 .slave_addr = 0xb0, /* pmu i2c address */
1093                 .reg = 0x23,        /* vdd_cpu rail reg address */
1094         },
1095         .vdd_map = e1736_cpu_vdd_map,
1096         .vdd_map_size = E1736_CPU_VDD_MAP_SIZE,
1097
1098         .cfg_param = &e1736_ardbeg_cl_dvfs_param,
1099 };
1100 static int __init ardbeg_cl_dvfs_init(struct board_info *pmu_board_info)
1101 {
1102         u16 pmu_board_id = pmu_board_info->board_id;
1103         struct tegra_cl_dvfs_platform_data *data = NULL;
1104         int v = tegra_dvfs_rail_get_nominal_millivolts(tegra_cpu_rail);
1105
1106         if (pmu_board_id == BOARD_E1735) {
1107                 bool e1767 = pmu_board_info->sku == E1735_EMULATE_E1767_SKU;
1108                 v = e1735_fill_reg_map(v);
1109                 data = &e1735_cl_dvfs_data;
1110
1111                 data->u.pmu_pwm.pwm_bus = e1767 ?
1112                         TEGRA_CL_DVFS_PWM_1WIRE_DIRECT :
1113                         TEGRA_CL_DVFS_PWM_1WIRE_BUFFER;
1114
1115                 if (data->u.pmu_pwm.dfll_bypass_dev) {
1116                         /* this has to be exact to 1uV level from table */
1117                         e1735_dfll_bypass_init_data.constraints.init_uV = v;
1118                         ardbeg_suspend_data.suspend_dfll_bypass = e1767 ?
1119                                 e1767_suspend_dfll_bypass :
1120                                 e1735_suspend_dfll_bypass;
1121                         ardbeg_suspend_data.resume_dfll_bypass = e1767 ?
1122                                 e1767_resume_dfll_bypass :
1123                                 e1735_resume_dfll_bypass;
1124                         tegra_init_cpu_reg_mode_limits(E1735_CPU_VDD_IDLE_MA,
1125                                                        REGULATOR_MODE_IDLE);
1126                 } else {
1127                         (void)e1735_dfll_bypass_dev;
1128                 }
1129         }
1130
1131
1132         if (pmu_board_id == BOARD_E1733) {
1133                 e1733_fill_reg_map();
1134                 data = &e1733_cl_dvfs_data;
1135         }
1136
1137         if (pmu_board_id == BOARD_E1736 ||
1138                 pmu_board_id == BOARD_E1769) {
1139                 e1736_fill_reg_map();
1140                 data = &e1736_cl_dvfs_data;
1141         }
1142
1143         if (data) {
1144                 data->flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
1145                 tegra_cl_dvfs_device.dev.platform_data = data;
1146                 platform_device_register(&tegra_cl_dvfs_device);
1147         }
1148         return 0;
1149 }
1150 #else
1151 static inline int ardbeg_cl_dvfs_init(struct board_info *pmu_board_info)
1152 { return 0; }
1153 #endif
1154
1155 int __init ardbeg_rail_alignment_init(void)
1156 {
1157         struct board_info pmu_board_info;
1158
1159         tegra_get_pmu_board_info(&pmu_board_info);
1160
1161         if (pmu_board_info.board_id == BOARD_E1735)
1162                 tegra12x_vdd_cpu_align(E1735_CPU_VDD_STEP_UV,
1163                                        E1735_CPU_VDD_MIN_UV);
1164         else
1165                 tegra12x_vdd_cpu_align(ARDBEG_DEFAULT_CVB_ALIGNMENT, 0);
1166         return 0;
1167 }
1168
1169 int __init ardbeg_regulator_init(void)
1170 {
1171         struct board_info pmu_board_info;
1172
1173         tegra_get_pmu_board_info(&pmu_board_info);
1174
1175         if ((pmu_board_info.board_id == BOARD_E1733) ||
1176                 (pmu_board_info.board_id == BOARD_E1734)) {
1177                 i2c_register_board_info(0, tca6408_expander,
1178                                 ARRAY_SIZE(tca6408_expander));
1179                 ardbeg_ams_regulator_init();
1180                 regulator_has_full_constraints();
1181         } else if (pmu_board_info.board_id == BOARD_E1735) {
1182                 regulator_has_full_constraints();
1183                 ardbeg_tps65913_regulator_init();
1184         } else if (pmu_board_info.board_id == BOARD_E1736 ||
1185                 pmu_board_info.board_id == BOARD_E1769) {
1186                 tn8_regulator_init();
1187                 ardbeg_cl_dvfs_init(&pmu_board_info);
1188                 return tn8_fixed_regulator_init();
1189         } else {
1190                 pr_warn("PMU board id 0x%04x is not supported\n",
1191                         pmu_board_info.board_id);
1192         }
1193
1194         if (get_power_supply_type() == POWER_SUPPLY_TYPE_BATTERY) {
1195                 i2c_register_board_info(1, bq2471x_boardinfo,
1196                         ARRAY_SIZE(bq2471x_boardinfo));
1197                 i2c_register_board_info(1, bq2477x_boardinfo,
1198                         ARRAY_SIZE(bq2477x_boardinfo));
1199         }
1200
1201         platform_device_register(&power_supply_extcon_device);
1202
1203         ardbeg_cl_dvfs_init(&pmu_board_info);
1204         return 0;
1205 }
1206
1207 static int __init ardbeg_fixed_regulator_init(void)
1208 {
1209         struct board_info pmu_board_info;
1210         struct board_info display_board_info;
1211
1212         if (!of_machine_is_compatible("nvidia,ardbeg"))
1213                 return 0;
1214
1215         tegra_get_display_board_info(&display_board_info);
1216
1217         if (display_board_info.board_id == BOARD_E1824)
1218                 platform_add_devices(fixed_reg_devs_e1824,
1219                         ARRAY_SIZE(fixed_reg_devs_e1824));
1220
1221         tegra_get_pmu_board_info(&pmu_board_info);
1222
1223         if (pmu_board_info.board_id == BOARD_E1733)
1224                 return platform_add_devices(fixed_reg_devs_e1733,
1225                         ARRAY_SIZE(fixed_reg_devs_e1733));
1226         else if (pmu_board_info.board_id == BOARD_E1735)
1227                 return platform_add_devices(fixed_reg_devs_e1735,
1228                         ARRAY_SIZE(fixed_reg_devs_e1735));
1229         else if (pmu_board_info.board_id == BOARD_E1736)
1230                 return 0;
1231         else
1232                 pr_warn("The PMU board id 0x%04x is not supported\n",
1233                         pmu_board_info.board_id);
1234
1235         return 0;
1236 }
1237
1238 subsys_initcall_sync(ardbeg_fixed_regulator_init);
1239
1240 int __init ardbeg_edp_init(void)
1241 {
1242         unsigned int regulator_mA;
1243
1244         regulator_mA = get_maximum_cpu_current_supported();
1245         if (!regulator_mA)
1246                 regulator_mA = 14000;
1247
1248         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1249         tegra_init_cpu_edp_limits(regulator_mA);
1250
1251         /* gpu maximum current */
1252         regulator_mA = 12000;
1253         pr_info("%s: GPU regulator %d mA\n", __func__, regulator_mA);
1254
1255         tegra_init_gpu_edp_limits(regulator_mA);
1256         return 0;
1257 }
1258
1259
1260 static struct pid_thermal_gov_params soctherm_pid_params = {
1261         .max_err_temp = 9000,
1262         .max_err_gain = 1000,
1263
1264         .gain_p = 1000,
1265         .gain_d = 0,
1266
1267         .up_compensation = 20,
1268         .down_compensation = 20,
1269 };
1270
1271 static struct thermal_zone_params soctherm_tzp = {
1272         .governor_name = "pid_thermal_gov",
1273         .governor_params = &soctherm_pid_params,
1274 };
1275
1276 static struct tegra_tsensor_pmu_data tpdata_palmas = {
1277         .reset_tegra = 1,
1278         .pmu_16bit_ops = 0,
1279         .controller_type = 0,
1280         .pmu_i2c_addr = 0x58,
1281         .i2c_controller_id = 4,
1282         .poweroff_reg_addr = 0xa0,
1283         .poweroff_reg_data = 0x0,
1284 };
1285
1286 static struct tegra_tsensor_pmu_data tpdata_as3722 = {
1287         .reset_tegra = 1,
1288         .pmu_16bit_ops = 0,
1289         .controller_type = 0,
1290         .pmu_i2c_addr = 0x40,
1291         .i2c_controller_id = 4,
1292         .poweroff_reg_addr = 0x36,
1293         .poweroff_reg_data = 0x2,
1294 };
1295
1296 static struct soctherm_platform_data ardbeg_soctherm_data = {
1297         .therm = {
1298                 [THERM_CPU] = {
1299                         .zone_enable = true,
1300                         .passive_delay = 1000,
1301                         .hotspot_offset = 6000,
1302                         .num_trips = 3,
1303                         .trips = {
1304                                 {
1305                                         .cdev_type = "tegra-shutdown",
1306                                         .trip_temp = 101000,
1307                                         .trip_type = THERMAL_TRIP_CRITICAL,
1308                                         .upper = THERMAL_NO_LIMIT,
1309                                         .lower = THERMAL_NO_LIMIT,
1310                                 },
1311                                 {
1312                                         .cdev_type = "tegra-heavy",
1313                                         .trip_temp = 99000,
1314                                         .trip_type = THERMAL_TRIP_HOT,
1315                                         .upper = THERMAL_NO_LIMIT,
1316                                         .lower = THERMAL_NO_LIMIT,
1317                                 },
1318                                 {
1319                                         .cdev_type = "cpu-balanced",
1320                                         .trip_temp = 89000,
1321                                         .trip_type = THERMAL_TRIP_PASSIVE,
1322                                         .upper = THERMAL_NO_LIMIT,
1323                                         .lower = THERMAL_NO_LIMIT,
1324                                 },
1325                         },
1326                         .tzp = &soctherm_tzp,
1327                 },
1328                 [THERM_GPU] = {
1329                         .zone_enable = true,
1330                         .passive_delay = 1000,
1331                         .hotspot_offset = 6000,
1332                         .num_trips = 2,
1333                         .trips = {
1334                                 {
1335                                         .cdev_type = "tegra-shutdown",
1336                                         .trip_temp = 103000,
1337                                         .trip_type = THERMAL_TRIP_CRITICAL,
1338                                         .upper = THERMAL_NO_LIMIT,
1339                                         .lower = THERMAL_NO_LIMIT,
1340                                 },
1341                                 {
1342                                         .cdev_type = "gpu-balanced",
1343                                         .trip_temp = 91000,
1344                                         .trip_type = THERMAL_TRIP_PASSIVE,
1345                                         .upper = THERMAL_NO_LIMIT,
1346                                         .lower = THERMAL_NO_LIMIT,
1347                                 },
1348 /*
1349                                 {
1350                                         .cdev_type = "gk20a_cdev",
1351                                         .trip_temp = 101000,
1352                                         .trip_type = THERMAL_TRIP_PASSIVE,
1353                                         .upper = THERMAL_NO_LIMIT,
1354                                         .lower = THERMAL_NO_LIMIT,
1355                                 },
1356                                 {
1357                                         .cdev_type = "tegra-heavy",
1358                                         .trip_temp = 101000,
1359                                         .trip_type = THERMAL_TRIP_HOT,
1360                                         .upper = THERMAL_NO_LIMIT,
1361                                         .lower = THERMAL_NO_LIMIT,
1362                                 },
1363 */
1364                         },
1365                         .tzp = &soctherm_tzp,
1366                 },
1367                 [THERM_MEM] = {
1368                         .zone_enable = true,
1369                         .num_trips = 1,
1370                         .trips = {
1371                                 {
1372                                         .cdev_type = "tegra-shutdown",
1373                                         .trip_temp = 103000, /* = GPU shut */
1374                                         .trip_type = THERMAL_TRIP_CRITICAL,
1375                                         .upper = THERMAL_NO_LIMIT,
1376                                         .lower = THERMAL_NO_LIMIT,
1377                                 },
1378                         },
1379                 },
1380                 [THERM_PLL] = {
1381                         .zone_enable = true,
1382                 },
1383         },
1384         .throttle = {
1385                 [THROTTLE_HEAVY] = {
1386                         .priority = 100,
1387                         .devs = {
1388                                 [THROTTLE_DEV_CPU] = {
1389                                         .enable = true,
1390                                         .depth = 80,
1391                                 },
1392                                 [THROTTLE_DEV_GPU] = {
1393                                         .enable = false,
1394                                         .throttling_depth = "heavy_throttling",
1395                                 },
1396                         },
1397                 },
1398         },
1399         .tshut_pmu_trip_data = &tpdata_palmas,
1400 };
1401
1402 int __init ardbeg_soctherm_init(void)
1403 {
1404         s32 base_cp, shft_cp;
1405         u32 base_ft, shft_ft;
1406         struct board_info pmu_board_info;
1407
1408         /* do this only for supported CP,FT fuses */
1409         if ((tegra_fuse_calib_base_get_cp(&base_cp, &shft_cp) >= 0) &&
1410             (tegra_fuse_calib_base_get_ft(&base_ft, &shft_ft) >= 0)) {
1411                 tegra_platform_edp_init(
1412                         ardbeg_soctherm_data.therm[THERM_CPU].trips,
1413                         &ardbeg_soctherm_data.therm[THERM_CPU].num_trips,
1414                         8000); /* edp temperature margin */
1415                 tegra_platform_gpu_edp_init(
1416                         ardbeg_soctherm_data.therm[THERM_GPU].trips,
1417                         &ardbeg_soctherm_data.therm[THERM_GPU].num_trips,
1418                         8000);
1419                 tegra_add_tj_trips(
1420                         ardbeg_soctherm_data.therm[THERM_CPU].trips,
1421                         &ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
1422                 tegra_add_tgpu_trips(
1423                         ardbeg_soctherm_data.therm[THERM_GPU].trips,
1424                         &ardbeg_soctherm_data.therm[THERM_GPU].num_trips);
1425                 tegra_add_vc_trips(
1426                         ardbeg_soctherm_data.therm[THERM_CPU].trips,
1427                         &ardbeg_soctherm_data.therm[THERM_CPU].num_trips);
1428         }
1429
1430         tegra_get_pmu_board_info(&pmu_board_info);
1431
1432         if ((pmu_board_info.board_id == BOARD_E1733) ||
1433                 (pmu_board_info.board_id == BOARD_E1734))
1434                 ardbeg_soctherm_data.tshut_pmu_trip_data = &tpdata_as3722;
1435         else if (pmu_board_info.board_id == BOARD_E1735 ||
1436                  pmu_board_info.board_id == BOARD_E1736 ||
1437                  pmu_board_info.board_id == BOARD_E1769)
1438                 ;/* tpdata_palmas is default */
1439         else
1440                 pr_warn("soctherm THERMTRIP is not supported on this PMIC\n");
1441
1442         return tegra11_soctherm_init(&ardbeg_soctherm_data);
1443 }