arch: arm: tegra: ardbeg: Support Raydium Touch
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-power.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-power.c
3  *
4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/resource.h>
23 #include <linux/io.h>
24 #include <mach/irqs.h>
25 #include <mach/hardware.h>
26 #include <linux/regulator/fixed.h>
27 #include <linux/mfd/palmas.h>
28 #include <linux/regulator/tps51632-regulator.h>
29 #include <linux/regulator/machine.h>
30 #include <linux/irq.h>
31
32 #include <asm/mach-types.h>
33
34 #include "pm.h"
35 #include "board.h"
36 #include "board-common.h"
37 #include "board-ardbeg.h"
38 #include "board-pmu-defines.h"
39 #include "devices.h"
40 #include "iomap.h"
41
42 #define PMC_CTRL                0x0
43 #define PMC_CTRL_INTR_LOW       (1 << 17)
44
45
46 /************************ ARDBEG based regulator *****************/
47 static struct regulator_consumer_supply palmas_smps12_supply[] = {
48         REGULATOR_SUPPLY("vdd_core", NULL),
49 };
50
51 static struct regulator_consumer_supply palmas_smps3_supply[] = {
52         REGULATOR_SUPPLY("vdd_modem", NULL),
53 };
54
55 static struct regulator_consumer_supply palmas_smps6_supply[] = {
56         REGULATOR_SUPPLY("vddio_ddr", NULL),
57         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
58         REGULATOR_SUPPLY("vddio_ddr3", NULL),
59         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
60 };
61
62 static struct regulator_consumer_supply palmas_smps8_supply[] = {
63         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
64         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
65         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
66         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
67         REGULATOR_SUPPLY("avdd_pll_m", NULL),
68         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
69         REGULATOR_SUPPLY("avdd_pll_utmip", NULL),
70         REGULATOR_SUPPLY("avdd_pll_x", NULL),
71         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"),
72         REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"),
73 };
74
75 static struct regulator_consumer_supply palmas_smps9_supply[] = {
76         REGULATOR_SUPPLY("vdd_aud_dgtl", NULL),
77         REGULATOR_SUPPLY("vdd_aud_anlg", NULL),
78         REGULATOR_SUPPLY("vdd_aud_mic", NULL),
79         REGULATOR_SUPPLY("avdd_osc", NULL),
80         REGULATOR_SUPPLY("vddio_sys", NULL),
81         REGULATOR_SUPPLY("vddio_sys_2", NULL),
82         REGULATOR_SUPPLY("vddio_gmi", NULL),
83         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
84         REGULATOR_SUPPLY("vdd_1v8b_pll_utmip", NULL),
85         REGULATOR_SUPPLY("vddio_cam", "vi"),
86         REGULATOR_SUPPLY("vddio_audio", NULL),
87         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
88         REGULATOR_SUPPLY("vddio_uart", NULL),
89         REGULATOR_SUPPLY("vddio_bb", NULL),
90         REGULATOR_SUPPLY("vdd_sys_mb", NULL),
91         REGULATOR_SUPPLY("vdd_gmi_mb", NULL),
92         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
93         REGULATOR_SUPPLY("vdd_1v8b_ts", NULL),
94         REGULATOR_SUPPLY("vdd_1v8b_audio_mb", NULL),
95         REGULATOR_SUPPLY("vdd_1v8b_com_f", NULL),
96         REGULATOR_SUPPLY("vdd_1v8b_gps_f", NULL),
97         REGULATOR_SUPPLY("vdd_1v8b_nfc", NULL),
98         REGULATOR_SUPPLY("vdd_1v8b_uart_mb", NULL),
99         REGULATOR_SUPPLY("vdd_1v8b", "0-0048"),
100         REGULATOR_SUPPLY("vdd_dtv", NULL),
101         REGULATOR_SUPPLY("vdd_1v8_bb_mb", NULL),
102         REGULATOR_SUPPLY("vdd_1v8_uart_mdm", NULL),
103         REGULATOR_SUPPLY("vdd_1v8_eeprom", NULL),
104         REGULATOR_SUPPLY("vdd_1v8_dbg", NULL),
105         REGULATOR_SUPPLY("vdd_1v8_pm", NULL),
106 };
107
108
109 static struct regulator_consumer_supply palmas_ldo1_supply[] = {
110         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
111 };
112
113 static struct regulator_consumer_supply palmas_ldo2_supply[] = {
114         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
115         REGULATOR_SUPPLY("avdd_hdmi", NULL),
116         REGULATOR_SUPPLY("avdd_pex_pll", NULL),
117         REGULATOR_SUPPLY("avddio_pex_pll", NULL),
118         REGULATOR_SUPPLY("dvddio_pex", NULL),
119 };
120
121 static struct regulator_consumer_supply palmas_ldo3_supply[] = {
122         REGULATOR_SUPPLY("vddio_cam_mb", NULL),
123         REGULATOR_SUPPLY("vdd_cam_1v8_cam", NULL),
124 };
125
126 static struct regulator_consumer_supply palmas_ldo4_supply[] = {
127         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
128 };
129
130 static struct regulator_consumer_supply palmas_ldo5_supply[] = {
131         REGULATOR_SUPPLY("vdd_rtc", NULL),
132 };
133
134 static struct regulator_consumer_supply palmas_ldo6_supply[] = {
135         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
136 };
137
138 static struct regulator_consumer_supply palmas_ldo7_supply[] = {
139         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
140 };
141
142 static struct regulator_consumer_supply palmas_ldo8_supply[] = {
143         REGULATOR_SUPPLY("vdd_snsr_mb", NULL),
144         REGULATOR_SUPPLY("vdd_snsr_temp", NULL),
145         REGULATOR_SUPPLY("vdd", "0-0048"),
146         REGULATOR_SUPPLY("vdd_snsr_pm", NULL),
147 };
148
149 static struct regulator_consumer_supply palmas_ldo9_supply[] = {
150         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
151         REGULATOR_SUPPLY("avdd_1v2_hsic_mdm", NULL),
152         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
153         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
154         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
155         REGULATOR_SUPPLY("avdd_1v2_hsic_com", NULL),
156         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
157 };
158
159 static struct regulator_consumer_supply palmas_ldo10_supply[] = {
160         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
161 };
162
163 static struct regulator_consumer_supply palmas_ldo11_supply[] = {
164         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
165         REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
166         REGULATOR_SUPPLY("avdd_3v3_pex", NULL),
167         REGULATOR_SUPPLY("avdd_3v3_pex_pll", NULL),
168 };
169
170 static struct regulator_consumer_supply palmas_ldo12_supply[] = {
171         REGULATOR_SUPPLY("vdd_lcd_1v8b_dis", NULL),
172         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
173         REGULATOR_SUPPLY("dvdd_lcd", NULL),
174 };
175
176 static struct regulator_consumer_supply palmas_ldo13_supply[] = {
177         REGULATOR_SUPPLY("dvdd", "spi0.0"),
178 };
179
180 static struct regulator_consumer_supply palmas_ldo14_supply[] = {
181         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
182 };
183
184 static struct regulator_consumer_supply palmas_ldoln_supply[] = {
185         REGULATOR_SUPPLY("avdd", "spi0.0"),
186 };
187
188 static struct regulator_consumer_supply palmas_ldousb_supply[] = {
189         REGULATOR_SUPPLY("vpp_fuse", NULL),
190 };
191
192 static struct regulator_consumer_supply palmas_regen1_supply[] = {
193         REGULATOR_SUPPLY("vdd_com_3v3", NULL),
194         REGULATOR_SUPPLY("vdd_gps_3v3", NULL),
195         REGULATOR_SUPPLY("vdd_nfc_3v3", NULL),
196 };
197
198 static struct regulator_consumer_supply palmas_regen2_supply[] = {
199 };
200
201 static struct regulator_consumer_supply palmas_regen4_supply[] = {
202         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
203 };
204
205 /* TPS51632 DC-DC converter */
206 static struct regulator_consumer_supply tps51632_dcdc_cpu_supply[] = {
207         REGULATOR_SUPPLY("vdd_cpu", NULL),
208 };
209
210 static struct regulator_init_data tps51632_cpu_init_data = {
211         .constraints = {                                                \
212                 .min_uV = 500000,                                       \
213                 .max_uV = 1520000,                                      \
214                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
215                                         REGULATOR_MODE_STANDBY),        \
216                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
217                                         REGULATOR_CHANGE_STATUS |       \
218                                          REGULATOR_CHANGE_CONTROL |     \
219                                         REGULATOR_CHANGE_VOLTAGE),      \
220                 .always_on = 1,                                         \
221                 .boot_on =  1,                                          \
222                 .apply_uV = 0,                                          \
223         },                                                              \
224         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_cpu_supply),  \
225         .consumer_supplies = tps51632_dcdc_cpu_supply,          \
226         .supply_regulator = palmas_rails(regen2),                       \
227 };
228
229 static struct tps51632_regulator_platform_data tps51632_pdata_cpu = {
230         .reg_init_data = &tps51632_cpu_init_data,               \
231         .enable_pwm = false,                            \
232         .max_voltage_uV = 1520000,                      \
233         .base_voltage_uV = 500000,                      \
234         .slew_rate_uv_per_us = 6000,                    \
235 };
236
237 static struct i2c_board_info tps51632_cpu_boardinfo[] = {
238         {
239                 I2C_BOARD_INFO("tps51632_cpu", 0x43),
240                 .platform_data  = &tps51632_pdata_cpu,
241         },
242 };
243
244 static struct regulator_consumer_supply tps51632_dcdc_gpu_supply[] = {
245         REGULATOR_SUPPLY("vdd_gpu", NULL),
246 };
247
248 static struct regulator_init_data tps51632_init_gpu_data = {
249         .constraints = {                                                \
250                 .min_uV = 500000,                                       \
251                 .max_uV = 1520000,                                      \
252                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |            \
253                                         REGULATOR_MODE_STANDBY),        \
254                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |              \
255                                         REGULATOR_CHANGE_STATUS |       \
256                                          REGULATOR_CHANGE_CONTROL |     \
257                                         REGULATOR_CHANGE_VOLTAGE),      \
258                 .always_on = 1,                                         \
259                 .boot_on =  1,                                          \
260                 .apply_uV = 0,                                          \
261         },                                                              \
262         .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_gpu_supply),  \
263         .consumer_supplies = tps51632_dcdc_gpu_supply,          \
264         .supply_regulator = palmas_rails(regen2),                       \
265 };
266
267 static struct tps51632_regulator_platform_data tps51632_pdata_gpu = {
268         .reg_init_data = &tps51632_init_gpu_data,               \
269         .enable_pwm = false,                            \
270         .max_voltage_uV = 1520000,                      \
271         .base_voltage_uV = 500000,                      \
272         .slew_rate_uv_per_us = 6000,                    \
273 };
274
275 static struct i2c_board_info tps51632_gpu_boardinfo[] = {
276         {
277                 I2C_BOARD_INFO("tps51632_gpu", 0x45),
278                 .platform_data  = &tps51632_pdata_gpu,
279         },
280 };
281
282 #define PALMAS_PDATA_INIT(_name, _minmv, _maxmv, _supply_reg, _always_on, \
283         _boot_on, _apply_uv)                                            \
284         static struct regulator_init_data reg_idata_##_name = {         \
285                 .constraints = {                                        \
286                         .name = palmas_rails(_name),                    \
287                         .min_uV = (_minmv)*1000,                        \
288                         .max_uV = (_maxmv)*1000,                        \
289                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
290                                         REGULATOR_MODE_STANDBY),        \
291                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
292                                         REGULATOR_CHANGE_STATUS |       \
293                                         REGULATOR_CHANGE_VOLTAGE),      \
294                         .always_on = _always_on,                        \
295                         .boot_on = _boot_on,                            \
296                         .apply_uV = _apply_uv,                          \
297                 },                                                      \
298                 .num_consumer_supplies =                                \
299                         ARRAY_SIZE(palmas_##_name##_supply),            \
300                 .consumer_supplies = palmas_##_name##_supply,           \
301                 .supply_regulator = _supply_reg,                        \
302         }
303
304 PALMAS_PDATA_INIT(smps12, 900, 1300, NULL, 0, 0, 0);
305 PALMAS_PDATA_INIT(smps3, 1000, 3300, NULL, 1, 1, 0);
306 PALMAS_PDATA_INIT(smps6, 500, 1650, NULL, 0, 0, 0);
307 PALMAS_PDATA_INIT(smps8, 1000, 3300, NULL, 0, 0, 0);
308 PALMAS_PDATA_INIT(smps9, 1800, 1800, NULL, 1, 1, 0);
309 PALMAS_PDATA_INIT(ldo1, 1050, 1050, palmas_rails(smps3), 0, 0, 1);
310 PALMAS_PDATA_INIT(ldo2, 2800, 3000, palmas_rails(smps6), 0, 0, 0);
311 PALMAS_PDATA_INIT(ldo3, 2800, 3000, NULL, 0, 0, 0);
312 PALMAS_PDATA_INIT(ldo4, 2800, 3000, palmas_rails(smps3), 0, 0, 0);
313 PALMAS_PDATA_INIT(ldo5, 1100, 1100, palmas_rails(smps6), 1, 1, 1);
314 PALMAS_PDATA_INIT(ldo6, 2700, 2700, NULL, 0, 0, 0);
315 PALMAS_PDATA_INIT(ldo7, 2800, 2800, NULL, 0, 0, 0);
316 PALMAS_PDATA_INIT(ldo8, 2800, 3000, NULL, 0, 0, 0);
317 PALMAS_PDATA_INIT(ldo9, 2800, 3000, palmas_rails(smps3), 1, 1, 0);
318 PALMAS_PDATA_INIT(ldo10, 1800, 3300, NULL, 0, 0, 0);
319 PALMAS_PDATA_INIT(ldo11, 3300, 3300, NULL, 0, 0, 0);
320 PALMAS_PDATA_INIT(ldo12, 2800, 3000, palmas_rails(smps9), 1, 1, 0);
321 PALMAS_PDATA_INIT(ldo13, 1800, 1800, palmas_rails(smps9), 1, 1, 1);
322 PALMAS_PDATA_INIT(ldo14, 2800, 3000, NULL, 0, 0, 0);
323 PALMAS_PDATA_INIT(ldoln, 3300, 3300, NULL, 1, 1, 1);
324 PALMAS_PDATA_INIT(ldousb, 2800, 3000, NULL, 0, 0, 0);
325 PALMAS_PDATA_INIT(regen1, 3300, 3300, NULL, 1, 0, 0);
326 PALMAS_PDATA_INIT(regen2, 5000, 5000, NULL, 1, 0, 0);
327 PALMAS_PDATA_INIT(regen4, 5000, 5000, NULL, 0, 0, 0);
328
329 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
330
331 static struct regulator_init_data *ardbeg_reg_data[PALMAS_NUM_REGS] = {
332         PALMAS_REG_PDATA(smps12),
333         NULL,
334         PALMAS_REG_PDATA(smps3),
335         NULL,
336         NULL,
337         PALMAS_REG_PDATA(smps6),
338         NULL,
339         PALMAS_REG_PDATA(smps8),
340         PALMAS_REG_PDATA(smps9),
341         NULL,
342         PALMAS_REG_PDATA(ldo1),
343         PALMAS_REG_PDATA(ldo2),
344         PALMAS_REG_PDATA(ldo3),
345         PALMAS_REG_PDATA(ldo4),
346         PALMAS_REG_PDATA(ldo5),
347         PALMAS_REG_PDATA(ldo6),
348         PALMAS_REG_PDATA(ldo7),
349         PALMAS_REG_PDATA(ldo8),
350         PALMAS_REG_PDATA(ldo9),
351         PALMAS_REG_PDATA(ldo10),
352         PALMAS_REG_PDATA(ldo11),
353         PALMAS_REG_PDATA(ldo12),
354         PALMAS_REG_PDATA(ldo13),
355         PALMAS_REG_PDATA(ldo14),
356         PALMAS_REG_PDATA(ldoln),
357         PALMAS_REG_PDATA(ldousb),
358         PALMAS_REG_PDATA(regen1),
359         PALMAS_REG_PDATA(regen2),
360         NULL,
361         PALMAS_REG_PDATA(regen4),
362         NULL,
363         NULL,
364         NULL,
365         NULL,
366         NULL,
367 };
368
369 #define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep,   \
370                 _tstep, _vsel)                                          \
371         static struct palmas_reg_init reg_init_data_##_name = {         \
372                 .warm_reset = _warm_reset,                              \
373                 .roof_floor =   _roof_floor,                            \
374                 .mode_sleep = _mode_sleep,              \
375                 .tstep = _tstep,                        \
376                 .vsel = _vsel,          \
377         }
378
379 PALMAS_REG_INIT(smps12, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
380 PALMAS_REG_INIT(smps123, 0, 0, 0, 0, 0);
381 PALMAS_REG_INIT(smps3, 0, 0, 0, 0, 0);
382 PALMAS_REG_INIT(smps45, 0, 0, 0, 0, 0);
383 PALMAS_REG_INIT(smps457, 0, 0, 0, 0, 0);
384 PALMAS_REG_INIT(smps6, 0, 0, 0, 0, 0);
385 PALMAS_REG_INIT(smps7, 0, 0, 0, 0, 0);
386 PALMAS_REG_INIT(smps8, 0, 0, 0, 0, 0);
387 PALMAS_REG_INIT(smps9, 0, 0, 0, 0, 0);
388 PALMAS_REG_INIT(smps10, 0, 0, 0, 0, 0);
389 PALMAS_REG_INIT(ldo1, 0, 0, 0, 0, 0);
390 PALMAS_REG_INIT(ldo2, 0, 0, 0, 0, 0);
391 PALMAS_REG_INIT(ldo3, 0, 0, 0, 0, 0);
392 PALMAS_REG_INIT(ldo4, 0, 0, 0, 0, 0);
393 PALMAS_REG_INIT(ldo5, 0, PALMAS_EXT_CONTROL_NSLEEP, 1, 0, 0);
394 PALMAS_REG_INIT(ldo6, 0, 0, 0, 0, 0);
395 PALMAS_REG_INIT(ldo7, 0, 0, 0, 0, 0);
396 PALMAS_REG_INIT(ldo8, 0, 0, 0, 0, 0);
397 PALMAS_REG_INIT(ldo9, 0, 0, 0, 0, 0);
398 PALMAS_REG_INIT(ldo10, 0, 0, 0, 0, 0);
399 PALMAS_REG_INIT(ldo11, 0, 0, 0, 0, 0);
400 PALMAS_REG_INIT(ldo12, 0, 0, 0, 0, 0);
401 PALMAS_REG_INIT(ldo13, 0, 0, 0, 0, 0);
402 PALMAS_REG_INIT(ldo14, 0, 0, 0, 0, 0);
403 PALMAS_REG_INIT(ldoln, 0, 0, 0, 0, 0);
404 PALMAS_REG_INIT(ldousb, 0, 0, 0, 0, 0);
405
406 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
407 static struct palmas_reg_init *ardbeg_reg_init[PALMAS_NUM_REGS] = {
408         PALMAS_REG_INIT_DATA(smps12),
409         PALMAS_REG_INIT_DATA(smps123),
410         PALMAS_REG_INIT_DATA(smps3),
411         PALMAS_REG_INIT_DATA(smps45),
412         PALMAS_REG_INIT_DATA(smps457),
413         PALMAS_REG_INIT_DATA(smps6),
414         PALMAS_REG_INIT_DATA(smps7),
415         PALMAS_REG_INIT_DATA(smps8),
416         PALMAS_REG_INIT_DATA(smps9),
417         PALMAS_REG_INIT_DATA(smps10),
418         PALMAS_REG_INIT_DATA(ldo1),
419         PALMAS_REG_INIT_DATA(ldo2),
420         PALMAS_REG_INIT_DATA(ldo3),
421         PALMAS_REG_INIT_DATA(ldo4),
422         PALMAS_REG_INIT_DATA(ldo5),
423         PALMAS_REG_INIT_DATA(ldo6),
424         PALMAS_REG_INIT_DATA(ldo7),
425         PALMAS_REG_INIT_DATA(ldo8),
426         PALMAS_REG_INIT_DATA(ldo9),
427         PALMAS_REG_INIT_DATA(ldo10),
428         PALMAS_REG_INIT_DATA(ldo11),
429         PALMAS_REG_INIT_DATA(ldo12),
430         PALMAS_REG_INIT_DATA(ldo13),
431         PALMAS_REG_INIT_DATA(ldo14),
432         PALMAS_REG_INIT_DATA(ldoln),
433         PALMAS_REG_INIT_DATA(ldousb),
434 };
435
436 /* Macro for defining fixed regulator sub device data */
437 #define FIXED_SUPPLY(_name) "fixed_reg_en"#_name
438 #define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,   \
439         _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts,  \
440         _sdelay)                                                        \
441         static struct regulator_init_data ri_data_##_var =              \
442         {                                                               \
443                 .supply_regulator = _in_supply,                         \
444                 .num_consumer_supplies =                                \
445                         ARRAY_SIZE(fixed_reg_en_##_name##_supply),      \
446                 .consumer_supplies = fixed_reg_en_##_name##_supply,     \
447                 .constraints = {                                        \
448                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
449                                         REGULATOR_MODE_STANDBY),        \
450                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
451                                         REGULATOR_CHANGE_STATUS |       \
452                                         REGULATOR_CHANGE_VOLTAGE),      \
453                         .always_on = _always_on,                        \
454                         .boot_on = _boot_on,                            \
455                 },                                                      \
456         };                                                              \
457         static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \
458         {                                                               \
459                 .supply_name = FIXED_SUPPLY(_name),                     \
460                 .microvolts = _millivolts * 1000,                       \
461                 .gpio = _gpio_nr,                                       \
462                 .gpio_is_open_drain = _open_drain,                      \
463                 .enable_high = _active_high,                            \
464                 .enabled_at_boot = _boot_state,                         \
465                 .init_data = &ri_data_##_var,                           \
466                 .startup_delay = _sdelay                                \
467         };                                                              \
468         static struct platform_device fixed_reg_en_##_var##_dev = {     \
469                 .name = "reg-fixed-voltage",                            \
470                 .id = _id,                                              \
471                 .dev = {                                                \
472                         .platform_data = &fixed_reg_en_##_var##_pdata,  \
473                 },                                                      \
474         }
475
476
477 /* Always ON /Battery regulator */
478 static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = {
479                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
480                 REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"),
481 };
482
483 static struct regulator_consumer_supply fixed_reg_en_vdd_cdc_1v2_aud_supply[] = {
484         REGULATOR_SUPPLY("vdd_cdc_1v2_aud", NULL),
485 };
486
487
488 static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v2_dis_supply[] = {
489         REGULATOR_SUPPLY("vdd_cdc_1v2_dis", NULL),
490 };
491
492 static struct regulator_consumer_supply fixed_reg_en_vdd_cdc_3v3a_aud_supply[] = {
493         REGULATOR_SUPPLY("vdd_cdc_3v3a_aud", NULL),
494 };
495
496 static struct regulator_consumer_supply fixed_reg_en_vdd_usb0_5v0_supply[] = {
497         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
498         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
499         REGULATOR_SUPPLY("usb_vbus", "tegra-xhci.1"),
500 };
501
502 static struct regulator_consumer_supply fixed_reg_en_vdd_dis_3v3a_sw_supply[] = {
503         REGULATOR_SUPPLY("vdd_dis_3v3_lcd", NULL),
504         REGULATOR_SUPPLY("vdd_dis_3v3_lvds", NULL),
505         REGULATOR_SUPPLY("avdd_usb", NULL),
506         REGULATOR_SUPPLY("avdd_lcd", NULL),
507 };
508
509 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
510         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
511 };
512
513 FIXED_REG(0,    battery,        battery,
514         NULL,   0,      0,
515         -1,     false, true,    0,      3300,   0);
516
517 FIXED_REG(1,    vdd_cdc_1v2_aud,        vdd_cdc_1v2_aud,
518         palmas_rails(smps3),    0,      0,
519         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO14, false, true,    0,      1200,
520         0);
521
522 FIXED_REG(2,    vdd_lcd_1v2_dis,        vdd_lcd_1v2_dis,
523         palmas_rails(smps3),    1,      1,
524         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,  false, true,    0,      1200,
525         0);
526
527 FIXED_REG(3,    vdd_cdc_3v3a_aud,       vdd_cdc_3v3a_aud,
528         NULL,   0,      0,
529         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO10, false, true,    0,      3300,
530         0);
531
532 FIXED_REG(4,    vdd_usb0_5v0,   vdd_usb0_5v0,
533         NULL,   0,      0,
534         TEGRA_GPIO_PN4, true, true,     0,      5000,
535         0);
536
537 FIXED_REG(5,    vdd_dis_3v3a_sw,        vdd_dis_3v3a_sw,
538         NULL,   1,      1,
539         PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO3,  true, true,     0,      3300,
540         0);
541
542 FIXED_REG(6,    vdd_hdmi_5v0,   vdd_hdmi_5v0,
543         NULL,   0,      0,
544         TEGRA_GPIO_PH7, true,   true,   0,      5000,   5000);
545
546 /*
547  * Creating fixed regulator device tables
548  */
549 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
550
551 #define E1780_COMMON_FIXED_REG                  \
552         ADD_FIXED_REG(battery),                 \
553         ADD_FIXED_REG(vdd_cdc_1v2_aud),         \
554         ADD_FIXED_REG(vdd_lcd_1v2_dis),         \
555         ADD_FIXED_REG(vdd_cdc_3v3a_aud),        \
556         ADD_FIXED_REG(vdd_usb0_5v0),            \
557         ADD_FIXED_REG(vdd_dis_3v3a_sw),         \
558         ADD_FIXED_REG(vdd_hdmi_5v0),
559
560 /* Gpio switch regulator platform data for ardbeg E1580 */
561 static struct platform_device *pfixed_reg_devs[] = {
562         E1780_COMMON_FIXED_REG
563 };
564
565 static struct palmas_pmic_platform_data pmic_platform = {
566         .enable_ldo8_tracking = false,
567         .disabe_ldo8_tracking_suspend = false,
568 };
569
570 static struct palmas_clk32k_init_data palmas_clk32k_idata[] = {
571         {
572                 .clk32k_id = PALMAS_CLOCK32KG,
573                 .enable = true,
574         }, {
575                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
576                 .enable = true,
577         },
578 };
579
580 static struct palmas_pinctrl_config palmas_pincfg[] = {
581         PALMAS_PINMUX(POWERGOOD, POWERGOOD, DEFAULT, DEFAULT),
582         PALMAS_PINMUX(VAC, VAC, DEFAULT, DEFAULT),
583         PALMAS_PINMUX(GPIO0, ID, DEFAULT, DEFAULT),
584         PALMAS_PINMUX(GPIO1, GPIO, DEFAULT, DEFAULT),
585         PALMAS_PINMUX(GPIO2, GPIO, DEFAULT, DEFAULT),
586         PALMAS_PINMUX(GPIO3, GPIO, DEFAULT, DEFAULT),
587         PALMAS_PINMUX(GPIO4, GPIO, DEFAULT, DEFAULT),
588         PALMAS_PINMUX(GPIO5, GPIO, DEFAULT, DEFAULT),
589         PALMAS_PINMUX(GPIO6, GPIO, DEFAULT, DEFAULT),
590         PALMAS_PINMUX(GPIO7, GPIO, DEFAULT, DEFAULT),
591         PALMAS_PINMUX(GPIO8, GPIO, DEFAULT, DEFAULT),
592         PALMAS_PINMUX(GPIO9, GPIO, DEFAULT, DEFAULT),
593         PALMAS_PINMUX(GPIO10, GPIO, DEFAULT, DEFAULT),
594         PALMAS_PINMUX(GPIO11, GPIO, DEFAULT, DEFAULT),
595         PALMAS_PINMUX(GPIO12, GPIO, DEFAULT, DEFAULT),
596         PALMAS_PINMUX(GPIO13, GPIO, DEFAULT, DEFAULT),
597         PALMAS_PINMUX(GPIO14, GPIO, DEFAULT, DEFAULT),
598         PALMAS_PINMUX(GPIO15, GPIO, DEFAULT, DEFAULT),
599 };
600
601 static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = {
602         .pincfg = palmas_pincfg,
603         .num_pinctrl = ARRAY_SIZE(palmas_pincfg),
604         .dvfs1_enable = false,
605         .dvfs2_enable = false,
606 };
607
608 static struct palmas_platform_data palmas_pdata = {
609         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
610         .irq_base = PALMAS_TEGRA_IRQ_BASE,
611         .pmic_pdata = &pmic_platform,
612         .clk32k_init_data =  palmas_clk32k_idata,
613         .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata),
614         .irq_flags = IRQ_TYPE_LEVEL_HIGH,
615         .use_power_off = true,
616         .pinctrl_pdata = &palmas_pinctrl_pdata,
617 };
618
619 static struct i2c_board_info palma_device[] = {
620         {
621                 I2C_BOARD_INFO("tps80036", 0x58),
622                 .irq            = INT_EXTERNAL_PMU,
623                 .platform_data  = &palmas_pdata,
624         },
625 };
626
627 static struct tegra_suspend_platform_data ardbeg_suspend_data = {
628         .cpu_timer      = 500,
629         .cpu_off_timer  = 300,
630         .suspend_mode   = TEGRA_SUSPEND_LP0,
631         .core_timer     = 0x157e,
632         .core_off_timer = 2000,
633         .corereq_high   = true,
634         .sysclkreq_high = true,
635         .cpu_lp2_min_residency = 1000,
636         .min_residency_crail = 20000,
637 };
638
639 int __init ardbeg_suspend_init(void)
640 {
641         tegra_init_suspend(&ardbeg_suspend_data);
642         return 0;
643 }
644
645 int __init ardbeg_regulator_init(void)
646 {
647         int i;
648         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
649         u32 pmc_ctrl;
650
651         /* configure the power management controller to trigger PMU
652          * interrupts when high */
653         pmc_ctrl = readl(pmc + PMC_CTRL);
654         writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
655
656
657         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
658                 pmic_platform.reg_data[i] = ardbeg_reg_data[i];
659                 pmic_platform.reg_init[i] = ardbeg_reg_init[i];
660         }
661
662         i2c_register_board_info(4, palma_device,
663                         ARRAY_SIZE(palma_device));
664         i2c_register_board_info(4, tps51632_cpu_boardinfo, 1);
665         i2c_register_board_info(4, tps51632_gpu_boardinfo, 1);
666         reg_init_data_ldo5.enable_tracking = true;
667         reg_init_data_ldo5.tracking_regulator = PALMAS_REG_SMPS12;
668
669         return 0;
670 }
671
672 static int __init ardbeg_fixed_regulator_init(void)
673 {
674         return platform_add_devices(pfixed_reg_devs,
675                         ARRAY_SIZE(pfixed_reg_devs));
676 }
677
678 subsys_initcall_sync(ardbeg_fixed_regulator_init);