15e1502f9b31e873eea91cdc39dc8a46130af687
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-power.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-power.c
3  *
4  * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18  */
19
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca954x.h>
22 #include <linux/i2c/pca953x.h>
23 #include <linux/platform_device.h>
24 #include <linux/resource.h>
25 #include <linux/io.h>
26 #include <mach/edp.h>
27 #include <mach/irqs.h>
28 #include <linux/edp.h>
29 #include <linux/platform_data/tegra_edp.h>
30 #include <linux/pid_thermal_gov.h>
31 #include <linux/regulator/fixed.h>
32 #include <linux/mfd/palmas.h>
33 #include <linux/mfd/as3722-reg.h>
34 #include <linux/mfd/as3722-plat.h>
35 #include <linux/power/power_supply_extcon.h>
36 #include <linux/regulator/tps51632-regulator.h>
37 #include <linux/regulator/machine.h>
38 #include <linux/irq.h>
39 #include <linux/gpio.h>
40 #include <linux/regulator/tegra-dfll-bypass-regulator.h>
41 #include <linux/power/bq2471x-charger.h>
42
43 #include <asm/mach-types.h>
44 #include <mach/tegra_fuse.h>
45
46 #include "pm.h"
47 #include "dvfs.h"
48 #include "board.h"
49 #include "tegra-board-id.h"
50 #include "board-common.h"
51 #include "board-ardbeg.h"
52 #include "board-pmu-defines.h"
53 #include "devices.h"
54 #include "iomap.h"
55 #include "tegra-board-id.h"
56 #include "tegra_cl_dvfs.h"
57 #include "tegra11_soctherm.h"
58 #include "tegra3_tsensor.h"
59
60 #define PMC_CTRL                0x0
61 #define PMC_CTRL_INTR_LOW       (1 << 17)
62
63 /************************ ARDBEG E1733 based regulators ***********/
64 static struct regulator_consumer_supply as3722_ldo0_supply[] = {
65         REGULATOR_SUPPLY("avdd_pll_m", NULL),
66         REGULATOR_SUPPLY("avdd_pll_ap_c2_c3", NULL),
67         REGULATOR_SUPPLY("avdd_pll_cud2dpd", NULL),
68         REGULATOR_SUPPLY("avdd_pll_c4", NULL),
69         REGULATOR_SUPPLY("avdd_lvds0_io", NULL),
70         REGULATOR_SUPPLY("vddio_ddr_hs", NULL),
71         REGULATOR_SUPPLY("avdd_pll_erefe", NULL),
72         REGULATOR_SUPPLY("avdd_pll_x", NULL),
73         REGULATOR_SUPPLY("avdd_pll_cg", NULL),
74 };
75
76 static struct regulator_consumer_supply as3722_ldo1_supply[] = {
77         REGULATOR_SUPPLY("vdd_cam1_1v8_cam", NULL),
78         REGULATOR_SUPPLY("vdd_cam2_1v8_cam", NULL),
79         REGULATOR_SUPPLY("vif", "2-0010"),
80         REGULATOR_SUPPLY("vif", "2-0036"),
81         REGULATOR_SUPPLY("vdd_i2c", "2-000c"),
82         REGULATOR_SUPPLY("vi2c", "2-0030"),
83
84 };
85
86 static struct regulator_consumer_supply as3722_ldo2_supply[] = {
87         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"),
88         REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"),
89         REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"),
90         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"),
91         REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"),
92         REGULATOR_SUPPLY("avdd_dsi_csi", "vi"),
93         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
94         REGULATOR_SUPPLY("avdd_hsic_com", NULL),
95         REGULATOR_SUPPLY("avdd_hsic_mdm", NULL),
96         REGULATOR_SUPPLY("vdd_lcd_bl", NULL),
97         REGULATOR_SUPPLY("vdd", "1-004c"),
98         REGULATOR_SUPPLY("vdd", "1-004d"),
99 };
100
101 static struct regulator_consumer_supply as3722_ldo3_supply[] = {
102         REGULATOR_SUPPLY("vdd_rtc", NULL),
103 };
104
105 static struct regulator_consumer_supply as3722_ldo4_supply[] = {
106         REGULATOR_SUPPLY("vdd_2v7_hv", NULL),
107         REGULATOR_SUPPLY("avdd_cam1_cam", NULL),
108         REGULATOR_SUPPLY("avdd_cam2_cam", NULL),
109         REGULATOR_SUPPLY("avdd_cam3_cam", NULL),
110         REGULATOR_SUPPLY("vana", "2-0010"),
111         REGULATOR_SUPPLY("vana", "2-0036"),
112 };
113
114 static struct regulator_consumer_supply as3722_ldo5_supply[] = {
115         REGULATOR_SUPPLY("vdd_1v2_cam", NULL),
116         REGULATOR_SUPPLY("vdig", "2-0010"),
117         REGULATOR_SUPPLY("vdig", "2-0036"),
118 };
119
120 static struct regulator_consumer_supply as3722_ldo6_supply[] = {
121         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
122         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
123 };
124
125 static struct regulator_consumer_supply as3722_ldo7_supply[] = {
126         REGULATOR_SUPPLY("vdd_cam_1v1_cam", NULL),
127         REGULATOR_SUPPLY("imx135_reg2", NULL),
128 };
129
130 static struct regulator_consumer_supply as3722_ldo9_supply[] = {
131         REGULATOR_SUPPLY("avdd", "spi0.0"),
132 };
133
134 static struct regulator_consumer_supply as3722_ldo10_supply[] = {
135         REGULATOR_SUPPLY("avdd_af1_cam", NULL),
136         REGULATOR_SUPPLY("imx135_reg1", NULL),
137         REGULATOR_SUPPLY("vdd", "2-000c"),
138         REGULATOR_SUPPLY("vin", "2-0030"),
139 };
140
141 static struct regulator_consumer_supply as3722_ldo11_supply[] = {
142         REGULATOR_SUPPLY("vpp_fuse", NULL),
143 };
144
145 static struct regulator_consumer_supply as3722_sd0_supply[] = {
146         REGULATOR_SUPPLY("vdd_cpu", NULL),
147 };
148
149 static struct regulator_consumer_supply as3722_sd1_supply[] = {
150         REGULATOR_SUPPLY("vdd_core", NULL),
151 };
152
153 static struct regulator_consumer_supply as3722_sd2_supply[] = {
154         REGULATOR_SUPPLY("vddio_ddr", NULL),
155         REGULATOR_SUPPLY("vddio_ddr_mclk", NULL),
156         REGULATOR_SUPPLY("vddio_ddr3", NULL),
157         REGULATOR_SUPPLY("vcore1_ddr3", NULL),
158 };
159
160 static struct regulator_consumer_supply as3722_sd4_supply[] = {
161         REGULATOR_SUPPLY("avdd_hdmi","tegradc.1"),
162         REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"),
163         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
164         REGULATOR_SUPPLY("avdd_pex_pll", "tegra-pcie"),
165         REGULATOR_SUPPLY("avddio_pex", "tegra-pcie"),
166         REGULATOR_SUPPLY("dvddio_pex", "tegra-pcie"),
167         REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"),
168 };
169
170 static struct regulator_consumer_supply as3722_sd5_supply[] = {
171         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5639.0"),
172         REGULATOR_SUPPLY("dbvdd", "tegra-snd-rt5645.0"),
173         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5639.0"),
174         REGULATOR_SUPPLY("avdd", "tegra-snd-rt5645.0"),
175         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5639.0"),
176         REGULATOR_SUPPLY("dmicvdd", "tegra-snd-rt5645.0"),
177         REGULATOR_SUPPLY("avdd_osc", NULL),
178         REGULATOR_SUPPLY("vddio_sys", NULL),
179         REGULATOR_SUPPLY("vddio_sys_2", NULL),
180         REGULATOR_SUPPLY("vddio_gmi", NULL),
181         REGULATOR_SUPPLY("pwrdet_nand", NULL),
182         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
183         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
184         REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
185         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
186         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-udc.0"),
187         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.0"),
188         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.1"),
189         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-ehci.2"),
190         REGULATOR_SUPPLY("avdd_pll_utmip", "tegra-xhci"),
191         REGULATOR_SUPPLY("vddio_audio", NULL),
192         REGULATOR_SUPPLY("pwrdet_audio", NULL),
193         REGULATOR_SUPPLY("vddio_uart", NULL),
194         REGULATOR_SUPPLY("pwrdet_uart", NULL),
195         REGULATOR_SUPPLY("vddio_bb", NULL),
196         REGULATOR_SUPPLY("pwrdet_bb", NULL),
197         REGULATOR_SUPPLY("vdd_1v8b", "0-0048"),
198         REGULATOR_SUPPLY("vdd_dtv", NULL),
199         REGULATOR_SUPPLY("vdd_1v8_eeprom", NULL),
200         REGULATOR_SUPPLY("vddio_cam", "tegra_camera"),
201         REGULATOR_SUPPLY("vddio_cam", "vi"),
202         REGULATOR_SUPPLY("pwrdet_cam", NULL),
203         REGULATOR_SUPPLY("dvdd", "spi0.0"),
204         REGULATOR_SUPPLY("vlogic", "0-0069"),
205         REGULATOR_SUPPLY("vid", "0-000c"),
206         REGULATOR_SUPPLY("vddio", "0-0077"),
207 };
208
209 static struct regulator_consumer_supply as3722_sd6_supply[] = {
210         REGULATOR_SUPPLY("vdd_gpu", NULL),
211 };
212
213
214 AMS_PDATA_INIT(sd0, NULL, 700000, 1400000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE2);
215 AMS_PDATA_INIT(sd1, NULL, 700000, 1400000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
216 AMS_PDATA_INIT(sd2, NULL, 1350000, 1350000, 1, 1, 1, 0);
217 AMS_PDATA_INIT(sd4, NULL, 1050000, 1050000, 0, 1, 1, 0);
218 AMS_PDATA_INIT(sd5, NULL, 1800000, 1800000, 1, 1, 1, 0);
219 AMS_PDATA_INIT(sd6, NULL, 700000, 1400000, 1, 1, 0, 0);
220 AMS_PDATA_INIT(ldo0, AS3722_SUPPLY(sd2), 1050000, 1250000, 1, 1, 1, AS3722_EXT_CONTROL_ENABLE1);
221 AMS_PDATA_INIT(ldo1, NULL, 1800000, 1800000, 0, 1, 1, 0);
222 AMS_PDATA_INIT(ldo2, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
223 AMS_PDATA_INIT(ldo3, NULL, 800000, 800000, 1, 1, 1, 0);
224 AMS_PDATA_INIT(ldo4, NULL, 2700000, 2700000, 0, 0, 1, 0);
225 AMS_PDATA_INIT(ldo5, AS3722_SUPPLY(sd5), 1200000, 1200000, 0, 0, 1, 0);
226 AMS_PDATA_INIT(ldo6, NULL, 1800000, 3300000, 0, 0, 1, 0);
227 AMS_PDATA_INIT(ldo7, AS3722_SUPPLY(sd5), 1050000, 1050000, 0, 0, 1, 0);
228 AMS_PDATA_INIT(ldo9, NULL, 3300000, 3300000, 0, 0, 1, 0);
229 AMS_PDATA_INIT(ldo10, NULL, 2700000, 2700000, 0, 0, 1, 0);
230 AMS_PDATA_INIT(ldo11, NULL, 1800000, 1800000, 0, 0, 1, 0);
231
232 /* config settings are OTP plus initial state
233  * GPIOsignal_out at 20h not configurable through OTP and is initialized to
234  * zero. To enable output, the invert bit must be turned on.
235  * GPIOxcontrol register format
236  * bit(s)  bitname
237  * ---------------------
238  *  7     gpiox_invert   invert input or output
239  * 6:3    gpiox_iosf     0: normal
240  * 2:0    gpiox_mode     0: input, 1: output push/pull, 3: ADC input (tristate)
241  *
242  * Examples:
243  * otp  meaning
244  * ------------
245  * 0x3  gpiox_invert=0(no invert), gpiox_iosf=0(normal), gpiox_mode=3(ADC input)
246  * 0x81 gpiox_invert=1(invert), gpiox_iosf=0(normal), gpiox_mode=1(output)
247  *
248  * Note: output state should be defined for gpiox_mode = output.  Do not change
249  * the state of the invert bit for critical devices such as GPIO 7 which enables
250  * SDRAM. Driver applies invert mask to output state to configure GPIOsignal_out
251  * register correctly.
252  * E.g. Invert = 1, (requested) output state = 1 => GPIOsignal_out = 0
253  */
254 static struct as3722_gpio_config as3722_gpio_cfgs[] = {
255         {
256                 /* otp = 0x3 IGPU_PRDGD*/
257                 .gpio = AS3722_GPIO0,
258                 .mode = AS3722_GPIO_MODE_OUTPUT_VDDL,
259         },
260         {
261                 /* otp = 0x1  => REGEN_3 = LP0 gate (1.8V, 5 V)*/
262                 .gpio = AS3722_GPIO1,
263                 .invert     = AS3722_GPIO_CFG_NO_INVERT,
264                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
265                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
266         },
267         {
268                 /* otp = 0x3 PMU_REGEN1*/
269                 .gpio = AS3722_GPIO2,
270                 .invert     = AS3722_GPIO_CFG_NO_INVERT, /* don't go into LP0 */
271                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
272                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
273         },
274         {
275                 /* otp = 0x03 AP THERMISTOR */
276                 .gpio = AS3722_GPIO3,
277                 .mode = AS3722_GPIO_MODE_ADC_IN,
278         },
279         {
280                 /* otp = 0x81 => on by default
281                  * gates EN_AVDD_LCD
282                  */
283                 .gpio       = AS3722_GPIO4,
284                 .invert     = AS3722_GPIO_CFG_NO_INVERT,
285                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
286                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
287         },
288         {
289                 /* otp = 0x3  CLK 23KHZ WIFI */
290                 .gpio = AS3722_GPIO5,
291                 .mode = AS3722_GPIO_MODE_OUTPUT_VDDL,
292                 .iosf = AS3722_GPIO_IOSF_Q32K_OUT,
293         },
294         {
295                 /* otp = 0x3  SKIN TEMP */
296                 .gpio = AS3722_GPIO6,
297                 .mode = AS3722_GPIO_MODE_ADC_IN,
298         },
299         {
300                 /* otp = 0x81  1.6V LP0*/
301                 .gpio       = AS3722_GPIO7,
302                 .invert     = AS3722_GPIO_CFG_INVERT,
303                 .mode       = AS3722_GPIO_MODE_OUTPUT_VDDH,
304                 .output_state = AS3722_GPIO_CFG_OUTPUT_ENABLED,
305         },
306 };
307
308 static struct as3722_rtc_platform_data as3722_rtc_pdata = {
309         .enable_clk32k  = 1,
310 };
311
312 static struct as3722_adc_extcon_platform_data as3722_adc_extcon_pdata = {
313         .connection_name = "as3722-extcon",
314         .enable_adc1_continuous_mode = true,
315         .enable_low_voltage_range = true,
316         .adc_channel = 12,
317         .hi_threshold =  0x100,
318         .low_threshold = 0x80,
319 };
320
321 static struct as3722_platform_data as3722_pdata = {
322         .reg_pdata[AS3722_SD0] = &as3722_sd0_reg_pdata,
323         .reg_pdata[AS3722_SD1] = &as3722_sd1_reg_pdata,
324         .reg_pdata[AS3722_SD2] = &as3722_sd2_reg_pdata,
325         .reg_pdata[AS3722_SD4] = &as3722_sd4_reg_pdata,
326         .reg_pdata[AS3722_SD5] = &as3722_sd5_reg_pdata,
327         .reg_pdata[AS3722_SD6] = &as3722_sd6_reg_pdata,
328         .reg_pdata[AS3722_LDO0] = &as3722_ldo0_reg_pdata,
329         .reg_pdata[AS3722_LDO1] = &as3722_ldo1_reg_pdata,
330         .reg_pdata[AS3722_LDO2] = &as3722_ldo2_reg_pdata,
331         .reg_pdata[AS3722_LDO3] = &as3722_ldo3_reg_pdata,
332         .reg_pdata[AS3722_LDO4] = &as3722_ldo4_reg_pdata,
333         .reg_pdata[AS3722_LDO5] = &as3722_ldo5_reg_pdata,
334         .reg_pdata[AS3722_LDO6] = &as3722_ldo6_reg_pdata,
335         .reg_pdata[AS3722_LDO7] = &as3722_ldo7_reg_pdata,
336         .reg_pdata[AS3722_LDO9] = &as3722_ldo9_reg_pdata,
337         .reg_pdata[AS3722_LDO10] = &as3722_ldo10_reg_pdata,
338         .reg_pdata[AS3722_LDO11] = &as3722_ldo11_reg_pdata,
339         .core_init_data = NULL,
340         .gpio_base = AS3722_GPIO_BASE,
341         .irq_base = AS3722_IRQ_BASE,
342         .use_internal_int_pullup = 0,
343         .use_internal_i2c_pullup = 0,
344         .num_gpio_cfgs = ARRAY_SIZE(as3722_gpio_cfgs),
345         .gpio_cfgs     = as3722_gpio_cfgs,
346         .rtc_pdata      = &as3722_rtc_pdata,
347         .use_power_off = true,
348         .enable_ldo3_tracking = true,
349         .disabe_ldo3_tracking_suspend = true,
350         .extcon_pdata = &as3722_adc_extcon_pdata,
351 };
352
353 static struct i2c_board_info __initdata as3722_regulators[] = {
354         {
355                 I2C_BOARD_INFO("as3722", 0x40),
356                 .flags = I2C_CLIENT_WAKE,
357                 .irq = INT_EXTERNAL_PMU,
358                 .platform_data = &as3722_pdata,
359         },
360 };
361
362 int __init ardbeg_as3722_regulator_init(void)
363 {
364         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
365         u32 pmc_ctrl;
366         struct board_info board_info;
367
368         /* AS3722: Normal state of INT request line is LOW.
369          * configure the power management controller to trigger PMU
370          * interrupts when HIGH.
371          */
372         pmc_ctrl = readl(pmc + PMC_CTRL);
373         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
374
375         /* Set vdd_gpu init uV to 1V */
376         as3722_sd6_reg_idata.constraints.init_uV = 900000;
377
378         as3722_sd6_reg_pdata.oc_configure_enable = true;
379         as3722_sd6_reg_pdata.oc_trip_thres_perphase = 3500;
380         as3722_sd6_reg_pdata.oc_alarm_thres_perphase = 0;
381
382         as3722_sd0_reg_pdata.oc_configure_enable = true;
383         as3722_sd0_reg_pdata.oc_trip_thres_perphase = 3500;
384         as3722_sd0_reg_pdata.oc_alarm_thres_perphase = 0;
385
386         as3722_sd1_reg_pdata.oc_configure_enable = true;
387         as3722_sd1_reg_pdata.oc_trip_thres_perphase = 2500;
388         as3722_sd1_reg_pdata.oc_alarm_thres_perphase = 0;
389
390         tegra_get_board_info(&board_info);
391         if (board_info.board_id == BOARD_E1792) {
392                 /*Default DDR voltage is 1.35V but lpddr3 supports 1.2V*/
393                 as3722_sd2_reg_idata.constraints.min_uV = 1200000;
394                 as3722_sd2_reg_idata.constraints.max_uV = 1200000;
395         }
396
397         pr_info("%s: i2c_register_board_info\n", __func__);
398         i2c_register_board_info(4, as3722_regulators,
399                         ARRAY_SIZE(as3722_regulators));
400         return 0;
401 }
402
403 int __init ardbeg_ams_regulator_init(void)
404 {
405         ardbeg_as3722_regulator_init();
406         return 0;
407 }
408
409 /**************** ARDBEG-TI913 based regulator ************/
410 #define palmas_ti913_smps123_supply as3722_sd6_supply
411 #define palmas_ti913_smps45_supply as3722_sd1_supply
412 #define palmas_ti913_smps6_supply as3722_sd5_supply
413 #define palmas_ti913_smps7_supply as3722_sd2_supply
414 #define palmas_ti913_smps9_supply as3722_sd4_supply
415 #define palmas_ti913_ldo1_supply as3722_ldo0_supply
416 #define palmas_ti913_ldo2_supply as3722_ldo5_supply
417 #define palmas_ti913_ldo3_supply as3722_ldo9_supply
418 #define palmas_ti913_ldo4_supply as3722_ldo2_supply
419 #define palmas_ti913_ldo5_supply as3722_ldo4_supply
420 #define palmas_ti913_ldo6_supply as3722_ldo1_supply
421 #define palmas_ti913_ldo7_supply as3722_ldo10_supply
422 #define palmas_ti913_ldo8_supply as3722_ldo3_supply
423 #define palmas_ti913_ldo9_supply as3722_ldo6_supply
424 #define palmas_ti913_ldoln_supply as3722_ldo7_supply
425 #define palmas_ti913_ldousb_supply as3722_ldo11_supply
426
427 static struct regulator_consumer_supply palmas_ti913_regen1_supply[] = {
428         REGULATOR_SUPPLY("micvdd", "tegra-snd-rt5645.0"),
429         REGULATOR_SUPPLY("vddio_hv", "tegradc.1"),
430         REGULATOR_SUPPLY("pwrdet_hv", NULL),
431         REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
432         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
433         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
434         REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
435         REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"),
436         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"),
437         REGULATOR_SUPPLY("hvdd_pex", "tegra-pcie"),
438         REGULATOR_SUPPLY("hvdd_pex_pll_e", "tegra-pcie"),
439         REGULATOR_SUPPLY("vddio_pex_ctl", "tegra-pcie"),
440         REGULATOR_SUPPLY("vdd", "0-0069"),
441         REGULATOR_SUPPLY("vdd", "0-0048"),
442         REGULATOR_SUPPLY("vdd", "0-000c"),
443         REGULATOR_SUPPLY("vdd", "0-0077"),
444 };
445
446 PALMAS_REGS_PDATA(ti913_smps123, 700, 1400, NULL, 1, 1, 1, NORMAL,
447         0, 0, 0, 0, 0);
448 PALMAS_REGS_PDATA(ti913_smps45, 900, 1400, NULL, 1, 1, 1, NORMAL,
449         0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
450 PALMAS_REGS_PDATA(ti913_smps6, 1800, 1800, NULL, 1, 1, 1, NORMAL,
451         0, 0, 0, 0, 0);
452 PALMAS_REGS_PDATA(ti913_smps7, 900, 1350, NULL, 1, 1, 1, NORMAL,
453         0, 0, 0, 0, 0);
454 PALMAS_REGS_PDATA(ti913_smps9, 1050, 1050, NULL, 0, 0, 0, NORMAL,
455         0, 0, 0, 0, 0);
456 PALMAS_REGS_PDATA(ti913_ldo1, 1050, 1250, palmas_rails(ti913_smps7),
457                 1, 1, 1, 0, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
458 PALMAS_REGS_PDATA(ti913_ldo2, 1200, 1200, palmas_rails(ti913_smps6),
459                 0, 0, 1, 0, 0, 0, 0, 0, 0);
460 PALMAS_REGS_PDATA(ti913_ldo3, 3100, 3100, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
461 PALMAS_REGS_PDATA(ti913_ldo4, 1200, 1200, palmas_rails(ti913_smps6),
462                 0, 0, 1, 0, 0, 0, 0, 0, 0);
463 PALMAS_REGS_PDATA(ti913_ldo5, 2700, 2700, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
464 PALMAS_REGS_PDATA(ti913_ldo6, 1800, 1800, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
465 PALMAS_REGS_PDATA(ti913_ldo7, 2700, 2700, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
466 PALMAS_REGS_PDATA(ti913_ldo8, 1000, 1000, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
467 PALMAS_REGS_PDATA(ti913_ldo9, 1800, 3300, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
468 PALMAS_REGS_PDATA(ti913_ldoln, 1050, 1050, palmas_rails(ti913_smps6),
469                 0, 0, 1, 0, 0, 0, 0, 0, 0);
470 PALMAS_REGS_PDATA(ti913_ldousb, 1800, 1800, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
471 PALMAS_REGS_PDATA(ti913_regen1, 2800, 3300, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
472
473 #define PALMAS_REG_PDATA(_sname) &reg_idata_##_sname
474 static struct regulator_init_data *ardbeg_1735_reg_data[PALMAS_NUM_REGS] = {
475         NULL,
476         PALMAS_REG_PDATA(ti913_smps123),
477         NULL,
478         PALMAS_REG_PDATA(ti913_smps45),
479         NULL,
480         PALMAS_REG_PDATA(ti913_smps6),
481         PALMAS_REG_PDATA(ti913_smps7),
482         NULL,
483         PALMAS_REG_PDATA(ti913_smps9),
484         NULL,
485         NULL,
486         PALMAS_REG_PDATA(ti913_ldo1),
487         PALMAS_REG_PDATA(ti913_ldo2),
488         PALMAS_REG_PDATA(ti913_ldo3),
489         PALMAS_REG_PDATA(ti913_ldo4),
490         PALMAS_REG_PDATA(ti913_ldo5),
491         PALMAS_REG_PDATA(ti913_ldo6),
492         PALMAS_REG_PDATA(ti913_ldo7),
493         PALMAS_REG_PDATA(ti913_ldo8),
494         PALMAS_REG_PDATA(ti913_ldo9),
495         NULL,
496         NULL,
497         NULL,
498         NULL,
499         NULL,
500         PALMAS_REG_PDATA(ti913_ldoln),
501         PALMAS_REG_PDATA(ti913_ldousb),
502         PALMAS_REG_PDATA(ti913_regen1),
503         NULL,
504         NULL,
505         NULL,
506         NULL,
507 };
508
509 #define PALMAS_REG_INIT_DATA(_sname) &reg_init_data_##_sname
510 static struct palmas_reg_init *ardbeg_1735_reg_init[PALMAS_NUM_REGS] = {
511         NULL,
512         PALMAS_REG_INIT_DATA(ti913_smps123),
513         NULL,
514         PALMAS_REG_INIT_DATA(ti913_smps45),
515         NULL,
516         PALMAS_REG_INIT_DATA(ti913_smps6),
517         PALMAS_REG_INIT_DATA(ti913_smps7),
518         NULL,
519         PALMAS_REG_INIT_DATA(ti913_smps9),
520         NULL,
521         NULL,
522         PALMAS_REG_INIT_DATA(ti913_ldo1),
523         PALMAS_REG_INIT_DATA(ti913_ldo2),
524         PALMAS_REG_INIT_DATA(ti913_ldo3),
525         PALMAS_REG_INIT_DATA(ti913_ldo4),
526         PALMAS_REG_INIT_DATA(ti913_ldo5),
527         PALMAS_REG_INIT_DATA(ti913_ldo6),
528         PALMAS_REG_INIT_DATA(ti913_ldo7),
529         PALMAS_REG_INIT_DATA(ti913_ldo8),
530         PALMAS_REG_INIT_DATA(ti913_ldo9),
531         NULL,
532         NULL,
533         NULL,
534         NULL,
535         NULL,
536         PALMAS_REG_INIT_DATA(ti913_ldoln),
537         PALMAS_REG_INIT_DATA(ti913_ldousb),
538         PALMAS_REG_INIT_DATA(ti913_regen1),
539         NULL,
540         NULL,
541         NULL,
542         NULL,
543 };
544
545 struct palmas_clk32k_init_data palmas_ti913_clk32k_idata[] = {
546         {
547                 .clk32k_id = PALMAS_CLOCK32KG,
548                 .enable = true,
549         }, {
550                 .clk32k_id = PALMAS_CLOCK32KG_AUDIO,
551                 .enable = true,
552         },
553 };
554
555 static struct palmas_extcon_platform_data palmas_extcon_pdata = {
556         .connection_name = "palmas-extcon",
557         .enable_vbus_detection = true,
558         .enable_id_pin_detection = true,
559 };
560
561 static struct palmas_pinctrl_config palmas_ti913_pincfg[] = {
562         PALMAS_PINMUX("powergood", "powergood", NULL, NULL),
563         PALMAS_PINMUX("vac", "vac", NULL, NULL),
564         PALMAS_PINMUX("gpio0", "id", "pull-up", NULL),
565         PALMAS_PINMUX("gpio1", "vbus_det", NULL, NULL),
566         PALMAS_PINMUX("gpio2", "gpio", NULL, NULL),
567         PALMAS_PINMUX("gpio3", "gpio", NULL, NULL),
568         PALMAS_PINMUX("gpio4", "gpio", NULL, NULL),
569         PALMAS_PINMUX("gpio5", "clk32kgaudio", NULL, NULL),
570         PALMAS_PINMUX("gpio6", "gpio", NULL, NULL),
571         PALMAS_PINMUX("gpio7", "gpio", NULL, NULL),
572 };
573
574 static struct palmas_pinctrl_platform_data palmas_ti913_pinctrl_pdata = {
575         .pincfg = palmas_ti913_pincfg,
576         .num_pinctrl = ARRAY_SIZE(palmas_ti913_pincfg),
577         .dvfs1_enable = true,
578         .dvfs2_enable = false,
579 };
580
581 static struct palmas_pmic_platform_data pmic_ti913_platform = {
582 };
583
584 static struct palmas_pm_platform_data palmas_pm_pdata = {
585         .use_power_off = true,
586         .use_power_reset = true,
587 };
588
589 static struct palmas_platform_data palmas_ti913_pdata = {
590         .gpio_base = PALMAS_TEGRA_GPIO_BASE,
591         .irq_base = PALMAS_TEGRA_IRQ_BASE,
592         .pmic_pdata = &pmic_ti913_platform,
593         .pinctrl_pdata = &palmas_ti913_pinctrl_pdata,
594         .clk32k_init_data =  palmas_ti913_clk32k_idata,
595         .clk32k_init_data_size = ARRAY_SIZE(palmas_ti913_clk32k_idata),
596         .extcon_pdata = &palmas_extcon_pdata,
597         .pm_pdata = &palmas_pm_pdata,
598 };
599
600 static struct i2c_board_info palma_ti913_device[] = {
601         {
602                 I2C_BOARD_INFO("tps65913", 0x58),
603                 .irq            = INT_EXTERNAL_PMU,
604                 .platform_data  = &palmas_ti913_pdata,
605         },
606 };
607
608 int __init ardbeg_tps65913_regulator_init(void)
609 {
610         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
611         u32 pmc_ctrl;
612         int i;
613         struct board_info board_info;
614
615         /* TPS65913: Normal state of INT request line is LOW.
616          * configure the power management controller to trigger PMU
617          * interrupts when HIGH.
618          */
619         pmc_ctrl = readl(pmc + PMC_CTRL);
620         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
621
622         /* Tracking configuration */
623         reg_init_data_ti913_ldo8.config_flags =
624                 PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE |
625                 PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE;
626
627         for (i = 0; i < PALMAS_NUM_REGS ; i++) {
628                 pmic_ti913_platform.reg_data[i] = ardbeg_1735_reg_data[i];
629                 pmic_ti913_platform.reg_init[i] = ardbeg_1735_reg_init[i];
630         }
631
632         /* Set vdd_gpu init uV to 1V */
633         reg_idata_ti913_smps123.constraints.init_uV = 900000;
634
635         tegra_get_board_info(&board_info);
636         if (board_info.board_id == BOARD_E1792) {
637                 /*Default DDR voltage is 1.35V but lpddr3 supports 1.2V*/
638                 reg_idata_ti913_smps7.constraints.max_uV = 1200000;
639         }
640
641         i2c_register_board_info(4, palma_ti913_device,
642                         ARRAY_SIZE(palma_ti913_device));
643         return 0;
644 }
645
646 static struct pca953x_platform_data tca6408_pdata = {
647                 .gpio_base = PMU_TCA6416_GPIO_BASE,
648 };
649
650 static const struct i2c_board_info tca6408_expander[] = {
651         {
652                 I2C_BOARD_INFO("tca6408", 0x20),
653                 .platform_data = &tca6408_pdata,
654         },
655 };
656
657 struct bq2471x_platform_data ardbeg_bq2471x_pdata = {
658         .dac_ichg               = 2240,
659         .dac_v                  = 9008,
660         .dac_minsv              = 4608,
661         .dac_iin                = 4992,
662         .wdt_refresh_timeout    = 40,
663         .gpio                   = TEGRA_GPIO_PK5,
664 };
665
666 static struct i2c_board_info __initdata bq2471x_boardinfo[] = {
667         {
668                 I2C_BOARD_INFO("bq2471x", 0x09),
669                 .platform_data  = &ardbeg_bq2471x_pdata,
670         },
671 };
672
673 static struct tegra_suspend_platform_data ardbeg_suspend_data = {
674         .cpu_timer      = 500,
675         .cpu_off_timer  = 300,
676         .suspend_mode   = TEGRA_SUSPEND_LP0,
677         .core_timer     = 0x157e,
678         .core_off_timer = 2000,
679         .corereq_high   = true,
680         .sysclkreq_high = true,
681         .cpu_lp2_min_residency = 1000,
682         .min_residency_crail = 20000,
683 };
684
685 static struct power_supply_extcon_plat_data extcon_pdata = {
686         .extcon_name = "tegra-udc",
687 };
688
689 static struct platform_device power_supply_extcon_device = {
690         .name   = "power-supply-extcon",
691         .id     = -1,
692         .dev    = {
693                 .platform_data = &extcon_pdata,
694         },
695 };
696
697 int __init ardbeg_suspend_init(void)
698 {
699         struct board_info pmu_board_info;
700
701         tegra_get_pmu_board_info(&pmu_board_info);
702
703         if (pmu_board_info.board_id == BOARD_E1735) {
704                 ardbeg_suspend_data.cpu_timer = 2000;
705                 ardbeg_suspend_data.crail_up_early = true;
706         }
707
708         tegra_init_suspend(&ardbeg_suspend_data);
709         return 0;
710 }
711
712 int __init ardbeg_regulator_init(void)
713 {
714         struct board_info pmu_board_info;
715
716         tegra_get_pmu_board_info(&pmu_board_info);
717
718         if ((pmu_board_info.board_id == BOARD_E1733) ||
719                 (pmu_board_info.board_id == BOARD_E1734)) {
720                 i2c_register_board_info(0, tca6408_expander,
721                                 ARRAY_SIZE(tca6408_expander));
722                 ardbeg_ams_regulator_init();
723                 regulator_has_full_constraints();
724         } else if (pmu_board_info.board_id == BOARD_E1735) {
725                 regulator_has_full_constraints();
726                 ardbeg_tps65913_regulator_init();
727         } else if (pmu_board_info.board_id == BOARD_E1736) {
728                 tn8_regulator_init();
729                 return tn8_fixed_regulator_init();
730         } else {
731                 pr_warn("PMU board id 0x%04x is not supported\n",
732                         pmu_board_info.board_id);
733         }
734
735         if (get_power_supply_type() == POWER_SUPPLY_TYPE_BATTERY)
736                 i2c_register_board_info(1, bq2471x_boardinfo,
737                         ARRAY_SIZE(bq2471x_boardinfo));
738
739         platform_device_register(&power_supply_extcon_device);
740         return 0;
741 }
742
743 /* Macro for defining fixed regulator sub device data */
744 #define FIXED_SUPPLY(_name) "fixed_reg_en_"#_name
745 #define FIXED_REG(_id, _var, _name, _in_supply,                 \
746         _always_on, _boot_on, _gpio_nr, _open_drain,            \
747         _active_high, _boot_state, _millivolts, _sdelay)        \
748 static struct regulator_init_data ri_data_##_var =              \
749 {                                                               \
750         .supply_regulator = _in_supply,                         \
751         .num_consumer_supplies =                                \
752         ARRAY_SIZE(fixed_reg_en_##_name##_supply),              \
753         .consumer_supplies = fixed_reg_en_##_name##_supply,     \
754         .constraints = {                                        \
755                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
756                                 REGULATOR_MODE_STANDBY),        \
757                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
758                                 REGULATOR_CHANGE_STATUS |       \
759                                 REGULATOR_CHANGE_VOLTAGE),      \
760                 .always_on = _always_on,                        \
761                 .boot_on = _boot_on,                            \
762         },                                                      \
763 };                                                              \
764 static struct fixed_voltage_config fixed_reg_en_##_var##_pdata =        \
765 {                                                               \
766         .supply_name = FIXED_SUPPLY(_name),                     \
767         .microvolts = _millivolts * 1000,                       \
768         .gpio = _gpio_nr,                                       \
769         .gpio_is_open_drain = _open_drain,                      \
770         .enable_high = _active_high,                            \
771         .enabled_at_boot = _boot_state,                         \
772         .init_data = &ri_data_##_var,                           \
773         .startup_delay = _sdelay                                \
774 };                                                              \
775 static struct platform_device fixed_reg_en_##_var##_dev = {     \
776         .name = "reg-fixed-voltage",                            \
777         .id = _id,                                              \
778         .dev = {                                                \
779                 .platform_data = &fixed_reg_en_##_var##_pdata,  \
780         },                                                      \
781 }
782
783 /* Always ON Battery regulator */
784 static struct regulator_consumer_supply fixed_reg_en_battery_ardbeg_supply[] = {
785                 REGULATOR_SUPPLY("vdd_sys_bl", NULL),
786 };
787
788 static struct regulator_consumer_supply fixed_reg_en_usb0_vbus_supply[] = {
789         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"),
790         REGULATOR_SUPPLY("usb_vbus", "tegra-otg"),
791         REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"),
792 };
793
794 static struct regulator_consumer_supply fixed_reg_en_usb1_vbus_supply[] = {
795         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.1"),
796         REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"),
797 };
798
799 static struct regulator_consumer_supply fixed_reg_en_usb2_vbus_supply[] = {
800         REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"),
801         REGULATOR_SUPPLY("usb_vbus2", "tegra-xhci"),
802 };
803
804 static struct regulator_consumer_supply fixed_reg_en_vdd_sd_supply[] = {
805         REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"),
806 };
807
808 static struct regulator_consumer_supply fixed_reg_en_vdd_sys_5v0_supply[] = {
809         REGULATOR_SUPPLY("vdd_spk_5v0", NULL),
810         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5639.0"),
811         REGULATOR_SUPPLY("spkvdd", "tegra-snd-rt5645.0"),
812 };
813
814 static struct regulator_consumer_supply fixed_reg_en_dcdc_1v8_supply[] = {
815         REGULATOR_SUPPLY("avdd_lvds0_pll", NULL),
816         REGULATOR_SUPPLY("vdd_ds_1v8", NULL),
817 };
818
819 static struct regulator_consumer_supply fixed_reg_en_lcd_bl_en_supply[] = {
820         REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL),
821 };
822
823 static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = {
824         REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"),
825 };
826
827 #define fixed_reg_en_as3722_gpio2_supply palmas_ti913_regen1_supply
828
829 static struct regulator_consumer_supply fixed_reg_en_as3722_gpio4_supply[] = {
830         REGULATOR_SUPPLY("avdd_lcd", NULL),
831 };
832
833 static struct regulator_consumer_supply fixed_reg_en_tca6408_p2_supply[] = {
834         REGULATOR_SUPPLY("ldoen", "tegra-snd-rt5639.0"),
835 };
836
837 static struct regulator_consumer_supply fixed_reg_en_as3722_gpio1_supply[] = {
838         REGULATOR_SUPPLY("vdd_wwan_mdm", NULL),
839 };
840
841 static struct regulator_consumer_supply fixed_reg_en_tca6408_p6_supply[] = {
842         REGULATOR_SUPPLY("dvdd_lcd", NULL),
843         REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL),
844 };
845
846 static struct regulator_consumer_supply fixed_reg_en_tca6408_p0_supply[] = {
847         REGULATOR_SUPPLY("vdd_lcd_1v2_s", NULL),
848 };
849
850 static struct regulator_consumer_supply fixed_reg_en_vdd_cpu_fixed_supply[] = {
851         REGULATOR_SUPPLY("vdd_cpu_fixed", NULL),
852 };
853
854 #define fixed_reg_en_ti913_gpio2_supply fixed_reg_en_as3722_gpio1_supply
855 #define fixed_reg_en_ti913_gpio3_supply fixed_reg_en_as3722_gpio4_supply
856 #define fixed_reg_en_ti913_gpio4_supply fixed_reg_en_tca6408_p0_supply
857 #define fixed_reg_en_ti913_gpio6_supply fixed_reg_en_tca6408_p2_supply
858 #define fixed_reg_en_ti913_gpio7_supply fixed_reg_en_tca6408_p6_supply
859
860 FIXED_REG(0,    battery_ardbeg, battery_ardbeg,
861         NULL,   0,      0,      -1,
862         false,  true,   0,      3300, 0);
863
864 FIXED_REG(1,    usb0_vbus,      usb0_vbus,
865         NULL,   0,      0,      TEGRA_GPIO_PN4,
866         true,   true,   0,      5000,   0);
867
868 FIXED_REG(2,    usb1_vbus,      usb1_vbus,
869         NULL,   0,      0,      TEGRA_GPIO_PN5,
870         true,   true,   0,      5000,   0);
871
872 FIXED_REG(3,    usb2_vbus,      usb2_vbus,
873         NULL,   0,      0,      TEGRA_GPIO_PFF1,
874         true,   true,   0,      5000,   0);
875
876 FIXED_REG(4,    vdd_sd, vdd_sd,
877         NULL,   0,      0,      TEGRA_GPIO_PR0,
878         false,  true,   0,      3300,   0);
879
880 FIXED_REG(5,    vdd_sys_5v0,    vdd_sys_5v0,
881         NULL,   0,      0,      -1,
882         false,  true,   0,      5000, 0);
883
884 FIXED_REG(6,    dcdc_1v8,       dcdc_1v8,
885         NULL,   0,      0,      -1,
886         false,  true,   0,      1800, 0);
887
888 FIXED_REG(7,    lcd_bl_en,      lcd_bl_en,
889         NULL,   0,      0, TEGRA_GPIO_PH2,
890         false,  true,   0,      5000,   0);
891
892 /* EN for LDO1/6/9/10 So keep always_ON */
893 FIXED_REG(8,    as3722_gpio2,   as3722_gpio2,
894         NULL,   1,      1, AS3722_GPIO_BASE + AS3722_GPIO2,
895         false,  true,   0,      3300, 0);
896
897 FIXED_REG(9,    as3722_gpio4,   as3722_gpio4,
898         NULL,   0,      0, AS3722_GPIO_BASE + AS3722_GPIO4,
899         false,  true,   0,      3300,   0);
900
901 FIXED_REG(10,   as3722_gpio1,   as3722_gpio1,
902         NULL,   0,      0,      AS3722_GPIO_BASE + AS3722_GPIO1,
903         false,  true,   0,      3300,   0);
904
905 FIXED_REG(11,   tca6408_p2,     tca6408_p2,
906         AS3722_SUPPLY(sd5),     0,      0,      PMU_TCA6416_GPIO(2),
907         false,  true,   0,      1200, 0);
908
909 FIXED_REG(12,   vdd_hdmi_5v0,   vdd_hdmi_5v0,
910         NULL,   0,      0,
911         TEGRA_GPIO_PK6, false,  true,   0,      5000,   5000);
912
913 FIXED_REG(13,   tca6408_p6,     tca6408_p6,
914         AS3722_SUPPLY(sd5),     0,      0,      PMU_TCA6416_GPIO(6),
915         false,  true,   0,      1800, 0);
916
917 FIXED_REG(14,   tca6408_p0,     tca6408_p0,
918         AS3722_SUPPLY(sd5),     0,      0,      PMU_TCA6416_GPIO(0),
919         false,  true,   0,      1200, 0);
920
921 FIXED_REG(15,   ti913_gpio2,    ti913_gpio2,
922         NULL,   1,      1,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2,
923         false,  true,   0,      3300, 0);
924
925 FIXED_REG(16,   ti913_gpio3,    ti913_gpio3,
926         NULL,   0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO3,
927         false,  true,   0,      3300,   0);
928
929 FIXED_REG(17,   ti913_gpio4,    ti913_gpio4,
930         NULL,   0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4,
931         false,  true,   0,      1200,   0);
932
933 FIXED_REG(18,   ti913_gpio6,    ti913_gpio6,
934         NULL,   0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6,
935         false,  true,   0,      1200,   0);
936
937 FIXED_REG(19,   ti913_gpio7,    ti913_gpio7,
938         NULL,   0,      0,      PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO7,
939         false,  true,   0,      1800,   0);
940
941 FIXED_REG(20,   vdd_cpu_fixed,  vdd_cpu_fixed,
942         NULL,   0,      1,      -1,
943         false,  true,   0,      1000,   0);
944
945 /*
946  * Creating fixed regulator device tables
947  */
948 #define ADD_FIXED_REG(_name)    (&fixed_reg_en_##_name##_dev)
949 #define ARDBEG_COMMON_FIXED_REG \
950         ADD_FIXED_REG(battery_ardbeg),          \
951         ADD_FIXED_REG(vdd_hdmi_5v0),            \
952         ADD_FIXED_REG(usb0_vbus),               \
953         ADD_FIXED_REG(usb1_vbus),               \
954         ADD_FIXED_REG(usb2_vbus),               \
955         ADD_FIXED_REG(lcd_bl_en),               \
956         ADD_FIXED_REG(dcdc_1v8),                \
957         ADD_FIXED_REG(vdd_sys_5v0),             \
958         ADD_FIXED_REG(vdd_sd),
959
960 #define ARDBEG_E1733_FIXED_REG                  \
961         ADD_FIXED_REG(as3722_gpio2),            \
962         ADD_FIXED_REG(as3722_gpio4),            \
963         ADD_FIXED_REG(as3722_gpio1),            \
964         ADD_FIXED_REG(tca6408_p2),              \
965         ADD_FIXED_REG(tca6408_p6),              \
966         ADD_FIXED_REG(tca6408_p0),
967
968 #define ARDBEG_E1735_FIXED_REG                  \
969         ADD_FIXED_REG(ti913_gpio2),             \
970         ADD_FIXED_REG(ti913_gpio3),             \
971         ADD_FIXED_REG(ti913_gpio4),             \
972         ADD_FIXED_REG(ti913_gpio6),             \
973         ADD_FIXED_REG(ti913_gpio7),             \
974         ADD_FIXED_REG(vdd_cpu_fixed),
975
976 static struct platform_device *fixed_reg_devs_e1733[] = {
977         ARDBEG_COMMON_FIXED_REG
978         ARDBEG_E1733_FIXED_REG
979 };
980
981 static struct platform_device *fixed_reg_devs_e1735[] = {
982         ARDBEG_COMMON_FIXED_REG
983         ARDBEG_E1735_FIXED_REG
984 };
985
986 /************************ ARDBEG CL-DVFS DATA *********************/
987 #define E1735_CPU_VDD_MAP_SIZE          33
988 #define E1735_CPU_VDD_MIN_UV            675000
989 #define E1735_CPU_VDD_STEP_UV           18750
990 #define E1735_CPU_VDD_STEP_US           80
991 #define ARDBEG_DEFAULT_CVB_ALIGNMENT    10000
992
993 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
994 /* Macro definition of dfll bypass device */
995 #define DFLL_BYPASS(_board, _min, _step, _size, _us_sel)                       \
996 static struct regulator_init_data _board##_dfll_bypass_init_data = {           \
997         .num_consumer_supplies = ARRAY_SIZE(_board##_dfll_bypass_consumers),   \
998         .consumer_supplies = _board##_dfll_bypass_consumers,                   \
999         .constraints = {                                                       \
1000                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |                   \
1001                                 REGULATOR_MODE_STANDBY),                       \
1002                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |                     \
1003                                 REGULATOR_CHANGE_STATUS |                      \
1004                                 REGULATOR_CHANGE_VOLTAGE),                     \
1005                 .min_uV = (_min),                                              \
1006                 .max_uV = ((_size) - 1) * (_step) + (_min),                    \
1007                 .always_on = 1,                                                \
1008                 .boot_on = 1,                                                  \
1009         },                                                                     \
1010 };                                                                             \
1011 static struct tegra_dfll_bypass_platform_data _board##_dfll_bypass_pdata = {   \
1012         .reg_init_data = &_board##_dfll_bypass_init_data,                      \
1013         .uV_step = (_step),                                                    \
1014         .linear_min_sel = 0,                                                   \
1015         .n_voltages = (_size),                                                 \
1016         .voltage_time_sel = _us_sel,                                           \
1017 };                                                                             \
1018 static struct platform_device e1735_dfll_bypass_dev = {                        \
1019         .name = "tegra_dfll_bypass",                                           \
1020         .id = -1,                                                              \
1021         .dev = {                                                               \
1022                 .platform_data = &_board##_dfll_bypass_pdata,                  \
1023         },                                                                     \
1024 }
1025
1026 /* E1735 board parameters for cpu dfll */
1027 static struct tegra_cl_dvfs_cfg_param e1735_cl_dvfs_param = {
1028         .sample_rate = 50000,
1029
1030         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
1031         .cf = 10,
1032         .ci = 0,
1033         .cg = 2,
1034
1035         .droop_cut_value = 0xF,
1036         .droop_restore_ramp = 0x0,
1037         .scale_out_ramp = 0x0,
1038 };
1039
1040 /* E1735 RT8812C volatge map */
1041 static struct voltage_reg_map e1735_cpu_vdd_map[E1735_CPU_VDD_MAP_SIZE];
1042 static inline int e1735_fill_reg_map(int nominal_mv)
1043 {
1044         int i, uv, nominal_uv = 0;
1045         for (i = 0; i < E1735_CPU_VDD_MAP_SIZE; i++) {
1046                 e1735_cpu_vdd_map[i].reg_value = i;
1047                 e1735_cpu_vdd_map[i].reg_uV = uv =
1048                         E1735_CPU_VDD_MIN_UV + E1735_CPU_VDD_STEP_UV * i;
1049                 if (!nominal_uv && uv >= nominal_mv * 1000)
1050                         nominal_uv = uv;
1051         }
1052         return nominal_uv;
1053 }
1054
1055 /* E1735 dfll bypass device for legacy dvfs control */
1056 static struct regulator_consumer_supply e1735_dfll_bypass_consumers[] = {
1057         REGULATOR_SUPPLY("vdd_cpu", NULL),
1058 };
1059 DFLL_BYPASS(e1735, E1735_CPU_VDD_MIN_UV, E1735_CPU_VDD_STEP_UV,
1060             E1735_CPU_VDD_MAP_SIZE, E1735_CPU_VDD_STEP_US);
1061
1062 static struct tegra_cl_dvfs_platform_data e1735_cl_dvfs_data = {
1063         .dfll_clk_name = "dfll_cpu",
1064         .pmu_if = TEGRA_CL_DVFS_PMU_PWM,
1065         .u.pmu_pwm = {
1066                 .pwm_rate = 12750000,
1067                 .out_gpio = TEGRA_GPIO_PS5,
1068                 .out_enable_high = false,
1069 #ifdef CONFIG_REGULATOR_TEGRA_DFLL_BYPASS
1070                 .dfll_bypass_dev = &e1735_dfll_bypass_dev,
1071 #endif
1072         },
1073         .vdd_map = e1735_cpu_vdd_map,
1074         .vdd_map_size = E1735_CPU_VDD_MAP_SIZE,
1075
1076         .cfg_param = &e1735_cl_dvfs_param,
1077 };
1078
1079 static void e1735_suspend_dfll_bypass(void)
1080 {
1081         __gpio_set_value(TEGRA_GPIO_PS5, 1); /* tristate external PWM buffer */
1082 }
1083
1084 static void e1735_resume_dfll_bypass(void)
1085 {
1086         __gpio_set_value(TEGRA_GPIO_PS5, 0); /* enable PWM buffer operations */
1087 }
1088
1089 static struct tegra_cl_dvfs_cfg_param e1733_ardbeg_cl_dvfs_param = {
1090         .sample_rate = 12500,
1091
1092         .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
1093         .cf = 10,
1094         .ci = 0,
1095         .cg = 2,
1096
1097         .droop_cut_value = 0xF,
1098         .droop_restore_ramp = 0x0,
1099         .scale_out_ramp = 0x0,
1100 };
1101
1102 /* E1733 volatge map. Fixed 10mv steps from 700mv to 1400mv */
1103 #define E1733_CPU_VDD_MAP_SIZE ((1400000 - 700000) / 10000 + 1)
1104 static struct voltage_reg_map e1733_cpu_vdd_map[E1733_CPU_VDD_MAP_SIZE];
1105 static inline void e1733_fill_reg_map(void)
1106 {
1107         int i;
1108         for (i = 0; i < E1733_CPU_VDD_MAP_SIZE; i++) {
1109                 e1733_cpu_vdd_map[i].reg_value = i + 0xa;
1110                 e1733_cpu_vdd_map[i].reg_uV = 700000 + 10000 * i;
1111         }
1112 }
1113
1114 static struct tegra_cl_dvfs_platform_data e1733_cl_dvfs_data = {
1115         .dfll_clk_name = "dfll_cpu",
1116         .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
1117         .u.pmu_i2c = {
1118                 .fs_rate = 400000,
1119                 .slave_addr = 0x80,
1120                 .reg = 0x00,
1121         },
1122         .vdd_map = e1733_cpu_vdd_map,
1123         .vdd_map_size = E1733_CPU_VDD_MAP_SIZE,
1124
1125         .cfg_param = &e1733_ardbeg_cl_dvfs_param,
1126 };
1127
1128 static int __init ardbeg_cl_dvfs_init(u16 pmu_board_id)
1129 {
1130         struct tegra_cl_dvfs_platform_data *data = NULL;
1131         int v = tegra_dvfs_rail_get_nominal_millivolts(tegra_cpu_rail);
1132
1133         if (pmu_board_id == BOARD_E1735) {
1134                 v = e1735_fill_reg_map(v);
1135                 data = &e1735_cl_dvfs_data;
1136                 if (data->u.pmu_pwm.dfll_bypass_dev) {
1137                         /* this has to be exact to 1uV level from table */
1138                         e1735_dfll_bypass_init_data.constraints.init_uV = v;
1139                         ardbeg_suspend_data.suspend_dfll_bypass =
1140                                 e1735_suspend_dfll_bypass;
1141                         ardbeg_suspend_data.resume_dfll_bypass =
1142                                 e1735_resume_dfll_bypass;
1143                 } else {
1144                         (void)e1735_dfll_bypass_dev;
1145                 }
1146         }
1147
1148
1149         if (pmu_board_id == BOARD_E1733) {
1150                 e1733_fill_reg_map();
1151                 data = &e1733_cl_dvfs_data;
1152         }
1153
1154         if (data) {
1155                 data->flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
1156                 tegra_cl_dvfs_device.dev.platform_data = data;
1157                 platform_device_register(&tegra_cl_dvfs_device);
1158         }
1159         return 0;
1160 }
1161 #else
1162 static inline int ardbeg_cl_dvfs_init(u16 pmu_board_id)
1163 { return 0; }
1164 #endif
1165
1166 int __init ardbeg_rail_alignment_init(void)
1167 {
1168         struct board_info pmu_board_info;
1169
1170         tegra_get_pmu_board_info(&pmu_board_info);
1171
1172         if (pmu_board_info.board_id == BOARD_E1735)
1173                 tegra12x_vdd_cpu_align(E1735_CPU_VDD_STEP_UV,
1174                                        E1735_CPU_VDD_MIN_UV);
1175         else
1176                 tegra12x_vdd_cpu_align(ARDBEG_DEFAULT_CVB_ALIGNMENT, 0);
1177         return 0;
1178 }
1179
1180 static int __init ardbeg_fixed_regulator_init(void)
1181 {
1182         struct board_info pmu_board_info;
1183
1184         if (!of_machine_is_compatible("nvidia,ardbeg"))
1185                 return 0;
1186
1187         tegra_get_pmu_board_info(&pmu_board_info);
1188         ardbeg_cl_dvfs_init(pmu_board_info.board_id);
1189
1190         if (pmu_board_info.board_id == BOARD_E1733)
1191                 return platform_add_devices(fixed_reg_devs_e1733,
1192                         ARRAY_SIZE(fixed_reg_devs_e1733));
1193         else if (pmu_board_info.board_id == BOARD_E1735)
1194                 return platform_add_devices(fixed_reg_devs_e1735,
1195                         ARRAY_SIZE(fixed_reg_devs_e1735));
1196         else
1197                 pr_warn("The PMU board id 0x%04x is not supported\n",
1198                         pmu_board_info.board_id);
1199
1200         return 0;
1201 }
1202
1203 subsys_initcall_sync(ardbeg_fixed_regulator_init);
1204
1205 int __init ardbeg_edp_init(void)
1206 {
1207         unsigned int regulator_mA;
1208
1209         regulator_mA = get_maximum_cpu_current_supported();
1210         if (!regulator_mA)
1211                 regulator_mA = 16000;
1212
1213         pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
1214         tegra_init_cpu_edp_limits(regulator_mA);
1215
1216         return 0;
1217 }
1218
1219
1220 static struct pid_thermal_gov_params soctherm_pid_params = {
1221         .max_err_temp = 9000,
1222         .max_err_gain = 1000,
1223
1224         .gain_p = 1000,
1225         .gain_d = 0,
1226
1227         .up_compensation = 20,
1228         .down_compensation = 20,
1229 };
1230
1231 static struct thermal_zone_params soctherm_tzp = {
1232         .governor_name = "pid_thermal_gov",
1233         .governor_params = &soctherm_pid_params,
1234 };
1235
1236 static struct tegra_tsensor_pmu_data tpdata_palmas = {
1237         .reset_tegra = 1,
1238         .pmu_16bit_ops = 0,
1239         .controller_type = 0,
1240         .pmu_i2c_addr = 0x58,
1241         .i2c_controller_id = 4,
1242         .poweroff_reg_addr = 0xa0,
1243         .poweroff_reg_data = 0x0,
1244 };
1245
1246 static struct tegra_tsensor_pmu_data tpdata_as3722 = {
1247         .reset_tegra = 1,
1248         .pmu_16bit_ops = 0,
1249         .controller_type = 0,
1250         .pmu_i2c_addr = 0x40,
1251         .i2c_controller_id = 4,
1252         .poweroff_reg_addr = 0x36,
1253         .poweroff_reg_data = 0x2,
1254 };
1255
1256 static struct soctherm_platform_data ardbeg_soctherm_data = {
1257         .therm = {
1258                 [THERM_CPU] = {
1259                         .zone_enable = true,
1260                         .passive_delay = 1000,
1261                         .hotspot_offset = 6000,
1262                         .num_trips = 3,
1263                         .trips = {
1264                                 {
1265                                         .cdev_type = "tegra-shutdown",
1266                                         .trip_temp = 98000,
1267                                         .trip_type = THERMAL_TRIP_CRITICAL,
1268                                         .upper = THERMAL_NO_LIMIT,
1269                                         .lower = THERMAL_NO_LIMIT,
1270                                 },
1271                                 {
1272                                         .cdev_type = "tegra-heavy",
1273                                         .trip_temp = 96000,
1274                                         .trip_type = THERMAL_TRIP_HOT,
1275                                         .upper = THERMAL_NO_LIMIT,
1276                                         .lower = THERMAL_NO_LIMIT,
1277                                 },
1278                                 {
1279                                         .cdev_type = "tegra-balanced",
1280                                         .trip_temp = 86000,
1281                                         .trip_type = THERMAL_TRIP_PASSIVE,
1282                                         .upper = THERMAL_NO_LIMIT,
1283                                         .lower = THERMAL_NO_LIMIT,
1284                                 },
1285                         },
1286                         .tzp = &soctherm_tzp,
1287                 },
1288                 [THERM_GPU] = {
1289                         .zone_enable = true,
1290                         .passive_delay = 1000,
1291                         .hotspot_offset = 6000,
1292                         .num_trips = 2,
1293                         .trips = {
1294                                 {
1295                                         .cdev_type = "tegra-shutdown",
1296                                         .trip_temp = 100000,
1297                                         .trip_type = THERMAL_TRIP_CRITICAL,
1298                                         .upper = THERMAL_NO_LIMIT,
1299                                         .lower = THERMAL_NO_LIMIT,
1300                                 },
1301                                 {
1302                                         .cdev_type = "tegra-balanced",
1303                                         .trip_temp = 88000,
1304                                         .trip_type = THERMAL_TRIP_PASSIVE,
1305                                         .upper = THERMAL_NO_LIMIT,
1306                                         .lower = THERMAL_NO_LIMIT,
1307                                 },
1308 /*
1309                                 {
1310                                         .cdev_type = "gk20a_cdev",
1311                                         .trip_temp = 80000,
1312                                         .trip_type = THERMAL_TRIP_PASSIVE,
1313                                         .upper = THERMAL_NO_LIMIT,
1314                                         .lower = THERMAL_NO_LIMIT,
1315                                 },
1316                                 {
1317                                         .cdev_type = "tegra-heavy",
1318                                         .trip_temp = 98000,
1319                                         .trip_type = THERMAL_TRIP_HOT,
1320                                         .upper = THERMAL_NO_LIMIT,
1321                                         .lower = THERMAL_NO_LIMIT,
1322                                 },
1323 */
1324                         },
1325                         .tzp = &soctherm_tzp,
1326                 },
1327                 [THERM_PLL] = {
1328                         .zone_enable = true,
1329                 },
1330         },
1331         .throttle = {
1332                 [THROTTLE_HEAVY] = {
1333                         .priority = 100,
1334                         .devs = {
1335                                 [THROTTLE_DEV_CPU] = {
1336                                         .enable = true,
1337                                         .depth = 80,
1338                                 },
1339                                 [THROTTLE_DEV_GPU] = {
1340                                         .enable = false,
1341                                         .throttling_depth = "heavy_throttling",
1342                                 },
1343                         },
1344                 },
1345         },
1346         .tshut_pmu_trip_data = &tpdata_palmas,
1347 };
1348
1349 int __init ardbeg_soctherm_init(void)
1350 {
1351         struct board_info pmu_board_info;
1352
1353         /* do this only for supported CP,FT fuses */
1354         if (!tegra_fuse_calib_base_get_cp(NULL, NULL) &&
1355             !tegra_fuse_calib_base_get_ft(NULL, NULL)) {
1356                 tegra_platform_edp_init(
1357                         ardbeg_soctherm_data.therm[THERM_CPU].trips,
1358                         &ardbeg_soctherm_data.therm[THERM_CPU].num_trips,
1359                         8000); /* edp temperature margin */
1360         }
1361
1362         tegra_get_pmu_board_info(&pmu_board_info);
1363
1364         if ((pmu_board_info.board_id == BOARD_E1733) ||
1365                 (pmu_board_info.board_id == BOARD_E1734))
1366                 ardbeg_soctherm_data.tshut_pmu_trip_data = &tpdata_as3722;
1367         else if (pmu_board_info.board_id == BOARD_E1735)
1368                 ;/* tpdata_palmas is default */
1369         else if (pmu_board_info.board_id == BOARD_E1736)
1370                 ;/* FIXME: Not supporting tn8 yet - assumes palmas PMIC */
1371         else
1372                 pr_warn("soctherm THERMTRIP is not supported on this PMIC\n");
1373
1374         return tegra11_soctherm_init(&ardbeg_soctherm_data);
1375 }