2 * arch/arm/mach-tegra/board-ardbeg-pinmux.c
4 * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/gpio.h>
20 #include <mach/pinmux.h>
21 #include <mach/gpio-tegra.h>
24 #include "board-ardbeg.h"
26 #include "gpio-names.h"
28 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
29 #include <mach/pinmux-t11.h>
31 #include <mach/pinmux-t12.h>
34 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
35 #define DEFAULT_DRIVE(_name) \
37 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
38 .hsm = TEGRA_HSM_DISABLE, \
39 .schmitt = TEGRA_SCHMITT_ENABLE, \
40 .drive = TEGRA_DRIVE_DIV_1, \
41 .pull_down = TEGRA_PULL_31, \
42 .pull_up = TEGRA_PULL_31, \
43 .slew_rising = TEGRA_SLEW_SLOWEST, \
44 .slew_falling = TEGRA_SLEW_SLOWEST, \
46 /* Setting the drive strength of pins
47 * hsm: Enable High speed mode (ENABLE/DISABLE)
48 * Schimit: Enable/disable schimit (ENABLE/DISABLE)
49 * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
50 * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
51 * strength code. Value from 0 to 31.
52 * pullup_drive - drive up (rising edge) - Driver Output Pull-Up drive
53 * strength code. Value from 0 to 31.
54 * pulldn_slew - Driver Output Pull-Up slew control code - 2bit code
55 * code 11 is least slewing of signal. code 00 is highest
56 * slewing of the signal.
57 * Value - FASTEST, FAST, SLOW, SLOWEST
58 * pullup_slew - Driver Output Pull-Down slew control code -
59 * code 11 is least slewing of signal. code 00 is highest
60 * slewing of the signal.
61 * Value - FASTEST, FAST, SLOW, SLOWEST
63 #define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive,\
64 _pullup_drive,_pulldn_slew, _pullup_slew) \
66 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
67 .hsm = TEGRA_HSM_##_hsm, \
68 .schmitt = TEGRA_SCHMITT_##_schmitt, \
69 .drive = TEGRA_DRIVE_##_drive, \
70 .pull_down = TEGRA_PULL_##_pulldn_drive, \
71 .pull_up = TEGRA_PULL_##_pullup_drive, \
72 .slew_rising = TEGRA_SLEW_##_pulldn_slew, \
73 .slew_falling = TEGRA_SLEW_##_pullup_slew, \
76 /* Setting the drive strength of pins
77 * hsm: Enable High speed mode (ENABLE/DISABLE)
78 * Schimit: Enable/disable schimit (ENABLE/DISABLE)
79 * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
80 * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
81 * strength code. Value from 0 to 31.
82 * pullup_drive - drive up (rising edge) - Driver Output Pull-Up drive
83 * strength code. Value from 0 to 31.
84 * pulldn_slew - Driver Output Pull-Up slew control code - 2bit code
85 * code 11 is least slewing of signal. code 00 is highest
86 * slewing of the signal.
87 * Value - FASTEST, FAST, SLOW, SLOWEST
88 * pullup_slew - Driver Output Pull-Down slew control code -
89 * code 11 is least slewing of signal. code 00 is highest
90 * slewing of the signal.
91 * Value - FASTEST, FAST, SLOW, SLOWEST
92 * drive_type - Drive type to be used depending on the resistors.
95 #define SET_DRIVE_WITH_TYPE(_name, _hsm, _schmitt, _drive, _pulldn_drive,\
96 _pullup_drive, _pulldn_slew, _pullup_slew, _drive_type) \
98 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
99 .hsm = TEGRA_HSM_##_hsm, \
100 .schmitt = TEGRA_SCHMITT_##_schmitt, \
101 .drive = TEGRA_DRIVE_##_drive, \
102 .pull_down = TEGRA_PULL_##_pulldn_drive, \
103 .pull_up = TEGRA_PULL_##_pullup_drive, \
104 .slew_rising = TEGRA_SLEW_##_pulldn_slew, \
105 .slew_falling = TEGRA_SLEW_##_pullup_slew, \
106 .drive_type = TEGRA_DRIVE_TYPE_##_drive_type, \
109 #define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io) \
111 .pingroup = TEGRA_PINGROUP_##_pingroup, \
112 .func = TEGRA_MUX_##_mux, \
113 .pupd = TEGRA_PUPD_##_pupd, \
114 .tristate = TEGRA_TRI_##_tri, \
115 .io = TEGRA_PIN_##_io, \
116 .lock = TEGRA_PIN_LOCK_DEFAULT, \
117 .od = TEGRA_PIN_OD_DEFAULT, \
118 .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
121 #define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
123 .pingroup = TEGRA_PINGROUP_##_pingroup, \
124 .func = TEGRA_MUX_##_mux, \
125 .pupd = TEGRA_PUPD_##_pupd, \
126 .tristate = TEGRA_TRI_##_tri, \
127 .io = TEGRA_PIN_##_io, \
128 .lock = TEGRA_PIN_LOCK_##_lock, \
129 .od = TEGRA_PIN_OD_##_od, \
130 .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
133 #define DDC_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _rcv_sel) \
135 .pingroup = TEGRA_PINGROUP_##_pingroup, \
136 .func = TEGRA_MUX_##_mux, \
137 .pupd = TEGRA_PUPD_##_pupd, \
138 .tristate = TEGRA_TRI_##_tri, \
139 .io = TEGRA_PIN_##_io, \
140 .lock = TEGRA_PIN_LOCK_##_lock, \
141 .rcv_sel = TEGRA_PIN_RCV_SEL_##_rcv_sel, \
142 .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
145 #define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
147 .pingroup = TEGRA_PINGROUP_##_pingroup, \
148 .func = TEGRA_MUX_##_mux, \
149 .pupd = TEGRA_PUPD_##_pupd, \
150 .tristate = TEGRA_TRI_##_tri, \
151 .io = TEGRA_PIN_##_io, \
152 .lock = TEGRA_PIN_LOCK_##_lock, \
153 .od = TEGRA_PIN_OD_DEFAULT, \
154 .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \
157 #define CEC_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
159 .pingroup = TEGRA_PINGROUP_##_pingroup, \
160 .func = TEGRA_MUX_##_mux, \
161 .pupd = TEGRA_PUPD_##_pupd, \
162 .tristate = TEGRA_TRI_##_tri, \
163 .io = TEGRA_PIN_##_io, \
164 .lock = TEGRA_PIN_LOCK_##_lock, \
165 .od = TEGRA_PIN_OD_##_od, \
166 .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
169 #define USB_PINMUX CEC_PINMUX
171 #define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value) \
174 .is_input = _is_input, \
177 #define GPIO_PINMUX(_pingroup, _pupd, _tri, _io, _od) \
179 .pingroup = TEGRA_PINGROUP_##_pingroup, \
180 .func = TEGRA_MUX_SAFE, \
181 .pupd = TEGRA_PUPD_##_pupd, \
182 .tristate = TEGRA_TRI_##_tri, \
183 .io = TEGRA_PIN_##_io, \
184 .lock = TEGRA_PIN_LOCK_DEFAULT, \
185 .od = TEGRA_PIN_OD_##_od, \
186 .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
188 #define UNUSED_PINMUX(_pingroup) \
190 .pingroup = TEGRA_PINGROUP_##_pingroup, \
191 .func = TEGRA_MUX_SAFE, \
192 .pupd = TEGRA_PUPD_PULL_DOWN, \
193 .tristate = TEGRA_TRI_TRISTATE, \
194 .io = TEGRA_PIN_OUTPUT, \
195 .lock = TEGRA_PIN_LOCK_DEFAULT, \
196 .od = TEGRA_PIN_OD_DEFAULT, \
197 .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
200 /* All the above macros are defined in pinmux-t12.h */
202 static __initdata struct tegra_drive_pingroup_config ardbeg_drive_pinmux[] = {
203 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
204 /* DEFAULT_DRIVE(<pin_group>), */
206 /*Set DAP2 drive (required for Codec Master Mode)*/
207 SET_DRIVE(DAP2, DISABLE, ENABLE, DIV_1, 51, 51, FASTEST, FASTEST),
210 SET_DRIVE(SDIO1, ENABLE, DISABLE, DIV_1, 36, 20, SLOW, SLOW),
213 SET_DRIVE(SDIO3, ENABLE, DISABLE, DIV_1, 22, 36, FASTEST, FASTEST),
216 SET_DRIVE_WITH_TYPE(GMA, ENABLE, DISABLE, DIV_1, 2, 1, FASTEST,
219 /*Set DAP2 drive (required for Codec Master Mode)*/
220 SET_DRIVE(DAP2, DISABLE, ENABLE, DIV_1, 51, 51, FASTEST, FASTEST),
223 SET_DRIVE(SDIO1, ENABLE, DISABLE, DIV_1, 54, 70, FASTEST, FASTEST),
226 SET_DRIVE(SDIO3, ENABLE, DISABLE, DIV_1, 20, 42, FASTEST, FASTEST),
229 SET_DRIVE_WITH_TYPE(GMA, ENABLE, DISABLE, DIV_1, 1, 2, FASTEST,
234 /* Initially setting all used GPIO's to non-TRISTATE */
235 static __initdata struct tegra_pingroup_config ardbeg_pinmux_set_nontristate[] = {
236 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
237 DEFAULT_PINMUX(GPIO_X4_AUD, RSVD, PULL_DOWN, NORMAL, OUTPUT),
238 DEFAULT_PINMUX(GPIO_X5_AUD, RSVD, PULL_UP, NORMAL, INPUT),
239 DEFAULT_PINMUX(GPIO_X6_AUD, RSVD3, PULL_UP, NORMAL, INPUT),
240 DEFAULT_PINMUX(GPIO_X7_AUD, RSVD, PULL_DOWN, NORMAL, OUTPUT),
241 DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, PULL_UP, NORMAL, INPUT),
242 DEFAULT_PINMUX(GPIO_W3_AUD, SPI6, PULL_UP, NORMAL, INPUT),
243 DEFAULT_PINMUX(GPIO_X1_AUD, RSVD3, PULL_DOWN, NORMAL, INPUT),
244 DEFAULT_PINMUX(GPIO_X3_AUD, RSVD3, PULL_UP, NORMAL, INPUT),
246 DEFAULT_PINMUX(DAP3_FS, I2S2, PULL_DOWN, NORMAL, OUTPUT),
247 DEFAULT_PINMUX(DAP3_DIN, I2S2, PULL_DOWN, NORMAL, OUTPUT),
248 DEFAULT_PINMUX(DAP3_DOUT, I2S2, PULL_DOWN, NORMAL, OUTPUT),
249 DEFAULT_PINMUX(DAP3_SCLK, I2S2, PULL_DOWN, NORMAL, OUTPUT),
250 DEFAULT_PINMUX(GPIO_PV0, RSVD3, NORMAL, NORMAL, INPUT),
251 DEFAULT_PINMUX(GPIO_PV1, RSVD, NORMAL, NORMAL, INPUT),
253 DEFAULT_PINMUX(GPIO_PBB3, RSVD3, PULL_DOWN, NORMAL, OUTPUT),
254 DEFAULT_PINMUX(GPIO_PBB5, RSVD3, PULL_DOWN, NORMAL, OUTPUT),
255 DEFAULT_PINMUX(GPIO_PBB6, RSVD3, PULL_DOWN, NORMAL, OUTPUT),
256 DEFAULT_PINMUX(GPIO_PBB7, RSVD3, PULL_DOWN, NORMAL, OUTPUT),
257 DEFAULT_PINMUX(GPIO_PCC1, RSVD3, PULL_DOWN, NORMAL, INPUT),
258 DEFAULT_PINMUX(GPIO_PCC2, RSVD3, PULL_DOWN, NORMAL, INPUT),
260 DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, OUTPUT),
261 DEFAULT_PINMUX(GMI_AD1, GMI, NORMAL, NORMAL, OUTPUT),
262 DEFAULT_PINMUX(GMI_AD10, GMI, PULL_DOWN, NORMAL, OUTPUT),
263 DEFAULT_PINMUX(GMI_AD11, GMI, PULL_DOWN, NORMAL, OUTPUT),
264 DEFAULT_PINMUX(GMI_AD12, GMI, PULL_UP, NORMAL, INPUT),
265 DEFAULT_PINMUX(GMI_AD13, GMI, PULL_DOWN, NORMAL, OUTPUT),
266 DEFAULT_PINMUX(GMI_AD2, GMI, NORMAL, NORMAL, INPUT),
267 DEFAULT_PINMUX(GMI_AD3, GMI, NORMAL, NORMAL, INPUT),
268 DEFAULT_PINMUX(GMI_AD8, GMI, PULL_DOWN, NORMAL, OUTPUT),
269 DEFAULT_PINMUX(GMI_ADV_N, GMI, PULL_UP, NORMAL, INPUT),
270 DEFAULT_PINMUX(GMI_CLK, GMI, PULL_DOWN, NORMAL, OUTPUT),
271 DEFAULT_PINMUX(GMI_CS0_N, GMI, PULL_UP, NORMAL, INPUT),
272 DEFAULT_PINMUX(GMI_CS2_N, GMI, PULL_UP, NORMAL, INPUT),
273 DEFAULT_PINMUX(GMI_CS3_N, GMI, PULL_UP, NORMAL, OUTPUT),
274 DEFAULT_PINMUX(GMI_CS4_N, GMI, PULL_UP, NORMAL, INPUT),
275 DEFAULT_PINMUX(GMI_CS7_N, GMI, PULL_UP, NORMAL, INPUT),
276 DEFAULT_PINMUX(GMI_DQS_P, GMI, PULL_UP, NORMAL, INPUT),
277 DEFAULT_PINMUX(GMI_IORDY, GMI, PULL_UP, NORMAL, INPUT),
278 DEFAULT_PINMUX(GMI_WP_N, GMI, PULL_UP, NORMAL, INPUT),
280 DEFAULT_PINMUX(SDMMC1_WP_N, SPI4, PULL_UP, NORMAL, OUTPUT),
281 DEFAULT_PINMUX(CLK2_REQ, RSVD3, NORMAL, NORMAL, OUTPUT),
283 DEFAULT_PINMUX(KB_COL3, KBC, PULL_UP, NORMAL, OUTPUT),
284 DEFAULT_PINMUX(KB_COL5, KBC, PULL_UP, NORMAL, INPUT),
285 DEFAULT_PINMUX(KB_COL6, KBC, PULL_UP, NORMAL, OUTPUT),
286 DEFAULT_PINMUX(KB_COL7, KBC, PULL_UP, NORMAL, OUTPUT),
287 DEFAULT_PINMUX(KB_ROW3, KBC, PULL_DOWN, NORMAL, INPUT),
288 DEFAULT_PINMUX(KB_ROW4, KBC, PULL_DOWN, NORMAL, INPUT),
289 DEFAULT_PINMUX(KB_ROW6, KBC, PULL_DOWN, NORMAL, INPUT),
290 DEFAULT_PINMUX(KB_ROW7, KBC, PULL_UP, NORMAL, INPUT),
291 DEFAULT_PINMUX(KB_ROW8, KBC, PULL_UP, NORMAL, INPUT),
293 DEFAULT_PINMUX(CLK3_REQ, RSVD3, NORMAL, NORMAL, OUTPUT),
294 DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
295 DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, INPUT),
296 DEFAULT_PINMUX(GPIO_PU6, PWM3, NORMAL, NORMAL, INPUT),
298 DEFAULT_PINMUX(HDMI_INT, RSVD, PULL_DOWN, NORMAL, INPUT),
300 DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
302 /* TODO: update for t124 ardbeg */
306 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
307 #include "board-ardbeg-pinmux-t11x.h"
309 #include "board-ardbeg-pinmux-t12x.h"
312 static void __init ardbeg_gpio_init_configure(void)
316 struct gpio_init_pin_info *pins_info;
318 len = ARRAY_SIZE(init_gpio_mode_ardbeg_common);
319 pins_info = init_gpio_mode_ardbeg_common;
321 for (i = 0; i < len; ++i) {
322 tegra_gpio_init_configure(pins_info->gpio_nr,
323 pins_info->is_input, pins_info->value);
328 int __init ardbeg_pinmux_init(void)
330 tegra_pinmux_config_table(ardbeg_pinmux_set_nontristate,
331 ARRAY_SIZE(ardbeg_pinmux_set_nontristate));
332 ardbeg_gpio_init_configure();
334 tegra_pinmux_config_table(ardbeg_pinmux_common, ARRAY_SIZE(ardbeg_pinmux_common));
335 tegra_drive_pinmux_config_table(ardbeg_drive_pinmux,
336 ARRAY_SIZE(ardbeg_drive_pinmux));
337 tegra_pinmux_config_table(unused_pins_lowpower,
338 ARRAY_SIZE(unused_pins_lowpower));