Revert "ARM: tegra12: enable DT support for host1x"
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-panel.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-panel.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20 #include <linux/ioport.h>
21 #include <linux/fb.h>
22 #include <linux/nvmap.h>
23 #include <linux/nvhost.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/gpio.h>
27 #include <linux/tegra_pwm_bl.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/pwm_backlight.h>
30 #include <linux/of.h>
31 #include <linux/dma-contiguous.h>
32
33 #include <mach/irqs.h>
34 #include <mach/dc.h>
35
36 #include "board.h"
37 #include "devices.h"
38 #include "gpio-names.h"
39 #include "board-ardbeg.h"
40 #include "board-panel.h"
41 #include "common.h"
42 #include "iomap.h"
43 #include "tegra12_host1x_devices.h"
44
45
46 struct platform_device * __init ardbeg_host1x_init(void)
47 {
48         struct platform_device *pdev = NULL;
49
50 #ifdef CONFIG_TEGRA_GRHOST
51         pdev = tegra12_register_host1x_devices();
52
53         if (!pdev) {
54                 pr_err("host1x devices registration failed\n");
55                 return NULL;
56         }
57 #endif
58         return pdev;
59 }
60
61 /* hdmi related regulators */
62 static struct regulator *ardbeg_hdmi_reg;
63 static struct regulator *ardbeg_hdmi_pll;
64 static struct regulator *ardbeg_hdmi_vddio;
65
66 static struct resource ardbeg_disp1_resources[] = {
67         {
68                 .name   = "irq",
69                 .start  = INT_DISPLAY_GENERAL,
70                 .end    = INT_DISPLAY_GENERAL,
71                 .flags  = IORESOURCE_IRQ,
72         },
73         {
74                 .name   = "regs",
75                 .start  = TEGRA_DISPLAY_BASE,
76                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
77                 .flags  = IORESOURCE_MEM,
78         },
79         {
80                 .name   = "fbmem",
81                 .start  = 0, /* Filled in by ardbeg_panel_init() */
82                 .end    = 0, /* Filled in by ardbeg_panel_init() */
83                 .flags  = IORESOURCE_MEM,
84         },
85         {
86                 .name   = "ganged_dsia_regs",
87                 .start  = 0, /* Filled in the panel file by init_resources() */
88                 .end    = 0, /* Filled in the panel file by init_resources() */
89                 .flags  = IORESOURCE_MEM,
90         },
91         {
92                 .name   = "ganged_dsib_regs",
93                 .start  = 0, /* Filled in the panel file by init_resources() */
94                 .end    = 0, /* Filled in the panel file by init_resources() */
95                 .flags  = IORESOURCE_MEM,
96         },
97         {
98                 .name   = "dsi_regs",
99                 .start  = 0, /* Filled in the panel file by init_resources() */
100                 .end    = 0, /* Filled in the panel file by init_resources() */
101                 .flags  = IORESOURCE_MEM,
102         },
103         {
104                 .name   = "mipi_cal",
105                 .start  = TEGRA_MIPI_CAL_BASE,
106                 .end    = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
107                 .flags  = IORESOURCE_MEM,
108         },
109 };
110
111 static struct resource ardbeg_disp1_edp_resources[] = {
112         {
113                 .name   = "irq",
114                 .start  = INT_DISPLAY_GENERAL,
115                 .end    = INT_DISPLAY_GENERAL,
116                 .flags  = IORESOURCE_IRQ,
117         },
118         {
119                 .name   = "regs",
120                 .start  = TEGRA_DISPLAY_BASE,
121                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
122                 .flags  = IORESOURCE_MEM,
123         },
124         {
125                 .name   = "fbmem",
126                 .start  = 0, /* Filled in by ardbeg_panel_init() */
127                 .end    = 0, /* Filled in by ardbeg_panel_init() */
128                 .flags  = IORESOURCE_MEM,
129         },
130         {
131                 .name   = "mipi_cal",
132                 .start  = TEGRA_MIPI_CAL_BASE,
133                 .end    = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
134                 .flags  = IORESOURCE_MEM,
135         },
136         {
137                 .name   = "sor",
138                 .start  = TEGRA_SOR_BASE,
139                 .end    = TEGRA_SOR_BASE + TEGRA_SOR_SIZE - 1,
140                 .flags  = IORESOURCE_MEM,
141         },
142         {
143                 .name   = "dpaux",
144                 .start  = TEGRA_DPAUX_BASE,
145                 .end    = TEGRA_DPAUX_BASE + TEGRA_DPAUX_SIZE - 1,
146                 .flags  = IORESOURCE_MEM,
147         },
148         {
149                 .name   = "irq_dp",
150                 .start  = INT_DPAUX,
151                 .end    = INT_DPAUX,
152                 .flags  = IORESOURCE_IRQ,
153         },
154 };
155
156 static struct resource ardbeg_disp2_resources[] = {
157         {
158                 .name   = "irq",
159                 .start  = INT_DISPLAY_B_GENERAL,
160                 .end    = INT_DISPLAY_B_GENERAL,
161                 .flags  = IORESOURCE_IRQ,
162         },
163         {
164                 .name   = "regs",
165                 .start  = TEGRA_DISPLAY2_BASE,
166                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
167                 .flags  = IORESOURCE_MEM,
168         },
169         {
170                 .name   = "fbmem",
171                 .start  = 0, /* Filled in by ardbeg_panel_init() */
172                 .end    = 0, /* Filled in by ardbeg_panel_init() */
173                 .flags  = IORESOURCE_MEM,
174         },
175         {
176                 .name   = "hdmi_regs",
177                 .start  = TEGRA_HDMI_BASE,
178                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
179                 .flags  = IORESOURCE_MEM,
180         },
181 };
182
183
184 static struct tegra_dc_sd_settings sd_settings;
185
186 static struct tegra_dc_out ardbeg_disp1_out = {
187         .type           = TEGRA_DC_OUT_DSI,
188         .sd_settings    = &sd_settings,
189 };
190
191 static int ardbeg_hdmi_enable(struct device *dev)
192 {
193         int ret;
194         if (!ardbeg_hdmi_reg) {
195                 ardbeg_hdmi_reg = regulator_get(dev, "avdd_hdmi");
196                 if (IS_ERR_OR_NULL(ardbeg_hdmi_reg)) {
197                         pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
198                         ardbeg_hdmi_reg = NULL;
199                         return PTR_ERR(ardbeg_hdmi_reg);
200                 }
201         }
202         ret = regulator_enable(ardbeg_hdmi_reg);
203         if (ret < 0) {
204                 pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
205                 return ret;
206         }
207         if (!ardbeg_hdmi_pll) {
208                 ardbeg_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll");
209                 if (IS_ERR_OR_NULL(ardbeg_hdmi_pll)) {
210                         pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
211                         ardbeg_hdmi_pll = NULL;
212                         regulator_put(ardbeg_hdmi_reg);
213                         ardbeg_hdmi_reg = NULL;
214                         return PTR_ERR(ardbeg_hdmi_pll);
215                 }
216         }
217         ret = regulator_enable(ardbeg_hdmi_pll);
218         if (ret < 0) {
219                 pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
220                 return ret;
221         }
222         return 0;
223 }
224
225 static int ardbeg_hdmi_disable(void)
226 {
227         if (ardbeg_hdmi_reg) {
228                 regulator_disable(ardbeg_hdmi_reg);
229                 regulator_put(ardbeg_hdmi_reg);
230                 ardbeg_hdmi_reg = NULL;
231         }
232
233         if (ardbeg_hdmi_pll) {
234                 regulator_disable(ardbeg_hdmi_pll);
235                 regulator_put(ardbeg_hdmi_pll);
236                 ardbeg_hdmi_pll = NULL;
237         }
238         return 0;
239 }
240
241 static int ardbeg_hdmi_postsuspend(void)
242 {
243         if (ardbeg_hdmi_vddio) {
244                 regulator_disable(ardbeg_hdmi_vddio);
245                 regulator_put(ardbeg_hdmi_vddio);
246                 ardbeg_hdmi_vddio = NULL;
247         }
248         return 0;
249 }
250
251 static int ardbeg_hdmi_hotplug_init(struct device *dev)
252 {
253         if (!ardbeg_hdmi_vddio) {
254                 ardbeg_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0");
255                 if (WARN_ON(IS_ERR(ardbeg_hdmi_vddio))) {
256                         pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %ld\n",
257                                 __func__, PTR_ERR(ardbeg_hdmi_vddio));
258                                 ardbeg_hdmi_vddio = NULL;
259                 } else {
260                         regulator_enable(ardbeg_hdmi_vddio);
261                 }
262         }
263
264         return 0;
265 }
266
267 struct tmds_config ardbeg_tmds_config[] = {
268         { /* 480p/576p / 25.2MHz/27MHz modes */
269         .pclk = 27000000,
270         .pll0 = 0x01003110,
271         .pll1 = 0x00300F00,
272         .pe_current = 0x08080808,
273         .drive_current = 0x2e2e2e2e,
274         .peak_current = 0x00000000,
275         },
276         { /* 720p / 74.25MHz modes */
277         .pclk = 74250000,
278         .pll0 =  0x01003310,
279         .pll1 = 0x10300F00,
280         .pe_current = 0x08080808,
281         .drive_current = 0x20202020,
282         .peak_current = 0x00000000,
283         },
284         { /* 1080p / 148.5MHz modes */
285         .pclk = 148500000,
286         .pll0 = 0x01003310,
287         .pll1 = 0x10300F00,
288         .pe_current = 0x08080808,
289         .drive_current = 0x20202020,
290         .peak_current = 0x00000000,
291         },
292         {
293         .pclk = INT_MAX,
294         .pll0 = 0x01003310,
295         .pll1 = 0x10300F00,
296         .pe_current = 0x08080808,
297         .drive_current = 0x3A353536, /* lane3 needs a slightly lower current */
298         .peak_current = 0x00000000,
299         },
300 };
301
302 struct tegra_hdmi_out ardbeg_hdmi_out = {
303         .tmds_config = ardbeg_tmds_config,
304         .n_tmds_config = ARRAY_SIZE(ardbeg_tmds_config),
305 };
306
307
308 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
309 static struct tegra_dc_mode hdmi_panel_modes[] = {
310         {
311                 .pclk =                 KHZ2PICOS(25200),
312                 .h_ref_to_sync =        1,
313                 .v_ref_to_sync =        1,
314                 .h_sync_width =         96,     /* hsync_len */
315                 .v_sync_width =         2,      /* vsync_len */
316                 .h_back_porch =         48,     /* left_margin */
317                 .v_back_porch =         33,     /* upper_margin */
318                 .h_active =             640,    /* xres */
319                 .v_active =             480,    /* yres */
320                 .h_front_porch =        16,     /* right_margin */
321                 .v_front_porch =        10,     /* lower_margin */
322         },
323 };
324 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
325
326 static struct tegra_dc_out ardbeg_disp2_out = {
327         .type           = TEGRA_DC_OUT_HDMI,
328         .flags          = TEGRA_DC_OUT_HOTPLUG_HIGH,
329         .parent_clk     = "pll_d2",
330
331         .dcc_bus        = 3,
332         .hotplug_gpio   = ardbeg_hdmi_hpd,
333         .hdmi_out       = &ardbeg_hdmi_out,
334
335         /* TODO: update max pclk to POR */
336         .max_pixclock   = KHZ2PICOS(297000),
337 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
338         .modes = hdmi_panel_modes,
339         .n_modes = ARRAY_SIZE(hdmi_panel_modes),
340         .depth = 24,
341 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
342
343         .align          = TEGRA_DC_ALIGN_MSB,
344         .order          = TEGRA_DC_ORDER_RED_BLUE,
345
346         .enable         = ardbeg_hdmi_enable,
347         .disable        = ardbeg_hdmi_disable,
348         .postsuspend    = ardbeg_hdmi_postsuspend,
349         .hotplug_init   = ardbeg_hdmi_hotplug_init,
350 };
351
352 static struct tegra_fb_data ardbeg_disp1_fb_data = {
353         .win            = 0,
354         .bits_per_pixel = 32,
355         .flags          = TEGRA_FB_FLIP_ON_PROBE,
356 };
357
358 static struct tegra_dc_platform_data ardbeg_disp1_pdata = {
359         .flags          = TEGRA_DC_FLAG_ENABLED,
360         .default_out    = &ardbeg_disp1_out,
361         .fb             = &ardbeg_disp1_fb_data,
362         .emc_clk_rate   = 204000000,
363 #ifdef CONFIG_TEGRA_DC_CMU
364         .cmu_enable     = 1,
365 #endif
366 };
367
368 static struct tegra_fb_data ardbeg_disp2_fb_data = {
369         .win            = 0,
370         .xres           = 1280,
371         .yres           = 720,
372         .bits_per_pixel = 32,
373         .flags          = TEGRA_FB_FLIP_ON_PROBE,
374 };
375
376 static struct tegra_dc_platform_data ardbeg_disp2_pdata = {
377         .flags          = TEGRA_DC_FLAG_ENABLED,
378         .default_out    = &ardbeg_disp2_out,
379         .fb             = &ardbeg_disp2_fb_data,
380         .emc_clk_rate   = 300000000,
381 };
382
383 static struct platform_device ardbeg_disp2_device = {
384         .name           = "tegradc",
385         .id             = 1,
386         .resource       = ardbeg_disp2_resources,
387         .num_resources  = ARRAY_SIZE(ardbeg_disp2_resources),
388         .dev = {
389                 .platform_data = &ardbeg_disp2_pdata,
390         },
391 };
392
393 static struct platform_device ardbeg_disp1_device = {
394         .name           = "tegradc",
395         .id             = 0,
396         .resource       = ardbeg_disp1_resources,
397         .num_resources  = ARRAY_SIZE(ardbeg_disp1_resources),
398         .dev = {
399                 .platform_data = &ardbeg_disp1_pdata,
400         },
401 };
402
403 static struct nvmap_platform_carveout ardbeg_carveouts[] = {
404         [0] = {
405                 .name           = "iram",
406                 .usage_mask     = NVMAP_HEAP_CARVEOUT_IRAM,
407                 .base           = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
408                 .size           = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
409         },
410         [1] = {
411                 .name           = "generic-0",
412                 .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
413                 .base           = 0, /* Filled in by ardbeg_panel_init() */
414                 .size           = 0, /* Filled in by ardbeg_panel_init() */
415         },
416         [2] = {
417                 .name           = "vpr",
418                 .usage_mask     = NVMAP_HEAP_CARVEOUT_VPR,
419                 .base           = 0, /* Filled in by ardbeg_panel_init() */
420                 .size           = 0, /* Filled in by ardbeg_panel_init() */
421         },
422 };
423
424 static struct nvmap_platform_data ardbeg_nvmap_data = {
425         .carveouts      = ardbeg_carveouts,
426         .nr_carveouts   = ARRAY_SIZE(ardbeg_carveouts),
427 };
428 static struct platform_device ardbeg_nvmap_device  = {
429         .name   = "tegra-nvmap",
430         .id     = -1,
431         .dev    = {
432                 .platform_data = &ardbeg_nvmap_data,
433         },
434 };
435
436 static struct tegra_dc_sd_settings ardbeg_sd_settings = {
437         .enable = 1, /* enabled by default. */
438         .use_auto_pwm = false,
439         .hw_update_delay = 0,
440         .bin_width = -1,
441         .aggressiveness = 5,
442         .use_vid_luma = false,
443         .phase_in_adjustments = 0,
444         .k_limit_enable = true,
445         .k_limit = 200,
446         .sd_window_enable = false,
447         .soft_clipping_enable = true,
448         /* Low soft clipping threshold to compensate for aggressive k_limit */
449         .soft_clipping_threshold = 128,
450         .smooth_k_enable = false,
451         .smooth_k_incr = 64,
452         /* Default video coefficients */
453         .coeff = {5, 9, 2},
454         .fc = {0, 0},
455         /* Immediate backlight changes */
456         .blp = {1024, 255},
457         /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
458         /* Default BL TF */
459         .bltf = {
460                         {
461                                 {57, 65, 73, 82},
462                                 {92, 103, 114, 125},
463                                 {138, 150, 164, 178},
464                                 {193, 208, 224, 241},
465                         },
466                 },
467         /* Default LUT */
468         .lut = {
469                         {
470                                 {255, 255, 255},
471                                 {199, 199, 199},
472                                 {153, 153, 153},
473                                 {116, 116, 116},
474                                 {85, 85, 85},
475                                 {59, 59, 59},
476                                 {36, 36, 36},
477                                 {17, 17, 17},
478                                 {0, 0, 0},
479                         },
480                 },
481         .sd_brightness = &sd_brightness,
482         .use_vpulse2 = true,
483 };
484
485 static void ardbeg_panel_select(void)
486 {
487         struct tegra_panel *panel = NULL;
488         struct board_info board;
489         u8 dsi_instance;
490
491         tegra_get_display_board_info(&board);
492
493         switch (board.board_id) {
494         case BOARD_E1639:
495         case BOARD_E1813:
496                 panel = &dsi_s_wqxga_10_1;
497                 dsi_instance = DSI_INSTANCE_0;
498                 break;
499         case BOARD_PM354:
500                 panel = &dsi_a_1080p_14_0;
501                 dsi_instance = DSI_INSTANCE_0;
502                 break;
503         case BOARD_E1627:
504                 panel = &dsi_p_wuxga_10_1;
505                 dsi_instance = DSI_INSTANCE_0;
506                 break;
507         case BOARD_E1549:
508                 panel = &dsi_lgd_wxga_7_0;
509                 dsi_instance = DSI_INSTANCE_0;
510                 break;
511         case BOARD_PM363:
512         case BOARD_E1824:
513                 panel = &edp_a_1080p_14_0;
514                 ardbeg_disp1_out.type = TEGRA_DC_OUT_DP;
515                 ardbeg_disp1_device.resource = ardbeg_disp1_edp_resources;
516                 ardbeg_disp1_device.num_resources =
517                         ARRAY_SIZE(ardbeg_disp1_edp_resources);
518                 break;
519         case BOARD_PM366:
520                 panel = &lvds_c_1366_14;
521                 ardbeg_disp1_out.type = TEGRA_DC_OUT_LVDS;
522                 ardbeg_disp1_device.resource = ardbeg_disp1_edp_resources;
523                 ardbeg_disp1_device.num_resources =
524                         ARRAY_SIZE(ardbeg_disp1_edp_resources);
525                 break;
526         default:
527                 panel = &dsi_p_wuxga_10_1;
528                 dsi_instance = DSI_INSTANCE_0;
529                 break;
530         }
531
532         if (panel) {
533                 if (panel->init_sd_settings)
534                         panel->init_sd_settings(&sd_settings);
535
536                 if (panel->init_dc_out) {
537                         panel->init_dc_out(&ardbeg_disp1_out);
538                         if (ardbeg_disp1_out.type == TEGRA_DC_OUT_DSI) {
539                                 ardbeg_disp1_out.dsi->dsi_instance =
540                                         dsi_instance;
541                                 ardbeg_disp1_out.dsi->dsi_panel_rst_gpio =
542                                         DSI_PANEL_RST_GPIO;
543                                 ardbeg_disp1_out.dsi->dsi_panel_bl_pwm_gpio =
544                                         DSI_PANEL_BL_PWM_GPIO;
545                                 ardbeg_disp1_out.dsi->te_gpio = TEGRA_GPIO_PR6;
546                         }
547                 }
548
549                 if (panel->init_fb_data)
550                         panel->init_fb_data(&ardbeg_disp1_fb_data);
551
552                 if (panel->init_cmu_data)
553                         panel->init_cmu_data(&ardbeg_disp1_pdata);
554
555                 if (panel->set_disp_device)
556                         panel->set_disp_device(&ardbeg_disp1_device);
557
558                 if (ardbeg_disp1_out.type == TEGRA_DC_OUT_DSI) {
559                         tegra_dsi_resources_init(dsi_instance,
560                                 ardbeg_disp1_resources,
561                                 ARRAY_SIZE(ardbeg_disp1_resources));
562                 }
563
564                 if (panel->register_bl_dev)
565                         panel->register_bl_dev();
566
567                 if (panel->register_i2c_bridge)
568                         panel->register_i2c_bridge();
569         }
570
571 }
572 int __init ardbeg_panel_init(void)
573 {
574         int err = 0;
575         struct resource __maybe_unused *res;
576         struct platform_device *phost1x = NULL;
577
578         sd_settings = ardbeg_sd_settings;
579
580         ardbeg_panel_select();
581
582 #ifdef CONFIG_TEGRA_NVMAP
583         ardbeg_carveouts[1].base = tegra_carveout_start;
584         ardbeg_carveouts[1].size = tegra_carveout_size;
585         ardbeg_carveouts[2].base = tegra_vpr_start;
586         ardbeg_carveouts[2].size = tegra_vpr_size;
587 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
588         ardbeg_carveouts[1].cma_dev = &tegra_generic_cma_dev;
589         ardbeg_carveouts[1].resize = false;
590         ardbeg_carveouts[2].cma_dev = &tegra_vpr_cma_dev;
591         ardbeg_carveouts[2].resize = true;
592         ardbeg_carveouts[2].cma_chunk_size = SZ_32M;
593 #endif
594
595         err = platform_device_register(&ardbeg_nvmap_device);
596         if (err) {
597                 pr_err("nvmap device registration failed\n");
598                 return err;
599         }
600 #endif
601
602         phost1x = ardbeg_host1x_init();
603         if (!phost1x) {
604                 pr_err("host1x devices registration failed\n");
605                 return -EINVAL;
606         }
607
608         res = platform_get_resource_byname(&ardbeg_disp1_device,
609                                          IORESOURCE_MEM, "fbmem");
610         res->start = tegra_fb_start;
611         res->end = tegra_fb_start + tegra_fb_size - 1;
612
613         /* Copy the bootloader fb to the fb. */
614         if (tegra_bootloader_fb_size)
615                 __tegra_move_framebuffer(&ardbeg_nvmap_device,
616                                 tegra_fb_start, tegra_bootloader_fb_start,
617                                 min(tegra_fb_size, tegra_bootloader_fb_size));
618         else
619                 __tegra_clear_framebuffer(&ardbeg_nvmap_device,
620                                           tegra_fb_start, tegra_fb_size);
621
622         ardbeg_disp1_device.dev.parent = &phost1x->dev;
623         err = platform_device_register(&ardbeg_disp1_device);
624         if (err) {
625                 pr_err("disp1 device registration failed\n");
626                 return err;
627         }
628
629         err = tegra_init_hdmi(&ardbeg_disp2_device, phost1x);
630         if (err)
631                 return err;
632
633 #ifdef CONFIG_TEGRA_NVAVP
634         nvavp_device.dev.parent = &phost1x->dev;
635         err = platform_device_register(&nvavp_device);
636         if (err) {
637                 pr_err("nvavp device registration failed\n");
638                 return err;
639         }
640 #endif
641         return err;
642 }