arm: tegra: remove setting of buddy_size in nvmap_platform_data
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-panel.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-panel.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20 #include <linux/ioport.h>
21 #include <linux/fb.h>
22 #include <linux/nvmap.h>
23 #include <linux/nvhost.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/gpio.h>
27 #include <linux/tegra_pwm_bl.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/pwm_backlight.h>
30 #include <linux/of.h>
31
32 #include <mach/irqs.h>
33 #include <mach/dc.h>
34
35 #include "board.h"
36 #include "devices.h"
37 #include "gpio-names.h"
38 #include "board-ardbeg.h"
39 #include "board-panel.h"
40 #include "common.h"
41 #include "iomap.h"
42 #include "tegra12_host1x_devices.h"
43
44
45 struct platform_device * __init ardbeg_host1x_init(void)
46 {
47         struct platform_device *pdev = NULL;
48
49 #ifdef CONFIG_TEGRA_GRHOST
50         pdev = tegra12_register_host1x_devices();
51
52         if (!pdev) {
53                 pr_err("host1x devices registration failed\n");
54                 return NULL;
55         }
56 #endif
57         return pdev;
58 }
59
60 /* hdmi related regulators */
61 static struct regulator *ardbeg_hdmi_reg;
62 static struct regulator *ardbeg_hdmi_pll;
63 static struct regulator *ardbeg_hdmi_vddio;
64
65 static struct resource ardbeg_disp1_resources[] = {
66         {
67                 .name   = "irq",
68                 .start  = INT_DISPLAY_GENERAL,
69                 .end    = INT_DISPLAY_GENERAL,
70                 .flags  = IORESOURCE_IRQ,
71         },
72         {
73                 .name   = "regs",
74                 .start  = TEGRA_DISPLAY_BASE,
75                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
76                 .flags  = IORESOURCE_MEM,
77         },
78         {
79                 .name   = "fbmem",
80                 .start  = 0, /* Filled in by ardbeg_panel_init() */
81                 .end    = 0, /* Filled in by ardbeg_panel_init() */
82                 .flags  = IORESOURCE_MEM,
83         },
84         {
85                 .name   = "ganged_dsia_regs",
86                 .start  = 0, /* Filled in the panel file by init_resources() */
87                 .end    = 0, /* Filled in the panel file by init_resources() */
88                 .flags  = IORESOURCE_MEM,
89         },
90         {
91                 .name   = "ganged_dsib_regs",
92                 .start  = 0, /* Filled in the panel file by init_resources() */
93                 .end    = 0, /* Filled in the panel file by init_resources() */
94                 .flags  = IORESOURCE_MEM,
95         },
96         {
97                 .name   = "dsi_regs",
98                 .start  = 0, /* Filled in the panel file by init_resources() */
99                 .end    = 0, /* Filled in the panel file by init_resources() */
100                 .flags  = IORESOURCE_MEM,
101         },
102         {
103                 .name   = "mipi_cal",
104                 .start  = TEGRA_MIPI_CAL_BASE,
105                 .end    = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
106                 .flags  = IORESOURCE_MEM,
107         },
108 };
109
110 static struct resource ardbeg_disp1_edp_resources[] = {
111         {
112                 .name   = "irq",
113                 .start  = INT_DISPLAY_GENERAL,
114                 .end    = INT_DISPLAY_GENERAL,
115                 .flags  = IORESOURCE_IRQ,
116         },
117         {
118                 .name   = "regs",
119                 .start  = TEGRA_DISPLAY_BASE,
120                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
121                 .flags  = IORESOURCE_MEM,
122         },
123         {
124                 .name   = "fbmem",
125                 .start  = 0, /* Filled in by ardbeg_panel_init() */
126                 .end    = 0, /* Filled in by ardbeg_panel_init() */
127                 .flags  = IORESOURCE_MEM,
128         },
129         {
130                 .name   = "mipi_cal",
131                 .start  = TEGRA_MIPI_CAL_BASE,
132                 .end    = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
133                 .flags  = IORESOURCE_MEM,
134         },
135         {
136                 .name   = "sor",
137                 .start  = TEGRA_SOR_BASE,
138                 .end    = TEGRA_SOR_BASE + TEGRA_SOR_SIZE - 1,
139                 .flags  = IORESOURCE_MEM,
140         },
141         {
142                 .name   = "dpaux",
143                 .start  = TEGRA_DPAUX_BASE,
144                 .end    = TEGRA_DPAUX_BASE + TEGRA_DPAUX_SIZE - 1,
145                 .flags  = IORESOURCE_MEM,
146         },
147 };
148
149 static struct resource ardbeg_disp2_resources[] = {
150         {
151                 .name   = "irq",
152                 .start  = INT_DISPLAY_B_GENERAL,
153                 .end    = INT_DISPLAY_B_GENERAL,
154                 .flags  = IORESOURCE_IRQ,
155         },
156         {
157                 .name   = "regs",
158                 .start  = TEGRA_DISPLAY2_BASE,
159                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
160                 .flags  = IORESOURCE_MEM,
161         },
162         {
163                 .name   = "fbmem",
164                 .start  = 0, /* Filled in by ardbeg_panel_init() */
165                 .end    = 0, /* Filled in by ardbeg_panel_init() */
166                 .flags  = IORESOURCE_MEM,
167         },
168         {
169                 .name   = "hdmi_regs",
170                 .start  = TEGRA_HDMI_BASE,
171                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
172                 .flags  = IORESOURCE_MEM,
173         },
174 };
175
176
177 static struct tegra_dc_sd_settings sd_settings;
178
179 static struct tegra_dc_out ardbeg_disp1_out = {
180         .type           = TEGRA_DC_OUT_DSI,
181         .sd_settings    = &sd_settings,
182 };
183
184 static int ardbeg_hdmi_enable(struct device *dev)
185 {
186         int ret;
187         if (!ardbeg_hdmi_reg) {
188                 ardbeg_hdmi_reg = regulator_get(dev, "avdd_hdmi");
189                 if (IS_ERR_OR_NULL(ardbeg_hdmi_reg)) {
190                         pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
191                         ardbeg_hdmi_reg = NULL;
192                         return PTR_ERR(ardbeg_hdmi_reg);
193                 }
194         }
195         ret = regulator_enable(ardbeg_hdmi_reg);
196         if (ret < 0) {
197                 pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
198                 return ret;
199         }
200         if (!ardbeg_hdmi_pll) {
201                 ardbeg_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll");
202                 if (IS_ERR_OR_NULL(ardbeg_hdmi_pll)) {
203                         pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
204                         ardbeg_hdmi_pll = NULL;
205                         regulator_put(ardbeg_hdmi_reg);
206                         ardbeg_hdmi_reg = NULL;
207                         return PTR_ERR(ardbeg_hdmi_pll);
208                 }
209         }
210         ret = regulator_enable(ardbeg_hdmi_pll);
211         if (ret < 0) {
212                 pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
213                 return ret;
214         }
215         return 0;
216 }
217
218 static int ardbeg_hdmi_disable(void)
219 {
220         if (ardbeg_hdmi_reg) {
221                 regulator_disable(ardbeg_hdmi_reg);
222                 regulator_put(ardbeg_hdmi_reg);
223                 ardbeg_hdmi_reg = NULL;
224         }
225
226         if (ardbeg_hdmi_pll) {
227                 regulator_disable(ardbeg_hdmi_pll);
228                 regulator_put(ardbeg_hdmi_pll);
229                 ardbeg_hdmi_pll = NULL;
230         }
231         return 0;
232 }
233
234 static int ardbeg_hdmi_postsuspend(void)
235 {
236         if (ardbeg_hdmi_vddio) {
237                 regulator_disable(ardbeg_hdmi_vddio);
238                 regulator_put(ardbeg_hdmi_vddio);
239                 ardbeg_hdmi_vddio = NULL;
240         }
241         return 0;
242 }
243
244 static int ardbeg_hdmi_hotplug_init(struct device *dev)
245 {
246         if (!ardbeg_hdmi_vddio) {
247                 ardbeg_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0");
248                 if (WARN_ON(IS_ERR(ardbeg_hdmi_vddio))) {
249                         pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %ld\n",
250                                 __func__, PTR_ERR(ardbeg_hdmi_vddio));
251                                 ardbeg_hdmi_vddio = NULL;
252                 } else {
253                         regulator_enable(ardbeg_hdmi_vddio);
254                 }
255         }
256
257         return 0;
258 }
259
260 /* Electrical characteristics for HDMI, all modes must be declared here */
261 struct tmds_config ardbeg_tmds_config[] = {
262         { /* 480p : 27 MHz and below */
263                 .pclk = 27000000,
264                 .pll0 = 0x01003010,
265                 .pll1 = 0x00301b00,
266                 .drive_current = 0x23232323,
267                 .pe_current = 0x00000000,
268                 .peak_current = 0x00000000,
269         },
270         { /* 720p : 74.25MHz modes */
271                 .pclk = 74250000,
272                 .pll0 = 0x01003110,
273                 .pll1 = 0x00301b00,
274                 .drive_current = 0x25252525,
275                 .pe_current = 0x00000000,
276                 .peak_current = 0x03030303,
277         },
278         { /* 1080p : 148.5MHz modes */
279                 .pclk = 148500000,
280                 .pll0 = 0x01003310,
281                 .pll1 = 0x00301b00,
282                 .drive_current = 0x27272727,
283                 .pe_current = 0x00000000,
284                 .peak_current = 0x03030303,
285         },
286         { /* 4K : 297MHz modes */
287                 .pclk = INT_MAX,
288                 .pll0 = 0x01003f10,
289                 .pll1 = 0x00300f00,
290                 .drive_current = 0x303f3f3f,
291                 .pe_current = 0x00000000,
292                 .peak_current = 0x040f0f0f,
293         },
294 };
295
296 struct tegra_hdmi_out ardbeg_hdmi_out = {
297         .tmds_config = ardbeg_tmds_config,
298         .n_tmds_config = ARRAY_SIZE(ardbeg_tmds_config),
299 };
300
301
302 static struct tegra_dc_out ardbeg_disp2_out = {
303         .type           = TEGRA_DC_OUT_HDMI,
304         .flags          = TEGRA_DC_OUT_HOTPLUG_HIGH,
305         .parent_clk     = "pll_d2",
306
307         .dcc_bus        = 3,
308         .hotplug_gpio   = ardbeg_hdmi_hpd,
309         .hdmi_out       = &ardbeg_hdmi_out,
310
311         /* TODO: update max pclk to POR */
312         .max_pixclock   = KHZ2PICOS(297000),
313
314         .align          = TEGRA_DC_ALIGN_MSB,
315         .order          = TEGRA_DC_ORDER_RED_BLUE,
316
317         .enable         = ardbeg_hdmi_enable,
318         .disable        = ardbeg_hdmi_disable,
319         .postsuspend    = ardbeg_hdmi_postsuspend,
320         .hotplug_init   = ardbeg_hdmi_hotplug_init,
321 };
322
323 static struct tegra_fb_data ardbeg_disp1_fb_data = {
324         .win            = 0,
325         .bits_per_pixel = 32,
326         .flags          = TEGRA_FB_FLIP_ON_PROBE,
327 };
328
329 static struct tegra_dc_platform_data ardbeg_disp1_pdata = {
330         .flags          = TEGRA_DC_FLAG_ENABLED,
331         .default_out    = &ardbeg_disp1_out,
332         .fb             = &ardbeg_disp1_fb_data,
333         .emc_clk_rate   = 204000000,
334 #ifdef CONFIG_TEGRA_DC_CMU
335         .cmu_enable     = 1,
336 #endif
337 };
338
339 static struct tegra_fb_data ardbeg_disp2_fb_data = {
340         .win            = 0,
341         .xres           = 1280,
342         .yres           = 720,
343         .bits_per_pixel = 32,
344         .flags          = TEGRA_FB_FLIP_ON_PROBE,
345 };
346
347 static struct tegra_dc_platform_data ardbeg_disp2_pdata = {
348         .flags          = TEGRA_DC_FLAG_ENABLED,
349         .default_out    = &ardbeg_disp2_out,
350         .fb             = &ardbeg_disp2_fb_data,
351         .emc_clk_rate   = 300000000,
352 };
353
354 static struct platform_device ardbeg_disp2_device = {
355         .name           = "tegradc",
356         .id             = 1,
357         .resource       = ardbeg_disp2_resources,
358         .num_resources  = ARRAY_SIZE(ardbeg_disp2_resources),
359         .dev = {
360                 .platform_data = &ardbeg_disp2_pdata,
361         },
362 };
363
364 static struct platform_device ardbeg_disp1_device = {
365         .name           = "tegradc",
366         .id             = 0,
367         .resource       = ardbeg_disp1_resources,
368         .num_resources  = ARRAY_SIZE(ardbeg_disp1_resources),
369         .dev = {
370                 .platform_data = &ardbeg_disp1_pdata,
371         },
372 };
373
374 static struct nvmap_platform_carveout ardbeg_carveouts[] = {
375         [0] = {
376                 .name           = "iram",
377                 .usage_mask     = NVMAP_HEAP_CARVEOUT_IRAM,
378                 .base           = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
379                 .size           = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
380         },
381         [1] = {
382                 .name           = "generic-0",
383                 .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
384                 .base           = 0, /* Filled in by ardbeg_panel_init() */
385                 .size           = 0, /* Filled in by ardbeg_panel_init() */
386         },
387         [2] = {
388                 .name           = "vpr",
389                 .usage_mask     = NVMAP_HEAP_CARVEOUT_VPR,
390                 .base           = 0, /* Filled in by ardbeg_panel_init() */
391                 .size           = 0, /* Filled in by ardbeg_panel_init() */
392         },
393 };
394
395 static struct nvmap_platform_data ardbeg_nvmap_data = {
396         .carveouts      = ardbeg_carveouts,
397         .nr_carveouts   = ARRAY_SIZE(ardbeg_carveouts),
398 };
399 static struct platform_device ardbeg_nvmap_device  = {
400         .name   = "tegra-nvmap",
401         .id     = -1,
402         .dev    = {
403                 .platform_data = &ardbeg_nvmap_data,
404         },
405 };
406
407 static struct tegra_dc_sd_settings ardbeg_sd_settings = {
408         .enable = 1, /* enabled by default. */
409         .use_auto_pwm = false,
410         .hw_update_delay = 0,
411         .bin_width = -1,
412         .aggressiveness = 5,
413         .use_vid_luma = false,
414         .phase_in_adjustments = 0,
415         .k_limit_enable = true,
416         .k_limit = 200,
417         .sd_window_enable = false,
418         .soft_clipping_enable = true,
419         /* Low soft clipping threshold to compensate for aggressive k_limit */
420         .soft_clipping_threshold = 128,
421         .smooth_k_enable = false,
422         .smooth_k_incr = 64,
423         /* Default video coefficients */
424         .coeff = {5, 9, 2},
425         .fc = {0, 0},
426         /* Immediate backlight changes */
427         .blp = {1024, 255},
428         /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
429         /* Default BL TF */
430         .bltf = {
431                         {
432                                 {57, 65, 73, 82},
433                                 {92, 103, 114, 125},
434                                 {138, 150, 164, 178},
435                                 {193, 208, 224, 241},
436                         },
437                 },
438         /* Default LUT */
439         .lut = {
440                         {
441                                 {255, 255, 255},
442                                 {199, 199, 199},
443                                 {153, 153, 153},
444                                 {116, 116, 116},
445                                 {85, 85, 85},
446                                 {59, 59, 59},
447                                 {36, 36, 36},
448                                 {17, 17, 17},
449                                 {0, 0, 0},
450                         },
451                 },
452         .sd_brightness = &sd_brightness,
453         .use_vpulse2 = true,
454 };
455
456 static void ardbeg_panel_select(void)
457 {
458         struct tegra_panel *panel = NULL;
459         struct board_info board;
460         u8 dsi_instance;
461
462         tegra_get_display_board_info(&board);
463
464         switch (board.board_id) {
465         case BOARD_E1639:
466         case BOARD_E1813:
467                 panel = &dsi_s_wqxga_10_1;
468                 dsi_instance = DSI_INSTANCE_0;
469                 break;
470         case BOARD_PM354:
471                 panel = &dsi_a_1080p_14_0;
472                 dsi_instance = DSI_INSTANCE_0;
473                 break;
474         case BOARD_E1627:
475                 panel = &dsi_p_wuxga_10_1;
476                 dsi_instance = DSI_INSTANCE_0;
477                 break;
478         case BOARD_PM363:
479         case BOARD_E1824:
480                 panel = &edp_a_1080p_14_0;
481                 ardbeg_disp1_out.type = TEGRA_DC_OUT_DP;
482                 ardbeg_disp1_device.resource = ardbeg_disp1_edp_resources;
483                 ardbeg_disp1_device.num_resources =
484                         ARRAY_SIZE(ardbeg_disp1_edp_resources);
485                 break;
486         case BOARD_PM366:
487                 panel = &lvds_c_1366_14;
488                 ardbeg_disp1_out.type = TEGRA_DC_OUT_LVDS;
489                 ardbeg_disp1_device.resource = ardbeg_disp1_edp_resources;
490                 ardbeg_disp1_device.num_resources =
491                         ARRAY_SIZE(ardbeg_disp1_edp_resources);
492                 break;
493         default:
494                 panel = &dsi_p_wuxga_10_1;
495                 dsi_instance = DSI_INSTANCE_0;
496                 break;
497         }
498
499         if (panel) {
500                 if (panel->init_sd_settings)
501                         panel->init_sd_settings(&sd_settings);
502
503                 if (panel->init_dc_out) {
504                         panel->init_dc_out(&ardbeg_disp1_out);
505                         if (ardbeg_disp1_out.type == TEGRA_DC_OUT_DSI) {
506                                 ardbeg_disp1_out.dsi->dsi_instance =
507                                         dsi_instance;
508                                 ardbeg_disp1_out.dsi->dsi_panel_rst_gpio =
509                                         DSI_PANEL_RST_GPIO;
510                                 ardbeg_disp1_out.dsi->dsi_panel_bl_pwm_gpio =
511                                         DSI_PANEL_BL_PWM_GPIO;
512                                 ardbeg_disp1_out.dsi->te_gpio = TEGRA_GPIO_PR6;
513                         }
514                 }
515
516                 if (panel->init_fb_data)
517                         panel->init_fb_data(&ardbeg_disp1_fb_data);
518
519                 if (panel->init_cmu_data)
520                         panel->init_cmu_data(&ardbeg_disp1_pdata);
521
522                 if (panel->set_disp_device)
523                         panel->set_disp_device(&ardbeg_disp1_device);
524
525                 if (ardbeg_disp1_out.type == TEGRA_DC_OUT_DSI) {
526                         tegra_dsi_resources_init(dsi_instance,
527                                 ardbeg_disp1_resources,
528                                 ARRAY_SIZE(ardbeg_disp1_resources));
529                 }
530
531                 if (panel->register_bl_dev)
532                         panel->register_bl_dev();
533
534                 if (panel->register_i2c_bridge)
535                         panel->register_i2c_bridge();
536         }
537
538 }
539 int __init ardbeg_panel_init(void)
540 {
541         int err = 0;
542         struct resource __maybe_unused *res;
543         struct platform_device *phost1x = NULL;
544
545         sd_settings = ardbeg_sd_settings;
546
547         ardbeg_panel_select();
548
549 #ifdef CONFIG_TEGRA_NVMAP
550         ardbeg_carveouts[1].base = tegra_carveout_start;
551         ardbeg_carveouts[1].size = tegra_carveout_size;
552         ardbeg_carveouts[2].base = tegra_vpr_start;
553         ardbeg_carveouts[2].size = tegra_vpr_size;
554
555         err = platform_device_register(&ardbeg_nvmap_device);
556         if (err) {
557                 pr_err("nvmap device registration failed\n");
558                 return err;
559         }
560 #endif
561
562         phost1x = ardbeg_host1x_init();
563         if (!phost1x) {
564                 pr_err("host1x devices registration failed\n");
565                 return -EINVAL;
566         }
567
568         res = platform_get_resource_byname(&ardbeg_disp1_device,
569                                          IORESOURCE_MEM, "fbmem");
570         res->start = tegra_fb_start;
571         res->end = tegra_fb_start + tegra_fb_size - 1;
572
573         /* Copy the bootloader fb to the fb. */
574         __tegra_move_framebuffer(&ardbeg_nvmap_device,
575                 tegra_fb_start, tegra_bootloader_fb_start,
576                         min(tegra_fb_size, tegra_bootloader_fb_size));
577
578         ardbeg_disp1_device.dev.parent = &phost1x->dev;
579         err = platform_device_register(&ardbeg_disp1_device);
580         if (err) {
581                 pr_err("disp1 device registration failed\n");
582                 return err;
583         }
584
585         err = tegra_init_hdmi(&ardbeg_disp2_device, phost1x);
586         if (err)
587                 return err;
588
589 #ifdef CONFIG_TEGRA_NVAVP
590         nvavp_device.dev.parent = &phost1x->dev;
591         err = platform_device_register(&nvavp_device);
592         if (err) {
593                 pr_err("nvavp device registration failed\n");
594                 return err;
595         }
596 #endif
597         return err;
598 }