ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-panel.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-panel.c
3  *
4  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20 #include <linux/ioport.h>
21 #include <linux/fb.h>
22 #include <linux/nvmap.h>
23 #include <linux/nvhost.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/gpio.h>
27 #include <linux/tegra_pwm_bl.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/pwm_backlight.h>
30 #include <linux/of.h>
31 #include <linux/of_address.h>
32 #include <linux/dma-contiguous.h>
33 #include <linux/clk.h>
34
35 #include <mach/irqs.h>
36 #include <mach/dc.h>
37 #include <mach/io_dpd.h>
38
39 #include "board.h"
40 #include "devices.h"
41 #include "gpio-names.h"
42 #include "board-ardbeg.h"
43 #include "board-panel.h"
44 #include "common.h"
45 #include "iomap.h"
46 #include "tegra12_host1x_devices.h"
47 #include "dvfs.h"
48
49 struct platform_device * __init ardbeg_host1x_init(void)
50 {
51         struct platform_device *pdev = NULL;
52
53 #ifdef CONFIG_TEGRA_GRHOST
54         if (!of_have_populated_dt())
55                 pdev = tegra12_register_host1x_devices();
56         else
57                 pdev = to_platform_device(bus_find_device_by_name(
58                         &platform_bus_type, NULL, "host1x"));
59
60         if (!pdev) {
61                 pr_err("host1x devices registration failed\n");
62                 return NULL;
63         }
64 #endif
65         return pdev;
66 }
67
68 /* hdmi related regulators */
69 static struct regulator *ardbeg_hdmi_reg;
70 static struct regulator *ardbeg_hdmi_pll;
71 static struct regulator *ardbeg_hdmi_vddio;
72
73 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
74 static struct resource ardbeg_disp1_resources[] = {
75         {
76                 .name   = "irq",
77                 .start  = INT_DISPLAY_GENERAL,
78                 .end    = INT_DISPLAY_GENERAL,
79                 .flags  = IORESOURCE_IRQ,
80         },
81         {
82                 .name   = "regs",
83                 .start  = TEGRA_DISPLAY_BASE,
84                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
85                 .flags  = IORESOURCE_MEM,
86         },
87         {
88                 .name   = "fbmem",
89                 .start  = 0, /* Filled in by ardbeg_panel_init() */
90                 .end    = 0, /* Filled in by ardbeg_panel_init() */
91                 .flags  = IORESOURCE_MEM,
92         },
93         {
94                 .name   = "ganged_dsia_regs",
95                 .start  = 0, /* Filled in the panel file by init_resources() */
96                 .end    = 0, /* Filled in the panel file by init_resources() */
97                 .flags  = IORESOURCE_MEM,
98         },
99         {
100                 .name   = "ganged_dsib_regs",
101                 .start  = 0, /* Filled in the panel file by init_resources() */
102                 .end    = 0, /* Filled in the panel file by init_resources() */
103                 .flags  = IORESOURCE_MEM,
104         },
105         {
106                 .name   = "dsi_regs",
107                 .start  = 0, /* Filled in the panel file by init_resources() */
108                 .end    = 0, /* Filled in the panel file by init_resources() */
109                 .flags  = IORESOURCE_MEM,
110         },
111         {
112                 .name   = "mipi_cal",
113                 .start  = TEGRA_MIPI_CAL_BASE,
114                 .end    = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
115                 .flags  = IORESOURCE_MEM,
116         },
117 };
118
119 static struct resource ardbeg_disp1_edp_resources[] = {
120         {
121                 .name   = "irq",
122                 .start  = INT_DISPLAY_GENERAL,
123                 .end    = INT_DISPLAY_GENERAL,
124                 .flags  = IORESOURCE_IRQ,
125         },
126         {
127                 .name   = "regs",
128                 .start  = TEGRA_DISPLAY_BASE,
129                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
130                 .flags  = IORESOURCE_MEM,
131         },
132         {
133                 .name   = "fbmem",
134                 .start  = 0, /* Filled in by ardbeg_panel_init() */
135                 .end    = 0, /* Filled in by ardbeg_panel_init() */
136                 .flags  = IORESOURCE_MEM,
137         },
138         {
139                 .name   = "mipi_cal",
140                 .start  = TEGRA_MIPI_CAL_BASE,
141                 .end    = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
142                 .flags  = IORESOURCE_MEM,
143         },
144         {
145                 .name   = "sor",
146                 .start  = TEGRA_SOR_BASE,
147                 .end    = TEGRA_SOR_BASE + TEGRA_SOR_SIZE - 1,
148                 .flags  = IORESOURCE_MEM,
149         },
150         {
151                 .name   = "dpaux",
152                 .start  = TEGRA_DPAUX_BASE,
153                 .end    = TEGRA_DPAUX_BASE + TEGRA_DPAUX_SIZE - 1,
154                 .flags  = IORESOURCE_MEM,
155         },
156         {
157                 .name   = "irq_dp",
158                 .start  = INT_DPAUX,
159                 .end    = INT_DPAUX,
160                 .flags  = IORESOURCE_IRQ,
161         },
162 };
163 #endif
164
165 static struct resource ardbeg_disp2_resources[] = {
166         {
167                 .name   = "irq",
168 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
169                 .start  = INT_DISPLAY_B_GENERAL,
170                 .end    = INT_DISPLAY_B_GENERAL,
171 #else
172                 .start  = INT_DISPLAY_GENERAL,
173                 .end    = INT_DISPLAY_GENERAL,
174 #endif
175                 .flags  = IORESOURCE_IRQ,
176         },
177         {
178                 .name   = "regs",
179 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
180                 .start  = TEGRA_DISPLAY2_BASE,
181                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
182 #else
183                 .start  = TEGRA_DISPLAY_BASE,
184                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
185 #endif
186                 .flags  = IORESOURCE_MEM,
187         },
188         {
189                 .name   = "fbmem",
190                 .start  = 0, /* Filled in by ardbeg_panel_init() */
191                 .end    = 0, /* Filled in by ardbeg_panel_init() */
192                 .flags  = IORESOURCE_MEM,
193         },
194         {
195                 .name   = "hdmi_regs",
196                 .start  = TEGRA_HDMI_BASE,
197                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
198                 .flags  = IORESOURCE_MEM,
199         },
200 };
201
202
203 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
204 static struct tegra_dc_sd_settings sd_settings;
205
206 static struct tegra_dc_out ardbeg_disp1_out = {
207         .type           = TEGRA_DC_OUT_DSI,
208         .sd_settings    = &sd_settings,
209 };
210 #endif
211
212 static int ardbeg_hdmi_enable(struct device *dev)
213 {
214         int ret;
215         if (!ardbeg_hdmi_reg) {
216                 ardbeg_hdmi_reg = regulator_get(dev, "avdd_hdmi");
217                 if (IS_ERR(ardbeg_hdmi_reg)) {
218                         pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
219                         ardbeg_hdmi_reg = NULL;
220                         return PTR_ERR(ardbeg_hdmi_reg);
221                 }
222         }
223         ret = regulator_enable(ardbeg_hdmi_reg);
224         if (ret < 0) {
225                 pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
226                 return ret;
227         }
228         if (!ardbeg_hdmi_pll) {
229                 ardbeg_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll");
230                 if (IS_ERR(ardbeg_hdmi_pll)) {
231                         pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
232                         ardbeg_hdmi_pll = NULL;
233                         regulator_put(ardbeg_hdmi_reg);
234                         ardbeg_hdmi_reg = NULL;
235                         return PTR_ERR(ardbeg_hdmi_pll);
236                 }
237         }
238         ret = regulator_enable(ardbeg_hdmi_pll);
239         if (ret < 0) {
240                 pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
241                 return ret;
242         }
243         return 0;
244 }
245
246 static int ardbeg_hdmi_disable(void)
247 {
248         if (ardbeg_hdmi_reg) {
249                 regulator_disable(ardbeg_hdmi_reg);
250                 regulator_put(ardbeg_hdmi_reg);
251                 ardbeg_hdmi_reg = NULL;
252         }
253
254         if (ardbeg_hdmi_pll) {
255                 regulator_disable(ardbeg_hdmi_pll);
256                 regulator_put(ardbeg_hdmi_pll);
257                 ardbeg_hdmi_pll = NULL;
258         }
259         return 0;
260 }
261
262 static int ardbeg_hdmi_postsuspend(void)
263 {
264         if (ardbeg_hdmi_vddio) {
265                 regulator_disable(ardbeg_hdmi_vddio);
266                 regulator_put(ardbeg_hdmi_vddio);
267                 ardbeg_hdmi_vddio = NULL;
268         }
269         return 0;
270 }
271
272 static int ardbeg_hdmi_hotplug_init(struct device *dev)
273 {
274         if (!ardbeg_hdmi_vddio) {
275 #ifdef CONFIG_TEGRA_HDMI_PRIMARY
276                 if (of_machine_is_compatible("nvidia,tn8"))
277                         ardbeg_hdmi_vddio = regulator_get(dev, "vdd-out1-5v0");
278                 else
279                         ardbeg_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0");
280 #else
281                 ardbeg_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0");
282 #endif
283                 if (WARN_ON(IS_ERR(ardbeg_hdmi_vddio))) {
284                         pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %ld\n",
285                                 __func__, PTR_ERR(ardbeg_hdmi_vddio));
286                                 ardbeg_hdmi_vddio = NULL;
287                 } else {
288                         return regulator_enable(ardbeg_hdmi_vddio);
289                 }
290         }
291
292         return 0;
293 }
294
295 struct tmds_config ardbeg_tmds_config[] = {
296         { /* 480p/576p / 25.2MHz/27MHz modes */
297         .pclk = 27000000,
298         .pll0 = 0x01003110,
299         .pll1 = 0x00300F00,
300         .pe_current = 0x08080808,
301         .drive_current = 0x2e2e2e2e,
302         .peak_current = 0x00000000,
303         },
304         { /* 720p / 74.25MHz modes */
305         .pclk = 74250000,
306         .pll0 =  0x01003310,
307         .pll1 = 0x10300F00,
308         .pe_current = 0x08080808,
309         .drive_current = 0x20202020,
310         .peak_current = 0x00000000,
311         },
312         { /* 1080p / 148.5MHz modes */
313         .pclk = 148500000,
314         .pll0 = 0x01003310,
315         .pll1 = 0x10300F00,
316         .pe_current = 0x08080808,
317         .drive_current = 0x20202020,
318         .peak_current = 0x00000000,
319         },
320         {
321         .pclk = INT_MAX,
322         .pll0 = 0x01003310,
323         .pll1 = 0x10300F00,
324         .pe_current = 0x08080808,
325         .drive_current = 0x3A353536, /* lane3 needs a slightly lower current */
326         .peak_current = 0x00000000,
327         },
328 };
329
330 struct tegra_hdmi_out ardbeg_hdmi_out = {
331         .tmds_config = ardbeg_tmds_config,
332         .n_tmds_config = ARRAY_SIZE(ardbeg_tmds_config),
333 };
334
335 #if defined(CONFIG_FRAMEBUFFER_CONSOLE)
336 static struct tegra_dc_mode hdmi_panel_modes[] = {
337         {
338                 .pclk =                 25200000,
339                 .h_ref_to_sync =        1,
340                 .v_ref_to_sync =        1,
341                 .h_sync_width =         96,     /* hsync_len */
342                 .v_sync_width =         2,      /* vsync_len */
343                 .h_back_porch =         48,     /* left_margin */
344                 .v_back_porch =         33,     /* upper_margin */
345                 .h_active =             640,    /* xres */
346                 .v_active =             480,    /* yres */
347                 .h_front_porch =        16,     /* right_margin */
348                 .v_front_porch =        10,     /* lower_margin */
349         },
350 };
351 #elif defined(CONFIG_TEGRA_HDMI_PRIMARY)
352 static struct tegra_dc_mode hdmi_panel_modes[] = {
353         {
354                 .pclk =                 148500000,
355                 .h_ref_to_sync =        1,
356                 .v_ref_to_sync =        1,
357                 .h_sync_width =         44,     /* hsync_len */
358                 .v_sync_width =         5,      /* vsync_len */
359                 .h_back_porch =         148,    /* left_margin */
360                 .v_back_porch =         36,     /* upper_margin */
361                 .h_active =             1920,   /* xres */
362                 .v_active =             1080,   /* yres */
363                 .h_front_porch =        88,     /* right_margin */
364                 .v_front_porch =        4,      /* lower_margin */
365         },
366 };
367 #endif /* CONFIG_FRAMEBUFFER_CONSOLE || CONFIG_TEGRA_HDMI_PRIMARY*/
368
369 static struct tegra_dc_out ardbeg_disp2_out = {
370         .type           = TEGRA_DC_OUT_HDMI,
371         .flags          = TEGRA_DC_OUT_HOTPLUG_HIGH,
372         .parent_clk     = "pll_d2",
373
374         .dcc_bus        = 3,
375         .hotplug_gpio   = ardbeg_hdmi_hpd,
376         .hdmi_out       = &ardbeg_hdmi_out,
377
378         /* TODO: update max pclk to POR */
379         .max_pixclock   = KHZ2PICOS(297000),
380 #if defined(CONFIG_FRAMEBUFFER_CONSOLE) || defined(CONFIG_TEGRA_HDMI_PRIMARY)
381         .modes = hdmi_panel_modes,
382         .n_modes = ARRAY_SIZE(hdmi_panel_modes),
383         .depth = 24,
384 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
385
386         .align          = TEGRA_DC_ALIGN_MSB,
387         .order          = TEGRA_DC_ORDER_RED_BLUE,
388
389         .enable         = ardbeg_hdmi_enable,
390         .disable        = ardbeg_hdmi_disable,
391         .postsuspend    = ardbeg_hdmi_postsuspend,
392         .hotplug_init   = ardbeg_hdmi_hotplug_init,
393 };
394
395 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
396 static struct tegra_fb_data ardbeg_disp1_fb_data = {
397         .win            = 0,
398         .bits_per_pixel = 32,
399         .flags          = TEGRA_FB_FLIP_ON_PROBE,
400 };
401
402 static struct tegra_dc_platform_data ardbeg_disp1_pdata = {
403         .flags          = TEGRA_DC_FLAG_ENABLED,
404         .default_out    = &ardbeg_disp1_out,
405         .fb             = &ardbeg_disp1_fb_data,
406         .emc_clk_rate   = 204000000,
407 #ifdef CONFIG_TEGRA_DC_CMU
408         .cmu_enable     = 1,
409 #endif
410         .low_v_win      = 0x02,
411 };
412 #endif
413
414 static struct tegra_fb_data ardbeg_disp2_fb_data = {
415         .win            = 0,
416         .xres           = 1920,
417         .yres           = 1080,
418         .bits_per_pixel = 32,
419         .flags          = TEGRA_FB_FLIP_ON_PROBE,
420 };
421
422 static struct tegra_dc_platform_data ardbeg_disp2_pdata = {
423         .flags          = TEGRA_DC_FLAG_ENABLED,
424         .default_out    = &ardbeg_disp2_out,
425         .fb             = &ardbeg_disp2_fb_data,
426         .emc_clk_rate   = 300000000,
427 };
428
429 static struct platform_device ardbeg_disp2_device = {
430         .name           = "tegradc",
431 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
432         .id             = 1,
433 #else
434         .id             = 0,
435 #endif
436         .resource       = ardbeg_disp2_resources,
437         .num_resources  = ARRAY_SIZE(ardbeg_disp2_resources),
438         .dev = {
439                 .platform_data = &ardbeg_disp2_pdata,
440         },
441 };
442
443 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
444 static struct platform_device ardbeg_disp1_device = {
445         .name           = "tegradc",
446         .id             = 0,
447         .resource       = ardbeg_disp1_resources,
448         .num_resources  = ARRAY_SIZE(ardbeg_disp1_resources),
449         .dev = {
450                 .platform_data = &ardbeg_disp1_pdata,
451         },
452 };
453 #endif
454
455 static struct nvmap_platform_carveout ardbeg_carveouts[] = {
456         [0] = {
457                 .name           = "iram",
458                 .usage_mask     = NVMAP_HEAP_CARVEOUT_IRAM,
459                 .base           = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
460                 .size           = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
461         },
462         [1] = {
463                 .name           = "generic-0",
464                 .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
465                 .base           = 0, /* Filled in by ardbeg_panel_init() */
466                 .size           = 0, /* Filled in by ardbeg_panel_init() */
467         },
468         [2] = {
469                 .name           = "vpr",
470                 .usage_mask     = NVMAP_HEAP_CARVEOUT_VPR,
471                 .base           = 0, /* Filled in by ardbeg_panel_init() */
472                 .size           = 0, /* Filled in by ardbeg_panel_init() */
473         },
474 };
475
476 static struct nvmap_platform_data ardbeg_nvmap_data = {
477         .carveouts      = ardbeg_carveouts,
478         .nr_carveouts   = ARRAY_SIZE(ardbeg_carveouts),
479 };
480 static struct platform_device ardbeg_nvmap_device  = {
481         .name   = "tegra-nvmap",
482         .id     = -1,
483         .dev    = {
484                 .platform_data = &ardbeg_nvmap_data,
485         },
486 };
487 static struct tegra_io_dpd dsic_io = {
488         .name                   = "DSIC",
489         .io_dpd_reg_index       = 1,
490         .io_dpd_bit             = 8,
491 };
492 static struct tegra_io_dpd dsid_io = {
493         .name                   = "DSID",
494         .io_dpd_reg_index       = 1,
495         .io_dpd_bit             = 9,
496 };
497
498 static struct tegra_dc_dp_lt_settings ardbeg_edp_lt_data[] = {
499         /* DriveCurrent Preemphasis     PostCursor      tx_pu   load_adj */
500         {0x13131313,    0x00000000,     0x00000000,     0x0,    0x3},
501         {0x13131313,    0x00000000,     0x00000000,     0x0,    0x4},
502         {0x19191919,    0x09090909,     0x00000000,     0x0,    0x6}
503 };
504
505 static struct tegra_dp_out dp_settings = {
506         /* Panel can override this with its own LT data */
507         .lt_settings = ardbeg_edp_lt_data,
508         .n_lt_settings = ARRAY_SIZE(ardbeg_edp_lt_data),
509         .tx_pu_disable = true,
510 };
511
512 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
513 /* can be called multiple times */
514 static struct tegra_panel *ardbeg_panel_configure(struct board_info *board_out,
515         u8 *dsi_instance_out)
516 {
517         struct tegra_panel *panel = NULL;
518         u8 dsi_instance = DSI_INSTANCE_0;
519         struct board_info boardtmp;
520
521         if (!board_out)
522                 board_out = &boardtmp;
523         tegra_get_display_board_info(board_out);
524
525         switch (board_out->board_id) {
526         case BOARD_E1639:
527         case BOARD_E1813:
528                 panel = &dsi_s_wqxga_10_1;
529                 break;
530         case BOARD_PM354:
531                 panel = &dsi_a_1080p_14_0;
532                 break;
533         case BOARD_E1627:
534                 panel = &dsi_p_wuxga_10_1;
535                 tegra_io_dpd_enable(&dsic_io);
536                 tegra_io_dpd_enable(&dsid_io);
537                 break;
538         case BOARD_E1549:
539                 panel = &dsi_lgd_wxga_7_0;
540                 break;
541         case BOARD_PM363:
542         case BOARD_E1824:
543                 panel = &edp_a_1080p_14_0;
544                 ardbeg_disp1_out.type = TEGRA_DC_OUT_DP;
545                 ardbeg_disp1_out.dp_out = &dp_settings;
546                 ardbeg_disp1_device.resource = ardbeg_disp1_edp_resources;
547                 ardbeg_disp1_device.num_resources =
548                         ARRAY_SIZE(ardbeg_disp1_edp_resources);
549                 break;
550         case BOARD_PM366:
551                 panel = &lvds_c_1366_14;
552                 ardbeg_disp1_out.type = TEGRA_DC_OUT_LVDS;
553                 ardbeg_disp1_device.resource = ardbeg_disp1_edp_resources;
554                 ardbeg_disp1_device.num_resources =
555                         ARRAY_SIZE(ardbeg_disp1_edp_resources);
556                 break;
557         case BOARD_E1807:
558                 panel = &dsi_a_1200_800_8_0;
559                 dsi_instance = DSI_INSTANCE_0;
560                 tegra_io_dpd_enable(&dsic_io);
561                 tegra_io_dpd_enable(&dsid_io);
562                 break;
563         case BOARD_E1937:
564                 panel = &dsi_a_1200_1920_7_0;
565                 dsi_instance = DSI_INSTANCE_0;
566                 break;
567         case BOARD_P1761:
568                 if (tegra_get_board_panel_id())
569                         panel = &dsi_a_1200_1920_7_0;
570                 else
571                         panel = &dsi_a_1200_800_8_0;
572                 dsi_instance = DSI_INSTANCE_0;
573                 tegra_io_dpd_enable(&dsic_io);
574                 tegra_io_dpd_enable(&dsid_io);
575                 break;
576         default:
577                 panel = &dsi_p_wuxga_10_1;
578                 tegra_io_dpd_enable(&dsic_io);
579                 tegra_io_dpd_enable(&dsid_io);
580                 break;
581         }
582         if (dsi_instance_out)
583                 *dsi_instance_out = dsi_instance;
584         return panel;
585 }
586
587 static void ardbeg_panel_select(void)
588 {
589         struct tegra_panel *panel = NULL;
590         struct board_info board;
591         u8 dsi_instance;
592
593         panel = ardbeg_panel_configure(&board, &dsi_instance);
594
595         if (panel) {
596                 if (panel->init_sd_settings)
597                         panel->init_sd_settings(&sd_settings);
598
599                 if (panel->init_dc_out) {
600                         panel->init_dc_out(&ardbeg_disp1_out);
601                         if (ardbeg_disp1_out.type == TEGRA_DC_OUT_DSI) {
602                                 ardbeg_disp1_out.dsi->dsi_instance =
603                                         dsi_instance;
604                                 ardbeg_disp1_out.dsi->dsi_panel_rst_gpio =
605                                         DSI_PANEL_RST_GPIO;
606                                 ardbeg_disp1_out.dsi->dsi_panel_bl_pwm_gpio =
607                                         DSI_PANEL_BL_PWM_GPIO;
608                                 ardbeg_disp1_out.dsi->te_gpio = TEGRA_GPIO_PR6;
609                         }
610                 }
611
612                 if (panel->init_fb_data)
613                         panel->init_fb_data(&ardbeg_disp1_fb_data);
614
615                 if (panel->init_cmu_data)
616                         panel->init_cmu_data(&ardbeg_disp1_pdata);
617
618                 if (panel->set_disp_device)
619                         panel->set_disp_device(&ardbeg_disp1_device);
620
621                 if (ardbeg_disp1_out.type == TEGRA_DC_OUT_DSI) {
622                         tegra_dsi_resources_init(dsi_instance,
623                                 ardbeg_disp1_resources,
624                                 ARRAY_SIZE(ardbeg_disp1_resources));
625                 }
626
627                 if (panel->register_bl_dev)
628                         panel->register_bl_dev();
629
630                 if (panel->register_i2c_bridge)
631                         panel->register_i2c_bridge();
632         }
633
634 }
635 #endif
636
637 int __init ardbeg_panel_init(void)
638 {
639         int err = 0;
640         struct resource __maybe_unused *res;
641         struct platform_device *phost1x = NULL;
642         static struct board_info board_info;
643         struct device_node *dc1_node = NULL;
644         struct device_node *dc2_node = NULL;
645
646         tegra_get_board_info(&board_info);
647         find_dc_node(&dc1_node, &dc2_node);
648
649 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
650         ardbeg_panel_select();
651 #endif
652         if (board_info.board_id == BOARD_PM375) {
653                 ardbeg_tmds_config[1].pe_current = 0x08080808;
654                 ardbeg_tmds_config[1].drive_current = 0x2d2d2d2d;
655                 ardbeg_tmds_config[1].peak_current = 0x0;
656                 ardbeg_tmds_config[2].pe_current = 0x0;
657                 ardbeg_tmds_config[2].drive_current = 0x2d2d2d2d;
658                 ardbeg_tmds_config[2].peak_current = 0x05050505;
659         }
660
661 #ifdef CONFIG_TEGRA_NVMAP
662         ardbeg_carveouts[1].base = tegra_carveout_start;
663         ardbeg_carveouts[1].size = tegra_carveout_size;
664         ardbeg_carveouts[2].base = tegra_vpr_start;
665         ardbeg_carveouts[2].size = tegra_vpr_size;
666 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
667         carveout_linear_set(&tegra_generic_cma_dev);
668         ardbeg_carveouts[1].cma_dev = &tegra_generic_cma_dev;
669         ardbeg_carveouts[1].resize = false;
670         carveout_linear_set(&tegra_vpr_cma_dev);
671         ardbeg_carveouts[2].cma_dev = &tegra_vpr_cma_dev;
672         ardbeg_carveouts[2].resize = true;
673         ardbeg_carveouts[2].cma_chunk_size = SZ_32M;
674 #endif
675
676         err = platform_device_register(&ardbeg_nvmap_device);
677         if (err) {
678                 pr_err("nvmap device registration failed\n");
679                 return err;
680         }
681 #endif
682
683         phost1x = ardbeg_host1x_init();
684         if (!phost1x) {
685                 pr_err("host1x devices registration failed\n");
686                 return -EINVAL;
687         }
688
689         if (!of_have_populated_dt() || !dc1_node ||
690                 !of_device_is_available(dc1_node)) {
691 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
692                 res = platform_get_resource_byname(&ardbeg_disp1_device,
693                                          IORESOURCE_MEM, "fbmem");
694 #else
695                 res = platform_get_resource_byname(&ardbeg_disp2_device,
696                                          IORESOURCE_MEM, "fbmem");
697 #endif
698                 res->start = tegra_fb_start;
699                 res->end = tegra_fb_start + tegra_fb_size - 1;
700         }
701
702         /* Copy the bootloader fb to the fb. */
703         if (tegra_bootloader_fb_size)
704                 __tegra_move_framebuffer(&ardbeg_nvmap_device,
705                                 tegra_fb_start, tegra_bootloader_fb_start,
706                                 min(tegra_fb_size, tegra_bootloader_fb_size));
707         else
708                 __tegra_clear_framebuffer(&ardbeg_nvmap_device,
709                                           tegra_fb_start, tegra_fb_size);
710
711 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
712         if (!of_have_populated_dt() || !dc1_node ||
713                 !of_device_is_available(dc1_node)) {
714                 ardbeg_disp1_device.dev.parent = &phost1x->dev;
715                 err = platform_device_register(&ardbeg_disp1_device);
716                 if (err) {
717                         pr_err("disp1 device registration failed\n");
718                         return err;
719                 }
720         }
721 #endif
722
723         if (!of_have_populated_dt() || !dc2_node ||
724                 !of_device_is_available(dc2_node)) {
725 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
726                 res = platform_get_resource_byname(&ardbeg_disp2_device,
727                                         IORESOURCE_MEM, "fbmem");
728                 res->start = tegra_fb2_start;
729                 res->end = tegra_fb2_start + tegra_fb2_size - 1;
730 #endif
731                 ardbeg_disp2_device.dev.parent = &phost1x->dev;
732                 err = platform_device_register(&ardbeg_disp2_device);
733                 if (err) {
734                         pr_err("disp2 device registration failed\n");
735                         return err;
736                 }
737         }
738
739 #ifdef CONFIG_TEGRA_NVAVP
740         nvavp_device.dev.parent = &phost1x->dev;
741         err = platform_device_register(&nvavp_device);
742         if (err) {
743                 pr_err("nvavp device registration failed\n");
744                 return err;
745         }
746 #endif
747         return err;
748 }
749
750 int __init ardbeg_display_init(void)
751 {
752         struct clk *disp1_clk = clk_get_sys("tegradc.0", NULL);
753         struct clk *disp2_clk = clk_get_sys("tegradc.1", NULL);
754         struct tegra_panel *panel;
755         struct board_info board;
756         long disp1_rate = 0;
757         long disp2_rate = 0;
758
759         /*
760          * TODO
761          * Need to skip ardbeg_display_init
762          * when disp is registered by device_tree
763          */
764
765         if (WARN_ON(IS_ERR(disp1_clk))) {
766                 if (disp2_clk && !IS_ERR(disp2_clk))
767                         clk_put(disp2_clk);
768                 return PTR_ERR(disp1_clk);
769         }
770
771         if (WARN_ON(IS_ERR(disp2_clk))) {
772                 clk_put(disp1_clk);
773                 return PTR_ERR(disp1_clk);
774         }
775
776 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
777         panel = ardbeg_panel_configure(&board, NULL);
778
779         if (panel && panel->init_dc_out) {
780                 panel->init_dc_out(&ardbeg_disp1_out);
781                 if (ardbeg_disp1_out.n_modes && ardbeg_disp1_out.modes)
782                         disp1_rate = ardbeg_disp1_out.modes[0].pclk;
783         } else {
784                 disp1_rate = 0;
785                 if (!panel || !panel->init_dc_out)
786                         printk(KERN_ERR "disp1 panel output not specified!\n");
787         }
788
789         printk(KERN_DEBUG "disp1 pclk=%ld\n", disp1_rate);
790         if (disp1_rate)
791                 tegra_dvfs_resolve_override(disp1_clk, disp1_rate);
792 #endif
793
794         /* set up disp2 */
795         if (ardbeg_disp2_out.max_pixclock)
796                 disp2_rate = PICOS2KHZ(ardbeg_disp2_out.max_pixclock) * 1000;
797         else
798                 disp2_rate = 297000000; /* HDMI 4K */
799         printk(KERN_DEBUG "disp2 pclk=%ld\n", disp2_rate);
800         if (disp2_rate)
801 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
802                 tegra_dvfs_resolve_override(disp2_clk, disp2_rate);
803 #else
804                 tegra_dvfs_resolve_override(disp1_clk, disp2_rate);
805 #endif
806
807         clk_put(disp1_clk);
808         clk_put(disp2_clk);
809         return 0;
810 }