ARM: tegra: fix regulator_get() return value check
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-panel.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-panel.c
3  *
4  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20 #include <linux/ioport.h>
21 #include <linux/fb.h>
22 #include <linux/nvmap.h>
23 #include <linux/nvhost.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/gpio.h>
27 #include <linux/tegra_pwm_bl.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/pwm_backlight.h>
30 #include <linux/of.h>
31 #include <linux/dma-contiguous.h>
32 #include <linux/clk.h>
33
34 #include <mach/irqs.h>
35 #include <mach/dc.h>
36
37 #include "board.h"
38 #include "devices.h"
39 #include "gpio-names.h"
40 #include "board-ardbeg.h"
41 #include "board-panel.h"
42 #include "common.h"
43 #include "iomap.h"
44 #include "tegra12_host1x_devices.h"
45 #include "dvfs.h"
46
47
48 struct platform_device * __init ardbeg_host1x_init(void)
49 {
50         struct platform_device *pdev = NULL;
51
52 #ifdef CONFIG_TEGRA_GRHOST
53         if (!of_have_populated_dt())
54                 pdev = tegra12_register_host1x_devices();
55         else
56                 pdev = to_platform_device(bus_find_device_by_name(
57                         &platform_bus_type, NULL, "host1x"));
58
59         if (!pdev) {
60                 pr_err("host1x devices registration failed\n");
61                 return NULL;
62         }
63 #endif
64         return pdev;
65 }
66
67 /* hdmi related regulators */
68 static struct regulator *ardbeg_hdmi_reg;
69 static struct regulator *ardbeg_hdmi_pll;
70 static struct regulator *ardbeg_hdmi_vddio;
71
72 static struct resource ardbeg_disp1_resources[] = {
73         {
74                 .name   = "irq",
75                 .start  = INT_DISPLAY_GENERAL,
76                 .end    = INT_DISPLAY_GENERAL,
77                 .flags  = IORESOURCE_IRQ,
78         },
79         {
80                 .name   = "regs",
81                 .start  = TEGRA_DISPLAY_BASE,
82                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
83                 .flags  = IORESOURCE_MEM,
84         },
85         {
86                 .name   = "fbmem",
87                 .start  = 0, /* Filled in by ardbeg_panel_init() */
88                 .end    = 0, /* Filled in by ardbeg_panel_init() */
89                 .flags  = IORESOURCE_MEM,
90         },
91         {
92                 .name   = "ganged_dsia_regs",
93                 .start  = 0, /* Filled in the panel file by init_resources() */
94                 .end    = 0, /* Filled in the panel file by init_resources() */
95                 .flags  = IORESOURCE_MEM,
96         },
97         {
98                 .name   = "ganged_dsib_regs",
99                 .start  = 0, /* Filled in the panel file by init_resources() */
100                 .end    = 0, /* Filled in the panel file by init_resources() */
101                 .flags  = IORESOURCE_MEM,
102         },
103         {
104                 .name   = "dsi_regs",
105                 .start  = 0, /* Filled in the panel file by init_resources() */
106                 .end    = 0, /* Filled in the panel file by init_resources() */
107                 .flags  = IORESOURCE_MEM,
108         },
109         {
110                 .name   = "mipi_cal",
111                 .start  = TEGRA_MIPI_CAL_BASE,
112                 .end    = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
113                 .flags  = IORESOURCE_MEM,
114         },
115 };
116
117 static struct resource ardbeg_disp1_edp_resources[] = {
118         {
119                 .name   = "irq",
120                 .start  = INT_DISPLAY_GENERAL,
121                 .end    = INT_DISPLAY_GENERAL,
122                 .flags  = IORESOURCE_IRQ,
123         },
124         {
125                 .name   = "regs",
126                 .start  = TEGRA_DISPLAY_BASE,
127                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
128                 .flags  = IORESOURCE_MEM,
129         },
130         {
131                 .name   = "fbmem",
132                 .start  = 0, /* Filled in by ardbeg_panel_init() */
133                 .end    = 0, /* Filled in by ardbeg_panel_init() */
134                 .flags  = IORESOURCE_MEM,
135         },
136         {
137                 .name   = "mipi_cal",
138                 .start  = TEGRA_MIPI_CAL_BASE,
139                 .end    = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
140                 .flags  = IORESOURCE_MEM,
141         },
142         {
143                 .name   = "sor",
144                 .start  = TEGRA_SOR_BASE,
145                 .end    = TEGRA_SOR_BASE + TEGRA_SOR_SIZE - 1,
146                 .flags  = IORESOURCE_MEM,
147         },
148         {
149                 .name   = "dpaux",
150                 .start  = TEGRA_DPAUX_BASE,
151                 .end    = TEGRA_DPAUX_BASE + TEGRA_DPAUX_SIZE - 1,
152                 .flags  = IORESOURCE_MEM,
153         },
154         {
155                 .name   = "irq_dp",
156                 .start  = INT_DPAUX,
157                 .end    = INT_DPAUX,
158                 .flags  = IORESOURCE_IRQ,
159         },
160 };
161
162 static struct resource ardbeg_disp2_resources[] = {
163         {
164                 .name   = "irq",
165                 .start  = INT_DISPLAY_B_GENERAL,
166                 .end    = INT_DISPLAY_B_GENERAL,
167                 .flags  = IORESOURCE_IRQ,
168         },
169         {
170                 .name   = "regs",
171                 .start  = TEGRA_DISPLAY2_BASE,
172                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
173                 .flags  = IORESOURCE_MEM,
174         },
175         {
176                 .name   = "fbmem",
177                 .start  = 0, /* Filled in by ardbeg_panel_init() */
178                 .end    = 0, /* Filled in by ardbeg_panel_init() */
179                 .flags  = IORESOURCE_MEM,
180         },
181         {
182                 .name   = "hdmi_regs",
183                 .start  = TEGRA_HDMI_BASE,
184                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
185                 .flags  = IORESOURCE_MEM,
186         },
187 };
188
189
190 static struct tegra_dc_sd_settings sd_settings;
191
192 static struct tegra_dc_out ardbeg_disp1_out = {
193         .type           = TEGRA_DC_OUT_DSI,
194         .sd_settings    = &sd_settings,
195 };
196
197 static int ardbeg_hdmi_enable(struct device *dev)
198 {
199         int ret;
200         if (!ardbeg_hdmi_reg) {
201                 ardbeg_hdmi_reg = regulator_get(dev, "avdd_hdmi");
202                 if (IS_ERR(ardbeg_hdmi_reg)) {
203                         pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
204                         ardbeg_hdmi_reg = NULL;
205                         return PTR_ERR(ardbeg_hdmi_reg);
206                 }
207         }
208         ret = regulator_enable(ardbeg_hdmi_reg);
209         if (ret < 0) {
210                 pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
211                 return ret;
212         }
213         if (!ardbeg_hdmi_pll) {
214                 ardbeg_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll");
215                 if (IS_ERR(ardbeg_hdmi_pll)) {
216                         pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
217                         ardbeg_hdmi_pll = NULL;
218                         regulator_put(ardbeg_hdmi_reg);
219                         ardbeg_hdmi_reg = NULL;
220                         return PTR_ERR(ardbeg_hdmi_pll);
221                 }
222         }
223         ret = regulator_enable(ardbeg_hdmi_pll);
224         if (ret < 0) {
225                 pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
226                 return ret;
227         }
228         return 0;
229 }
230
231 static int ardbeg_hdmi_disable(void)
232 {
233         if (ardbeg_hdmi_reg) {
234                 regulator_disable(ardbeg_hdmi_reg);
235                 regulator_put(ardbeg_hdmi_reg);
236                 ardbeg_hdmi_reg = NULL;
237         }
238
239         if (ardbeg_hdmi_pll) {
240                 regulator_disable(ardbeg_hdmi_pll);
241                 regulator_put(ardbeg_hdmi_pll);
242                 ardbeg_hdmi_pll = NULL;
243         }
244         return 0;
245 }
246
247 static int ardbeg_hdmi_postsuspend(void)
248 {
249         if (ardbeg_hdmi_vddio) {
250                 regulator_disable(ardbeg_hdmi_vddio);
251                 regulator_put(ardbeg_hdmi_vddio);
252                 ardbeg_hdmi_vddio = NULL;
253         }
254         return 0;
255 }
256
257 static int ardbeg_hdmi_hotplug_init(struct device *dev)
258 {
259         if (!ardbeg_hdmi_vddio) {
260                 ardbeg_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0");
261                 if (WARN_ON(IS_ERR(ardbeg_hdmi_vddio))) {
262                         pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %ld\n",
263                                 __func__, PTR_ERR(ardbeg_hdmi_vddio));
264                                 ardbeg_hdmi_vddio = NULL;
265                 } else {
266                         return regulator_enable(ardbeg_hdmi_vddio);
267                 }
268         }
269
270         return 0;
271 }
272
273 struct tmds_config ardbeg_tmds_config[] = {
274         { /* 480p/576p / 25.2MHz/27MHz modes */
275         .pclk = 27000000,
276         .pll0 = 0x01003110,
277         .pll1 = 0x00300F00,
278         .pe_current = 0x08080808,
279         .drive_current = 0x2e2e2e2e,
280         .peak_current = 0x00000000,
281         },
282         { /* 720p / 74.25MHz modes */
283         .pclk = 74250000,
284         .pll0 =  0x01003310,
285         .pll1 = 0x10300F00,
286         .pe_current = 0x08080808,
287         .drive_current = 0x20202020,
288         .peak_current = 0x00000000,
289         },
290         { /* 1080p / 148.5MHz modes */
291         .pclk = 148500000,
292         .pll0 = 0x01003310,
293         .pll1 = 0x10300F00,
294         .pe_current = 0x08080808,
295         .drive_current = 0x20202020,
296         .peak_current = 0x00000000,
297         },
298         {
299         .pclk = INT_MAX,
300         .pll0 = 0x01003310,
301         .pll1 = 0x10300F00,
302         .pe_current = 0x08080808,
303         .drive_current = 0x3A353536, /* lane3 needs a slightly lower current */
304         .peak_current = 0x00000000,
305         },
306 };
307
308 struct tegra_hdmi_out ardbeg_hdmi_out = {
309         .tmds_config = ardbeg_tmds_config,
310         .n_tmds_config = ARRAY_SIZE(ardbeg_tmds_config),
311 };
312
313
314 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
315 static struct tegra_dc_mode hdmi_panel_modes[] = {
316         {
317                 .pclk =                 KHZ2PICOS(25200),
318                 .h_ref_to_sync =        1,
319                 .v_ref_to_sync =        1,
320                 .h_sync_width =         96,     /* hsync_len */
321                 .v_sync_width =         2,      /* vsync_len */
322                 .h_back_porch =         48,     /* left_margin */
323                 .v_back_porch =         33,     /* upper_margin */
324                 .h_active =             640,    /* xres */
325                 .v_active =             480,    /* yres */
326                 .h_front_porch =        16,     /* right_margin */
327                 .v_front_porch =        10,     /* lower_margin */
328         },
329 };
330 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
331
332 static struct tegra_dc_out ardbeg_disp2_out = {
333         .type           = TEGRA_DC_OUT_HDMI,
334         .flags          = TEGRA_DC_OUT_HOTPLUG_HIGH,
335         .parent_clk     = "pll_d2",
336
337         .dcc_bus        = 3,
338         .hotplug_gpio   = ardbeg_hdmi_hpd,
339         .hdmi_out       = &ardbeg_hdmi_out,
340
341         /* TODO: update max pclk to POR */
342         .max_pixclock   = KHZ2PICOS(297000),
343 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
344         .modes = hdmi_panel_modes,
345         .n_modes = ARRAY_SIZE(hdmi_panel_modes),
346         .depth = 24,
347 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
348
349         .align          = TEGRA_DC_ALIGN_MSB,
350         .order          = TEGRA_DC_ORDER_RED_BLUE,
351
352         .enable         = ardbeg_hdmi_enable,
353         .disable        = ardbeg_hdmi_disable,
354         .postsuspend    = ardbeg_hdmi_postsuspend,
355         .hotplug_init   = ardbeg_hdmi_hotplug_init,
356 };
357
358 static struct tegra_fb_data ardbeg_disp1_fb_data = {
359         .win            = 0,
360         .bits_per_pixel = 32,
361         .flags          = TEGRA_FB_FLIP_ON_PROBE,
362 };
363
364 static struct tegra_dc_platform_data ardbeg_disp1_pdata = {
365         .flags          = TEGRA_DC_FLAG_ENABLED,
366         .default_out    = &ardbeg_disp1_out,
367         .fb             = &ardbeg_disp1_fb_data,
368         .emc_clk_rate   = 204000000,
369 #ifdef CONFIG_TEGRA_DC_CMU
370         .cmu_enable     = 1,
371 #endif
372 };
373
374 static struct tegra_fb_data ardbeg_disp2_fb_data = {
375         .win            = 0,
376         .xres           = 1280,
377         .yres           = 720,
378         .bits_per_pixel = 32,
379         .flags          = TEGRA_FB_FLIP_ON_PROBE,
380 };
381
382 static struct tegra_dc_platform_data ardbeg_disp2_pdata = {
383         .flags          = TEGRA_DC_FLAG_ENABLED,
384         .default_out    = &ardbeg_disp2_out,
385         .fb             = &ardbeg_disp2_fb_data,
386         .emc_clk_rate   = 300000000,
387 };
388
389 static struct platform_device ardbeg_disp2_device = {
390         .name           = "tegradc",
391         .id             = 1,
392         .resource       = ardbeg_disp2_resources,
393         .num_resources  = ARRAY_SIZE(ardbeg_disp2_resources),
394         .dev = {
395                 .platform_data = &ardbeg_disp2_pdata,
396         },
397 };
398
399 static struct platform_device ardbeg_disp1_device = {
400         .name           = "tegradc",
401         .id             = 0,
402         .resource       = ardbeg_disp1_resources,
403         .num_resources  = ARRAY_SIZE(ardbeg_disp1_resources),
404         .dev = {
405                 .platform_data = &ardbeg_disp1_pdata,
406         },
407 };
408
409 static struct nvmap_platform_carveout ardbeg_carveouts[] = {
410         [0] = {
411                 .name           = "iram",
412                 .usage_mask     = NVMAP_HEAP_CARVEOUT_IRAM,
413                 .base           = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
414                 .size           = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
415         },
416         [1] = {
417                 .name           = "generic-0",
418                 .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
419                 .base           = 0, /* Filled in by ardbeg_panel_init() */
420                 .size           = 0, /* Filled in by ardbeg_panel_init() */
421         },
422         [2] = {
423                 .name           = "vpr",
424                 .usage_mask     = NVMAP_HEAP_CARVEOUT_VPR,
425                 .base           = 0, /* Filled in by ardbeg_panel_init() */
426                 .size           = 0, /* Filled in by ardbeg_panel_init() */
427         },
428 };
429
430 static struct nvmap_platform_data ardbeg_nvmap_data = {
431         .carveouts      = ardbeg_carveouts,
432         .nr_carveouts   = ARRAY_SIZE(ardbeg_carveouts),
433 };
434 static struct platform_device ardbeg_nvmap_device  = {
435         .name   = "tegra-nvmap",
436         .id     = -1,
437         .dev    = {
438                 .platform_data = &ardbeg_nvmap_data,
439         },
440 };
441
442 static struct tegra_dc_sd_settings ardbeg_sd_settings = {
443         .enable = 1, /* enabled by default. */
444         .use_auto_pwm = false,
445         .hw_update_delay = 0,
446         .bin_width = -1,
447         .aggressiveness = 5,
448         .use_vid_luma = false,
449         .phase_in_adjustments = 0,
450         .k_limit_enable = true,
451         .k_limit = 200,
452         .sd_window_enable = false,
453         .soft_clipping_enable = true,
454         /* Low soft clipping threshold to compensate for aggressive k_limit */
455         .soft_clipping_threshold = 128,
456         .smooth_k_enable = false,
457         .smooth_k_incr = 64,
458         /* Default video coefficients */
459         .coeff = {5, 9, 2},
460         .fc = {0, 0},
461         /* Immediate backlight changes */
462         .blp = {1024, 255},
463         /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
464         /* Default BL TF */
465         .bltf = {
466                         {
467                                 {57, 65, 73, 82},
468                                 {92, 103, 114, 125},
469                                 {138, 150, 164, 178},
470                                 {193, 208, 224, 241},
471                         },
472                 },
473         /* Default LUT */
474         .lut = {
475                         {
476                                 {255, 255, 255},
477                                 {199, 199, 199},
478                                 {153, 153, 153},
479                                 {116, 116, 116},
480                                 {85, 85, 85},
481                                 {59, 59, 59},
482                                 {36, 36, 36},
483                                 {17, 17, 17},
484                                 {0, 0, 0},
485                         },
486                 },
487         .sd_brightness = &sd_brightness,
488         .use_vpulse2 = true,
489 };
490
491 /* can be called multiple times */
492 static struct tegra_panel *ardbeg_panel_configure(struct board_info *board_out,
493         u8 *dsi_instance_out)
494 {
495         struct tegra_panel *panel = NULL;
496         u8 dsi_instance;
497         struct board_info boardtmp;
498
499         if (!board_out)
500                 board_out = &boardtmp;
501         tegra_get_display_board_info(board_out);
502
503         switch (board_out->board_id) {
504         case BOARD_E1639:
505         case BOARD_E1813:
506                 panel = &dsi_s_wqxga_10_1;
507                 dsi_instance = DSI_INSTANCE_0;
508                 break;
509         case BOARD_PM354:
510                 panel = &dsi_a_1080p_14_0;
511                 dsi_instance = DSI_INSTANCE_0;
512                 break;
513         case BOARD_E1627:
514                 panel = &dsi_p_wuxga_10_1;
515                 dsi_instance = DSI_INSTANCE_0;
516                 break;
517         case BOARD_E1549:
518                 panel = &dsi_lgd_wxga_7_0;
519                 dsi_instance = DSI_INSTANCE_0;
520                 break;
521         case BOARD_PM363:
522         case BOARD_E1824:
523                 panel = &edp_a_1080p_14_0;
524                 ardbeg_disp1_out.type = TEGRA_DC_OUT_DP;
525                 ardbeg_disp1_device.resource = ardbeg_disp1_edp_resources;
526                 ardbeg_disp1_device.num_resources =
527                         ARRAY_SIZE(ardbeg_disp1_edp_resources);
528                 break;
529         case BOARD_PM366:
530                 panel = &lvds_c_1366_14;
531                 ardbeg_disp1_out.type = TEGRA_DC_OUT_LVDS;
532                 ardbeg_disp1_device.resource = ardbeg_disp1_edp_resources;
533                 ardbeg_disp1_device.num_resources =
534                         ARRAY_SIZE(ardbeg_disp1_edp_resources);
535                 break;
536         default:
537                 panel = &dsi_p_wuxga_10_1;
538                 dsi_instance = DSI_INSTANCE_0;
539                 break;
540         }
541         if (dsi_instance_out)
542                 *dsi_instance_out = dsi_instance;
543         return panel;
544 }
545
546 static void ardbeg_panel_select(void)
547 {
548         struct tegra_panel *panel = NULL;
549         struct board_info board;
550         u8 dsi_instance;
551
552         panel = ardbeg_panel_configure(&board, &dsi_instance);
553
554         if (panel) {
555                 if (panel->init_sd_settings)
556                         panel->init_sd_settings(&sd_settings);
557
558                 if (panel->init_dc_out) {
559                         panel->init_dc_out(&ardbeg_disp1_out);
560                         if (ardbeg_disp1_out.type == TEGRA_DC_OUT_DSI) {
561                                 ardbeg_disp1_out.dsi->dsi_instance =
562                                         dsi_instance;
563                                 ardbeg_disp1_out.dsi->dsi_panel_rst_gpio =
564                                         DSI_PANEL_RST_GPIO;
565                                 ardbeg_disp1_out.dsi->dsi_panel_bl_pwm_gpio =
566                                         DSI_PANEL_BL_PWM_GPIO;
567                                 ardbeg_disp1_out.dsi->te_gpio = TEGRA_GPIO_PR6;
568                         }
569                 }
570
571                 if (panel->init_fb_data)
572                         panel->init_fb_data(&ardbeg_disp1_fb_data);
573
574                 if (panel->init_cmu_data)
575                         panel->init_cmu_data(&ardbeg_disp1_pdata);
576
577                 if (panel->set_disp_device)
578                         panel->set_disp_device(&ardbeg_disp1_device);
579
580                 if (ardbeg_disp1_out.type == TEGRA_DC_OUT_DSI) {
581                         tegra_dsi_resources_init(dsi_instance,
582                                 ardbeg_disp1_resources,
583                                 ARRAY_SIZE(ardbeg_disp1_resources));
584                 }
585
586                 if (panel->register_bl_dev)
587                         panel->register_bl_dev();
588
589                 if (panel->register_i2c_bridge)
590                         panel->register_i2c_bridge();
591         }
592
593 }
594 int __init ardbeg_panel_init(void)
595 {
596         int err = 0;
597         struct resource __maybe_unused *res;
598         struct platform_device *phost1x = NULL;
599
600         sd_settings = ardbeg_sd_settings;
601
602         ardbeg_panel_select();
603
604 #ifdef CONFIG_TEGRA_NVMAP
605         ardbeg_carveouts[1].base = tegra_carveout_start;
606         ardbeg_carveouts[1].size = tegra_carveout_size;
607         ardbeg_carveouts[2].base = tegra_vpr_start;
608         ardbeg_carveouts[2].size = tegra_vpr_size;
609 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
610         carveout_linear_set(&tegra_generic_cma_dev);
611         ardbeg_carveouts[1].cma_dev = &tegra_generic_cma_dev;
612         ardbeg_carveouts[1].resize = false;
613         carveout_linear_set(&tegra_vpr_cma_dev);
614         ardbeg_carveouts[2].cma_dev = &tegra_vpr_cma_dev;
615         ardbeg_carveouts[2].resize = true;
616         ardbeg_carveouts[2].cma_chunk_size = SZ_32M;
617 #endif
618
619         err = platform_device_register(&ardbeg_nvmap_device);
620         if (err) {
621                 pr_err("nvmap device registration failed\n");
622                 return err;
623         }
624 #endif
625
626         phost1x = ardbeg_host1x_init();
627         if (!phost1x) {
628                 pr_err("host1x devices registration failed\n");
629                 return -EINVAL;
630         }
631
632         res = platform_get_resource_byname(&ardbeg_disp1_device,
633                                          IORESOURCE_MEM, "fbmem");
634         res->start = tegra_fb_start;
635         res->end = tegra_fb_start + tegra_fb_size - 1;
636
637         /* Copy the bootloader fb to the fb. */
638         if (tegra_bootloader_fb_size)
639                 __tegra_move_framebuffer(&ardbeg_nvmap_device,
640                                 tegra_fb_start, tegra_bootloader_fb_start,
641                                 min(tegra_fb_size, tegra_bootloader_fb_size));
642         else
643                 __tegra_clear_framebuffer(&ardbeg_nvmap_device,
644                                           tegra_fb_start, tegra_fb_size);
645
646         ardbeg_disp1_device.dev.parent = &phost1x->dev;
647         err = platform_device_register(&ardbeg_disp1_device);
648         if (err) {
649                 pr_err("disp1 device registration failed\n");
650                 return err;
651         }
652
653         err = tegra_init_hdmi(&ardbeg_disp2_device, phost1x);
654         if (err)
655                 return err;
656
657 #ifdef CONFIG_TEGRA_NVAVP
658         nvavp_device.dev.parent = &phost1x->dev;
659         err = platform_device_register(&nvavp_device);
660         if (err) {
661                 pr_err("nvavp device registration failed\n");
662                 return err;
663         }
664 #endif
665         return err;
666 }
667
668 int __init ardbeg_display_init(void)
669 {
670         struct clk *disp1_clk = clk_get_sys("tegradc.0", NULL);
671         struct clk *disp2_clk = clk_get_sys("tegradc.1", NULL);
672         struct tegra_panel *panel;
673         struct board_info board;
674         long disp1_rate;
675         long disp2_rate;
676
677         if (WARN_ON(IS_ERR(disp1_clk))) {
678                 if (disp2_clk && !IS_ERR(disp2_clk))
679                         clk_put(disp2_clk);
680                 return PTR_ERR(disp1_clk);
681         }
682
683         if (WARN_ON(IS_ERR(disp2_clk))) {
684                 clk_put(disp1_clk);
685                 return PTR_ERR(disp1_clk);
686         }
687
688         panel = ardbeg_panel_configure(&board, NULL);
689
690         if (panel && panel->init_dc_out) {
691                 panel->init_dc_out(&ardbeg_disp1_out);
692                 if (ardbeg_disp1_out.n_modes && ardbeg_disp1_out.modes)
693                         disp1_rate = ardbeg_disp1_out.modes[0].pclk;
694         } else {
695                 disp1_rate = 0;
696                 if (!panel || !panel->init_dc_out)
697                         printk(KERN_ERR "disp1 panel output not specified!\n");
698         }
699
700         printk(KERN_DEBUG "disp1 pclk=%ld\n", disp1_rate);
701         if (disp1_rate)
702                 tegra_dvfs_resolve_override(disp1_clk, disp1_rate);
703
704
705         /* set up disp2 */
706         if (ardbeg_disp2_out.max_pixclock)
707                 disp2_rate = PICOS2KHZ(ardbeg_disp2_out.max_pixclock) * 1000;
708         else
709                 disp2_rate = 297000000; /* HDMI 4K */
710         printk(KERN_DEBUG "disp2 pclk=%ld\n", disp2_rate);
711         if (disp2_rate)
712                 tegra_dvfs_resolve_override(disp2_clk, disp2_rate);
713
714         clk_put(disp1_clk);
715         clk_put(disp2_clk);
716         return 0;
717 }