4e3537924775545f9d11d88a9d3bc97242ebe187
[linux-3.10.git] / arch / arm / mach-tegra / board-ardbeg-panel.c
1 /*
2  * arch/arm/mach-tegra/board-ardbeg-panel.c
3  *
4  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20 #include <linux/ioport.h>
21 #include <linux/fb.h>
22 #include <linux/nvmap.h>
23 #include <linux/nvhost.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/gpio.h>
27 #include <linux/tegra_pwm_bl.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/pwm_backlight.h>
30 #include <linux/of.h>
31 #include <linux/of_address.h>
32 #include <linux/dma-contiguous.h>
33 #include <linux/clk.h>
34
35 #include <mach/irqs.h>
36 #include <mach/dc.h>
37 #include <mach/io_dpd.h>
38
39 #include "board.h"
40 #include "devices.h"
41 #include "gpio-names.h"
42 #include "board-ardbeg.h"
43 #include "board-panel.h"
44 #include "common.h"
45 #include "iomap.h"
46 #include "tegra12_host1x_devices.h"
47 #include "dvfs.h"
48
49 struct platform_device * __init ardbeg_host1x_init(void)
50 {
51         struct platform_device *pdev = NULL;
52
53 #ifdef CONFIG_TEGRA_GRHOST
54         if (!of_have_populated_dt())
55                 pdev = tegra12_register_host1x_devices();
56         else
57                 pdev = to_platform_device(bus_find_device_by_name(
58                         &platform_bus_type, NULL, "host1x"));
59
60         if (!pdev) {
61                 pr_err("host1x devices registration failed\n");
62                 return NULL;
63         }
64 #endif
65         return pdev;
66 }
67
68 /* hdmi related regulators */
69 static struct regulator *ardbeg_hdmi_reg;
70 static struct regulator *ardbeg_hdmi_pll;
71 static struct regulator *ardbeg_hdmi_vddio;
72
73 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
74 static struct resource ardbeg_disp1_resources[] = {
75         {
76                 .name   = "irq",
77                 .start  = INT_DISPLAY_GENERAL,
78                 .end    = INT_DISPLAY_GENERAL,
79                 .flags  = IORESOURCE_IRQ,
80         },
81         {
82                 .name   = "regs",
83                 .start  = TEGRA_DISPLAY_BASE,
84                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
85                 .flags  = IORESOURCE_MEM,
86         },
87         {
88                 .name   = "fbmem",
89                 .start  = 0, /* Filled in by ardbeg_panel_init() */
90                 .end    = 0, /* Filled in by ardbeg_panel_init() */
91                 .flags  = IORESOURCE_MEM,
92         },
93         {
94                 .name   = "ganged_dsia_regs",
95                 .start  = 0, /* Filled in the panel file by init_resources() */
96                 .end    = 0, /* Filled in the panel file by init_resources() */
97                 .flags  = IORESOURCE_MEM,
98         },
99         {
100                 .name   = "ganged_dsib_regs",
101                 .start  = 0, /* Filled in the panel file by init_resources() */
102                 .end    = 0, /* Filled in the panel file by init_resources() */
103                 .flags  = IORESOURCE_MEM,
104         },
105         {
106                 .name   = "dsi_regs",
107                 .start  = 0, /* Filled in the panel file by init_resources() */
108                 .end    = 0, /* Filled in the panel file by init_resources() */
109                 .flags  = IORESOURCE_MEM,
110         },
111         {
112                 .name   = "mipi_cal",
113                 .start  = TEGRA_MIPI_CAL_BASE,
114                 .end    = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
115                 .flags  = IORESOURCE_MEM,
116         },
117 };
118
119 static struct resource ardbeg_disp1_edp_resources[] = {
120         {
121                 .name   = "irq",
122                 .start  = INT_DISPLAY_GENERAL,
123                 .end    = INT_DISPLAY_GENERAL,
124                 .flags  = IORESOURCE_IRQ,
125         },
126         {
127                 .name   = "regs",
128                 .start  = TEGRA_DISPLAY_BASE,
129                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
130                 .flags  = IORESOURCE_MEM,
131         },
132         {
133                 .name   = "fbmem",
134                 .start  = 0, /* Filled in by ardbeg_panel_init() */
135                 .end    = 0, /* Filled in by ardbeg_panel_init() */
136                 .flags  = IORESOURCE_MEM,
137         },
138         {
139                 .name   = "mipi_cal",
140                 .start  = TEGRA_MIPI_CAL_BASE,
141                 .end    = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
142                 .flags  = IORESOURCE_MEM,
143         },
144         {
145                 .name   = "sor",
146                 .start  = TEGRA_SOR_BASE,
147                 .end    = TEGRA_SOR_BASE + TEGRA_SOR_SIZE - 1,
148                 .flags  = IORESOURCE_MEM,
149         },
150         {
151                 .name   = "dpaux",
152                 .start  = TEGRA_DPAUX_BASE,
153                 .end    = TEGRA_DPAUX_BASE + TEGRA_DPAUX_SIZE - 1,
154                 .flags  = IORESOURCE_MEM,
155         },
156         {
157                 .name   = "irq_dp",
158                 .start  = INT_DPAUX,
159                 .end    = INT_DPAUX,
160                 .flags  = IORESOURCE_IRQ,
161         },
162 };
163 #endif
164
165 static struct resource ardbeg_disp2_resources[] = {
166         {
167                 .name   = "irq",
168 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
169                 .start  = INT_DISPLAY_B_GENERAL,
170                 .end    = INT_DISPLAY_B_GENERAL,
171 #else
172                 .start  = INT_DISPLAY_GENERAL,
173                 .end    = INT_DISPLAY_GENERAL,
174 #endif
175                 .flags  = IORESOURCE_IRQ,
176         },
177         {
178                 .name   = "regs",
179 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
180                 .start  = TEGRA_DISPLAY2_BASE,
181                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
182 #else
183                 .start  = TEGRA_DISPLAY_BASE,
184                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
185 #endif
186                 .flags  = IORESOURCE_MEM,
187         },
188         {
189                 .name   = "fbmem",
190                 .start  = 0, /* Filled in by ardbeg_panel_init() */
191                 .end    = 0, /* Filled in by ardbeg_panel_init() */
192                 .flags  = IORESOURCE_MEM,
193         },
194         {
195                 .name   = "hdmi_regs",
196                 .start  = TEGRA_HDMI_BASE,
197                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
198                 .flags  = IORESOURCE_MEM,
199         },
200 };
201
202
203 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
204 static struct tegra_dc_sd_settings sd_settings;
205
206 static struct tegra_dc_out ardbeg_disp1_out = {
207         .type           = TEGRA_DC_OUT_DSI,
208         .sd_settings    = &sd_settings,
209 };
210 #endif
211
212 static int ardbeg_hdmi_enable(struct device *dev)
213 {
214         int ret;
215         if (!ardbeg_hdmi_reg) {
216                 ardbeg_hdmi_reg = regulator_get(dev, "avdd_hdmi");
217                 if (IS_ERR(ardbeg_hdmi_reg)) {
218                         pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
219                         ardbeg_hdmi_reg = NULL;
220                         return PTR_ERR(ardbeg_hdmi_reg);
221                 }
222         }
223         ret = regulator_enable(ardbeg_hdmi_reg);
224         if (ret < 0) {
225                 pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
226                 return ret;
227         }
228         if (!ardbeg_hdmi_pll) {
229                 ardbeg_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll");
230                 if (IS_ERR(ardbeg_hdmi_pll)) {
231                         pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
232                         ardbeg_hdmi_pll = NULL;
233                         regulator_put(ardbeg_hdmi_reg);
234                         ardbeg_hdmi_reg = NULL;
235                         return PTR_ERR(ardbeg_hdmi_pll);
236                 }
237         }
238         ret = regulator_enable(ardbeg_hdmi_pll);
239         if (ret < 0) {
240                 pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
241                 return ret;
242         }
243         return 0;
244 }
245
246 static int ardbeg_hdmi_disable(void)
247 {
248         if (ardbeg_hdmi_reg) {
249                 regulator_disable(ardbeg_hdmi_reg);
250                 regulator_put(ardbeg_hdmi_reg);
251                 ardbeg_hdmi_reg = NULL;
252         }
253
254         if (ardbeg_hdmi_pll) {
255                 regulator_disable(ardbeg_hdmi_pll);
256                 regulator_put(ardbeg_hdmi_pll);
257                 ardbeg_hdmi_pll = NULL;
258         }
259         return 0;
260 }
261
262 static int ardbeg_hdmi_postsuspend(void)
263 {
264         if (ardbeg_hdmi_vddio) {
265                 regulator_disable(ardbeg_hdmi_vddio);
266                 regulator_put(ardbeg_hdmi_vddio);
267                 ardbeg_hdmi_vddio = NULL;
268         }
269         return 0;
270 }
271
272 static int ardbeg_hdmi_hotplug_init(struct device *dev)
273 {
274         if (!ardbeg_hdmi_vddio) {
275 #ifdef CONFIG_TEGRA_HDMI_PRIMARY
276                 if (of_machine_is_compatible("nvidia,tn8"))
277                         ardbeg_hdmi_vddio = regulator_get(dev, "vdd-out1-5v0");
278                 else
279                         ardbeg_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0");
280 #else
281                 ardbeg_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0");
282 #endif
283                 if (WARN_ON(IS_ERR(ardbeg_hdmi_vddio))) {
284                         pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %ld\n",
285                                 __func__, PTR_ERR(ardbeg_hdmi_vddio));
286                                 ardbeg_hdmi_vddio = NULL;
287                 } else {
288                         return regulator_enable(ardbeg_hdmi_vddio);
289                 }
290         }
291
292         return 0;
293 }
294
295 struct tmds_config ardbeg_tmds_config[] = {
296         { /* 480p/576p / 25.2MHz/27MHz modes */
297         .pclk = 27000000,
298         .pll0 = 0x01003110,
299         .pll1 = 0x00300F00,
300         .pe_current = 0x08080808,
301         .drive_current = 0x2e2e2e2e,
302         .peak_current = 0x00000000,
303         },
304         { /* 720p / 74.25MHz modes */
305         .pclk = 74250000,
306         .pll0 =  0x01003310,
307         .pll1 = 0x10300F00,
308         .pe_current = 0x08080808,
309         .drive_current = 0x20202020,
310         .peak_current = 0x00000000,
311         },
312         { /* 1080p / 148.5MHz modes */
313         .pclk = 148500000,
314         .pll0 = 0x01003310,
315         .pll1 = 0x10300F00,
316         .pe_current = 0x08080808,
317         .drive_current = 0x20202020,
318         .peak_current = 0x00000000,
319         },
320         {
321         .pclk = INT_MAX,
322         .pll0 = 0x01003310,
323         .pll1 = 0x10300F00,
324         .pe_current = 0x08080808,
325         .drive_current = 0x3A353536, /* lane3 needs a slightly lower current */
326         .peak_current = 0x00000000,
327         },
328 };
329
330 struct tegra_hdmi_out ardbeg_hdmi_out = {
331         .tmds_config = ardbeg_tmds_config,
332         .n_tmds_config = ARRAY_SIZE(ardbeg_tmds_config),
333 };
334
335
336 #if defined(CONFIG_FRAMEBUFFER_CONSOLE)
337 static struct tegra_dc_mode hdmi_panel_modes[] = {
338         {
339                 .pclk =                 KHZ2PICOS(25200),
340                 .h_ref_to_sync =        1,
341                 .v_ref_to_sync =        1,
342                 .h_sync_width =         96,     /* hsync_len */
343                 .v_sync_width =         2,      /* vsync_len */
344                 .h_back_porch =         48,     /* left_margin */
345                 .v_back_porch =         33,     /* upper_margin */
346                 .h_active =             640,    /* xres */
347                 .v_active =             480,    /* yres */
348                 .h_front_porch =        16,     /* right_margin */
349                 .v_front_porch =        10,     /* lower_margin */
350         },
351 };
352 #elif defined(CONFIG_TEGRA_HDMI_PRIMARY)
353 static struct tegra_dc_mode hdmi_panel_modes[] = {
354         {
355                 .pclk =                 148500000,
356                 .h_ref_to_sync =        1,
357                 .v_ref_to_sync =        1,
358                 .h_sync_width =         44,     /* hsync_len */
359                 .v_sync_width =         5,      /* vsync_len */
360                 .h_back_porch =         148,    /* left_margin */
361                 .v_back_porch =         36,     /* upper_margin */
362                 .h_active =             1920,   /* xres */
363                 .v_active =             1080,   /* yres */
364                 .h_front_porch =        88,     /* right_margin */
365                 .v_front_porch =        4,      /* lower_margin */
366         },
367 };
368 #endif /* CONFIG_FRAMEBUFFER_CONSOLE || CONFIG_TEGRA_HDMI_PRIMARY*/
369
370 static struct tegra_dc_out ardbeg_disp2_out = {
371         .type           = TEGRA_DC_OUT_HDMI,
372         .flags          = TEGRA_DC_OUT_HOTPLUG_HIGH,
373         .parent_clk     = "pll_d2",
374
375         .dcc_bus        = 3,
376         .hotplug_gpio   = ardbeg_hdmi_hpd,
377         .hdmi_out       = &ardbeg_hdmi_out,
378
379         /* TODO: update max pclk to POR */
380         .max_pixclock   = KHZ2PICOS(297000),
381 #if defined(CONFIG_FRAMEBUFFER_CONSOLE) || defined(CONFIG_TEGRA_HDMI_PRIMARY)
382         .modes = hdmi_panel_modes,
383         .n_modes = ARRAY_SIZE(hdmi_panel_modes),
384         .depth = 24,
385 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
386
387         .align          = TEGRA_DC_ALIGN_MSB,
388         .order          = TEGRA_DC_ORDER_RED_BLUE,
389
390         .enable         = ardbeg_hdmi_enable,
391         .disable        = ardbeg_hdmi_disable,
392         .postsuspend    = ardbeg_hdmi_postsuspend,
393         .hotplug_init   = ardbeg_hdmi_hotplug_init,
394 };
395
396 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
397 static struct tegra_fb_data ardbeg_disp1_fb_data = {
398         .win            = 0,
399         .bits_per_pixel = 32,
400         .flags          = TEGRA_FB_FLIP_ON_PROBE,
401 };
402
403 static struct tegra_dc_platform_data ardbeg_disp1_pdata = {
404         .flags          = TEGRA_DC_FLAG_ENABLED,
405         .default_out    = &ardbeg_disp1_out,
406         .fb             = &ardbeg_disp1_fb_data,
407         .emc_clk_rate   = 204000000,
408 #ifdef CONFIG_TEGRA_DC_CMU
409         .cmu_enable     = 1,
410 #endif
411         .low_v_win      = 0x02,
412 };
413 #endif
414
415 static struct tegra_fb_data ardbeg_disp2_fb_data = {
416         .win            = 0,
417         .xres           = 1920,
418         .yres           = 1080,
419         .bits_per_pixel = 32,
420         .flags          = TEGRA_FB_FLIP_ON_PROBE,
421 };
422
423 static struct tegra_dc_platform_data ardbeg_disp2_pdata = {
424         .flags          = TEGRA_DC_FLAG_ENABLED,
425         .default_out    = &ardbeg_disp2_out,
426         .fb             = &ardbeg_disp2_fb_data,
427         .emc_clk_rate   = 300000000,
428 };
429
430 static struct platform_device ardbeg_disp2_device = {
431         .name           = "tegradc",
432 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
433         .id             = 1,
434 #else
435         .id             = 0,
436 #endif
437         .resource       = ardbeg_disp2_resources,
438         .num_resources  = ARRAY_SIZE(ardbeg_disp2_resources),
439         .dev = {
440                 .platform_data = &ardbeg_disp2_pdata,
441         },
442 };
443
444 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
445 static struct platform_device ardbeg_disp1_device = {
446         .name           = "tegradc",
447         .id             = 0,
448         .resource       = ardbeg_disp1_resources,
449         .num_resources  = ARRAY_SIZE(ardbeg_disp1_resources),
450         .dev = {
451                 .platform_data = &ardbeg_disp1_pdata,
452         },
453 };
454 #endif
455
456 static struct nvmap_platform_carveout ardbeg_carveouts[] = {
457         [0] = {
458                 .name           = "iram",
459                 .usage_mask     = NVMAP_HEAP_CARVEOUT_IRAM,
460                 .base           = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
461                 .size           = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
462         },
463         [1] = {
464                 .name           = "generic-0",
465                 .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
466                 .base           = 0, /* Filled in by ardbeg_panel_init() */
467                 .size           = 0, /* Filled in by ardbeg_panel_init() */
468         },
469         [2] = {
470                 .name           = "vpr",
471                 .usage_mask     = NVMAP_HEAP_CARVEOUT_VPR,
472                 .base           = 0, /* Filled in by ardbeg_panel_init() */
473                 .size           = 0, /* Filled in by ardbeg_panel_init() */
474         },
475 };
476
477 static struct nvmap_platform_data ardbeg_nvmap_data = {
478         .carveouts      = ardbeg_carveouts,
479         .nr_carveouts   = ARRAY_SIZE(ardbeg_carveouts),
480 };
481 static struct platform_device ardbeg_nvmap_device  = {
482         .name   = "tegra-nvmap",
483         .id     = -1,
484         .dev    = {
485                 .platform_data = &ardbeg_nvmap_data,
486         },
487 };
488 static struct tegra_io_dpd dsic_io = {
489         .name                   = "DSIC",
490         .io_dpd_reg_index       = 1,
491         .io_dpd_bit             = 8,
492 };
493 static struct tegra_io_dpd dsid_io = {
494         .name                   = "DSID",
495         .io_dpd_reg_index       = 1,
496         .io_dpd_bit             = 9,
497 };
498
499 static struct tegra_dc_dp_lt_settings ardbeg_edp_lt_data[] = {
500         /* DriveCurrent Preemphasis     PostCursor      tx_pu   load_adj */
501         {0x13131313,    0x00000000,     0x00000000,     0x0,    0x3},
502         {0x13131313,    0x00000000,     0x00000000,     0x0,    0x4},
503         {0x19191919,    0x09090909,     0x00000000,     0x0,    0x6}
504 };
505
506 static struct tegra_dp_out dp_settings = {
507         /* Panel can override this with its own LT data */
508         .lt_settings = ardbeg_edp_lt_data,
509         .n_lt_settings = ARRAY_SIZE(ardbeg_edp_lt_data),
510         .tx_pu_disable = true,
511 };
512
513 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
514 /* can be called multiple times */
515 static struct tegra_panel *ardbeg_panel_configure(struct board_info *board_out,
516         u8 *dsi_instance_out)
517 {
518         struct tegra_panel *panel = NULL;
519         u8 dsi_instance = DSI_INSTANCE_0;
520         struct board_info boardtmp;
521
522         if (!board_out)
523                 board_out = &boardtmp;
524         tegra_get_display_board_info(board_out);
525
526         switch (board_out->board_id) {
527         case BOARD_E1639:
528         case BOARD_E1813:
529                 panel = &dsi_s_wqxga_10_1;
530                 break;
531         case BOARD_PM354:
532                 panel = &dsi_a_1080p_14_0;
533                 break;
534         case BOARD_E1627:
535                 panel = &dsi_p_wuxga_10_1;
536                 tegra_io_dpd_enable(&dsic_io);
537                 tegra_io_dpd_enable(&dsid_io);
538                 break;
539         case BOARD_E1549:
540                 panel = &dsi_lgd_wxga_7_0;
541                 break;
542         case BOARD_PM363:
543         case BOARD_E1824:
544                 panel = &edp_a_1080p_14_0;
545                 ardbeg_disp1_out.type = TEGRA_DC_OUT_DP;
546                 ardbeg_disp1_out.dp_out = &dp_settings;
547                 ardbeg_disp1_device.resource = ardbeg_disp1_edp_resources;
548                 ardbeg_disp1_device.num_resources =
549                         ARRAY_SIZE(ardbeg_disp1_edp_resources);
550                 break;
551         case BOARD_PM366:
552                 panel = &lvds_c_1366_14;
553                 ardbeg_disp1_out.type = TEGRA_DC_OUT_LVDS;
554                 ardbeg_disp1_device.resource = ardbeg_disp1_edp_resources;
555                 ardbeg_disp1_device.num_resources =
556                         ARRAY_SIZE(ardbeg_disp1_edp_resources);
557                 break;
558         case BOARD_E1807:
559                 panel = &dsi_a_1200_800_8_0;
560                 dsi_instance = DSI_INSTANCE_0;
561                 break;
562         case BOARD_E1937:
563                 panel = &dsi_a_1200_1920_7_0;
564                 dsi_instance = DSI_INSTANCE_0;
565                 break;
566         case BOARD_P1761:
567                 if (tegra_get_board_panel_id())
568                         panel = &dsi_a_1200_1920_7_0;
569                 else
570                         panel = &dsi_a_1200_800_8_0;
571                 dsi_instance = DSI_INSTANCE_0;
572                 break;
573         default:
574                 panel = &dsi_p_wuxga_10_1;
575                 tegra_io_dpd_enable(&dsic_io);
576                 tegra_io_dpd_enable(&dsid_io);
577                 break;
578         }
579         if (dsi_instance_out)
580                 *dsi_instance_out = dsi_instance;
581         return panel;
582 }
583
584 static void ardbeg_panel_select(void)
585 {
586         struct tegra_panel *panel = NULL;
587         struct board_info board;
588         u8 dsi_instance;
589
590         panel = ardbeg_panel_configure(&board, &dsi_instance);
591
592         if (panel) {
593                 if (panel->init_sd_settings)
594                         panel->init_sd_settings(&sd_settings);
595
596                 if (panel->init_dc_out) {
597                         panel->init_dc_out(&ardbeg_disp1_out);
598                         if (ardbeg_disp1_out.type == TEGRA_DC_OUT_DSI) {
599                                 ardbeg_disp1_out.dsi->dsi_instance =
600                                         dsi_instance;
601                                 ardbeg_disp1_out.dsi->dsi_panel_rst_gpio =
602                                         DSI_PANEL_RST_GPIO;
603                                 ardbeg_disp1_out.dsi->dsi_panel_bl_pwm_gpio =
604                                         DSI_PANEL_BL_PWM_GPIO;
605                                 ardbeg_disp1_out.dsi->te_gpio = TEGRA_GPIO_PR6;
606                         }
607                 }
608
609                 if (panel->init_fb_data)
610                         panel->init_fb_data(&ardbeg_disp1_fb_data);
611
612                 if (panel->init_cmu_data)
613                         panel->init_cmu_data(&ardbeg_disp1_pdata);
614
615                 if (panel->set_disp_device)
616                         panel->set_disp_device(&ardbeg_disp1_device);
617
618                 if (ardbeg_disp1_out.type == TEGRA_DC_OUT_DSI) {
619                         tegra_dsi_resources_init(dsi_instance,
620                                 ardbeg_disp1_resources,
621                                 ARRAY_SIZE(ardbeg_disp1_resources));
622                 }
623
624                 if (panel->register_bl_dev)
625                         panel->register_bl_dev();
626
627                 if (panel->register_i2c_bridge)
628                         panel->register_i2c_bridge();
629         }
630
631 }
632 #endif
633
634 int __init ardbeg_panel_init(void)
635 {
636         int err = 0;
637         struct resource __maybe_unused *res;
638         struct platform_device *phost1x = NULL;
639
640         struct device_node *dc1_node = NULL;
641         struct device_node *dc2_node = NULL;
642
643         find_dc_node(&dc1_node, &dc2_node);
644
645 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
646         ardbeg_panel_select();
647 #endif
648
649 #ifdef CONFIG_TEGRA_NVMAP
650         ardbeg_carveouts[1].base = tegra_carveout_start;
651         ardbeg_carveouts[1].size = tegra_carveout_size;
652         ardbeg_carveouts[2].base = tegra_vpr_start;
653         ardbeg_carveouts[2].size = tegra_vpr_size;
654 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
655         carveout_linear_set(&tegra_generic_cma_dev);
656         ardbeg_carveouts[1].cma_dev = &tegra_generic_cma_dev;
657         ardbeg_carveouts[1].resize = false;
658         carveout_linear_set(&tegra_vpr_cma_dev);
659         ardbeg_carveouts[2].cma_dev = &tegra_vpr_cma_dev;
660         ardbeg_carveouts[2].resize = true;
661         ardbeg_carveouts[2].cma_chunk_size = SZ_32M;
662 #endif
663
664         err = platform_device_register(&ardbeg_nvmap_device);
665         if (err) {
666                 pr_err("nvmap device registration failed\n");
667                 return err;
668         }
669 #endif
670
671         phost1x = ardbeg_host1x_init();
672         if (!phost1x) {
673                 pr_err("host1x devices registration failed\n");
674                 return -EINVAL;
675         }
676
677         if (!of_have_populated_dt() || !dc1_node ||
678                 !of_device_is_available(dc1_node)) {
679 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
680                 res = platform_get_resource_byname(&ardbeg_disp1_device,
681                                          IORESOURCE_MEM, "fbmem");
682 #else
683                 res = platform_get_resource_byname(&ardbeg_disp2_device,
684                                          IORESOURCE_MEM, "fbmem");
685 #endif
686                 res->start = tegra_fb_start;
687                 res->end = tegra_fb_start + tegra_fb_size - 1;
688         }
689
690         /* Copy the bootloader fb to the fb. */
691         if (tegra_bootloader_fb_size)
692                 __tegra_move_framebuffer(&ardbeg_nvmap_device,
693                                 tegra_fb_start, tegra_bootloader_fb_start,
694                                 min(tegra_fb_size, tegra_bootloader_fb_size));
695         else
696                 __tegra_clear_framebuffer(&ardbeg_nvmap_device,
697                                           tegra_fb_start, tegra_fb_size);
698
699 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
700         if (!of_have_populated_dt() || !dc1_node ||
701                 !of_device_is_available(dc1_node)) {
702                 ardbeg_disp1_device.dev.parent = &phost1x->dev;
703                 err = platform_device_register(&ardbeg_disp1_device);
704                 if (err) {
705                         pr_err("disp1 device registration failed\n");
706                         return err;
707                 }
708         }
709 #endif
710
711         if (!of_have_populated_dt() || !dc2_node ||
712                 !of_device_is_available(dc2_node)) {
713 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
714                 res = platform_get_resource_byname(&ardbeg_disp2_device,
715                                         IORESOURCE_MEM, "fbmem");
716                 res->start = tegra_fb2_start;
717                 res->end = tegra_fb2_start + tegra_fb2_size - 1;
718 #endif
719                 ardbeg_disp2_device.dev.parent = &phost1x->dev;
720                 err = platform_device_register(&ardbeg_disp2_device);
721                 if (err) {
722                         pr_err("disp2 device registration failed\n");
723                         return err;
724                 }
725         }
726
727 #ifdef CONFIG_TEGRA_NVAVP
728         nvavp_device.dev.parent = &phost1x->dev;
729         err = platform_device_register(&nvavp_device);
730         if (err) {
731                 pr_err("nvavp device registration failed\n");
732                 return err;
733         }
734 #endif
735         return err;
736 }
737
738 int __init ardbeg_display_init(void)
739 {
740         struct clk *disp1_clk = clk_get_sys("tegradc.0", NULL);
741         struct clk *disp2_clk = clk_get_sys("tegradc.1", NULL);
742         struct tegra_panel *panel;
743         struct board_info board;
744         long disp1_rate = 0;
745         long disp2_rate = 0;
746
747         /*
748          * TODO
749          * Need to skip ardbeg_display_init
750          * when disp is registered by device_tree
751          */
752
753         if (WARN_ON(IS_ERR(disp1_clk))) {
754                 if (disp2_clk && !IS_ERR(disp2_clk))
755                         clk_put(disp2_clk);
756                 return PTR_ERR(disp1_clk);
757         }
758
759         if (WARN_ON(IS_ERR(disp2_clk))) {
760                 clk_put(disp1_clk);
761                 return PTR_ERR(disp1_clk);
762         }
763
764 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
765         panel = ardbeg_panel_configure(&board, NULL);
766
767         if (panel && panel->init_dc_out) {
768                 panel->init_dc_out(&ardbeg_disp1_out);
769                 if (ardbeg_disp1_out.n_modes && ardbeg_disp1_out.modes)
770                         disp1_rate = ardbeg_disp1_out.modes[0].pclk;
771         } else {
772                 disp1_rate = 0;
773                 if (!panel || !panel->init_dc_out)
774                         printk(KERN_ERR "disp1 panel output not specified!\n");
775         }
776
777         printk(KERN_DEBUG "disp1 pclk=%ld\n", disp1_rate);
778         if (disp1_rate)
779                 tegra_dvfs_resolve_override(disp1_clk, disp1_rate);
780 #endif
781
782         /* set up disp2 */
783         if (ardbeg_disp2_out.max_pixclock)
784                 disp2_rate = PICOS2KHZ(ardbeg_disp2_out.max_pixclock) * 1000;
785         else
786                 disp2_rate = 297000000; /* HDMI 4K */
787         printk(KERN_DEBUG "disp2 pclk=%ld\n", disp2_rate);
788         if (disp2_rate)
789 #ifndef CONFIG_TEGRA_HDMI_PRIMARY
790                 tegra_dvfs_resolve_override(disp2_clk, disp2_rate);
791 #else
792                 tegra_dvfs_resolve_override(disp1_clk, disp2_rate);
793 #endif
794
795         clk_put(disp1_clk);
796         clk_put(disp2_clk);
797         return 0;
798 }