1 # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 # This program is free software; you can redistribute it and/or modify it
4 # under the terms and conditions of the GNU General Public License,
5 # version 2, as published by the Free Software Foundation.
7 # This program is distributed in the hope it will be useful, but WITHOUT
8 # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
9 # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 # You should have received a copy of the GNU General Public License
13 # along with this program. If not, see <http://www.gnu.org/licenses/>.
17 comment "NVIDIA Tegra options"
19 config ARCH_TEGRA_2x_SOC
20 bool "Enable support for Tegra20 family"
21 depends on !ARCH_TEGRA_3x_SOC
22 depends on !ARCH_TEGRA_11x_SOC
23 depends on !ARCH_TEGRA_12x_SOC
24 depends on !ARCH_TEGRA_14x_SOC
25 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
26 select ARCH_SUPPORTS_MSI if TEGRA_PCI
27 select ARCH_TEGRA_HAS_ARM_SCU
28 select ARCH_TEGRA_HAS_PCIE
29 select ARM_CPU_SUSPEND if PM
30 select ARM_ERRATA_716044
31 select ARM_ERRATA_720789
32 select ARM_ERRATA_742230 if SMP
33 select ARM_ERRATA_751472
34 select ARM_ERRATA_754327 if SMP
35 select ARM_ERRATA_761320 if SMP
36 select ARM_ERRATA_764369 if SMP
38 select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
41 select CPU_FREQ_TABLE if CPU_FREQ
43 select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
44 select NVMAP_DEFERRED_CACHE_MAINT if TEGRA_NVMAP
45 select NVMAP_HANDLE_MARSHAL if TEGRA_NVMAP
46 select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
47 select PCI_MSI if TEGRA_PCI
49 select PINCTRL_TEGRA20
52 select PL310_ERRATA_769419 if CACHE_L2X0
53 select PM_GENERIC_DOMAINS if PM
55 select USB_ARCH_HAS_EHCI if USB_SUPPORT
56 select USB_ULPI if USB_PHY
57 select USB_ULPI_VIEWPORT if USB_PHY
59 Support for NVIDIA Tegra AP20 and T20 processors, based on the
60 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
62 config ARCH_TEGRA_3x_SOC
63 bool "Enable support for Tegra30 family"
64 depends on !ARCH_TEGRA_11x_SOC
65 depends on !ARCH_TEGRA_12x_SOC
66 depends on !ARCH_TEGRA_14x_SOC
67 select ARCH_SUPPORTS_MSI if TEGRA_PCI
68 select ARCH_TEGRA_HAS_ARM_SCU
69 select ARCH_TEGRA_HAS_PCIE
70 select ARCH_TEGRA_HAS_SATA
71 select ARCH_TEGRA_HAS_DUAL_3D
72 select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
73 select ARM_CPU_SUSPEND if PM
74 select ARM_ERRATA_743622
75 select ARM_ERRATA_751472
76 select ARM_ERRATA_754322
77 select ARM_ERRATA_761320 if SMP
78 select ARM_ERRATA_764369 if SMP
80 select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
83 select CPU_FREQ_TABLE if CPU_FREQ
85 select GIC_SET_MULTIPLE_CPUS if SMP
86 select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
87 select NVMAP_DEFERRED_CACHE_MAINT if TEGRA_NVMAP
88 select NVMAP_HANDLE_MARSHAL if TEGRA_NVMAP
89 select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
90 select PCI_MSI if TEGRA_PCI
92 select PINCTRL_TEGRA30
95 select PL310_ERRATA_727915
96 select PL310_ERRATA_769419 if CACHE_L2X0
97 select PM_GENERIC_DOMAINS if PM
98 select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
100 select TEGRA_ERRATA_1053704 if TEGRA_IOMMU_SMMU
101 select TEGRA_LP2_CPU_TIMER if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS
102 select USB_ARCH_HAS_EHCI if USB_SUPPORT
103 select USB_ULPI if USB_PHY
104 select USB_ULPI_VIEWPORT if USB_PHY
106 Support for NVIDIA Tegra T30 processor family, based on the
107 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
109 config ARCH_TEGRA_11x_SOC
110 bool "Tegra 11x family SOC"
111 depends on !ARCH_TEGRA_12x_SOC
112 depends on !ARCH_TEGRA_14x_SOC
114 select ARCH_TEGRA_4GB_MEMORY
115 select ARCH_TEGRA_HAS_CL_DVFS
116 select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
117 select ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
118 select ARM_CPU_SUSPEND if PM
119 select ARM_ERRATA_798181
120 select ARM_ERRATA_799270
122 select ARM_L1_CACHE_SHIFT_6
123 select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
125 select HAVE_ARM_ARCH_TIMER
126 select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
127 select NVMAP_CACHE_MAINT_BY_SET_WAYS_ON_ONE_CPU if TEGRA_NVMAP
128 select NVMAP_DEFERRED_CACHE_MAINT if TEGRA_NVMAP
129 select NVMAP_HANDLE_MARSHAL if TEGRA_NVMAP
131 select PINCTRL_TEGRA114
134 select PM_GENERIC_DOMAINS if PM
135 select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
137 select TEGRA_DUAL_CBUS
138 select TEGRA_CORE_EDP_LIMITS
139 select TEGRA_ERRATA_977223
140 select TEGRA_ERRATA_1053704 if TEGRA_IOMMU_SMMU
141 select TEGRA_ERRATA_1157520
143 select TEGRA_ISOMGR_SYSFS
144 select TEGRA_LP2_CPU_TIMER if !TEGRA_RAIL_OFF_MULTIPLE_CPUS
145 select TEGRA_MC_PTSA if !TEGRA_FPGA_PLATFORM
146 select TEGRA_VDD_CORE_OVERRIDE if TEGRA_EMC_SCALING_ENABLE
147 select USB_ARCH_HAS_EHCI if USB_SUPPORT
148 select USB_EHCI_TEGRA if USB_SUPPORT
149 select USB_ULPI if USB_SUPPORT
150 select USB_ULPI_VIEWPORT if USB_SUPPORT
152 Support for NVIDIA Tegra 11x family of SoCs, based upon the
155 config ARCH_TEGRA_12x_SOC
156 bool "Tegra 12x family SOC"
157 depends on !ARCH_TEGRA_14x_SOC
158 select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
159 select ARCH_TEGRA_HAS_PCIE
161 select ARM_L1_CACHE_SHIFT_6
162 select ARM_ARCH_TIMER
163 select ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
164 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
165 select ARM_CPU_SUSPEND if PM
166 select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
167 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
169 select ARCH_REQUIRE_GPIOLIB
170 select USB_ARCH_HAS_EHCI if USB_SUPPORT
171 select USB_EHCI_TEGRA if USB_SUPPORT
172 select USB_ULPI if USB_SUPPORT
173 select USB_ULPI_VIEWPORT if USB_SUPPORT
175 select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
176 select TEGRA_LP2_CPU_TIMER if !TEGRA_RAIL_OFF_MULTIPLE_CPUS
177 select ARCH_SUPPORTS_MSI if TEGRA_PCI
178 select PCI_MSI if TEGRA_PCI
179 select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
180 select NVMAP_CACHE_MAINT_BY_SET_WAYS_ON_ONE_CPU if TEGRA_NVMAP
181 select NVMAP_DEFERRED_CACHE_MAINT if TEGRA_NVMAP
182 select NVMAP_HANDLE_MARSHAL if TEGRA_NVMAP
183 select ARCH_TEGRA_HAS_CL_DVFS
184 select TEGRA_DUAL_CBUS
187 select PM_GENERIC_DOMAINS if PM
189 select PINCTRL_TEGRA124
192 select TEGRA_DC_TEMPORAL_DITHER
193 select TEGRA_VDD_CORE_OVERRIDE if TEGRA_EMC_SCALING_ENABLE
194 select REGULATOR_TEGRA_DFLL_BYPASS
195 select HAVE_ARM_ARCH_TIMER
199 Support for NVIDIA Tegra 12x family of SoCs, based upon the
202 config ARCH_TEGRA_14x_SOC
203 bool "Tegra 14x family SOC"
205 select ARCH_TEGRA_HAS_ARM_SCU
206 select ARCH_TEGRA_HAS_CL_DVFS
207 select ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
208 select ARM_CPU_SUSPEND if PM
209 select ARM_ERRATA_754322
210 select ARM_ERRATA_764369 if SMP
212 select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
216 select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
217 select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
221 select GIC_SET_MULTIPLE_CPUS if SMP
222 select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
223 select NVMAP_DEFERRED_CACHE_MAINT if TEGRA_NVMAP
224 select NVMAP_HANDLE_MARSHAL if TEGRA_NVMAP
225 select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP
226 select PM_GENERIC_DOMAINS if PM
227 select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
229 select TEGRA_DISABLE_BBC_LATENCY_ALLOWANCE
230 select TEGRA_DUAL_CBUS
231 select TEGRA_ERRATA_977223
232 select TEGRA_ERRATA_1053704 if TEGRA_IOMMU_SMMU
233 select TEGRA_ERRATA_1213083
234 select TEGRA_ERRATA_1252872
236 select TEGRA_ISOMGR_SYSFS
237 select TEGRA_LP2_CPU_TIMER if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS
238 select TEGRA_VDD_CORE_OVERRIDE if TEGRA_EMC_SCALING_ENABLE
239 select USB_ARCH_HAS_EHCI if USB_SUPPORT
240 select USB_EHCI_TEGRA if USB_SUPPORT
241 select USB_ULPI if USB_SUPPORT
242 select USB_ULPI_VIEWPORT if USB_SUPPORT
244 Support for NVIDIA Tegra 14x family of SoCs, based upon the
245 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
247 config TEGRA_NO_CARVEOUT
248 bool "Disable Tegra carveout"
251 config ARCH_TEGRA_HAS_ARM_SCU
254 config ARCH_TEGRA_HAS_DUAL_3D
257 config ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
260 config ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
263 config ARCH_TEGRA_HAS_PCIE
266 config ARCH_TEGRA_HAS_SATA
269 config ARCH_TEGRA_HAS_CL_DVFS
273 bool "PCIe host controller driver"
275 select TEGRA_USB_SHARED_PAD
276 depends on ARCH_TEGRA_HAS_PCIE
278 Adds PCIe Host controller driver for tegra based systems
280 config TEGRA_PCIE_SKIP_POWERGATING
281 bool "Skip PCIE powergating"
284 Do not powergate PCIE partition on boot up.
287 bool "Enable AHB driver for NVIDIA Tegra SoCs"
290 Adds AHB configuration functionality for NVIDIA Tegra SoCs,
291 which controls AHB bus master arbitration and some
292 performance parameters(priority, prefech size).
294 comment "Tegra board type"
298 depends on ARCH_TEGRA_12x_SOC
299 select TEGRA_FPGA_PLATFORM
301 Support for NVIDIA Bonaire FPGA development platform
305 depends on ARCH_TEGRA_12x_SOC || ARCH_TEGRA_11x_SOC
306 select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
307 select MACH_HAS_SND_SOC_TEGRA_RT5645 if SND_SOC
308 select SYSEDP_FRAMEWORK
310 Support for NVIDIA ARDBEG Development platform
314 depends on ARCH_TEGRA_12x_SOC
315 select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
316 select MACH_HAS_SND_SOC_TEGRA_RT5645 if SND_SOC
318 Support for NVIDIA LOKI Development platform
320 config MACH_VCM30_T124
321 bool "VCM30_T124(Automotive) board"
322 depends on ARCH_TEGRA_12x_SOC
324 Support for NVIDIA VCM30_T124 Automotive Development platform
328 depends on ARCH_TEGRA_12x_SOC || ARCH_TEGRA_11x_SOC
329 select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
330 select MACH_HAS_SND_SOC_TEGRA_RT5645 if SND_SOC
332 Support for NVIDIA LAGUNA Development platform
336 depends on ARCH_TEGRA_11x_SOC
337 select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
338 select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
340 Support for NVIDIA DALMORE development platform
344 depends on ARCH_TEGRA_11x_SOC
345 select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
346 select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
348 Support for NVIDIA PISMO development platform
351 bool "Macallan board"
352 depends on ARCH_TEGRA_11x_SOC
353 select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
354 select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
357 Support for NVIDIA MACALLAN development platform
359 config MACH_TEGRA_PLUTO
361 depends on ARCH_TEGRA_11x_SOC
362 select MACH_HAS_SND_SOC_TEGRA_CS42L73 if SND_SOC
363 select MACH_HAS_SND_SOC_TEGRA_TLV320AIC326X if SND_SOC
366 Support for NVIDIA PLUTO development platform
370 depends on ARCH_TEGRA_11x_SOC
371 select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
372 select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
374 Support for NVIDIA THOR development platform
377 prompt "Tegra platform type"
378 default TEGRA_SILICON_PLATFORM
380 config TEGRA_SILICON_PLATFORM
383 This enables support for a Tegra silicon platform.
385 config TEGRA_SIMULATION_PLATFORM
387 select TEGRA_PRE_SILICON_SUPPORT
388 select LESS_GCC_OPT if DEBUG_KERNEL
389 select READABLE_ASM if DEBUG_KERNEL
390 select TEGRA_SIMULATION_SPLIT_MEM
392 This enables support for a Tegra simulation platform.
393 Select this only if you are an NVIDIA developer working
394 on a simulation platform.
396 config TEGRA_FPGA_PLATFORM
398 select TEGRA_PRE_SILICON_SUPPORT
399 select LESS_GCC_OPT if DEBUG_KERNEL
400 select READABLE_ASM if DEBUG_KERNEL
402 This enables support for a Tegra FPGA platform.
403 Select this only if you are an NVIDIA developer working
407 config TEGRA_PRE_SILICON_SUPPORT
408 bool "Enable pre-silicon platform support"
410 This enables support for Tegra early development platforms.
411 Select this only if you are an NVIDIA developer working on
412 FPGA, Emulation or Simulation.
414 config TEGRA_SIMULATION_SPLIT_MEM
415 bool "Tegra Simulation Split Memory Configuration"
418 This enables support for a Tegra split memory
419 simulation. It can be used as part of ASIM/QT test
420 setup. Select this only if you are an NVIDIA developer
421 working on a simulation platform.
423 config TEGRA_FIQ_DEBUGGER
424 bool "Enable the FIQ serial debugger on Tegra"
428 Enables the FIQ serial debugger on Tegra
430 config TEGRA_EMC_SCALING_ENABLE
431 bool "Enable scaling the memory frequency"
434 config TEGRA_CPU_DVFS
435 bool "Enable voltage scaling on Tegra CPU"
438 config TEGRA_CORE_DVFS
439 bool "Enable voltage scaling on Tegra core"
440 depends on TEGRA_CPU_DVFS
443 config TEGRA_GPU_DVFS
444 bool "Enable voltage scaling on Tegra GPU"
445 depends on TEGRA_SILICON_PLATFORM
446 depends on ARCH_TEGRA_12x_SOC
450 bool "Enable the GK20A graphics engine"
451 depends on ARCH_TEGRA_12x_SOC
454 Enable support for the GK20A graphics engine
456 config TEGRA_AVP_KERNEL_ON_MMU
457 bool "Use AVP MMU to relocate AVP kernel"
458 depends on ARCH_TEGRA_2x_SOC
461 Use AVP MMU to relocate AVP kernel (nvrm_avp.bin).
463 config TEGRA_AVP_KERNEL_ON_SMMU
464 bool "Use SMMU to relocate AVP kernel"
465 depends on TEGRA_IOVMM_SMMU || TEGRA_IOMMU_SMMU
468 Use SMMU to relocate AVP kernel (nvrm_avp.bin).
470 config TEGRA_ARB_SEMAPHORE
473 config TEGRA_THERMAL_THROTTLE
474 bool "Enable throttling of CPU speed on overtemp"
479 Also requires enabling a temperature sensor such as NCT1008.
481 config TEGRA_THERMAL_THROTTLE_EXACT_FREQ
482 bool "Use exact cpu frequency capping when thermal throttling"
483 depends on TEGRA_THERMAL_THROTTLE
484 default y if TEGRA_THERMAL_THROTTLE
487 When this option is enabled, the cpu will run at the exact
488 frequency specified in the thermal throttle table when thermal
489 throttling; when disabled, the cpu frequency will clip to
490 the next lower frequency from the cpu frequency table.
492 config TEGRA_CLOCK_DEBUG_WRITE
493 bool "Enable debugfs write access to clock tree"
497 config TEGRA_CLOCK_DEBUG_FUNC
498 bool "Enable extra debug functions to access to clock tree"
499 depends on TEGRA_CLOCK_DEBUG_WRITE
502 config TEGRA_CLUSTER_CONTROL
504 depends on ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
505 default y if PM_SLEEP
507 config TEGRA_CPUQUIET
510 config TEGRA_AUTO_HOTPLUG
511 bool "Enable automatic CPU hot-plugging"
512 depends on HOTPLUG_CPU && CPU_FREQ && !ARCH_CPU_PROBE_RELEASE && !ARCH_TEGRA_2x_SOC
513 select TEGRA_CPUQUIET
516 This option enables turning CPUs off/on and switching tegra
517 high/low power CPU clusters automatically, corresponding to
518 CPU frequency scaling.
520 config TEGRA_MC_EARLY_ACK
521 bool "Enable early acknowledgement from mermory controller"
522 depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_11x_SOC
525 This option enables early acknowledgement from memory
526 controller. This feature is used to improve CPU memory
529 config TEGRA_ERRATA_1252872
530 bool "DLL experiences internal sychronization issue"
531 depends on ARCH_TEGRA_14x_SOC
533 The digital DLL in the T148 A01 chip has an internal synchronization
534 issue that can lead to reading invalid results. These invalid results
535 are returned when multiple bits change in one calibration value to
536 the next. To work around this a two step process is used: (1) the DLL
537 is enabled and locked (but not sampled); and (2) the DLL clock is
538 disabled and the internal state machine is reinvoked (and then
539 sampled). This requires that the DLL is never placed in a continuous
542 config TEGRA_ERRATA_1213083
543 bool "HOTRESET_STAT can return invalid status"
544 depends on ARCH_TEGRA_14x_SOC
546 On T14x it is possible to read the HOTRESET_STAT register before
547 the HW has had a chance to transition into the flush state. Thus
548 the flush status appears to be done. This errata adds a small delay
549 (at least 25 mcclk cycles) before polling the HOTRESET_STAT register.
551 config TEGRA_ERRATA_1157520
552 bool "Memory writes are not consistent/ordered from CPU"
553 depends on ARCH_TEGRA_11x_SOC
555 On T11x With early ack scoreboard on, the read/writes to
556 SO and Non-Cached meory are randomly not observed in the
557 order they are performed. Enabling this errata disables
558 early ack scoreboard for T11x.
560 config TEGRA_ERRATA_977223
561 bool "PTSA ring 1 to ring 0 does not account for forced coalescing"
562 depends on ARCH_TEGRA_11x_SOC || ARCH_TEGRA_14x_SOC
564 The forced coalescing logic will "drop" the first request of the
565 coalesced pair after the ring 1 snap arbiter. This means that for
566 forced coalescing clients, ring 0 only sees half the requests.
567 Therefore the grant decrement for the ptsa would only happen 1/2 of
568 the expected times resulting in ring 1 input always being
569 high priority. A SW work around is to program the ring 1 input to
570 ring 0 ptsa rate to be 1/2 of the value intended.
572 config TEGRA_EDP_LIMITS
573 bool "Enforce electrical design limits on CPU rail"
576 default y if ARCH_TEGRA_3x_SOC
579 Limit maximum CPU frequency based on temperature and number
580 of on-line CPUs to keep CPU rail current within power supply
583 config TEGRA_CPU_EDP_FIXED_LIMITS
584 bool "Enforce fixed EDP limits on CPU rail per chip SKU"
585 depends on ARCH_TEGRA_11x_SOC
586 depends on TEGRA_EDP_LIMITS
589 Enforce CPU EDP frequency limits which are fixed for a given
590 chip SKU. By default, the max frequency is determined optimally
591 for each individual chip.
593 config TEGRA_EMC_TO_DDR_CLOCK
594 int "EMC to DDR clocks ratio"
595 default "2" if ARCH_TEGRA_2x_SOC
598 config TEGRA_GADGET_BOOST_CPU_FREQ
599 int "Boost cpu frequency for tegra usb gadget"
600 range 0 1300 if ARCH_TEGRA_3x_SOC
601 range 0 1800 if ARCH_TEGRA_11x_SOC
602 range 0 2000 if ARCH_TEGRA_14x_SOC
603 range 0 2000 if ARCH_TEGRA_12x_SOC
606 Devices need to boost frequency of CPU when they are connected
607 to host pc through usb cable for better performance. This value
608 is the amount of the frequency (in Mhz) to be boosted. If it is
609 zero boosting frequency will not be enabled. This value will be
610 used only by usb gadget driver.
612 config TEGRA_EHCI_BOOST_CPU_FREQ
613 int "Boost cpu frequency(in Mhz) for tegra usb host"
614 range 0 1300 if ARCH_TEGRA_3x_SOC
615 range 0 1800 if ARCH_TEGRA_11x_SOC
616 range 0 2000 if ARCH_TEGRA_14x_SOC
617 range 0 2000 if ARCH_TEGRA_12x_SOC
620 This value is the amount of the cpu frequency (in Mhz)
621 to be boosted. If it is zero boosting frequency will not
622 be enabled. This value will be used only by usb ehci driver.
624 config TEGRA_DYNAMIC_PWRDET
625 bool "Enable dynamic activation of IO level auto-detection"
628 This option allows turning off tegra IO level auto-detection
629 when IO power is stable. If set auto-detection cells are active
630 only during power transitions, otherwise, the cells are active
633 config TEGRA_EDP_EXACT_FREQ
634 bool "Use maximum possible cpu frequency when EDP capping"
635 depends on TEGRA_EDP_LIMITS
638 When enabled the cpu will run at the exact frequency
639 specified in the EDP table when EDP capping is applied; when
640 disabled the next lower cpufreq frequency will be used.
642 config TEGRA_WAKEUP_MONITOR
643 bool "Enable tegra wakeup monitor"
646 This option enables support for the monitor of tegra wakeups, it will
647 send out wakeup source and uevents which indicate suspend_prepare and
650 config TEGRA_INTERNAL_USB_CABLE_WAKE_SUPPORT
651 bool "Enable Tegra internal USB cable wake support"
655 Enables Tegra suspend wakeup with USB cable through Tegra
656 integrated hardware. Enabled for selected Tegra chipsets.
657 This feature allows wakeup from suspend using either
658 device or host type USB cable.
660 config TEGRA_BB_XMM_POWER
661 bool "Enable power driver for XMM modem"
664 Enables power driver which controls gpio signals to XMM modem.
666 config TEGRA_BB_XMM_POWER2
667 tristate "Enable power driver for XMM modem (flashless)"
670 Enables power driver which controls gpio signals to XMM modem
671 (in flashless configuration). User-mode application must
672 insert this LKM to initiate 2nd USB enumeration power sequence
673 - after modem software has been downloaded to flashless device.
675 config TEGRA_BBC_PROXY
676 bool "Enable BBC Proxy driver"
679 Enables driver which handles miscellaneous services required
680 by the BB core. Handles initialization of EDP, ISO Bandwidth,
681 and Latency Allowance settings. Additional setting adjustments
682 can be done from user space through sysfs.
684 config TEGRA_BBC_THERMAL
685 bool "Enable BBC Thermal reporting support"
687 depends on TEGRA_BBC_PROXY
690 Enables the reporting of BBC-managed temperature sensors values as
691 thermal zones. This uses the statistics framework where the data
692 reside, and thus depends on the NVSHM driver to provides the API to
693 browse the BBC statistics and be notified of modem [re-]boot.
695 config TEGRA_PLLM_RESTRICTED
696 bool "Restrict PLLM usage as module clock source"
697 depends on !ARCH_TEGRA_2x_SOC
700 When enabled, PLLM usage may be restricted to modules with dividers
701 capable of dividing maximum PLLM frequency at minimum voltage. When
702 disabled, PLLM is used as a clock source with no restrictions (which
703 may effectively increase lower limit for core voltage).
705 config TEGRA_WDT_RECOVERY
706 bool "Enable suspend/resume watchdog recovery mechanism"
709 Enables watchdog recovery mechanism to protect against
710 suspend/resume hangs.
712 config TEGRA_LP2_CPU_TIMER
715 config TEGRA_RAIL_OFF_MULTIPLE_CPUS
718 config TEGRA_SLOW_CSITE
719 bool "lower csite clock to 1 Mhz to reduce its power consumption"
722 When enabled, csite will be running at 1 Mhz and the performance of
723 jtag, lauterbach and other debugger will be extremely slow.
725 config TEGRA_PREPOWER_WIFI
726 bool "Pre-power up WiFi "
729 Pre-power up the on board WiFi chip
731 config TEGRA_DYNAMIC_CBUS
732 bool "Adjust dynamically graphics clocks cumulative dvfs table"
734 config TEGRA_DUAL_CBUS
735 bool "Use two plls (PLLC2/PLLC3) as graphics clocks sources"
737 config TEGRA_MIGRATE_CBUS_USERS
738 bool "Move cbus users between source plls to optimize cumulative dvfs"
739 depends on TEGRA_DYNAMIC_CBUS && TEGRA_DUAL_CBUS
741 config TEGRA_SKIN_THROTTLE
742 bool "Skin Temperature throttling"
743 depends on TEGRA_THERMAL_THROTTLE
747 Enable throttling to control the temperature of the skin/case
750 config ARCH_TEGRA_4GB_MEMORY
751 bool "Full 4GB physical memory support"
754 Harmless to select this even if hardware does not support full
757 config TEGRA_LP1_LOW_COREVOLTAGE
758 bool "LP1 low core voltage"
760 depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_11x_SOC
762 Enable support for LP1 Core voltage to set to lowest
764 config TEGRA_DISABLE_BBC_LATENCY_ALLOWANCE
765 bool "Disable BBCRW latency allowance"
767 Disables BBCRW latency allowance configuration by
768 clients. The BBCRW latency allowance would remain
769 same as boot time configured value.
771 config TEGRA_BASEBAND
772 bool "Enable integrated tegra baseband support"
775 This option enables support for integrated icera baseband
776 This driver is used to setup shared memory space, provide
777 functions to handle IPC mechanism and a sysfs interface for IPC
778 notification which support polling on sysfs file.
780 config TEGRA_BASEBAND_SIMU
781 bool "Enable integrated tegra baseband simulation"
782 select TEGRA_BASEBAND
784 This option enables tegra baseband simulation when actual hardware
785 is not present. IPC is simulated when writing to status file which
786 allow high level tests in local loopback
789 bool "Enable MC PTSA programming"
791 Enables Priority Tier Snap Arbiter programming in
792 Memory Controller. PTSA is a Memory Controller feature that
793 allows specifying the bandwidth necessary for ISO clients.
796 bool "Isochronous Bandwidth Manager "
798 When enabled, drivers for ISO units can obtain ISO BW.
799 The memory controller (MC) for each Tegra platform can supply
800 a limited amount of isochronous (real-time) bandwidth. When
801 enabled, isomgr will manage a pool of ISO BW.
803 config TEGRA_ISOMGR_POOL_KB_PER_SEC
804 int "Size of isomgr pool "
807 Set this maximum ISO BW (in Kbytes/sec) that platform supports.
808 The memory controller (MC) for each Tegra platform can supply
809 a limited amount of isochronous (real-time) bandwidth. Each
810 platform must specify the maximum amount of ISO BW that isomgr
813 config TEGRA_ISOMGR_SYSFS
814 bool "Visibility into Isochronous Bandwidth Manager state "
815 depends on TEGRA_ISOMGR
817 When enabled, sysfs can be used to query isomgr state.
818 This is used for visibility into isomgr state. It could
819 be useful in debug or in understanding performance on a
822 config TEGRA_ISOMGR_MAX_ISO_BW_QUIRK
823 bool "Relax Max ISO Bw limit"
824 depends on TEGRA_ISOMGR
827 When enabled, allows system with less ISO bw continue to
828 work. This is necessary for systems running at lower
829 EMC clock freq or on FPGA.
833 depends on ARCH_TEGRA_3x_SOC
837 Allow devices listed in tegra_list_io_dpd[] to go into
838 Deep Power Down (DPD) state. This is a temporary config
839 option until a proper way is implemented to resolve this issue.
841 config TEGRA_USE_DFLL_RANGE
842 int "Default CPU DFLL operating range"
843 depends on ARCH_TEGRA_HAS_CL_DVFS
845 default "2" if TEGRA_SILICON_PLATFORM && ARCH_TEGRA_11x_SOC
848 Defines default range for dynamic frequency lock loop (DFLL)
849 to be used as CPU clock source:
850 "0" - DFLL is not used,
851 "1" - DFLL is used as a source for all CPU rates
852 "2" - DFLL is used only for high rates above crossover with
855 config REGULATOR_TEGRA_DFLL_BYPASS
856 bool "Use dfll bypass regulator"
857 depends on ARCH_TEGRA_HAS_CL_DVFS
860 Enables use of dfll bypass interfaces for voltage control
863 config TEGRA_TIMER_HZ
864 int "Kernel HZ (jiffies per second)"
865 default "100" if TEGRA_PRE_SILICON_SUPPORT
868 config TEGRA_SOCTHERM
869 bool "Enable soctherm"
870 depends on ARCH_TEGRA_11x_SOC || ARCH_TEGRA_14x_SOC || ARCH_TEGRA_12x_SOC
873 Enables use of soctherm for thermal management.
875 config TEGRA_USE_SECURE_KERNEL
876 bool "Boot the linux kernel in non-secure mode"
878 When enabled, the CPU will boot in the non-secure mode and issue
879 SMCs in order to access secure registers. SMC requests would be
880 serviced by a third party software component running in the secure
883 config TEGRA_VIRTUAL_CPUID
884 bool "virtualized CPUID"
885 depends on !TEGRA_USE_SECURE_KERNEL
886 depends on ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
889 Enables virtualized CPUID.
891 config TEGRA_NVDUMPER
892 bool "Enable NvDumper for post-mortem debugging"
895 The nvdumper is a tool that saves a copy of RAM following a crash.
896 nvdumper kernel module tracks whether the system has been rebooted
897 cleanly. It does this by writing 'dirty' to a fixed physical memory
898 address when the kernel starts.
899 Then, on a planned reboot, we write 'clean' to this location.
900 The bootloader can then examine this location and see if the reboot
902 It will dump the contents of memory after a dirty reboot.
903 This tool would be helpful for debugging kernel crash.
904 In order to use this feature, you should enable debug feature in
905 bootloader compiling option also (-DENABLE_NVDUMPER).
906 You can dump RAM with nvflash tool in dirty boot status.
907 usage: nvflash --dumpram [phy. RAM offset] [length] <filename>
909 config TEGRA_ARBITRATION_EMEM_INTR
910 bool "Enable the ARBITRATION_EMEM interrupt in the MC"
912 Enable this to allow the kernel to track arbitration conflicts
913 in the memory controller.
915 config TEGRA_CORE_EDP_LIMITS
916 bool "Enforce electrical design limits on core rail"
917 depends on TEGRA_SILICON_PLATFORM
921 Limit maximum GPU and memory frequency to keep core rail current
922 within power supply capabilities.
924 config TEGRA_PLLM_SCALED
925 bool "Enable memory PLLM run time scaling"
926 depends on TEGRA_DUAL_CBUS
927 select TEGRA_PLLM_RESTRICTED
930 When enabled, memory PLLM can be scaled at run time to reduce
931 granularity of possible memory rate steps. In this case PLLC
932 provides a backup memory clock while PLLM is re-locking to the
935 config ARCH_TEGRA_VIC
936 bool "Tegra Video Image Compositor present"
939 Say Y here if the SOC supports the Tegra Video Image Compositor.
940 Note that this not the same as the ARM Vectored Interrupt Controller.
942 config TEGRA_MC_DOMAINS
943 bool "Enable MC domains"
944 depends on PM_GENERIC_DOMAINS
947 When enabled, clock gates MC when it's not needed.
950 bool "Enable NCT partition access"
952 When enabled, we can read non-volatile items from NCT partition.
954 config TEGRA_VDD_CORE_OVERRIDE
955 bool "Enable core rail override support"
956 depends on TEGRA_SILICON_PLATFORM
959 When enabled, core rail can be fixed and locked at specified voltage
960 within override range, and core modules clocks are capped at rates
961 safe at override level.
966 config TEGRA_SOC_TIMERS
967 bool "Enable support for SOC timers"
970 When enabled, cpu clock events will be using SOC timers instead
971 of arm private timers.