1 # Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 # This program is free software; you can redistribute it and/or modify it
4 # under the terms and conditions of the GNU General Public License,
5 # version 2, as published by the Free Software Foundation.
7 # This program is distributed in the hope it will be useful, but WITHOUT
8 # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
9 # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 # You should have received a copy of the GNU General Public License
13 # along with this program. If not, see <http://www.gnu.org/licenses/>.
17 comment "NVIDIA Tegra options"
19 config ARCH_TEGRA_2x_SOC
20 bool "Enable support for Tegra20 family"
21 depends on !ARCH_TEGRA_3x_SOC
22 depends on !ARCH_TEGRA_11x_SOC
23 depends on !ARCH_TEGRA_14x_SOC
24 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
25 select ARCH_SUPPORTS_MSI if TEGRA_PCI
26 select ARCH_TEGRA_HAS_ARM_SCU
27 select ARCH_TEGRA_HAS_PCIE
28 select ARM_CPU_SUSPEND if PM
29 select ARM_ERRATA_716044
30 select ARM_ERRATA_720789
31 select ARM_ERRATA_742230 if SMP
32 select ARM_ERRATA_751472
33 select ARM_ERRATA_754327 if SMP
34 select ARM_ERRATA_761320 if SMP
35 select ARM_ERRATA_764369 if SMP
37 select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
40 select CPU_FREQ_TABLE if CPU_FREQ
42 select NVMAP_CACHE_MAINT_BY_SET_WAYS
43 select NVMAP_DEFERRED_CACHE_MAINT
44 select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS
45 select PCI_MSI if TEGRA_PCI
47 select PINCTRL_TEGRA20
48 select PL310_ERRATA_769419 if CACHE_L2X0
49 select PM_GENERIC_DOMAINS if PM
51 select USB_ARCH_HAS_EHCI if USB_SUPPORT
52 select USB_ULPI if USB_PHY
53 select USB_ULPI_VIEWPORT if USB_PHY
55 Support for NVIDIA Tegra AP20 and T20 processors, based on the
56 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
58 config ARCH_TEGRA_3x_SOC
59 bool "Enable support for Tegra30 family"
60 depends on !ARCH_TEGRA_11x_SOC
61 depends on !ARCH_TEGRA_14x_SOC
62 select ARCH_SUPPORTS_MSI if TEGRA_PCI
63 select ARCH_TEGRA_HAS_ARM_SCU
64 select ARCH_TEGRA_HAS_PCIE
65 select ARCH_TEGRA_HAS_SATA
66 select ARCH_TEGRA_HAS_DUAL_3D
67 select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
68 select ARM_CPU_SUSPEND if PM
69 select ARM_ERRATA_743622
70 select ARM_ERRATA_751472
71 select ARM_ERRATA_754322
72 select ARM_ERRATA_761320 if SMP
73 select ARM_ERRATA_764369 if SMP
75 select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
78 select CPU_FREQ_TABLE if CPU_FREQ
80 select GIC_SET_MULTIPLE_CPUS if SMP
81 select NVMAP_CACHE_MAINT_BY_SET_WAYS
82 select NVMAP_DEFERRED_CACHE_MAINT
83 select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS
84 select PCI_MSI if TEGRA_PCI
86 select PINCTRL_TEGRA30
87 select PL310_ERRATA_727915
88 select PL310_ERRATA_769419 if CACHE_L2X0
89 select PM_GENERIC_DOMAINS if PM
90 select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
92 select TEGRA_ERRATA_1053704
93 select TEGRA_LATENCY_ALLOWANCE
94 select TEGRA_LATENCY_ALLOWANCE_SCALING
95 select TEGRA_LP2_CPU_TIMER if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS
96 select USB_ARCH_HAS_EHCI if USB_SUPPORT
97 select USB_ULPI if USB_PHY
98 select USB_ULPI_VIEWPORT if USB_PHY
100 Support for NVIDIA Tegra T30 processor family, based on the
101 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
103 config ARCH_TEGRA_11x_SOC
104 bool "Tegra 11x family SOC"
105 depends on !ARCH_TEGRA_14x_SOC
107 select ARCH_REQUIRE_GPIOLIB
108 select ARCH_TEGRA_4GB_MEMORY
109 select ARCH_TEGRA_HAS_CL_DVFS
110 select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
111 select ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
112 select ARM_ARCH_TIMER
113 select ARM_CPU_SUSPEND if PM
114 select ARM_ERRATA_798181
115 select ARM_ERRATA_799270
117 select ARM_L1_CACHE_SHIFT_6
118 select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
120 select NVMAP_CACHE_MAINT_BY_SET_WAYS
121 select NVMAP_DEFERRED_CACHE_MAINT
123 select PM_GENERIC_DOMAINS if PM
124 select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
126 select TEGRA_DUAL_CBUS
127 select TEGRA_CORE_EDP_LIMITS
128 select TEGRA_ERRATA_977223
129 select TEGRA_ERRATA_1053704
130 select TEGRA_ERRATA_1157520
132 select TEGRA_ISOMGR_SYSFS
133 select TEGRA_LATENCY_ALLOWANCE
134 select TEGRA_LP2_CPU_TIMER if !TEGRA_RAIL_OFF_MULTIPLE_CPUS
135 select TEGRA_MC_PTSA if !TEGRA_FPGA_PLATFORM
136 select TEGRA_THERMAL_THROTTLE_EXACT_FREQ
137 select TEGRA_VDD_CORE_OVERRIDE if TEGRA_EMC_SCALING_ENABLE
138 select USB_ARCH_HAS_EHCI if USB_SUPPORT
139 select USB_EHCI_TEGRA if USB_SUPPORT
140 select USB_ULPI if USB_SUPPORT
141 select USB_ULPI_VIEWPORT if USB_SUPPORT
143 Support for NVIDIA Tegra 11x family of SoCs, based upon the
146 config ARCH_TEGRA_HAS_ARM_SCU
149 config ARCH_TEGRA_14x_SOC
150 bool "Tegra 14x family SOC"
152 select ARCH_TEGRA_HAS_ARM_SCU
153 select ARCH_TEGRA_HAS_CL_DVFS
154 select ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
155 select ARM_CPU_SUSPEND if PM
156 select ARM_ERRATA_754322
157 select ARM_ERRATA_764369 if SMP
159 select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
161 select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
162 select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
166 select GIC_SET_MULTIPLE_CPUS if SMP
167 select NVMAP_CACHE_MAINT_BY_SET_WAYS
168 select NVMAP_DEFERRED_CACHE_MAINT
169 select NVMAP_OUTER_CACHE_MAINT_BY_SET_WAYS
170 select PM_GENERIC_DOMAINS if PM
171 select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
173 select TEGRA_DUAL_CBUS
174 select TEGRA_ERRATA_977223
175 select TEGRA_ERRATA_1053704
176 select TEGRA_ERRATA_1213083
177 select TEGRA_ERRATA_1252872
179 select TEGRA_ISOMGR_SYSFS
180 select TEGRA_LP2_CPU_TIMER if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS
181 select USB_ARCH_HAS_EHCI if USB_SUPPORT
182 select USB_EHCI_TEGRA if USB_SUPPORT
183 select USB_ULPI if USB_SUPPORT
184 select USB_ULPI_VIEWPORT if USB_SUPPORT
186 Support for NVIDIA Tegra 14x family of SoCs, based upon the
187 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
189 config ARCH_TEGRA_HAS_DUAL_3D
192 config ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
195 config ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
198 config ARCH_TEGRA_HAS_PCIE
201 config ARCH_TEGRA_HAS_SATA
204 config ARCH_TEGRA_HAS_CL_DVFS
208 bool "PCIe host controller driver"
210 depends on ARCH_TEGRA_HAS_PCIE
212 Adds PCIe Host controller driver for tegra based systems
215 bool "Enable AHB driver for NVIDIA Tegra SoCs"
218 Adds AHB configuration functionality for NVIDIA Tegra SoCs,
219 which controls AHB bus master arbitration and some
220 performance parameters(priority, prefech size).
222 comment "Tegra board type"
226 depends on ARCH_TEGRA_11x_SOC
227 select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
228 select TEGRA_FPGA_PLATFORM
230 Support for NVIDIA Curacao FPGA development platform
235 depends on ARCH_TEGRA_11x_SOC
236 select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
237 select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
239 Support for NVIDIA DALMORE development platform
243 depends on ARCH_TEGRA_11x_SOC
244 select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
245 select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
247 Support for NVIDIA PISMO development platform
250 bool "Macallan board"
251 depends on ARCH_TEGRA_11x_SOC
252 select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
253 select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
256 Support for NVIDIA MACALLAN development platform
258 config MACH_TEGRA_PLUTO
260 depends on ARCH_TEGRA_11x_SOC
261 select MACH_HAS_SND_SOC_TEGRA_CS42L73 if SND_SOC
262 select MACH_HAS_SND_SOC_TEGRA_TLV320AIC326X if SND_SOC
265 Support for NVIDIA PLUTO development platform
269 depends on ARCH_TEGRA_11x_SOC
270 select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
271 select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
273 Support for NVIDIA THOR development platform
276 prompt "Tegra platform type"
277 default TEGRA_SILICON_PLATFORM
279 config TEGRA_SILICON_PLATFORM
282 This enables support for a Tegra silicon platform.
284 config TEGRA_SIMULATION_PLATFORM
286 select TEGRA_PRE_SILICON_SUPPORT
287 select LESS_GCC_OPT if DEBUG_KERNEL
289 This enables support for a Tegra simulation platform.
290 Select this only if you are an NVIDIA developer working
291 on a simulation platform.
293 config TEGRA_FPGA_PLATFORM
295 select TEGRA_PRE_SILICON_SUPPORT
297 This enables support for a Tegra FPGA platform.
298 Select this only if you are an NVIDIA developer working
302 config TEGRA_PRE_SILICON_SUPPORT
303 bool "Enable pre-silicon platform support"
305 This enables support for Tegra early development platforms.
306 Select this only if you are an NVIDIA developer working on
307 FPGA, Emulation or Simulation.
309 config TEGRA_FIQ_DEBUGGER
310 bool "Enable the FIQ serial debugger on Tegra"
314 Enables the FIQ serial debugger on Tegra
316 config TEGRA_EMC_SCALING_ENABLE
317 bool "Enable scaling the memory frequency"
318 depends on TEGRA_SILICON_PLATFORM
321 config TEGRA_CPU_DVFS
322 bool "Enable voltage scaling on Tegra CPU"
323 depends on TEGRA_SILICON_PLATFORM
326 config TEGRA_CORE_DVFS
327 bool "Enable voltage scaling on Tegra core"
328 depends on TEGRA_SILICON_PLATFORM
329 depends on TEGRA_CPU_DVFS
332 config TEGRA_AVP_KERNEL_ON_MMU
333 bool "Use AVP MMU to relocate AVP kernel"
334 depends on ARCH_TEGRA_2x_SOC
337 Use AVP MMU to relocate AVP kernel (nvrm_avp.bin).
339 config TEGRA_AVP_KERNEL_ON_SMMU
340 bool "Use SMMU to relocate AVP kernel"
341 depends on TEGRA_IOVMM_SMMU || TEGRA_IOMMU_SMMU
344 Use SMMU to relocate AVP kernel (nvrm_avp.bin).
346 config TEGRA_ARB_SEMAPHORE
349 config TEGRA_THERMAL_THROTTLE
350 bool "Enable throttling of CPU speed on overtemp"
351 depends on TEGRA_SILICON_PLATFORM
356 Also requires enabling a temperature sensor such as NCT1008.
358 config TEGRA_THERMAL_THROTTLE_EXACT_FREQ
359 bool "Use exact cpu frequency capping when thermal throttling"
360 depends on TEGRA_THERMAL_THROTTLE
363 When this option is enabled, the cpu will run at the exact
364 frequency specified in the thermal throttle table when thermal
365 throttling; when disabled, the cpu frequency will clip to
366 the next lower frequency from the cpu frequency table.
368 config TEGRA_CLOCK_DEBUG_WRITE
369 bool "Enable debugfs write access to clock tree"
373 config TEGRA_CLUSTER_CONTROL
375 depends on ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
376 default y if PM_SLEEP
378 config TEGRA_CPUQUIET
381 config TEGRA_AUTO_HOTPLUG
382 bool "Enable automatic CPU hot-plugging"
383 depends on HOTPLUG_CPU && CPU_FREQ && !ARCH_CPU_PROBE_RELEASE && !ARCH_TEGRA_2x_SOC
384 select TEGRA_CPUQUIET
387 This option enables turning CPUs off/on and switching tegra
388 high/low power CPU clusters automatically, corresponding to
389 CPU frequency scaling.
391 config TEGRA_MC_EARLY_ACK
392 bool "Enable early acknowledgement from mermory controller"
393 depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_11x_SOC
396 This option enables early acknowledgement from memory
397 controller. This feature is used to improve CPU memory
400 config TEGRA_ERRATA_1252872
401 bool "DLL experiences internal sychronization issue"
402 depends on ARCH_TEGRA_14x_SOC
404 The digital DLL in the T148 A01 chip has an internal synchronization
405 issue that can lead to reading invalid results. These invalid results
406 are returned when multiple bits change in one calibration value to
407 the next. To work around this a two step process is used: (1) the DLL
408 is enabled and locked (but not sampled); and (2) the DLL clock is
409 disabled and the internal state machine is reinvoked (and then
410 sampled). This requires that the DLL is never placed in a continuous
413 config TEGRA_ERRATA_1213083
414 bool "HOTRESET_STAT can return invalid status"
415 depends on ARCH_TEGRA_14x_SOC
417 On T14x it is possible to read the HOTRESET_STAT register before
418 the HW has had a chance to transition into the flush state. Thus
419 the flush status appears to be done. This errata adds a small delay
420 (at least 25 mcclk cycles) before polling the HOTRESET_STAT register.
422 config TEGRA_ERRATA_1157520
423 bool "Memory writes are not consistent/ordered from CPU"
424 depends on ARCH_TEGRA_11x_SOC
426 On T11x With early ack scoreboard on, the read/writes to
427 SO and Non-Cached meory are randomly not observed in the
428 order they are performed. Enabling this errata disables
429 early ack scoreboard for T11x.
431 config TEGRA_ERRATA_977223
432 bool "PTSA ring 1 to ring 0 does not account for forced coalescing"
433 depends on ARCH_TEGRA_11x_SOC || ARCH_TEGRA_14x_SOC
435 The forced coalescing logic will "drop" the first request of the
436 coalesced pair after the ring 1 snap arbiter. This means that for
437 forced coalescing clients, ring 0 only sees half the requests.
438 Therefore the grant decrement for the ptsa would only happen 1/2 of
439 the expected times resulting in ring 1 input always being
440 high priority. A SW work around is to program the ring 1 input to
441 ring 0 ptsa rate to be 1/2 of the value intended.
443 config TEGRA_EDP_LIMITS
444 bool "Enforce electrical design limits on CPU rail"
445 depends on TEGRA_SILICON_PLATFORM
448 default y if ARCH_TEGRA_3x_SOC
451 Limit maximum CPU frequency based on temperature and number
452 of on-line CPUs to keep CPU rail current within power supply
455 config TEGRA_EMC_TO_DDR_CLOCK
456 int "EMC to DDR clocks ratio"
457 default "2" if ARCH_TEGRA_2x_SOC
460 config TEGRA_GADGET_BOOST_CPU_FREQ
461 int "Boost cpu frequency for tegra usb gadget"
462 range 0 1300 if ARCH_TEGRA_3x_SOC
463 range 0 1800 if ARCH_TEGRA_11x_SOC
464 range 0 2000 if ARCH_TEGRA_14x_SOC
467 Devices need to boost frequency of CPU when they are connected
468 to host pc through usb cable for better performance. This value
469 is the amount of the frequency (in Mhz) to be boosted. If it is
470 zero boosting frequency will not be enabled. This value will be
471 used only by usb gadget driver.
473 config TEGRA_EHCI_BOOST_CPU_FREQ
474 int "Boost cpu frequency(in Mhz) for tegra usb host"
475 range 0 1300 if ARCH_TEGRA_3x_SOC
476 range 0 1800 if ARCH_TEGRA_11x_SOC
477 range 0 2000 if ARCH_TEGRA_14x_SOC
480 This value is the amount of the cpu frequency (in Mhz)
481 to be boosted. If it is zero boosting frequency will not
482 be enabled. This value will be used only by usb ehci driver.
484 config TEGRA_DYNAMIC_PWRDET
485 bool "Enable dynamic activation of IO level auto-detection"
486 depends on TEGRA_SILICON_PLATFORM
489 This option allows turning off tegra IO level auto-detection
490 when IO power is stable. If set auto-detection cells are active
491 only during power transitions, otherwise, the cells are active
494 config TEGRA_EDP_EXACT_FREQ
495 bool "Use maximum possible cpu frequency when EDP capping"
496 depends on TEGRA_EDP_LIMITS
499 When enabled the cpu will run at the exact frequency
500 specified in the EDP table when EDP capping is applied; when
501 disabled the next lower cpufreq frequency will be used.
503 config TEGRA_WAKEUP_MONITOR
504 bool "Enable tegra wakeup monitor"
507 This option enables support for the monitor of tegra wakeups, it will
508 send out wakeup source and uevents which indicate suspend_prepare and
511 config TEGRA_BB_XMM_POWER
512 bool "Enable power driver for XMM modem"
515 Enables power driver which controls gpio signals to XMM modem.
517 config TEGRA_BB_XMM_POWER2
518 tristate "Enable power driver for XMM modem (flashless)"
521 Enables power driver which controls gpio signals to XMM modem
522 (in flashless configuration). User-mode application must
523 insert this LKM to initiate 2nd USB enumeration power sequence
524 - after modem software has been downloaded to flashless device.
526 config TEGRA_BBC_PROXY
527 bool "Enable BBC Proxy driver"
530 Enables driver which handles miscellaneous services required
531 by the BB core. Handles initialization of EDP, ISO Bandwidth,
532 and Latency Allowance settings. Additional setting adjustments
533 can be done from user space through sysfs.
535 config TEGRA_PLLM_RESTRICTED
536 bool "Restrict PLLM usage as module clock source"
537 depends on !ARCH_TEGRA_2x_SOC
540 When enabled, PLLM usage may be restricted to modules with dividers
541 capable of dividing maximum PLLM frequency at minimum voltage. When
542 disabled, PLLM is used as a clock source with no restrictions (which
543 may effectively increase lower limit for core voltage).
545 config TEGRA_WDT_RECOVERY
546 bool "Enable suspend/resume watchdog recovery mechanism"
549 Enables watchdog recovery mechanism to protect against
550 suspend/resume hangs.
552 config TEGRA_LP2_CPU_TIMER
555 config TEGRA_RAIL_OFF_MULTIPLE_CPUS
558 config TEGRA_SLOW_CSITE
559 bool "lower csite clock to 1 Mhz to reduce its power consumption"
562 When enabled, csite will be running at 1 Mhz and the performance of
563 jtag, lauterbach and other debugger will be extremely slow.
565 config TEGRA_PREPOWER_WIFI
566 bool "Pre-power up WiFi "
569 Pre-power up the on board WiFi chip
571 config TEGRA_DYNAMIC_CBUS
572 bool "Adjust dynamically graphics clocks cumulative dvfs table"
574 config TEGRA_DUAL_CBUS
575 bool "Use two plls (PLLC2/PLLC3) as graphics clocks sources"
577 config TEGRA_MIGRATE_CBUS_USERS
578 bool "Move cbus users between source plls to optimize cumulative dvfs"
579 depends on TEGRA_DYNAMIC_CBUS && TEGRA_DUAL_CBUS
581 config TEGRA_SKIN_THROTTLE
582 bool "Skin Temperature throttling"
583 depends on TEGRA_THERMAL_THROTTLE
587 Enable throttling to control the temperature of the skin/case
590 config ARCH_TEGRA_4GB_MEMORY
591 bool "Full 4GB physical memory support"
594 Harmless to select this even if hardware does not support full
597 config TEGRA_LP1_LOW_COREVOLTAGE
598 bool "LP1 low core voltage"
600 depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_11x_SOC
602 Enable support for LP1 Core voltage to set to lowest
604 config TEGRA_LATENCY_ALLOWANCE
605 bool "Allow memory clients to configure latency allowance"
607 Latency allowance is a per-memory-client setting that tells the
608 memory controller how long it can ignore a request in favor of
609 others. In other words, It indicates how long a request from specific
610 memory client can wait before it is served.
611 Enabling this option allows memory clients configure the
612 latency allowance as per their bandwidth requirement.
614 config TEGRA_LATENCY_ALLOWANCE_SCALING
615 bool "Enable latency allowance scaling"
616 depends on TEGRA_LATENCY_ALLOWANCE
618 Enables latency allowance scaling, which enables scaling
619 programmed latency allowance values based on fifo threshold levels
620 set for for display and vi hardware.
622 config TEGRA_BASEBAND
623 bool "Enable integrated tegra baseband support"
626 This option enables support for integrated icera baseband
627 This driver is used to setup shared memory space, provide
628 functions to handle IPC mechanism and a sysfs interface for IPC
629 notification which support polling on sysfs file.
631 config TEGRA_BASEBAND_SIMU
632 bool "Enable integrated tegra baseband simulation"
633 select TEGRA_BASEBAND
635 This option enables tegra baseband simulation when actual hardware
636 is not present. IPC is simulated when writing to status file which
637 allow high level tests in local loopback
640 bool "Enable MC PTSA programming"
641 depends on TEGRA_LATENCY_ALLOWANCE
643 Enables Priority Tier Snap Arbiter programming in
644 Memory Controller. PTSA is a Memory Controller feature that
645 allows specifying the bandwidth necessary for ISO clients.
648 bool "Isochronous Bandwidth Manager "
650 When enabled, drivers for ISO units can obtain ISO BW.
651 The memory controller (MC) for each Tegra platform can supply
652 a limited amount of isochronous (real-time) bandwidth. When
653 enabled, isomgr will manage a pool of ISO BW.
655 config TEGRA_ISOMGR_POOL_KB_PER_SEC
656 int "Size of isomgr pool "
659 Set this maximum ISO BW (in Kbytes/sec) that platform supports.
660 The memory controller (MC) for each Tegra platform can supply
661 a limited amount of isochronous (real-time) bandwidth. Each
662 platform must specify the maximum amount of ISO BW that isomgr
665 config TEGRA_ISOMGR_SYSFS
666 bool "Visibility into Isochronous Bandwidth Manager state "
667 depends on TEGRA_ISOMGR
669 When enabled, sysfs can be used to query isomgr state.
670 This is used for visibility into isomgr state. It could
671 be useful in debug or in understanding performance on a
674 config TEGRA_ISOMGR_MAX_ISO_BW_QUIRK
675 bool "Relax Max ISO Bw limit"
676 depends on TEGRA_ISOMGR
679 When enabled, allows system with less ISO bw continue to
680 work. This is necessary for systems running at lower
681 EMC clock freq or on FPGA.
685 depends on ARCH_TEGRA_3x_SOC
689 Allow devices listed in tegra_list_io_dpd[] to go into
690 Deep Power Down (DPD) state. This is a temporary config
691 option until a proper way is implemented to resolve this issue.
693 config TEGRA_USE_DFLL_RANGE
694 int "Default CPU DFLL operating range"
695 depends on ARCH_TEGRA_HAS_CL_DVFS
697 default "1" if TEGRA_SILICON_PLATFORM
700 Defines default range for dynamic frequency lock loop (DFLL)
701 to be used as CPU clock source:
702 "0" - DFLL is not used,
703 "1" - DFLL is used as a source for all CPU rates
704 "2" - DFLL is used only for high rates above crossover with
707 config TEGRA_TIMER_HZ
708 int "Kernel HZ (jiffies per second)"
709 default "100" if TEGRA_FPGA_PLATFORM
712 config TEGRA_SOCTHERM
713 bool "Enable soctherm"
714 depends on ARCH_TEGRA_11x_SOC || ARCH_TEGRA_14x_SOC
717 Enables use of soctherm for thermal management.
719 config TEGRA_USE_SECURE_KERNEL
720 bool "Boot the linux kernel in non-secure mode"
722 When enabled, the CPU will boot in the non-secure mode and issue
723 SMCs in order to access secure registers. SMC requests would be
724 serviced by a third party software component running in the secure
727 config TEGRA_VIRTUAL_CPUID
728 bool "virtualized CPUID"
729 depends on !TEGRA_USE_SECURE_KERNEL
730 depends on ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
733 Enables virtualized CPUID.
735 config TEGRA_NVDUMPER
736 bool "Enable NvDumper for post-mortem debugging"
739 The nvdumper is a tool that saves a copy of RAM following a crash.
740 nvdumper kernel module tracks whether the system has been rebooted
741 cleanly. It does this by writing 'dirty' to a fixed physical memory
742 address when the kernel starts.
743 Then, on a planned reboot, we write 'clean' to this location.
744 The bootloader can then examine this location and see if the reboot
746 It will dump the contents of memory after a dirty reboot.
747 This tool would be helpful for debugging kernel crash.
748 In order to use this feature, you should enable debug feature in
749 bootloader compiling option also (-DENABLE_NVDUMPER).
750 You can dump RAM with nvflash tool in dirty boot status.
751 usage: nvflash --dumpram [phy. RAM offset] [length] <filename>
753 config TEGRA_ARBITRATION_EMEM_INTR
754 bool "Enable the ARBITRATION_EMEM interrupt in the MC"
756 Enable this to allow the kernel to track arbitration conflicts
757 in the memory controller.
759 config TEGRA_CORE_EDP_LIMITS
760 bool "Enforce electrical design limits on core rail"
761 depends on TEGRA_SILICON_PLATFORM
765 Limit maximum GPU and memory frequency to keep core rail current
766 within power supply capabilities.
768 config TEGRA_PLLM_SCALED
769 bool "Enable memory PLLM run time scaling"
770 depends on TEGRA_DUAL_CBUS
771 select TEGRA_PLLM_RESTRICTED
774 When enabled, memory PLLM can be scaled at run time to reduce
775 granularity of possible memory rate steps. In this case PLLC
776 provides a backup memory clock while PLLM is re-locking to the
779 config TEGRA_MC_DOMAINS
780 bool "Enable MC domains"
781 depends on PM_GENERIC_DOMAINS
784 When enabled, clock gates MC when it's not needed.
787 bool "Enable NCT partition access"
789 When enabled, we can read non-volatile items from NCT partition.
791 config TEGRA_VDD_CORE_OVERRIDE
792 bool "Enable core rail override support"
793 depends on TEGRA_SILICON_PLATFORM
796 When enabled, core rail can be fixed and locked at specified voltage
797 within override range, and core modules clocks are capped at rates
798 safe at override level.